Pulse signal transmission circuit

Abstract

To provide a pulse signal transmission circuit that can transmit a pulse signal without variation in pulse width or duty ratio without increasing drastically the circuit scale or a chip size.SOLUTION: A pulse signal transmission circuit includes an output transistor (M0) having an output terminal connected to a drain terminal, and an inverter circuit (12) that is provided to a pre-stage of the output transistor and generates a signal to be input to a gate terminal of the output transistor. The output terminal outputs a pulse signal. The pulse signal transmission circuit includes a delay circuit (13) that receives the input of the pulse signal and delays one of a rise and a fall of the input pulse signal. The pulse signal delayed by the delay circuit is input to the inverter circuit.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a pulse signal transmitting circuit and a technology that is effective when used in a semiconductor integrated circuit incorporating the same, and in particular to a pulse signal transmitting circuit that has a function of preventing fluctuations in the pulse width and duty ratio of a transmitted pulse signal. [Background technology]

[0002] In circuits that transmit or output pulse signals (rectangular wave signals), a function to smooth out changes by adding a slope to the rising and falling edges of the output waveform is sometimes required as a countermeasure against EMI (electromagnetic interference). As an example of a pulse signal transmission circuit with such a slope control function, there is a circuit that includes a resistive load inverter with a resistive element as a load, and a CMOS inverter in a front stage that controls the on / off of the inverter's drive transistor M0, as shown in Figure 9.

[0003] 9, the desired slope can be imparted to the rising or falling edge of the output waveform by the feedback capacitance Crss (=Cgd) of the gate terminal of the drive transistor M0 and the current capacity of the CMOS inverter in the previous stage that drives the drive transistor M0. By imparting a slope to the rising and falling edges of the output waveform in this way, it is possible to suppress noise caused by a steep change in the waveform. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2004-166012 Summary of the Invention [Problem to be solved by the invention]

[0005] In the pulse signal transmission circuit shown in Fig. 9, when a square wave signal IN as shown in Fig. 10(a) is input to the CMOS inverter in the previous stage, a signal with a waveform with gradual rising and falling edges as shown in (c) is output, but the rise delay time trise and fall delay time tfall of the output waveform are not equal, and as a result, the pulse width and duty ratio of the output signal OUT do not match the pulse width and duty ratio of the input signal IN. As a result, when transmitting a pulse signal having a pulse width and duty ratio required by a receiving circuit, or in a system that transmits a pulse signal with information contained in the pulse width and duty ratio, there is a problem that an inappropriate signal is transmitted.

[0006] Incidentally, an invention relating to a pulse width adjustment circuit having a function of adjusting the pulse width has been proposed in the past (Patent Document 1). By providing such a pulse width adjustment circuit in the preceding stage of the pulse signal transmission circuit shown in Fig. 9, it is possible to configure it to transmit a pulse signal having a desired pulse width and duty ratio. However, the pulse width adjustment circuit described in Patent Document 1 is configured to include two inverters, multiple resistance elements, and multiple switch elements, which increases the circuit size. When applied to a semiconductor integrated circuit, there is a problem that the resistance elements in particular lead to a significant increase in chip size.

[0007] The present invention has been made in light of the above-mentioned background, and its object is to provide a pulse signal transmitting circuit that can transmit a pulse signal with no fluctuation in pulse width or duty ratio, without incurring a significant increase in circuit scale or chip size. Another object of the present invention is to provide a pulse signal transmission circuit that can accurately control the slope of the output waveform. [Means for solving the problem]

[0008] In order to achieve the above object, the present invention provides A pulse signal transmission circuit comprising: an output transistor having a drain terminal connected to an output terminal; and an inverter circuit provided in a stage preceding the output transistor and generating a signal to be input to a gate terminal of the output transistor, wherein the pulse signal transmission circuit outputs an output pulse signal from the output terminal, a delay circuit for delaying either a rising edge or a falling edge of an input pulse signal inputted from an input terminal; The pulse signal delayed by the delay circuit is input to the inverter circuit, The delay circuit adjusts the delay time for delaying either the rising or falling edge of the input pulse signal, thereby controlling the time (trise) required from the start of the rising edge of the input pulse signal to the end of the rising edge of the output pulse signal to be equal to the time (tfall) required from the start of the falling edge of the input pulse signal to the end of the falling edge of the output pulse signal. death, the inverter circuit is a CMOS inverter circuit having a P-channel MOS transistor and an N-channel MOS transistor connected in series, a first constant current source is connected in series with the P-channel MOS transistor between a first power supply voltage terminal and an output node; a second constant current source is connected in series with the N-channel MOS transistor between the output node and a second power supply voltage terminal; a third power supply voltage terminal to which a power supply voltage having a potential different from that of the first power supply voltage terminal is supplied, and a resistive element is connected between the third power supply voltage terminal or the second power supply voltage terminal and the drain terminal of the output transistor; This is what we have done.

[0009] The pulse signal transmission circuit having the above configuration includes a delay circuit that receives a pulse signal as an input and delays either the rising or falling edge of the input pulse signal, so that by providing the pulse signal transmission circuit with a slope control function, even if the rising delay time and falling delay time of the output waveform are no longer equal, the pulse signal delayed by the delay circuit is input to the inverter circuit that drives the output transistor, making it possible to transmit a pulse signal without fluctuations in pulse width or duty ratio.Furthermore, the pulse signal can be transmitted using an open-drain method. Furthermore, the device includes a third power supply voltage terminal to which a power supply voltage of a different potential from that of the first power supply voltage terminal is supplied, and a resistive element is connected between the third power supply voltage terminal or the second power supply voltage terminal and the drain terminal of the output transistor, so that a pulse signal obtained by level-shifting an input pulse signal can be transmitted without varying the pulse width or duty ratio.

[0010] Preferably, the inverter circuit is a CMOS inverter circuit having a P-channel MOS transistor and an N-channel MOS transistor connected in series, a first constant current source is connected in series with the P-channel MOS transistor between a first power supply voltage terminal and an output node; A second constant current source is connected in series with the N-channel MOS transistor between the output node and a second power supply voltage terminal. With this configuration, the rate of change of the gate voltage of the output transistor can be adjusted by the current of the constant current source, thereby controlling the rising and falling slopes of the output waveform.

[0011] Preferably, a resistive element is connected between the first power supply voltage terminal or the second power supply voltage terminal and the drain terminal of the output transistor. According to this configuration, a pulse signal can be transmitted without providing a pull-up or pull-down resistor in the circuit that receives the output pulse signal.

[0013] Preferably, the delay circuit is configured to have a function for adjusting the amount of delay. As a result, even if the time difference between the rise delay time and fall delay time of the output waveform varies depending on the system to which the pulse signal transmitting circuit is applied, for example due to differences in the period of the pulse signal, by adjusting the delay amount in the delay circuit, it is possible to transmit a pulse signal without fluctuations in pulse width or duty ratio.

[0014] Also, preferably, the delay circuit a switching MOS transistor and a constant current source connected in series between a first power supply voltage terminal and a second power supply voltage terminal; a capacitance element connected between a connection node of the switching MOS transistor and the constant current source and a second power supply voltage terminal or a first power supply voltage terminal; The configuration is such that: According to this configuration, a delay circuit that delays either the rising or falling edge of an input pulse signal can be realized using a circuit with a relatively small scale and simple configuration. [Effects of the Invention]

[0015] The pulse signal transmission circuit according to the present invention can transmit a pulse signal with no fluctuation in pulse width or duty ratio without significantly increasing the circuit scale or chip size, and also has the effect of being able to precisely control the slope of the output waveform. [Brief explanation of the drawings]

[0016] [Figure 1] 1 is a circuit configuration diagram showing an embodiment of a pulse signal transmission circuit to which the present invention is applied. [Figure 2] 1A, 1B, and 1C are circuit diagrams showing specific examples of falling edge delay circuits constituting the pulse signal transmission circuits of the first embodiment and the modified examples. [Figure 3] 10A and 10B are waveform diagrams showing the relationship between the input signal IN, the potential of an internal node, and the output voltage OUT in the pulse signal transmission circuits of the first embodiment and the modified example. [Figure 4] FIG. 2 is a circuit configuration diagram showing a first modified example of the pulse signal transmission circuit of the first embodiment. [Figure 5] 10 is a waveform diagram showing the relationship between an input signal IN, the potential of an internal node, and the output voltage OUT in the pulse signal transmission circuit of the first modified example. FIG. [Figure 6] FIG. 4 is a circuit configuration diagram showing a second modified example of the pulse signal transmission circuit of the first embodiment. [Figure 7] FIG. 4 is a circuit configuration diagram showing a second example of the pulse signal transmission circuit according to the embodiment. [Figure 8] 10 is a waveform diagram showing the relationship between an input signal IN, the potential of an internal node, and the output voltage OUT in the pulse signal transmission circuit of the second embodiment. FIG. [Figure 9] FIG. 1 is a circuit configuration diagram showing an example of a conventional pulse signal transmission circuit. [Figure 10] 10 is a waveform diagram showing the relationship between an input signal IN, the potential of an internal node, and the output voltage OUT in the conventional pulse signal transmission circuit shown in FIG. DETAILED DESCRIPTION OF THE INVENTION

[0017] Preferred embodiments of the present invention will now be described with reference to the accompanying drawings. FIG. 1 shows an embodiment of a pulse signal transmission circuit to which the present invention is applied. As shown in FIG. 1, the pulse signal transmission circuit 10 of this embodiment is composed of an output stage 11 consisting of a resistive load inverter having a resistor R0 and an N-channel MOS transistor M0 connected in series between a power supply voltage terminal and a ground point, a CMOS inverter circuit 12 in a preceding stage that controls the on / off of the MOS transistor M0 of the output stage 11, and a falling edge delay circuit 13 that is provided in a preceding stage of the CMOS inverter circuit 12 and delays the falling edge of an input pulse signal IN.

[0018] The CMOS inverter circuit 12 is composed of a P-channel MOS transistor M1 and an N-channel MOS transistor M2, whose gate terminals receive a common signal from the preceding falling edge delay circuit 13, a constant current source CC1 connected in series between a power supply voltage terminal and the P-channel MOS transistor M1, and a constant current source CC2 connected in series between the N-channel MOS transistor M2 and ground, and the gate terminal of the MOS transistor M0 in the output stage 11 is connected to a connection node N2 between M1 and M2. Note that the current value I1 of the current source CC1 and the current value I2 of CC2 are the same, i.e., I1=I2.

[0019] As shown in FIG. 2A, the falling edge delay circuit 13 is composed of an inverter INV that inverts the input signal IN, a P-channel MOS transistor Mp3 and a constant current source CC3 connected in series between the power supply voltage terminal and the ground point, and a capacitor C1 connected between the connection node N1 between the transistor Mp3 and the constant current source CC3 and the ground point. The constant current sources CC1, CC2, and CC3 can be configured by, for example, a current mirror circuit.

[0020] Next, the operation of the pulse signal transmitting circuit 10 of this embodiment will be described. In the conventional pulse signal transmission circuit shown in Fig. 9, the rise delay time trise and fall delay time tfall of the output waveform are not equal, as shown in Fig. 10(c), because the threshold voltage of MOS transistor M0 in output stage 11 is equal to or less than half the power supply voltage VDD, and the timing when M0 turns on and the drain current starts to flow occurs before the gate terminal voltage reaches VDD / 2. In contrast, the pulse signal transmission circuit of the embodiment in Fig. 1 is provided with fall delay circuit 13 to delay the timing when MOS transistor M0 in output stage 11 turns on. This makes the rise delay time trise and fall delay time tfall of the output waveform equal. Here, the rise delay time trise is the time from when the input signal IN starts to rise until the rise of the output OUT ends, as shown in Figure 10, and the fall delay time tfall is the time from when the input signal IN starts to fall until the fall of the output OUT ends.

[0021] Figure 3(A) shows the relationship between the input signal IN, the potential V1 of the internal node N1, the gate voltage Vg of the MOS transistor M0, and the output voltage OUT in the pulse signal transmission circuit 10 of the embodiment of Figure 1. Figure 3(B) shows the relationship when the circuit of Figure 2(B) is used as the falling edge delay circuit 13 in the pulse signal transmission circuit of the embodiment of Figure 1. In Figures 3(A) and (B), Vth is the threshold voltage of the MOS transistor M0, and is smaller than VDD / 2. This relationship can be set by selecting a voltage that is more than twice Vth as the power supply voltage VDD of resistor R0. The gate voltage Vg of M0 temporarily flattens during the rise and fall periods due to the feedback capacitance of the gate terminal of the MOS transistor M0, and the output voltage OUT changes during the flat period of Vg. In other words, by designing the circuit so that the flat period is of an appropriate length, the net rise delay time and fall delay time of the output waveform can be set.

[0022] As shown in FIG. 3(A), in the pulse signal transmission circuit 10 of the embodiment of FIG. 1, the fall of the potential V1 of the node N1 is delayed by the fall delay circuit 13 from the fall timing t1 of the input signal IN by the delay time tdelay of the delay circuit, so that the rise delay time trise and fall delay time tfall of the output waveform are made equal. Conversely, the delay time td of the falling edge delay circuit 13 is set so that trise = tfall. As a result, the pulse width and duty ratio of the output voltage OUT match those of the input signal IN, preventing fluctuations. The same is true in Figure 3(B). 9, when a rectangular wave signal IN as shown in FIG. 10(a) is input to the CMOS inverter in the preceding stage, a signal with a waveform having gradual rising and falling edges as shown in FIG. 10(c) is output, but the rising delay time trise and falling delay time tfall of the output waveform are not equal, and as a result, the pulse width and duty ratio of the output signal OUT do not match those of the input signal IN. In contrast, in the pulse signal transmission circuit 10 of this embodiment, the value of the delay time td of the falling delay circuit 13 is set so that trise = tfall, and the pulse width and duty ratio of the output voltage OUT match those of the input signal IN, preventing fluctuations.

[0023] 1, constant current sources CC1 and CC2 are connected in series with the P-MOS and N-MOS of the CMOS inverter circuit 12, so that the rising and falling waveform slopes of the gate voltage Vg of M0 and the output voltage OUT can be adjusted with high precision to desired values, compared to a conventional pulse signal transmission circuit (see FIG. 9) that does not have constant current sources CC1 and CC2. However, in the pulse signal transmission circuit of the embodiment of FIG. 1, it is also possible to adopt a configuration in which the constant current sources CC1 and CC2 are omitted by adjusting the output waveform slope through the design of the MOS transistor M0 in the output stage, as in a conventional circuit.

[0024] In the pulse signal transmission circuit 10 of FIG. 1, the circuit portion excluding the resistor R0 may be formed as a semiconductor integrated circuit (regulator IC) on a semiconductor chip such as single crystal silicon, and the load resistor may be connected as an external element between the external terminal and the power supply voltage terminal, or may be connected as a pull-up resistor between the input terminal and the power supply voltage terminal in the receiving circuit. Such open-drain signal transmission requiring EMI countermeasures is regulated, for example, by a communication standard for in-vehicle systems called LIN (Local Interconnect Network), and the pulse signal transmission circuit of this embodiment can be applied to a signal transmission circuit constituting a system having a LIN bus. The LIN standard requires that the duty ratio of the transmission signal (pulse) be 50%. This embodiment can also be applied to a signal transmission circuit constituting an in-vehicle network system that communicates according to a standard called CAN (Controller Area Network).

[0025] Furthermore, if the pulse signal transmission circuit 10 of this embodiment is configured as an open-drain circuit, the fall delay circuit 13 may include constant current sources CC4, CC5, etc. in parallel with the constant current source CC3, and switches S1, S2, etc. in series with the constant current sources CC4, CC5, etc., as shown in FIG. 2(B). This allows the current value discharging capacitor C1 to be switched according to the resistance of the pull-up resistor on the signal receiving side, thereby varying the fall delay time tfall of the output waveform and ensuring that the rise delay time trise and fall delay time tfall of the output waveform are equal regardless of the power supply voltage VDD of the pull-up resistor R0. As a result, fluctuations in the pulse width and duty cycle of the output voltage OUT can be effectively prevented in an open-drain pulse signal transmission circuit. Note that instead of switching the current value (constant current source) discharging capacitor C1, a circuit configuration that switches the capacitance value of capacitor C1 may be adopted.

[0026] FIG. 4 shows a first modified example of the pulse signal transmitting circuit of the above embodiment. The pulse signal transmission circuit of the first modification is obtained by applying the above embodiment (FIG. 1) to a circuit in which a P-channel MOS transistor Mp0 is used as the MOS transistor M0 of the output stage 11 instead of an N-channel MOS transistor, and a rising edge delay circuit 14 is provided instead of the falling edge delay circuit 13. The threshold voltage Vthp of the MOS transistor Mp0 is higher than VDD / 2. This relationship can be established by selecting a voltage higher than twice Vthp as the power supply voltage VDD of the resistor R0. A timing chart for this modification is shown in Fig. 5. As can be seen from Fig. 5, in this modification as well, the rise delay circuit 14 is provided, so that the rise delay time trise and fall delay time tfall of the waveform of the output voltage OUT can be made equal, thereby effectively preventing fluctuations in the pulse width and duty ratio of the output voltage OUT.

[0027] A specific example of the rising edge delay circuit 14 in this first modified example is a circuit including an inverter INV that inverts the input signal IN, a constant current source CC3 and an N-channel MOS transistor M3 connected in series between a power supply voltage terminal and a ground point, and a capacitor C1 connected between a connection node N1 between the transistor M3 and the constant current source CC3 and the ground point, as shown in Fig. 2(C). Note that the timing chart of the pulse signal transmission circuit when using the rising edge delay circuit 14 shown in Fig. 2(C) is almost the same as the timing chart of Fig. 5 except that the rise of the potential V1 of the node N1 is gradual, as indicated by the dotted line A in Fig. 5, and therefore is not shown.

[0028] FIG. 6 shows a second modified example of the pulse signal transmitting circuit of the above embodiment. The pulse signal transmission circuit of the second modification example has a power supply voltage of the output stage 11 different from the power supply voltage VDD of the CMOS inverter circuit 12 and the falling delay circuit 13, which is Vdd. By configuring in this way, a level shift function for outputting a signal with the potential on the high level side shifted with respect to the input signal IN can be provided to the pulse signal transmission circuit. Note that the power supply voltage Vdd of the output stage 11 can be considered as the battery voltage when applied to, for example, an in-vehicle system. In that case, VDD < Vdd, but depending on the system to be used, VDD > Vdd may also be acceptable.

[0029] Next, a second embodiment of the pulse signal transmission circuit of the present invention will be described with reference to FIGS. 7 and 8. As shown in FIG. 7, the pulse signal transmission circuit of the second embodiment is provided with a pulse adjustment circuit 15 that changes and outputs the pulse width of the input pulse signal IN instead of the falling delay circuit 13 in the first embodiment shown in FIG. 1. The pulse adjustment circuit 15 is configured to realize the function of the falling delay circuit 13 in the first embodiment by digital processing, and is composed of a logic circuit having a counter circuit, a logic gate circuit, etc. that operates with a clock signal ck having a period Ta sufficiently shorter than the period of the input pulse signal IN.

[0030] Specifically, the falling delay circuit 13 uses, for example, signals b1 to b3 having the period Tin information of the input pulse signal IN as control signals. When the period Tin is long, as shown in FIG. 8, with respect to the input pulse signal IN, the timing of falling to the low level for one period Ta of the clock signal ck is delayed. Also, when the period Tin is short, with respect to the input pulse signal IN, the timing of falling to the low level for one period Ta of the clock signal ck is advanced. In this embodiment, since the control signal b1 ~ b3 is 3 bits, the timing of falling to the low level can be adjusted in 8 steps.

[0031] Although the invention made by the present inventor has been specifically described above based on the embodiments, the present invention is not limited to the above embodiments. For example, in the description of the first embodiment, the current value I1 of the constant current source CC1 and the current value I2 of the constant current source CC2 constituting the CMOS inverter circuit 12 are the same. However, in a pulse signal transmission circuit of a second modified example equipped with a level shift function, the current value I1 of the constant current source CC1 and the current value I2 of the constant current source CC2 may be made different. Furthermore, in the above embodiment, the pulse signal transmission circuit is described as being configured as one semiconductor integrated circuit, but it may be configured as a circuit that realizes the signal transmission function of a semiconductor integrated circuit having various functions. [Explanation of symbols]

[0032] 10...pulse signal transmission circuit, 11...output stage, 12...CMOS inverter circuit, 13...falling edge delay circuit, 14...rising edge delay circuit, 15...pulse adjustment circuit, M0...output MOS transistor, IN...input pulse signal

Claims

1. A pulse signal transmission circuit comprising: an output transistor having a drain terminal connected to an output terminal; and an inverter circuit provided in a stage preceding the output transistor and generating a signal to be input to a gate terminal of the output transistor, wherein the pulse signal transmission circuit outputs an output pulse signal from the output terminal, a delay circuit for delaying either a rising edge or a falling edge of an input pulse signal inputted from an input terminal; The pulse signal delayed by the delay circuit is input to the inverter circuit, the delay circuit adjusts a delay time for delaying either the rising or falling edge of the input pulse signal so that a time (trise) required from the start of the rising edge of the input pulse signal to the end of the rising edge of the output pulse signal becomes equal to a time (tfall) required from the start of the falling edge of the input pulse signal to the end of the falling edge of the output pulse signal; the inverter circuit is a CMOS inverter circuit having a P-channel MOS transistor and an N-channel MOS transistor connected in series, a first constant current source is connected in series with the P-channel MOS transistor between a first power supply voltage terminal and an output node; a second constant current source is connected in series with the N-channel MOS transistor between the output node and a second power supply voltage terminal; a third power supply voltage terminal to which a power supply voltage of a potential different from that of the first power supply voltage terminal is supplied, and a resistance element is connected between the third power supply voltage terminal or the second power supply voltage terminal and the drain terminal of the output transistor; A pulse signal transmitting circuit comprising:

2. 2. The pulse signal transmission circuit according to claim 1, wherein a resistive element is connected between the first power supply voltage terminal or the second power supply voltage terminal and the drain terminal of the output transistor.

3. 3. The pulse signal transmission circuit according to claim 1, wherein the delay circuit has a capacitor and charging and discharging means for the capacitor, and the discharging means is configured to have the function of adjusting the delay amount by changing the current value discharging the capacitor.

4. The delay circuit a switching MOS transistor and a constant current source connected in series between a first power supply voltage terminal and a second power supply voltage terminal; a capacitance element connected between a connection node of the switching MOS transistor and the constant current source and a second power supply voltage terminal or a first power supply voltage terminal; 4. The pulse signal transmission circuit according to claim 1, wherein the pulse signal transmission circuit is configured to have:

5. A pulse signal transmission circuit comprising: an output transistor having a drain terminal connected to an output terminal; and an inverter circuit provided in a stage preceding the output transistor for generating a signal to be input to a gate terminal of the output transistor, the pulse signal transmission circuit outputting an output pulse signal from the output terminal, a delay circuit for delaying either a rising edge or a falling edge of an input pulse signal inputted from an input terminal; The pulse signal delayed by the delay circuit is input to the inverter circuit, the delay circuit adjusts a delay time for delaying either the rising or falling edge of the input pulse signal so that a time (trise) required from the start of the rising edge of the input pulse signal to the end of the rising edge of the output pulse signal becomes equal to a time (tfall) required from the start of the falling edge of the input pulse signal to the end of the falling edge of the output pulse signal; The delay circuit has a capacitor and charging and discharging means for the capacitor, and the discharging means is configured to have the function of adjusting the amount of delay by changing the current value discharging the capacitor.

6. the inverter circuit is a CMOS inverter circuit having a P-channel MOS transistor and an N-channel MOS transistor connected in series, a first constant current source is connected in series with the P-channel MOS transistor between a first power supply voltage terminal and an output node; 6. The pulse signal transmission circuit according to claim 5, wherein a second constant current source is connected in series with the N-channel MOS transistor between the output node and a second power supply voltage terminal.

7. A pulse signal transmitting circuit as described in Claim 6, characterized in that a resistive element is connected between the first power supply voltage terminal or the second power supply voltage terminal and the drain terminal of the output transistor.

8. The delay circuit a switching MOS transistor and a constant current source connected in series between a first power supply voltage terminal and a second power supply voltage terminal; a capacitance element connected between a connection node of the switching MOS transistor and the constant current source and a second power supply voltage terminal or a first power supply voltage terminal; 8. The pulse signal transmission circuit according to claim 5, wherein the pulse signal transmission circuit is configured to have:

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