Semiconductor device and manufacturing method thereof

Abstract

To improve reliability of a nonvolatile memory cell including a ferroelectric film.SOLUTION: A nonvolatile memory cell MC comprises a paraelectric film IL formed on a semiconductor substrate SUB, a ferroelectric film FE formed on the paraelectric film IL, a gate electrode GE formed on the ferroelectric film FE, a high-dielectric-constant film HK formed on the ferroelectric film FE so as to cover a side surface of the gate electrode GE, and a source region SR and a drain region DR formed on the semiconductor substrate SUB so as to sandwich the semiconductor substrate SUB located below the ferroelectric film FE. A relative dielectric constant of the high-dielectric-constant film HK is higher than a relative dielectric constant of the ferroelectric film FE.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a nonvolatile memory cell with a ferroelectric film and a manufacturing method thereof. [Background technology]

[0002] In recent years, nonvolatile memory cells using ferroelectric films such as HfZrO2 films (commonly known as HZO films) have been developed. As structures of such memory cells, a MFIS-FET (Metal Ferroelectric Insulator Semiconductor - FET) structure in which an HZO film is formed on the gate insulating film of a MIS-FET (Metal Insulator Semiconductor - Field Effect Transistor), or a MFMIS-FET (Metal Ferroelectric Metal Insulator Semiconductor - FET) structure in which a metal film is formed between the gate insulating film and the HZO film has been proposed. For example, Patent Document 1 discloses a memory cell with an MFIS-FET structure. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2019-201172 Summary of the Invention [Problem to be solved by the invention]

[0004] 1 and 2 show a nonvolatile memory cell having an MFIS-FET structure that has been studied by the present inventors, and is a nonvolatile memory cell in a study example. Note that Fig. 2 is an enlarged view of the vicinity of the end of the ferroelectric film FE in Fig. 1.

[0005] When the nonvolatile memory cell is an n-type FET, the write and erase operations of the nonvolatile memory cell are as follows: In the write operation, a negative bias is applied to the gate electrode GE, which changes the polarization direction in the ferroelectric film FE upward, thereby increasing the threshold voltage. On the other hand, in the erase operation, a positive bias is applied to the gate electrode GE, which changes the polarization direction in the ferroelectric film FE downward, thereby decreasing the threshold voltage.

[0006] Such a nonvolatile memory cell is manufactured as follows. First, a paraelectric film IL, a metal film MF, an amorphous HZO film, and a gate electrode GE are sequentially deposited on a semiconductor substrate SUB. Next, an orthorhombic HZO film is formed by heat treating the amorphous HZO film at 600 to 800°C. Since the orthorhombic HZO film has ferroelectricity, it can be used as the ferroelectric film FE.

[0007] Next, the paraelectric film IL, the ferroelectric film FE, and the gate electrode GE are patterned using a mask pattern such as a resist pattern. Here, a plasma etching process is performed when patterning the ferroelectric film FE. Therefore, as shown in FIG. 2, the side surface of the ferroelectric film FE is exposed to plasma and remains as a characteristic fluctuation portion FEa.

[0008] The inventors of the present application have found that there is a problem in that the polarization may not change in the area where such a characteristic variation portion FEa exists. That is, if there is an area where the polarization does not change, there is a risk that it may not be possible to determine whether the nonvolatile memory cell is in a written state or an erased state during a read operation, which reduces the reliability of the nonvolatile memory cell.

[0009] In recent years, there has been a demand for fabricating nonvolatile memory cells using finer processes, such as gate lengths of 40 nm or less. Because the ferroelectric film FE is located directly below the gate electrode GE, as miniaturization advances, the proportion of the characteristic fluctuation portion FEa in the ferroelectric film FE increases. In other words, as miniaturization advances, there is a problem in that the area in which polarization does not change increases. Therefore, a technology to solve this problem is needed.

[0010] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0011] In one embodiment, the semiconductor device includes a nonvolatile memory cell, the nonvolatile memory cell including: a paraelectric film formed on a semiconductor substrate; a ferroelectric film formed on the paraelectric film; a gate electrode formed on the ferroelectric film; a high-k film formed on the ferroelectric film so as to cover side surfaces of the gate electrode; and a source region and a drain region formed in the semiconductor substrate so as to sandwich the semiconductor substrate located below the ferroelectric film, wherein the dielectric constant of the high-k film is higher than the dielectric constant of the ferroelectric film.

[0012] In one embodiment, a method for manufacturing a semiconductor device having a nonvolatile memory cell includes the steps of: (a) forming a paraelectric film on a semiconductor substrate; (b) forming a ferroelectric film on the paraelectric film; (c) forming a conductive film on the ferroelectric film; (d) patterning the conductive film to form a gate electrode; (e) forming a high-k film on the ferroelectric film to cover the gate electrode; (f) performing an anisotropic plasma etching process on the high-k film to remove a portion of the high-k film so that the high-k film remains on a side surface of the gate electrode; (g) removing the ferroelectric film exposed from the gate electrode and the high-k film after the step (f); (h) patterning the paraelectric film after the step (g); and (i) forming a source region and a drain region in the semiconductor substrate to sandwich the semiconductor substrate located below the ferroelectric film after the step (h). Here, the dielectric constant of the high-k film is higher than that of the ferroelectric film. [Effects of the Invention]

[0013] According to one embodiment, the reliability of a nonvolatile memory cell having a ferroelectric film can be improved. [Brief explanation of the drawings]

[0014] [Figure 1] 1 is a cross-sectional view showing a semiconductor device having a nonvolatile memory cell in a study example. [Figure 2] FIG. 10 is an enlarged view of a portion of a nonvolatile memory cell in the study example. [Figure 3] 1 is a plan view showing a semiconductor device having nonvolatile memory cells according to a first embodiment. [Figure 4] 1 is a cross-sectional view showing a semiconductor device having a nonvolatile memory cell according to a first embodiment. [Figure 5] 10 is a table showing applied voltages for each operation of the nonvolatile memory cell in the first embodiment. [Figure 6]1 is a graph showing the relationship between the strength of an electric field and the magnitude of polarization in a ferroelectric film. [Figure 7] 2 is an enlarged view of a part of the nonvolatile memory cell according to the first embodiment. FIG. [Figure 8] 3 is a schematic diagram for explaining the capacitance between the gate electrode and the semiconductor substrate in the first embodiment. FIG. [Figure 9] 2A to 2C are cross-sectional views illustrating a method for manufacturing the semiconductor device in the first embodiment. [Figure 10] 10 is a cross-sectional view showing the method of manufacturing the semiconductor device subsequent to FIG. 9. [Figure 11] 11A to 11C are cross-sectional views showing the method of manufacturing the semiconductor device subsequent to FIG. [Figure 12] 12 is a cross-sectional view showing the method of manufacturing the semiconductor device subsequent to FIG. 11. [Figure 13] 13 is a cross-sectional view showing the method of manufacturing the semiconductor device subsequent to FIG. 12. [Figure 14] FIG. 10 is a cross-sectional view showing a semiconductor device having a nonvolatile memory cell according to a second embodiment. [Figure 15] FIG. 10 is an equivalent circuit diagram of a nonvolatile memory cell according to the second embodiment. [Figure 16] 10A to 10C are cross-sectional views showing a method for manufacturing a semiconductor device in a second embodiment. [Figure 17] 17A to 17C are cross-sectional views showing the manufacturing method of the semiconductor device subsequent to FIG. 16. [Figure 18] 18 is a cross-sectional view showing the method of manufacturing the semiconductor device subsequent to FIG. 17. [Figure 19] 19 is a cross-sectional view showing the method of manufacturing the semiconductor device subsequent to FIG. 18. [Figure 20] 20 is a cross-sectional view showing the method of manufacturing the semiconductor device subsequent to FIG. 19. [Figure 21] 21 is a cross-sectional view showing the method of manufacturing the semiconductor device subsequent to FIG. 20. [Figure 22] 22 is a cross-sectional view showing the method of manufacturing the semiconductor device subsequent to FIG. 21. DETAILED DESCRIPTION OF THE INVENTION

[0015] Hereinafter, embodiments will be described in detail with reference to the drawings. In all drawings for explaining the embodiments, components having the same functions are designated by the same reference numerals, and repeated explanations thereof will be omitted. In the following embodiments, explanations of the same or similar parts will not be repeated unless particularly necessary.

[0016] Furthermore, the X, Y, and Z directions described herein intersect and are perpendicular to one another. In this application, the Z direction is described as the longitudinal, vertical, height, or thickness direction of a structure. The expression "planar view" described herein means that the plane formed by the X and Y directions is viewed from the Z direction. Furthermore, with regard to the numerical ranges described herein, for example, an expression such as "1 to 3 nm" means "1 nm or more and 3 nm or less."

[0017] (Embodiment 1) <Configuration of Nonvolatile Memory Cell in Semiconductor Device> An overview of the semiconductor device in the first embodiment will be described below with reference to Figures 3 and 4. Figure 3 is a plan view showing a semiconductor device having nonvolatile memory cells MC. Figure 4 is a cross-sectional view taken along line AA in Figure 3.

[0018] The semiconductor device is, for example, a semiconductor chip, and includes a plurality of nonvolatile memory cells MC, etc. The nonvolatile memory cells MC are ferroelectric memory cells with an MFIS-FET structure, and are n-type FETs.

[0019] As shown in FIGS. 3 and 4, the nonvolatile memory cell MC includes a semiconductor substrate SUB, a paraelectric film IL, a ferroelectric film FE, a gate electrode GE, a high dielectric constant film HK, a sidewall spacer SW, a source region SR, and a drain region DR.

[0020] The semiconductor substrate SUB is made of p-type single crystal silicon having a resistivity of, for example, about 1 to 10 Ωcm. The paraelectric film IL is formed on the semiconductor substrate SUB and is, for example, a silicon oxide film. The thickness of the paraelectric film IL is, for example, 1 to 5 nm.

[0021] The ferroelectric film FE is formed on the paraelectric film IL and is, for example, an orthorhombic HfO2 film or an orthorhombic HfO2 film doped with at least one of zirconium (Zr), silicon (Si), nitrogen (N), carbon (C), and aluminum (Al). More preferably, the ferroelectric film FE is an orthorhombic HfZrO2 film. The thickness of the ferroelectric film FE is, for example, 4 to 16 nm, more preferably 10 nm. The relative dielectric constant of the ferroelectric film FE is about 30.

[0022] The gate electrode GE is formed on the ferroelectric film FE and is, for example, an n-type polycrystalline silicon film. The gate electrode GE may be a metal film such as a titanium nitride film, an aluminum film, or a tungsten film, or may be a laminated film in which these metal films are appropriately laminated. The thickness of the gate electrode GE is, for example, 50 to 200 nm. The gate length of the nonvolatile memory cell MC is 40 nm or less. The gate length is the length of the gate electrode GE in the direction from the drain region DR to the source region SR (X direction).

[0023] Sidewall spacers SW are formed on the semiconductor substrate SUB so as to cover the side surfaces of the gate electrode GE, the ferroelectric film FE, and the paraelectric film IL. The sidewall spacers SW are made of, for example, a silicon oxide film or a silicon nitride film. The sidewall spacers SW may also be a laminated film of a silicon oxide film and a silicon nitride film.

[0024] In the nonvolatile memory cell MC, the semiconductor substrate SUB located directly below the ferroelectric film FE serves as a channel region. A source region SR and a drain region DR are formed in the semiconductor substrate SUB so as to sandwich this channel region. The source region SR and the drain region DR are impurity regions into which impurities exhibiting n-type conductivity, such as arsenic (As) or phosphorus (P), have been introduced.

[0025] In the first embodiment, a high-dielectric-constant film HK is formed on the ferroelectric film FE so as to cover the side surface of the gate electrode GE. The high-dielectric-constant film HK is located between the side surface of the gate electrode GE and the sidewall spacer SW. The relative dielectric constant of the high-dielectric-constant film HK is higher than that of the ferroelectric film FE, and is about 80. Such a high-dielectric-constant film HK is, for example, a titanium oxide film (TiO2 film). The length of the high-dielectric-constant film HK in the gate length direction (X direction) is, for example, 10 to 20 nm.

[0026] In the first embodiment, the area of ​​the ferroelectric film FE and the area of ​​the paraelectric film IL are larger than the area of ​​the gate electrode GE in plan view because the high dielectric constant film HK is formed on the side surface of the gate electrode GE. In other words, the length of the ferroelectric film FE and the length of the paraelectric film IL in the gate length direction (X direction) are longer than the length of the gate electrode GE.

[0027] <Operations of nonvolatile memory cell MC> The write operation, erase operation and read operation of the nonvolatile memory cell MC will be described below with reference to FIGS.

[0028] 5 shows the applied voltages during each operation of the nonvolatile memory cell MC. A gate voltage Vg is applied to the gate electrode GE, a source voltage Vs is applied to the source region SR, a drain voltage Vd is applied to the drain region DR, and a back gate voltage Vsub is applied to the semiconductor substrate SUB.

[0029] Figure 6 is a graph showing the strength of the electric field received by the ferroelectric film FE and the magnitude of polarization retained in the ferroelectric film FE when each voltage shown in Figure 5 is applied to the nonvolatile memory cell MC during the write operation and erase operation.

[0030] The following characteristics are known for ferroelectric film FE. First, its relative permittivity changes significantly depending on the external electric field (E). Second, polarization (P) is maintained in the ferroelectric film FE even when the external electric field (E) becomes zero. Furthermore, the magnitude of polarization (P) varies depending on the way (history) the external electric field (E) changes. These characteristics are shown in a graph called a hysteresis loop, as shown in Figure 6.

[0031] First, as shown by the dashed line in Figure 6, a positive external electric field is applied to the ferroelectric film FE when no external electric field (E) is applied and the magnitude of polarization (P) is zero. As the external electric field is gradually increased from zero, the positive polarization increases slightly at first and then begins to increase rapidly at a certain electric field value. As the positive external electric field is further increased, the positive polarization saturates at a certain value. After confirming that the positive polarization is tending to saturate, the positive external electric field is weakened until the external electric field reaches zero. Then, the positive polarization drops slightly from its maximum value and remains as positive remnant polarization (Pr). This remnant polarization (Pr) is the magnitude of the polarization retained in the ferroelectric film FE.

[0032] Once the ferroelectric film FE has retained its polarization, it no longer follows the path indicated by the dashed line in Figure 6, but instead follows the hysteresis loop indicated by the solid line in Figure 6. In other words, the following changes in polarization occur in the ferroelectric film FE.

[0033] When a negative external electric field is applied from a state in which the external electric field (E) is zero and a positive remanent polarization (Pr) is maintained in the ferroelectric film FE, the polarization begins to decrease. The polarization hardly decreases at first, but begins to decrease rapidly at a certain electric field value. When the negative external electric field reaches a certain strength (coercive field -Ec), the polarization becomes zero. If the negative external electric field is further strengthened, the negative polarization saturates at a certain value. After confirming that the negative polarization is tending to saturate, the negative external electric field is weakened until the external electric field becomes zero. Then, the negative polarization rises slightly from its maximum value and remains as a negative remanent polarization (-Pr). This remanent polarization (-Pr) is the magnitude of the polarization maintained in the ferroelectric film FE.

[0034] When a positive external electric field is applied from a state in which the external electric field (E) is zero and a negative remnant polarization (-Pr) is maintained in the ferroelectric film FE, the polarization begins to increase. The polarization barely increases at first, but begins to increase rapidly at a certain electric field value. When the positive external electric field reaches a certain strength (coercive field Ec), the polarization becomes zero. If the positive external electric field is further strengthened, the positive polarization saturates at a certain value. After confirming that the positive polarization is tending to saturate, the positive external electric field is weakened until the external electric field becomes zero. Then, the positive polarization drops slightly from its maximum value and remains as a positive remnant polarization (Pr). This remnant polarization (Pr) also becomes the magnitude of the polarization maintained in the ferroelectric film FE.

[0035] Here, the case where the magnitude of polarization of the ferroelectric film FE is remanent polarization (Pr) is referred to as the "erased state," and the case where the magnitude of polarization of the ferroelectric film FE is remanent polarization (-Pr) is referred to as the "written state." The threshold voltage of the nonvolatile memory cell MC in the written state is higher than the threshold voltage of the nonvolatile memory cell MC in the erased state. Note that when the magnitude of polarization is remanent polarization (Pr), it can also be said that the direction of polarization is upward, and when the magnitude of polarization is remanent polarization (-Pr), it can also be said that the direction of polarization is downward.

[0036] The voltage applied to the gate electrode GE during a read operation is set to be smaller than the threshold voltage of the nonvolatile memory cell MC in the written state and larger than the threshold voltage of the nonvolatile memory cell MC in the erased state. As a result, no current flows in the nonvolatile memory cell MC in the written state, but a current flows in the nonvolatile memory cell MC in the erased state. In this way, the state of the nonvolatile memory cell MC is read based on the magnitude of the current flowing through the nonvolatile memory cell MC.

[0037] <Main features of the first embodiment> The main features of the first embodiment will be described below with reference to Fig. 7 and Fig. 8. Fig. 7 is an enlarged view of the vicinity of the end of the ferroelectric film FE in Fig. 4. Fig. 8 is a schematic view for explaining the capacitance between the gate electrode GE and the semiconductor substrate SUB.

[0038] 7, similarly to the study example, also in the embodiment 1, a characteristic fluctuation portion FEa is formed on the side surface of the ferroelectric film FE. As will be described in detail later, the characteristic fluctuation portion FEa in the embodiment 1 is formed by exposing the ferroelectric film FE to plasma when a plasma etching process is performed on the ferroelectric film FE using the gate electrode GE and the high dielectric constant film HK as a mask.

[0039] Since the ferroelectric film FE is patterned in this manner, in the first embodiment, the characteristic variation portion FEa is located immediately below the high dielectric constant film HK, and the upper surface of the characteristic variation portion FEa is covered by the high dielectric constant film HK. That is, while the characteristic variation portion FEa in the studied example is located immediately below the gate electrode GE, the characteristic variation portion FEa in the first embodiment is formed at a position away from the side surface of the gate electrode GE.

[0040] In the characteristic variation portion FEa, the magnitude of polarization is unlikely to change even when a predetermined voltage is applied to the gate electrode GE. The reason why the characteristic variation portion FEa is formed is presumed to be that elements contained in the etching gas used in the plasma etching process are mixed into the ferroelectric film FE as impurities. Another presumed cause is that the crystallinity of the characteristic variation portion FEa exposed to plasma becomes different from the crystallinity of the other ferroelectric film FE.

[0041] Furthermore, if the magnitude of polarization of the characteristic variation portion FEa does not change, the portion of the channel region directly below the characteristic variation portion FEa will exist as a resistance component. For example, when the nonvolatile memory cell MC is in an erased state, the channel region directly below the ferroelectric film FE is in a state where current can easily flow, but directly below the characteristic variation portion FEa, current cannot easily flow. Therefore, there is a risk that an accurate read operation cannot be performed.

[0042] Here, if a large voltage can be applied to the characteristic variation portion FEa, a large electric field can be generated directly below the characteristic variation portion FEa regardless of the magnitude of polarization of the characteristic variation portion FEa, which makes it easier for current to flow directly below the characteristic variation portion FEa, making it easier to perform an accurate read operation.

[0043] As shown in Figure 8, the capacitance between the gate electrode GE and the semiconductor substrate SUB directly below the gate electrode GE is represented by the capacitance C0 of the ferroelectric film FE. On the other hand, at a position away from the side of the gate electrode GE, the capacitance between the gate electrode GE and the semiconductor substrate SUB is represented by a combined capacitance obtained by connecting the capacitance C1 of the characteristic variation portion FEa and the capacitance C2 of the high dielectric constant film HK in series. Here, when a gate voltage Vg is applied to the gate electrode GE, the voltage V1 applied to the characteristic variation portion FEa can be calculated using the following "Equation 1."

[0044] V1={C2 / (C1+C2)}Vg ··· Formula 1

[0045] Therefore, by increasing the capacitance C2, the voltage V1 applied to the characteristic variation portion FEa can be increased. Therefore, in the first embodiment, in order to increase the capacitance C2, the relative dielectric constant (about 80) of the high dielectric constant film HK is made higher than the relative dielectric constant (about 30) of the ferroelectric film FE. Note that the relative dielectric constant of the high dielectric constant film HK is made higher than the relative dielectric constant of the silicon oxide film (about 3.9) or the relative dielectric constant of the silicon nitride film (about 7.8) that constitutes the sidewall spacer SW.

[0046] As described above, by covering the characteristic variation portion FEa with the high dielectric constant film HK, it becomes easier to perform an accurate read operation even when the magnitude of polarization of the characteristic variation portion FEa is difficult to change. That is, according to the first embodiment, the reliability of the nonvolatile memory cell MC can be improved.

[0047] <Method of manufacturing a semiconductor device> A method for manufacturing the semiconductor device according to the first embodiment will be described below with reference to FIGS.

[0048] As shown in Fig. 9, first, a semiconductor substrate SUB is prepared. Next, a paraelectric film IL is formed on the semiconductor substrate SUB by, for example, thermal oxidation or ISSG oxidation. Next, a ferroelectric film FE is formed on the paraelectric film IL by, for example, ALD. At this point, the ferroelectric film FE is in an amorphous state.

[0049] Next, a conductive film CF is formed on the ferroelectric film FE by, for example, CVD or sputtering. The conductive film CF is, for example, a polycrystalline silicon film. The conductive film CF may be a metal film such as a titanium nitride film, an aluminum film, or a tungsten film, or may be a laminated film in which these metal films are appropriately laminated. Next, the amorphous ferroelectric film FE is subjected to a heat treatment at 600 to 800°C to crystallize the ferroelectric film FE. As a result, the ferroelectric film FE is formed as an orthorhombic crystal.

[0050] Next, as shown in FIG. 10, a resist pattern RP1 is formed on the conductive film CF. Next, using the resist pattern RP1 as a mask, an anisotropic plasma etching process is performed on the conductive film CF. The conductive film CF is patterned to form a gate electrode GE. Thereafter, the resist pattern RP1 is removed by ashing.

[0051] Next, as shown in FIG. 11, a high dielectric constant film HK is formed on the ferroelectric film FE by, for example, the CVD method or the ALD method so as to cover the gate electrode GE.

[0052] 12, an anisotropic plasma etching process is performed on the high-k dielectric film HK to remove a portion of the high-k dielectric film HK so that the high-k dielectric film HK remains on the side surfaces of the gate electrode GE. At this point, the length of the high-k dielectric film HK in the gate length direction (X direction) is, for example, 10 to 20 nm.

[0053] Next, as shown in FIG. 13, an anisotropic plasma etching process is performed on the ferroelectric film FE using the gate electrode GE and the high-dielectric-constant film HK as a mask. This plasma etching process is performed using an etching gas such as a mixed gas containing CF4 and Ar or a mixed gas containing Cl2 and HBr. This removes the ferroelectric film FE exposed from the gate electrode GE and the high-dielectric-constant film HK. At this point, since the vicinity of the side surface of the ferroelectric film FE has been exposed to plasma, a characteristic fluctuation portion FEa as described in FIG. 7 is formed in the ferroelectric film FE located directly below the high-dielectric-constant film HK.

[0054] Next, the paraelectric film IL is patterned. For example, the paraelectric film IL exposed from the ferroelectric film FE is removed by wet etching using an aqueous solution containing hydrofluoric acid. Through these steps, the areas of the ferroelectric film FE and the paraelectric film IL become larger than the area of ​​the gate electrode GE in plan view.

[0055] Thereafter, the nonvolatile memory cell MC shown in FIG. 4 is formed through the following manufacturing steps.

[0056] First, an insulating film such as a silicon oxide film or a silicon nitride film is formed on the semiconductor substrate SUB by, for example, a CVD method so as to cover the gate electrode GE, the high-dielectric film HK, the ferroelectric film FE, and the paraelectric film IL. Next, an anisotropic plasma etching process is performed on the insulating film to remove a portion of the insulating film so that the insulating film remains on the side surfaces of the gate electrode GE, the ferroelectric film FE, and the paraelectric film IL via the high-dielectric film HK. The insulating film thus left becomes the sidewall spacer SW.

[0057] Next, impurities exhibiting n-type conductivity, such as arsenic (As) or phosphorus (P), are introduced into the semiconductor substrate SUB by photolithography and ion implantation. As a result, a source region SR and a drain region DR are formed in the semiconductor substrate SUB, sandwiching the semiconductor substrate SUB located under the ferroelectric film FE. The semiconductor substrate SUB is then subjected to a heat treatment to diffuse and activate the impurities contained in the source region SR and the drain region DR. Thereafter, although not shown, the nonvolatile memory cell MC is covered with an interlayer insulating film, and plugs reaching the gate electrode GE, the source region SR, and the drain region DR are formed in the interlayer insulating film.

[0058] Although not shown, a gate-last process may be used when the gate electrode GE is formed using a metal film instead of a polycrystalline silicon film. In this case, in the process shown in FIG. 9, a laminated film of a metal film such as a titanium nitride film and a polycrystalline silicon film is formed as the conductive film CF on the ferroelectric film FE. After covering the nonvolatile memory cell MC with an interlayer insulating film, the upper surface of the polycrystalline silicon film is exposed by polishing using the CMP method. An opening is formed by removing the polycrystalline silicon film, exposing the metal film (titanium nitride film). A metal film such as an aluminum film or a tungsten film is formed on the titanium nitride film so as to fill the opening. In this way, a laminated film made of multiple metal films can be used as the gate electrode GE.

[0059] (Embodiment 2) The semiconductor device according to the second embodiment will be described below with reference to Figures 14 and 15. In the following description, differences from the first embodiment will be mainly described, and descriptions of points that overlap with the first embodiment will be omitted.

[0060] The nonvolatile memory cell MC of the first embodiment is a ferroelectric memory cell with an MFIS-FET structure. The nonvolatile memory cell MC of the second embodiment is a ferroelectric memory cell with an MFMIS-FET structure. Therefore, as shown in FIG. 14, a metal film MF is formed between the ferroelectric film FE and the paraelectric film IL. The metal film MF is made of a metal material such as a titanium nitride film. The thickness of the metal film MF is, for example, 3 to 10 nm.

[0061] 15, during a write operation and an erase operation of the nonvolatile memory cell MC, a gate voltage Vg is applied to the gate electrode GE, and the gate voltage Vg is divided into a gate voltage Vg_FE and a gate voltage Vg_IL in the ferroelectric film FE and the paraelectric film IL. In order to apply a higher voltage to the ferroelectric film FE, it is effective to make the capacitance of the ferroelectric film FE relatively small and the capacitance of the paraelectric film IL relatively large.

[0062] One effective way to achieve this is to change the area ratio between the gate electrode GE and the metal film MF. Therefore, in the second embodiment, the area of ​​the paraelectric film IL and the area of ​​the metal film MF are made larger than the area of ​​the ferroelectric film FE and the area of ​​the gate electrode GE in a plan view. In other words, in the gate length direction (X direction), the length of the ferroelectric film FE and the length of the gate electrode GE are made longer than the length of the paraelectric film IL and the length of the metal film MF. That is, the contact area between the ferroelectric film FE and the metal film MF is made smaller, and the contact area between the paraelectric film IL and the metal film MF is made larger.

[0063] In the second embodiment, a high-dielectric-constant film HK is also formed on the ferroelectric film FE so as to cover the side surfaces of the gate electrode GE. Therefore, since the high-dielectric-constant film HK is formed on the side surfaces of the gate electrode GE, the area of ​​the ferroelectric film FE is larger than the area of ​​the gate electrode GE in plan view. In other words, the length of the ferroelectric film FE in the gate length direction (X direction) is longer than the length of the gate electrode GE.

[0064] An insulating film IF1 is formed between the high-dielectric-constant film HK and the sidewall spacer SW. The insulating film IF1 is, for example, a silicon oxide film.

[0065] The metal film MF is electrically insulated from the gate electrode GE and the semiconductor substrate SUB, and is in a floating state during the write operation, erase operation, and read operation of the nonvolatile memory cell MC.

[0066] The metal film MF does not have to be in a floating state. Although not shown, for example, a lead-out portion exposed from the gate electrode GE and the ferroelectric film FE may be provided in a part of the metal film MF, and a plug different from the plug connected to the gate electrode GE may be provided in this lead-out portion. This allows the gate voltage Vg to be applied to the gate electrode GE and a voltage different from the gate voltage Vg to be applied to the metal film MF during write and erase operations of the nonvolatile memory cell MC.

[0067] In this case, in the write and erase operations, a voltage (-Vg) having the opposite polarity to the gate voltage Vg is applied to the metal film MF. In the read operation, the same voltage as the gate voltage Vg is applied to the metal film MF. This allows the write, erase, and read operations of the nonvolatile memory cell MC to be performed. This method allows the voltages applied to the gate electrode GE and the metal film MF to be controlled independently, thereby improving the controllability of the nonvolatile memory cell MC. In other words, since the division of the gate voltage Vg into the gate voltage Vg_IL in the paraelectric film IL can be reduced, a higher voltage can be applied to the ferroelectric film FE.

[0068] In the second embodiment, as in the first embodiment, the ferroelectric film FE has a characteristic variation portion FEa formed therein as described in FIG. 7. However, by covering the characteristic variation portion FEa with the high dielectric constant film HK, it becomes easier to perform an accurate read operation even when the magnitude of polarization of the characteristic variation portion FEa is difficult to change. That is, in the second embodiment as well, the reliability of the nonvolatile memory cell MC can be improved.

[0069] <Method of Manufacturing Semiconductor Device in Second Embodiment> A method for manufacturing the semiconductor device according to the second embodiment will be described below with reference to FIGS.

[0070] As shown in FIG. 16, first, a semiconductor substrate SUB is prepared. Next, a paraelectric film IL, a ferroelectric film FE, and a conductive film CF are sequentially formed on the semiconductor substrate SUB in the same manner as in the first embodiment. In the second embodiment, a step of forming a metal film MF on the paraelectric film IL is performed between the step of forming the paraelectric film IL and the step of forming the ferroelectric film FE. The metal film MF is formed by, for example, a CVD method or a sputtering method.

[0071] 17, a resist pattern RP1 is formed on the conductive film CF, and the conductive film CF is patterned in the same manner as in Embodiment 1 to form a gate electrode GE. Thereafter, the resist pattern RP1 is removed by ashing.

[0072] Next, as shown in FIG. 18, a high dielectric constant film HK is formed on the ferroelectric film FE so as to cover the gate electrode GE by the same method as in the first embodiment.

[0073] Next, as shown in FIG. 19, an anisotropic plasma etching process is performed on the high dielectric constant film HK to remove a part of the high dielectric constant film HK so that the high dielectric constant film HK is left on the side surfaces of the gate electrode GE.

[0074] 20, an anisotropic plasma etching process is performed on the ferroelectric film FE using the gate electrode GE and the high dielectric constant film HK as a mask. As a result, the ferroelectric film FE exposed from the gate electrode GE and the high dielectric constant film HK is removed. As a result of this process, the area of ​​the ferroelectric film FE becomes larger than the area of ​​the gate electrode GE in plan view.

[0075] Next, as shown in FIG. 21, an insulating film IF1 is formed on the metal film MF by, for example, the CVD method so as to cover the gate electrode GE, the high dielectric constant film HK, and the ferroelectric film FE.

[0076] 22, an anisotropic plasma etching process is performed on the insulating film IF1 to remove a part of the insulating film IF1 so that the insulating film IF1 is left on the side surfaces of the ferroelectric film FE. At this point, the length of the insulating film IF1 in the gate length direction (X direction) is, for example, 15 to 25 nm.

[0077] Next, the metal film MF is patterned. Using the gate electrode GE, the high-dielectric-constant film HK, and the insulating film IF1 as a mask, the ferroelectric film FE is subjected to an anisotropic plasma etching process. As a result, the metal film MF exposed from the gate electrode GE, the high-dielectric-constant film HK, and the insulating film IF1 is removed.

[0078] Next, the paraelectric film IL is patterned. Using the gate electrode GE, the high-dielectric film HK, and the insulating film IF1 as a mask, the paraelectric film IL is subjected to a wet etching process using, for example, an aqueous solution containing hydrofluoric acid. As a result, the paraelectric film IL exposed from the gate electrode GE, the high-dielectric film HK, and the insulating film IF1 is removed. Through these steps, the areas of the metal film MF and the paraelectric film IL become larger than the areas of the ferroelectric film FE and the gate electrode GE in plan view.

[0079] Thereafter, sidewall spacers SW, source regions SR and drain regions DR are formed in the same manner as in the first embodiment, thereby forming the nonvolatile memory cells MC shown in FIG.

[0080] When the gate electrode GE is formed of a metal film instead of a polycrystalline silicon film, a gate-last process may be employed as in the first embodiment.

[0081] The present invention has been specifically described above based on the above embodiment, but the present invention is not limited to the above embodiment and can be modified in various ways without departing from the spirit of the present invention. [Explanation of symbols]

[0082] DR drain region FE ferroelectric film FEa characteristic fluctuation part GE gate electrode HK high dielectric constant film IF1 insulating film IL paraelectric film MC nonvolatile memory cell MF metal film RP1 resist pattern SR Source Region SUB Semiconductor substrate SW Sidewall Spacer

Claims

1. A semiconductor device having a nonvolatile memory cell, The nonvolatile memory cell a paraelectric film formed on a semiconductor substrate; a ferroelectric film formed on the paraelectric film; a gate electrode formed on the ferroelectric film; a high dielectric constant film formed on the ferroelectric film so as to cover a side surface of the gate electrode; a source region and a drain region formed in the semiconductor substrate so as to sandwich the semiconductor substrate located under the ferroelectric film; Equipped with the high-dielectric-constant film has a higher dielectric constant than the ferroelectric film; a metal film is formed between the ferroelectric film and the paraelectric film; an area of ​​the ferroelectric film is larger than an area of ​​the gate electrode in a plan view; In a plan view, the area of ​​the metal film and the area of ​​the paraelectric film are larger than the area of ​​the ferroelectric film.

2. 2. The semiconductor device according to claim 1, In a plan view, the area of ​​the ferroelectric film is larger than the area of ​​the gate electrode.

3. 2. The semiconductor device according to claim 1, The ferroelectric film is made of orthorhombic HfO ２ orthorhombic HfO film doped with at least one of Zr, Si, N, C and Al. ２ The semiconductor device is a film.

4. 4. The semiconductor device according to claim 3, The semiconductor device, wherein the high dielectric constant film is a titanium oxide film.

5. A method of manufacturing a semiconductor device having a nonvolatile memory cell, comprising: (a) forming a paraelectric film on a semiconductor substrate; (b) forming a metal film on the paraelectric film; (c) forming a ferroelectric film on the metal film; (d) forming a conductive film on the ferroelectric film; (e) patterning the conductive film to form a gate electrode; (f) forming a high dielectric constant film on the ferroelectric film so as to cover the gate electrode; (g) performing an anisotropic plasma etching process on the high-k dielectric film to remove a portion of the high-k dielectric film so that the high-k dielectric film remains on the side surfaces of the gate electrode; (h) after the step (g), removing the ferroelectric film exposed from the gate electrode and the high dielectric constant film; (i) after the step (h), forming a first insulating film on the metal film so as to cover the gate electrode, the high dielectric constant film, and the ferroelectric film; (j) after the step (i), performing an anisotropic plasma etching process on the first insulating film to remove a part of the first insulating film so that the first insulating film is left on a side surface of the ferroelectric film; (k) after the step (j), a step of patterning the metal film; (l) after the step (k), a step of patterning the paraelectric film; (m) after the step (l), forming a source region and a drain region in the semiconductor substrate so as to sandwich the semiconductor substrate located under the ferroelectric film; Equipped with the high-dielectric-constant film has a higher dielectric constant than the ferroelectric film; In the step (h), an anisotropic plasma etching process is performed on the ferroelectric film using the gate electrode and the high dielectric constant film as a mask; an area of ​​the ferroelectric film is larger than an area of ​​the gate electrode in a plan view; In the steps (k) and (l), the paraelectric film and the metal film are patterned using the gate electrode, the high dielectric constant film, and the first insulating film as masks; an area of ​​the ferroelectric film is larger than an area of ​​the gate electrode in a plan view; a metal film and a paraelectric film each having an area larger than an area of ​​the ferroelectric film in a plan view;

6. 6. The method for manufacturing a semiconductor device according to claim 5, The ferroelectric film is made of orthorhombic HfO ２ orthorhombic HfO film doped with at least one of Zr, Si, N, C and Al. ２ A method for manufacturing a semiconductor device,

7. 7. The method for manufacturing a semiconductor device according to claim 6, The method for manufacturing a semiconductor device, wherein the high dielectric constant film is a titanium oxide film.

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