Display device and method for manufacturing same

Abstract

This display device includes a transistor provided in a first region of an amorphous substrate, and an LED provided in a second region of the amorphous substrate that is different from the first region. The transistor and the LED each include an electroconductive orientation layer, a first semiconductor layer on the electroconductive orientation layer, and a second semiconductor layer on the first semiconductor layer. The electroconductive orientation layer, the first semiconductor layer, and the second semiconductor layer of the transistor are respectively identical to the electroconductive orientation layer, the first semiconductor layer, and the second semiconductor layer of the LED. In the transistor, the first semiconductor layer is in contact with the second semiconductor layer. In the LED, a light-emitting layer is provided between the first and second semiconductor layers.

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a display device including a transistor and a light-emitting diode (LED) that utilizes a compound semiconductor. [Background technology]

[0002] Gallium nitride (GaN), a compound semiconductor, is a direct transition semiconductor with a wide band gap. Gallium nitride has already been put to practical use in light-emitting diodes (LEDs), and it is characterized by high saturated electron mobility and high breakdown voltage. In recent years, these characteristics of gallium nitride have been utilized to develop transistors for use in high-frequency power devices. Gallium nitride films for LEDs or transistors are generally formed on sapphire substrates at high temperatures of 800°C to 1000°C using MOCVD (Metal Organic Chemical Vapor Deposition) or HVPE (Hydride Vapor Phase Epitaxy).

[0003] Recently, development of so-called micro LED display devices or mini LED display devices, which incorporate tiny LED chips within the pixels of a circuit board, has been progressing as next-generation display devices. Micro LED display devices or mini LED display devices have high efficiency, high brightness, and high reliability. Such micro LED display devices or mini LED display devices are manufactured by transferring LED chips to a backplane on which transistors made of oxide semiconductors or low-temperature polysilicon are formed (see, for example, Patent Document 1). A method of forming transistors and LEDs containing gallium nitride on the same substrate has also been investigated (see, for example, Patent Document 2). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] U.S. Patent No. 8,791,474 [Patent Document 2] US Patent Application Publication No. 2020 / 0075664 Summary of the Invention [Problem to be solved by the invention]

[0005] The manufacturing method of micro LED displays by transferring LED chips is expensive, making it difficult to manufacture micro LED displays inexpensively. Fabricating gallium nitride transistors along with LEDs on a large-area substrate, such as an amorphous glass substrate, would reduce manufacturing costs. However, as mentioned above, gallium nitride films are formed on sapphire substrates at high temperatures, making it difficult to fabricate gallium nitride transistors and LEDs directly on amorphous glass substrates.

[0006] In view of the above problems, one object of one embodiment of the present invention is to provide a display device including a transistor and an LED provided directly on an amorphous substrate. [Means for solving the problem]

[0007] A display device according to one embodiment of the present invention includes a transistor provided in a first region of a non-amorphous substrate and an LED provided in a second region different from the first region of the amorphous substrate, wherein each of the transistor and the LED includes a conductive alignment layer, a first semiconductor layer on the conductive alignment layer, and a second semiconductor layer on the first semiconductor layer, and the conductive alignment layer, first semiconductor layer, and second semiconductor layer of the transistor are the same layers as the conductive alignment layer, first semiconductor layer, and second semiconductor layer of the LED, respectively, and in the transistor, the first semiconductor layer is in contact with the second semiconductor layer, and in the LED, a light-emitting layer is provided between the first semiconductor layer and the second semiconductor layer.

[0008] In addition, a method for manufacturing a display device according to one embodiment of the present invention includes forming a conductive alignment film on an amorphous substrate, forming a first semiconductor film on the conductive alignment film, forming a gate electrode in a first region of the amorphous substrate, forming a light-emitting film in a second region of the amorphous substrate different from the first region, forming a second semiconductor film on the gate electrode and the light-emitting film, patterning the second semiconductor film to separate the first region from the second region, forming a transistor in the first region, and forming an LED in the second region.

[0009] In addition, a method for manufacturing a display device according to one embodiment of the present invention includes forming a conductive alignment film on an amorphous substrate and patterning the conductive alignment film to form a conductive alignment layer in each of a first region and a second region different from the first region of the amorphous substrate; forming a first semiconductor film on the conductive alignment layer and patterning the first semiconductor film to form a first semiconductor layer on the conductive alignment layer in each of the first region and the second region; forming a light-emitting layer on the first semiconductor layer in the second region; forming a second semiconductor film on the first semiconductor layer in the first region and on the light-emitting layer in the second region; and patterning the second semiconductor film to form a second semiconductor layer on each of the first semiconductor layer in the first region and the light-emitting layer in the second region; and forming a gate electrode layer on the second semiconductor layer in the second region. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a schematic diagram illustrating an overview of a display device according to an embodiment of the present invention. [Figure 2] 1 is a circuit diagram showing a configuration of a pixel circuit of a pixel of a display device according to one embodiment of the present invention. [Figure 3] 1 is a schematic cross-sectional view showing the configuration of a transistor formation region and an LED formation region of a display device according to one embodiment of the present invention. [Figure 4A] 3A to 3C are schematic cross-sectional views showing a method for manufacturing a transistor formation region and an LED formation region of a display device according to one embodiment of the present invention. [Figure 4B]3A to 3C are schematic cross-sectional views illustrating a method for fabricating a transistor formation region and an LED formation region of a display device according to one embodiment of the present invention. [Figure 4C] 3A to 3C are schematic cross-sectional views showing a method for manufacturing a transistor formation region and an LED formation region of a display device according to one embodiment of the present invention. [Figure 4D] 3A to 3C are schematic cross-sectional views illustrating a method for fabricating a transistor formation region and an LED formation region of a display device according to one embodiment of the present invention. [Figure 4E] 3A to 3C are schematic cross-sectional views illustrating a method for fabricating a transistor formation region and an LED formation region of a display device according to one embodiment of the present invention. [Figure 4F] 3A to 3C are schematic cross-sectional views illustrating a method for fabricating a transistor formation region and an LED formation region of a display device according to one embodiment of the present invention. [Figure 4G] 3A to 3C are schematic cross-sectional views illustrating a method for fabricating a transistor formation region and an LED formation region of a display device according to one embodiment of the present invention. [Figure 4H] 3A to 3C are schematic cross-sectional views illustrating a method for fabricating a transistor formation region and an LED formation region of a display device according to one embodiment of the present invention. [Figure 5] 1 is a schematic cross-sectional view showing the configuration of a transistor formation region and an LED formation region of a display device according to one embodiment of the present invention. [Figure 6A] 3A to 3C are schematic cross-sectional views illustrating a method for fabricating a transistor formation region and an LED formation region of a display device according to one embodiment of the present invention. [Figure 6B] 3A to 3C are schematic cross-sectional views illustrating a method for fabricating a transistor formation region and an LED formation region of a display device according to one embodiment of the present invention. [Figure 6C] 3A to 3C are schematic cross-sectional views illustrating a method for fabricating a transistor formation region and an LED formation region of a display device according to one embodiment of the present invention. [Figure 6D] 3A to 3C are schematic cross-sectional views showing a method for manufacturing a transistor formation region and an LED formation region of a display device according to one embodiment of the present invention. [Figure 6E]3A to 3C are schematic cross-sectional views showing a method for manufacturing a transistor formation region and an LED formation region of a display device according to one embodiment of the present invention. [Figure 7] 1 is a schematic cross-sectional view showing the configuration of a transistor formation region and an LED formation region of a display device according to one embodiment of the present invention. [Figure 8A] 3A to 3C are schematic cross-sectional views showing a method for manufacturing a transistor formation region and an LED formation region of a display device according to one embodiment of the present invention. [Figure 8B] 3A to 3C are schematic cross-sectional views showing a method for manufacturing a transistor formation region and an LED formation region of a display device according to one embodiment of the present invention. [Figure 9] 1 is a schematic cross-sectional view showing the configuration of a transistor formation region and an LED formation region of a display device according to one embodiment of the present invention. [Figure 10] 1 is a schematic cross-sectional view showing the configuration of a transistor formation region and an LED formation region of a display device according to one embodiment of the present invention. [Figure 11] 1 is a schematic cross-sectional view showing the configuration of a transistor formation region and an LED formation region of a display device according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, each embodiment of the present invention will be described with reference to the drawings. Note that each embodiment is merely an example, and any embodiment that a person skilled in the art could easily come up with by making appropriate modifications while maintaining the gist of the invention is naturally included in the scope of the present invention. Furthermore, in order to clarify the explanation, the drawings may show the width, thickness, shape, etc. of each part schematically compared to the actual embodiment. However, the illustrated shapes are merely examples and do not limit the interpretation of the present invention.

[0012] In this specification, unless otherwise specified, expressions such as "α includes A, B, or C," "α includes any one of A, B, and C," and "α includes one selected from the group consisting of A, B, and C" do not exclude cases where α includes multiple combinations of A to C. Furthermore, these expressions do not exclude cases where α includes other elements.

[0013] In this specification, for the sake of convenience, the terms "above" or "upper" or "below" or "belower" are used. In principle, the substrate on which the structure is formed is used as the reference, and the direction from the substrate toward the structure is referred to as "above" or "upper." Conversely, the direction from the structure toward the substrate is referred to as "below" or "belower." Therefore, in the expression "structure on a substrate," the surface of the structure facing the substrate is the lower surface of the structure, and the surface opposite to that is the upper surface of the structure. Furthermore, the expression "structure on a substrate" merely describes the vertical relationship between the substrate and the structure, and other components may be disposed between the substrate and the structure. Furthermore, the terms "above" or "upper" or "below" or "belower" refer to the stacking order in a structure in which multiple layers are stacked, and do not necessarily have to be in an overlapping positional relationship in a planar view.

[0014] In this specification, the letters "first," "second," or "third" attached to each component are convenient labels used to distinguish each component, and have no other meaning unless otherwise specified.

[0015] In this specification and drawings, the same reference numeral is used to collectively represent multiple identical or similar components, and lowercase or uppercase letters may be added to distinguish between the multiple components. Furthermore, a hyphen and a natural number may be used to distinguish between multiple parts of a single component.

[0016] The following embodiments can be combined with each other unless a technical contradiction occurs.

[0017] First Embodiment A display device 10 according to one embodiment of the present invention will be described with reference to FIGS. 1 to 4H.

[0018] 1. Overview of the display device 10 FIG. 1 is a schematic diagram illustrating an overview of a display device 10 according to one embodiment of the present invention. The display device 10 includes a display unit 10a, a drive circuit unit 10b, and a terminal unit 10c provided on an amorphous substrate 500. The drive circuit unit 10b is provided outside the display unit 10a and is capable of controlling the display unit 10a. The terminal unit 10c is provided at an end of the amorphous substrate 500 and is capable of supplying signals or power to the display device 10. The terminal unit 10c is connected to, for example, a flexible printed circuit board (FPC). A driver IC or the like may be provided on the flexible printed circuit board (FPC).

[0019] The display unit 10a displays a still image or a moving image and includes a plurality of pixels 10px arranged in a matrix. Each of the plurality of pixels 10px includes a transistor formation region 100 and an LED formation region 200. A transistor and an LED are formed in the transistor formation region 100 and the LED formation region 200, respectively. A capacitive element may be formed in the transistor formation region 100.

[0020] 2 is a circuit diagram showing the configuration of a pixel circuit of a pixel 10px of a display device 10 according to one embodiment of the present invention. The pixel 10px includes a first transistor 11-1, a second transistor 11-2, an LED 12, and a capacitive element 13.

[0021] The first transistor 11-1 can function as a selection transistor. That is, the conduction state of the first transistor 11-1 is controlled by the scanning line 610. The gate, source, and drain of the first transistor 11-1 are electrically connected to the scanning line 610, the signal line 620, and the gate of the second transistor 11-2, respectively.

[0022] The second transistor 11-2 can function as a drive transistor. That is, the second transistor 11-2 controls the light emission brightness of the LED 12. The gate, source, and drain of the second transistor 11-2 are electrically connected to the source of the first transistor 11-1, the drive power line 630, and the cathode (n-type electrode) of the LED 12, respectively.

[0023] The cathode of the LED 12 is electrically connected to the drain electrode of the second transistor 11-2, and the anode of the LED 12 is electrically connected to the reference power supply line 640.

[0024] One of the electrodes of the capacitor 13 is electrically connected to the gate of the second transistor 11-2 and the drain of the first transistor 11-1, and the other electrode of the capacitor 13 is electrically connected to the drive power supply line 630.

[0025] In the display device 10, a first transistor 11-1, a second transistor 11-2, and a capacitance element 13 are formed in a transistor formation region 100, and an LED 12 is formed in an LED formation region 200.

[0026] The configuration of the pixel circuit shown in FIG. 2 is just an example, and the pixel circuit of the display device 10 is not limited to this.

[0027] 2. Configuration of the Transistor Formation Region 100 and the LED Formation Region 200 3 is a schematic cross-sectional view showing the configuration of a transistor formation region 100 and an LED formation region 200 of a display device 10 according to one embodiment of the present invention. The configuration of the first transistor 11-1 is similar to the configuration of the second transistor 11-2, and therefore, for the sake of convenience, only the second transistor 11-2 and the LED 12 are shown in FIG. 3. In the following description, the first transistor 11-1 and the second transistor 11-2 will not be distinguished from each other and will be referred to as the transistor 11.

[0028] The transistor 11 and the LED 12 are provided on an amorphous substrate 500. The amorphous substrate 500 is a support substrate for the transistor 11 and the LED 12. For example, an amorphous glass substrate can be used as the amorphous substrate 500. Furthermore, in the display device 10, a resin substrate such as a polyimide resin, an acrylic resin, a siloxane resin, or a fluororesin, or a polycrystalline substrate such as polysilicon can be used instead of the amorphous substrate 500. Although not shown, an underlayer may be provided on the amorphous substrate 500. The underlayer can prevent the diffusion of impurities from the amorphous substrate 500 or external impurities (for example, moisture or sodium (Na)). For example, silicon nitride (SiN x ) film can be used as the underlayer. x ) film and silicon nitride (SiN x ) film may also be used.

[0029] The transistor 11 includes a first conductive alignment layer 110, a first p-type semiconductor layer 120, a first n-type semiconductor layer 130, a gate insulating layer 160, a gate electrode layer 162, an insulating layer 164, a source electrode layer 166, and a drain electrode layer 168. The LED 12 includes a second conductive alignment layer 210, a second p-type semiconductor layer 220, a second n-type semiconductor layer 230, a light-emitting layer 260, and an n-type electrode layer 262. As will be described in detail later, the first conductive alignment layer 110 and the second conductive alignment layer 210 are the same layer formed by patterning a film deposited in the same process. Similarly, the first p-type semiconductor layer 120 and the second p-type semiconductor layer 220, and the first n-type semiconductor layer 130 and the second n-type semiconductor layer 230 are the same layer formed by patterning a film deposited in the same process.

[0030] In the transistor 11, a first conductive orientation layer 110 is provided on an amorphous substrate 500. A first p-type semiconductor layer 120 is provided on the first conductive orientation layer 110 and in contact with the first conductive orientation layer 110. A gate electrode layer 162 is provided on the first p-type semiconductor layer 120 with a gate insulating layer 160 interposed therebetween. An insulating layer 164 is provided to cover the gate insulating layer 160 and the gate electrode layer 162. A first n-type semiconductor layer 130 is provided on the first p-type semiconductor layer 120 and in contact with the first p-type semiconductor layer 120 and the insulating layer 164. The first n-type semiconductor layer 130 is divided into two regions by a groove provided on the insulating layer 164. A source electrode layer 166 is provided on one of the regions of the first n-type semiconductor layer 130 and in contact with the other of the regions. The drain electrode layer 168 is in contact with the other region of the first n-type semiconductor layer 130 and is provided on the other region.

[0031] In the LED 12, a second conductive orientation layer 210 is provided on an amorphous substrate 500. A second p-type semiconductor layer 220 is provided on the second conductive orientation layer 210 and in contact with the second conductive orientation layer 210. A second n-type semiconductor layer 230 is provided on the second p-type semiconductor layer 220 with a light-emitting layer 260 therebetween. An n-type electrode layer 262 is provided on the second n-type semiconductor layer 230.

[0032] The transistor 11 and the LED 12 are covered with a planarization layer 502. An opening is provided in the planarization layer 502 on the drain electrode layer 168 of the transistor 11 and on the n-type electrode layer 262 of the LED 12. A wiring layer 504 is provided on the planarization layer 502 and in the opening of the planarization layer 502. Therefore, the drain electrode layer 168 is electrically connected to the n-type electrode layer 262 via the wiring layer 504.

[0033] The first conductive orientation layer 110 can improve the crystallinity of the first p-type semiconductor layer 120 formed on the first conductive orientation layer 110. Similarly, the second conductive orientation layer 210 can improve the crystallinity of the second p-type semiconductor layer 220 formed on the second conductive orientation layer 210. Specifically, the first conductive orientation layer 110 and the second conductive orientation layer 210 can be controlled so that the first p-type semiconductor layer 120 and the second p-type semiconductor layer 220, respectively, have a c-axis orientation. Here, a layer having a c-axis orientation means that the c-axis of the crystal structure of the layer is oriented in a direction approximately perpendicular to the surface on which it is formed. As will be described in detail later, a p-type semiconductor film is formed on a conductive orientation film before the first conductive orientation layer 110 and the second conductive orientation layer 210 are formed by patterning, and the c-axis of the p-type semiconductor film is controlled to grow in the film thickness direction.

[0034] The first conductive orientation layer 110 and the second conductive orientation layer 210 can each be made of a conductive material having a hexagonal close-packed structure, a face-centered cubic structure, or a structure similar thereto. Here, a hexagonal close-packed structure or a structure similar thereto includes a crystal structure in which the c-axis is not 90° relative to the a-axis and b-axis. The first conductive orientation layer 110 and the second conductive orientation layer 210 made of a conductive material having a hexagonal close-packed structure or a structure similar thereto are oriented in the (0001) direction, i.e., the c-axis direction, relative to the amorphous substrate 500 (hereinafter referred to as the (0001) orientation of the hexagonal close-packed structure). Furthermore, the first conductive orientation layer 110 and the second conductive orientation layer 210 made of a material having a face-centered cubic structure or a structure similar thereto are oriented in the (111) direction relative to the amorphous substrate 500 (hereinafter referred to as the (111) orientation of the face-centered cubic structure). Since the first conductive orientation layer 110 and the second conductive orientation layer 210 have a (0001) orientation of a hexagonal close-packed structure or a (111) orientation of a face-centered cubic structure, crystal growth in the c-axis direction of the p-type semiconductor film formed on the first conductive orientation layer 110 and the second conductive orientation layer 210 (i.e., the conductive orientation film) is promoted.

[0035] Each of the first conductive alignment layer 110 and the second conductive alignment layer 210 has electrical conductivity. The conductive alignment film constituting the first conductive alignment layer 110 and the second conductive alignment layer 210 may be made of, for example, titanium (Ti), titanium nitride (TiN), or the like. x ), titanium oxide (TiO x ), graphene, zinc oxide (ZnO), magnesium diboride (MgB2), aluminum (Al), silver (Ag), calcium (Ca), nickel (Ni), copper (Cu), strontium (Sr), rhodium (Rh), palladium (Pd), cerium (Ce), ytterbium (Yb), iridium (Ir), platinum (Pt), gold (Au), lead (Pb), actinium (Ac), thorium (Th), BiLaTiO, SrFeO, BiFeO, BaFeO, ZnFeO, or PMnN-PZT can be used. In particular, titanium, graphene, zinc oxide, or aluminum is preferably used as the conductive alignment film. The conductive alignment film can be formed using any method (apparatus) such as sputtering or CVD.

[0036] The crystallinity of the p-type semiconductor film formed on the first conductive alignment layer 110 and the second conductive alignment layer 210 (i.e., the conductive alignment film) is affected by the surface condition of the conductive alignment film. Therefore, it is preferable that each of the first conductive alignment layer 110 and the second conductive alignment layer 210, or the conductive alignment film, has a smooth surface with few irregularities. For example, it is preferable that the arithmetic mean roughness (Ra) of the surface of each of the first conductive alignment layer 110 and the second conductive alignment layer 210, or the conductive alignment film, is smaller than 2.3 nm. It is also preferable that the root mean square roughness (Rq) of the surface of each of the first conductive alignment layer 110 and the second conductive alignment layer 210, or the conductive alignment film, is smaller than 2.9 nm. When the surface roughness of each of the first conductive orientation layer 110 and the second conductive orientation layer 210, or the conductive orientation film, satisfies the above conditions, crystal growth in the c-axis direction of the p-type semiconductor film formed on the first conductive orientation layer 110 and the second conductive orientation layer 210 (i.e., the conductive orientation film) is further promoted. Note that the film thickness of each of the first conductive orientation layer 110 and the second conductive orientation layer 210, or the conductive orientation film, is preferably 50 nm or more.

[0037] For example, a magnesium (Mg)-doped gallium nitride film can be used as the p-type semiconductor film constituting the first p-type semiconductor layer 120 and the second p-type semiconductor layer 220. As will be described in detail later, the p-type semiconductor film can be formed by sputtering. The film formation temperature for sputtering is at most about 600°C. Therefore, the display device 10 can use an amorphous substrate 500 that has lower heat resistance than a sapphire substrate.

[0038] For example, a gallium nitride film doped with silicon (Si) can be used as the n-type semiconductor film that constitutes the first n-type semiconductor layer 130 and the second n-type semiconductor layer 230. The n-type semiconductor film can also be formed by sputtering.

[0039] The gate insulating layer 160 and the insulating layer 164 are each made of, for example, silicon oxide (SiO x ) or silicon nitride (SiNx ) can be used as the gate insulating layer 160. For example, aluminum oxide (AlO x ), hafnium oxide (HfO x ), or lanthanum oxide (LaO x ) or the like can also be used. Each of the gate insulating layer 160 and the insulating layer 164 may be a single film or a stacked film.

[0040] The gate electrode layer 162, the source electrode layer 166, and the drain electrode layer 168 may each be made of a metal such as aluminum (Al), titanium (Ti), platinum (Pt), nickel (Ni), tantalum (Ta), or gold (Au), or an alloy thereof. The gate electrode layer 162, the source electrode layer 166, and the drain electrode layer 168 may each be a single film or a stacked film.

[0041] The light emitting layer 260 can emit light by recombining holes from the second p-type semiconductor layer 220 and electrons from the second n-type semiconductor layer 230. The light emitting layer 260 has a multiple quantum well (MQW) structure. For example, the light emitting layer 260 can be a laminated film in which indium gallium nitride (InGaN) films and gallium nitride films are alternately stacked.

[0042] The n-type electrode layer 262 functions as an n-type electrode that injects electrons into the second n-type semiconductor layer 230. In the LED 12, the second conductive alignment layer 210 functions as a p-type electrode that injects holes into the second p-type semiconductor layer 220. When the second conductive alignment layer 210 is non-transparent, the n-type electrode layer 262 is transparent or semi-transparent, and light emitted from the light-emitting layer 260 passes through the n-type electrode layer 262 and is emitted. In this case, the second conductive alignment layer 210 preferably reflects the light emitted from the light-emitting layer 260. When the second conductive alignment layer 210 is reflective, the light extraction efficiency of the LED 12 can be improved. When the second conductive alignment layer 210 is transparent or semi-transparent, the light emitted from the light-emitting layer 260 passes through the second conductive alignment layer 210 and is emitted. In this case, it is preferable that the n-type electrode layer 262 be able to reflect the light emitted from the light emitting layer 260. When the n-type electrode layer 262 has reflectivity, the light extraction efficiency of the LED 12 can be improved.

[0043] The n-type electrode layer 262 may be made of, for example, a metal such as silver (Ag) or indium (In), or a transparent conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), or zinc oxide (ZnO). The n-type electrode layer 262 may be a single film or a laminated film. For example, the n-type electrode layer 262 may be a laminated film including the above-mentioned metal and transparent conductive oxide.

[0044] The planarization layer 502 may be an organic insulating film such as an acrylic resin film or a polyimide resin film. The planarization layer 502 may be a single film or a laminated film. When the planarization layer 502 is a laminated film, it may be made of not only an organic insulating film but also a silicon oxide (SiO x ) film or silicon nitride (SiN x The insulating film may include an inorganic insulating film such as a .

[0045] For example, metals such as aluminum (Al), titanium (Ti), or copper (Cu), or alloys thereof, can be used for the wiring layer 504. The wiring layer 504 may be a single film or a laminated film.

[0046] 3. Method for Fabricating Transistor Formation Region 100 and LED Formation Region 200 4A to 4H are schematic cross-sectional views showing a method for fabricating the transistor formation region 100 and the LED formation region 200 of the display device 10 of the present invention.

[0047] First, as shown in Fig. 4A, a conductive alignment film 510 is formed on an amorphous substrate 500. The conductive alignment film 510 can be formed using any method (apparatus) such as sputtering or CVD.

[0048] Next, as shown in FIG. 4B, a p-type semiconductor film 520 is formed on the conductive alignment film 510. The p-type semiconductor film 520 can be formed by sputtering. Here, the formation of the p-type semiconductor film 520 by sputtering will be described. Note that, for convenience, the following description will be given assuming that the p-type semiconductor film 520 is a magnesium-doped gallium nitride film, but the p-type semiconductor film 520 is not limited to this.

[0049] An amorphous substrate 500 having a conductive alignment film 510 formed thereon is placed in a vacuum chamber, facing a magnesium-doped gallium nitride target. The gallium nitride composition ratio in the magnesium-doped gallium nitride target is preferably 0.7 to 2 (gallium to nitrogen). Nitrogen can be supplied to the vacuum chamber separately from the sputtering gas (argon, krypton, etc.). In this case, the gallium nitride composition ratio in the magnesium-doped gallium nitride target is preferably higher in gallium than in nitrogen. For example, nitrogen can be supplied using a nitrogen radical supply source. The sputtering power supply may be a DC power supply, an RF power supply, or a pulsed DC power supply.

[0050] The amorphous substrate 500 in the vacuum chamber may be heated. For example, the amorphous substrate 500 can be heated to a temperature of 400° C. or higher and lower than 600° C. This temperature is lower than the film formation temperature of MOCVD or HVPE, and can be applied to an amorphous substrate 500 that has lower heat resistance than a sapphire substrate.

[0051] After the vacuum chamber is fully evacuated, a sputtering gas is supplied, and a voltage is applied between the amorphous substrate 500 and the magnesium-doped gallium nitride target at a predetermined pressure to generate plasma, which deposits a magnesium-doped gallium nitride film.

[0052] The above describes a method for forming a p-type semiconductor film 520 by sputtering, using a magnesium-doped gallium nitride film as an example, but the sputtering configuration or conditions can be changed as appropriate. Furthermore, if a silicon-doped gallium nitride target is used instead of a magnesium-doped gallium nitride target, an n-type semiconductor film such as a silicon-doped gallium nitride film can be formed. Furthermore, if an indium gallium nitride target and a gallium nitride target are used, a laminated film in which indium gallium nitride films and gallium nitride films are alternately stacked can be formed.

[0053] Next, as shown in FIG. 4C, a laminated film in which indium gallium nitride films and gallium nitride films are alternately laminated is formed, and a multi-quantum well film 560 (light-emitting film 560) is formed in the LED formation region 200 by patterning using photolithography.

[0054] 4D, an insulating film and a metal film are formed and patterned using photolithography to form a gate insulating layer 160 and a gate electrode layer 162 in the transistor formation region 100. An insulating film covering the gate insulating layer 160 and the gate electrode layer 162 is formed and patterned using photolithography to form an insulating layer 164 in the transistor formation region 100.

[0055] Next, as shown in FIG. 4E, an n-type semiconductor film 530 is formed to cover the insulating layer 164 and the multiple quantum well film 560 and to be in contact with the p-type semiconductor film 520.

[0056] 4F, a metal film is formed and patterned using photolithography to form a source electrode layer 166 and a drain electrode layer 168 in the transistor formation region 100. Also, a metal film or a transparent conductive oxide film is formed and patterned using photolithography to form an n-type electrode film 562 in the LED formation region 200.

[0057] Next, as shown in FIG. 4G, a groove is formed by patterning using photolithography in a region of the n-type semiconductor film 530 overlapping with the gate electrode layer 162, and the n-type semiconductor film 530 is divided into a region in contact with the source electrode layer 166 and a region in contact with the drain electrode layer 168.

[0058] 4H, patterning is performed using photolithography to separate the transistor formation region 100 and the LED formation region 200. As a result, a first conductive alignment layer 110, a first p-type semiconductor layer 120, and a first n-type semiconductor layer 130 are formed in the transistor formation region 100, and a second conductive alignment layer 210, a second p-type semiconductor layer 220, a light-emitting layer 260, a second n-type semiconductor layer 230, and an n-type electrode layer 262 are formed in the LED formation region 200. In other words, a transistor 11 and an LED 12 are formed.

[0059] The first conductive alignment layer 110 and the second conductive alignment layer 210 are the same layer formed by patterning the conductive alignment film 510 formed in the process shown in Fig. 4A. The first p-type semiconductor layer 120 and the second p-type semiconductor layer 220 are the same layer formed by patterning the p-type semiconductor film 520 formed in the process shown in Fig. 4B. The first n-type semiconductor layer 130 and the second n-type semiconductor layer 230 are the same layer formed by patterning the n-type semiconductor film 530 formed in the process shown in Fig. 4E.

[0060] Finally, a planarization layer 502 is formed to cover the transistor 11 and the LED 12 and to have openings on the drain electrode layer 168 and the n-type electrode layer 262, and a wiring layer 504 is formed to electrically connect the drain electrode layer 168 and the n-type electrode layer 262. This completes the transistor formation region 100 and the LED formation region 200 of the display device 10 shown in FIG.

[0061] As described above, the display device 10 has the transistor 11 and the LED 12 directly provided on the amorphous substrate 500. Furthermore, the display device 10 has the conductive orientation layer (first conductive orientation layer 110 or second conductive orientation layer 210) of each of the transistor 11 and the LED 12, the first semiconductor layer (first p-type semiconductor layer 120 or second p-type semiconductor layer 220), and the second semiconductor layer (first n-type semiconductor layer 130 or second n-type semiconductor layer 230) of each of the transistor 11 and the LED 12, which are the same layer formed by patterning films formed in the same process. Therefore, the display device 10 can be manufactured inexpensively, reducing manufacturing costs.

[0062] Second Embodiment 5 to 6E, a display device 20 according to one embodiment of the present invention will be described. In the following, when the configuration of the display device 20 is the same as that of the display device 10, the description of the configuration of the display device 20 may be omitted.

[0063] [1. Configuration of the Transistor Formation Region 300 and the LED Formation Region 400] FIG. 5 is a schematic cross-sectional view showing the configuration of a transistor formation region 300 and an LED formation region 400 of a display device 20 according to one embodiment of the present invention.

[0064] In the display device 20, a transistor 21 and an LED 22 are provided on an amorphous substrate 500. That is, the transistor 21 is provided in a transistor formation region 300, and the LED 22 is provided in an LED formation region 400. The transistor 21 includes a first conductive alignment layer 310, a first p-type semiconductor layer 320, a first n-type semiconductor layer 330, a gate insulating layer 360, a gate electrode layer 362, a source electrode layer 366, and a drain electrode layer 368. The LED 22 includes a second conductive alignment layer 410, a second p-type semiconductor layer 420, a second n-type semiconductor layer 430, a light-emitting layer 460, and an n-type electrode layer 462. Although details will be described later, the first conductive orientation layer 310 and the second conductive orientation layer 410, the first p-type semiconductor layer 320 and the second p-type semiconductor layer 420, and the first n-type semiconductor layer 330 and the second n-type semiconductor layer 430 are each the same layer formed by patterning a film formed in the same process.

[0065] In the transistor 21, a first conductive orientation layer 310 is provided on an amorphous substrate 500. The first conductive orientation layer 310 has grooves formed therein, dividing the layer into a plurality of regions. Specifically, the first conductive orientation layer 310 is divided into three regions: a region overlapping with a gate electrode layer 362, a region overlapping with a source electrode layer 366, and a region overlapping with a drain electrode layer 368. The first p-type semiconductor layer 320 is provided on the first conductive orientation layer 310 and in contact with the first conductive orientation layer 310. The first p-type semiconductor layer 320 may be provided so as to fill the grooves in the first conductive orientation layer 310. The first n-type semiconductor layer 330 is in contact with the first conductive orientation layer 310 and the first p-type semiconductor layer 320 and is provided on the first conductive orientation layer 310 and the first p-type semiconductor layer 320. The first n-type semiconductor layer 330 is divided into two regions by a groove provided on the first p-type semiconductor layer 320. The source electrode layer 366 is in contact with one of the regions of the first n-type semiconductor layer 330 and is provided on one of the regions. The drain electrode layer 368 is in contact with the other region of the first n-type semiconductor layer 330 and is provided on the other region. The gate electrode layer 362 is provided on the first p-type semiconductor layer 320 with a gate insulating layer 360 interposed therebetween. The gate insulating layer 360 may be provided within the groove of the first n-type semiconductor layer 330 or may be provided so as to cover the groove of the first n-type semiconductor layer 330.

[0066] The configuration of the LED 22 is similar to that of the LED 12, and therefore a description of the configuration of the LED 22 will be omitted.

[0067] The transistor 21 and the LED 22 are covered with a planarization layer 502. An opening is provided in the planarization layer 502 on the drain electrode layer 368 of the transistor 21 and on the n-type electrode layer 462 of the LED 22. A wiring layer 504 is provided on the planarization layer 502 and in the opening of the planarization layer 502. Therefore, the drain electrode layer 368 is electrically connected to the n-type electrode layer 462 via the wiring layer 504.

[0068] Because the first conductive alignment layer 310 is conductive, leakage current may occur between the first conductive alignment layer 310 and the source electrode layer 366 or the drain electrode layer 368. However, in the transistor 21, the first conductive alignment layer 310 is divided into multiple regions that are insulated from each other. Therefore, in the transistor 21, leakage current between the source electrode layer 366 and the drain electrode layer 368 via the first conductive alignment layer 310 is suppressed. Furthermore, because the first conductive alignment layer 310 is divided, the parasitic capacitance generated by the first conductive alignment layer 310 can be reduced.

[0069] The number of regions into which the first conductive alignment layer 310 is divided is not limited to three. However, it is preferable that the number of regions into which the first conductive alignment layer 310 is divided be three or more so that leakage current of the gate electrode layer 362 can be suppressed as well as leakage current of the source electrode layer 366 and the drain electrode layer 368. The shape of the grooves dividing the first conductive alignment layer 310 may be a strip shape extending in one direction or a lattice shape.

[0070] 2. Method for Fabricating Transistor Formation Region 300 and LED Formation Region 400 6A to 6E are schematic cross-sectional views showing a method for fabricating the transistor formation region 300 and the LED formation region 400 of the display device 20 according to one embodiment of the present invention.

[0071] First, as shown in Figure 6A, a conductive alignment film is formed on an amorphous substrate 500 by sputtering, and then patterned using photolithography to form a first conductive alignment layer 310 and a second conductive alignment layer 410. That is, the first conductive alignment layer 310 and the second conductive alignment layer 410 are the same layer formed by patterning a conductive alignment film formed in the same process. Note that the first conductive alignment layer 310 has grooves that divide it into three regions.

[0072] 6B, a p-type semiconductor film is formed on the first conductive orientation layer 310 and the second conductive orientation layer 410, and then patterned using photolithography to form a first p-type semiconductor layer 320 on the first conductive orientation layer 310 and a second p-type semiconductor layer 420 on the second conductive orientation layer 410. In other words, the first p-type semiconductor layer 320 and the second p-type semiconductor layer 420 are the same layer formed by patterning a p-type semiconductor film formed in the same sputtering process.

[0073] Next, as shown in FIG. 6C, a laminated film in which indium gallium nitride films and gallium nitride films are alternately laminated is formed on second p-type semiconductor layer 420, and light emitting layer 460 is formed by patterning using photolithography.

[0074] Next, as shown in FIG. 6D, an n-type semiconductor film is formed by sputtering on the first conductive alignment layer 310, the first p-type semiconductor layer 320, and the light-emitting layer 460. Then, by patterning using photolithography, a first n-type semiconductor layer 330 is formed on the first conductive alignment layer 310 and the first p-type semiconductor layer 320, and a second n-type semiconductor layer 430 is formed on the light-emitting layer 460. That is, the first n-type semiconductor layer 330 and the second n-type semiconductor layer 430 are the same layer formed by patterning an n-type semiconductor film formed in the same sputtering process. Note that a groove is formed in the first n-type semiconductor layer 330 to divide it into two regions. One of the two regions of the first n-type semiconductor layer 330 is in contact with one of the three regions of the first conductive orientation layer 310, and the other of the two regions of the first n-type semiconductor layer 330 is in contact with the other one of the three regions of the first conductive orientation layer 310.

[0075] Next, as shown in FIG. 6E, an insulating film and a metal film are formed at least on the first p-type semiconductor layer 320, and then a gate insulating layer 360 and a gate electrode layer 362 are formed by photolithography patterning. A metal film is formed at least on the first n-type semiconductor layer 330, and then a source electrode layer 366 and a drain electrode layer 368 are formed by photolithography patterning. The source electrode layer 366 contacts one of the two regions of the first n-type semiconductor layer 330, and the drain electrode layer 368 contacts the other of the two regions of the first n-type semiconductor layer 330. A metal film or a transparent conductive oxide film is formed at least on the second n-type semiconductor layer 430, and then an n-type electrode layer 462 is formed by photolithography patterning. As a result, a transistor 21 is formed in the transistor formation region 300, and an LED 22 is formed in the LED formation region 400.

[0076] Finally, a planarization layer 502 is formed to cover the transistor 21 and the LED 22 and to have openings on the drain electrode layer 368 and the n-type electrode layer 462, and a wiring layer 504 is formed to electrically connect the drain electrode layer 368 and the n-type electrode layer 462. In this way, the transistor formation region 300 and the LED formation region 400 of the display device 20 shown in FIG.

[0077] As described above, the display device 20 has the transistor 21 and the LED 22 directly provided on the amorphous substrate 500. Furthermore, in the display device 20, the conductive orientation layer (first conductive orientation layer 310 or second conductive orientation layer 410), the first semiconductor layer (first p-type semiconductor layer 320 or second p-type semiconductor layer 420), and the second semiconductor layer (first n-type semiconductor layer 330 or second n-type semiconductor layer 430) of each of the transistor 21 and the LED 22 are the same layer formed by patterning films formed in the same process. Therefore, the display device 20 can be manufactured inexpensively, reducing manufacturing costs.

[0078] <Variation 1> 7 to 8B, a display device 20A according to a modified example of the second embodiment will be described. In the following, when the configuration of the display device 20A is the same as that of the display device 20, the description of the configuration of the display device 20A may be omitted.

[0079] [1. Configuration of transistor formation area 300A and LED formation area 400A] FIG. 7 is a schematic cross-sectional view showing the configuration of a transistor formation region 300A and an LED formation region 400A of a display device 20A according to one embodiment of the present invention.

[0080] In the display device 20A, a transistor 21A and an LED 22 are provided on an amorphous substrate 500. That is, the transistor 21A is provided in a transistor formation region 300A, and the LED 22A is provided in an LED formation region 400A. The transistor 21A includes a first conductive alignment layer 310A, a first n-type semiconductor layer 330A, a first p-type semiconductor layer 320A, a gate insulating layer 360, a gate electrode layer 362, a source electrode layer 366, and a drain electrode layer 368. The LED 22A includes a second conductive alignment layer 410A, a second n-type semiconductor layer 430A, a second p-type semiconductor layer 420A, a light-emitting layer 460, and a p-type electrode layer 464A. Although details will be described later, the first conductive orientation layer 310A and the second conductive orientation layer 410A, the first n-type semiconductor layer 330A and the second n-type semiconductor layer 430A, and the first p-type semiconductor layer 320A and the second p-type semiconductor layer 420A are each the same layer formed by patterning a film formed in the same process.

[0081] In the transistor 21A, a first conductive orientation layer 310A is provided on an amorphous substrate 500. The first conductive orientation layer 310A is divided into multiple regions by grooves. Specifically, the first conductive orientation layer 310A is divided into three regions: a region overlapping with a gate electrode layer 362, a region overlapping with a source electrode layer 366, and a region overlapping with a drain electrode layer 368. The first n-type semiconductor layer 330A is provided on the first conductive orientation layer 310A and in contact with the first conductive orientation layer 310A. The first n-type semiconductor layer 330A is divided into two regions by a groove provided on one of the three regions of the first conductive orientation layer 310A. The source electrode layer 366 is provided on one of the regions and in contact with the first n-type semiconductor layer 330A. The drain electrode layer 368 is in contact with the other region of the first n-type semiconductor layer 330A and is provided on the other region. The first p-type semiconductor layer 320A is in contact with the first conductive orientation layer 310A and the first n-type semiconductor layer 330A and is provided on the first conductive orientation layer 310A and the first n-type semiconductor layer 330A. Specifically, the first p-type semiconductor layer 320A is provided to cover a groove provided in the first n-type semiconductor layer 330A and is in contact with one of the three regions of the first conductive orientation layer 310A exposed by the groove. The gate electrode layer 362 is provided on the first p-type semiconductor layer 320A with the gate insulating layer 360 interposed therebetween.

[0082] In the LED 22A, a second conductive alignment layer 410A is provided on an amorphous substrate 500. A second n-type semiconductor layer 430A is provided on the second conductive alignment layer 410A and in contact with the second conductive alignment layer 410A. A second p-type semiconductor layer 420A is provided on the second n-type semiconductor layer 430A with a light-emitting layer 460 interposed therebetween. A p-type electrode layer 464A is provided on the second p-type semiconductor layer 420A.

[0083] The transistor 21A and the LED 22A are covered with a planarization layer 502A. The planarization layer 502A has openings on the drain electrode layer 368 of the transistor 21A and on the second conductive alignment layer 410A of the LED 12. The wiring layer 504A is provided on the planarization layer 502A and in the opening of the planarization layer 502A. Therefore, the drain electrode layer 368 is electrically connected to the second conductive alignment layer 410A via the wiring layer 504A.

[0084] The p-type electrode layer 464A functions as a p-type electrode that injects holes into the second p-type semiconductor layer 420A. In the LED 22A, the second conductive alignment layer 410A functions as an n-type electrode that injects electrons into the second n-type semiconductor layer 430A. When the second conductive alignment layer 410A is opaque, the p-type electrode layer 464A is transparent or semi-transparent, and light emitted from the light-emitting layer 460 passes through the p-type electrode layer 464A and is emitted. In this case, the second conductive alignment layer 410A preferably reflects light emitted from the light-emitting layer 460. When the second conductive alignment layer 410A is reflective, the light extraction efficiency of the LED 22A can be improved. When the second conductive alignment layer 410A is transparent or semi-transparent, the light emitted from the light-emitting layer 460 passes through the second conductive alignment layer 410A and is emitted. In this case, it is preferable that the p-type electrode layer 464A be able to reflect the light emitted from the light emitting layer 460. When the p-type electrode layer 464A has reflectivity, it is possible to improve the light extraction efficiency of the LED 22A.

[0085] The p-type electrode layer 464A can be made of a metal such as gold (Au) or platinum (Pt), or a transparent conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), or zinc oxide (ZnO). The p-type electrode layer 464A can be a single film or a laminated film. For example, the p-type electrode layer 464A can be a laminated film including the above-mentioned metal and transparent conductive oxide.

[0086] Because the first conductive alignment layer 310A is conductive, leakage current may occur between the first conductive alignment layer 310A and the source electrode layer 366 or the drain electrode layer 368. However, in the transistor 21A, the first conductive alignment layer 310A is divided into multiple regions that are insulated from each other. Therefore, in the transistor 21A, leakage current between the source electrode layer 366 and the drain electrode layer 368 via the first conductive alignment layer 310A is suppressed. Furthermore, because the first conductive alignment layer 310A is divided, the parasitic capacitance generated by the first conductive alignment layer 310A can be reduced.

[0087] 2. Method for Fabricating Transistor Formation Region 300A and LED Formation Region 400A 8A and 8B are schematic cross-sectional views showing a method for fabricating a transistor formation region 300A and an LED formation region 400A of a display device 20A according to one embodiment of the present invention.

[0088] As shown in Figure 8A, a conductive alignment film is formed on an amorphous substrate 500 by sputtering, and then patterned using photolithography to form a first conductive alignment layer 310A in the transistor formation region 300A and a second conductive alignment layer 410A in the LED formation region 400A. That is, the first conductive alignment layer 310A and the second conductive alignment layer 410A are the same layer formed by patterning a conductive alignment film formed in the same sputtering process. Note that the first conductive alignment layer 310A has grooves that divide it into three regions.

[0089] Furthermore, an n-type semiconductor film is formed on the first conductive orientation layer 310A and the second conductive orientation layer 410A by sputtering, and then a first n-type semiconductor layer 330A is formed on the first conductive orientation layer 310A by patterning using photolithography, and a second n-type semiconductor layer 430A is formed on the second conductive orientation layer 410A. That is, the first n-type semiconductor layer 330A and the second n-type semiconductor layer 430A are the same layer formed by patterning an n-type semiconductor film formed in the same sputtering process. Note that a groove is formed in the first n-type semiconductor layer 330A to divide it into two regions. Furthermore, the second n-type semiconductor layer 430A is formed on a portion of the second conductive orientation layer 410A so that a portion of the surface of the second conductive orientation layer 410A is exposed.

[0090] Next, as shown in FIG. 8B, a laminated film in which indium gallium nitride films and gallium nitride films are alternately laminated is formed on second n-type semiconductor layer 430A, and light emitting layer 460 is formed by patterning using photolithography.

[0091] Furthermore, a p-type semiconductor film is formed by sputtering on the first conductive alignment layer 310A, the first n-type semiconductor layer 330A, and the light-emitting layer 460, and then a first p-type semiconductor layer 320A is formed on the first conductive alignment layer 310A and the first n-type semiconductor layer 330A by patterning using photolithography, and a second p-type semiconductor layer 420A is formed on the light-emitting layer 460. That is, the first p-type semiconductor layer 320A and the second p-type semiconductor layer 420A are the same layer formed by patterning a p-type semiconductor film formed in the same sputtering process. The first p-type semiconductor layer 320A is formed so as to cover a groove formed in the first n-type semiconductor layer 330A, and is in contact with one of the three regions of the first conductive alignment layer 310A exposed by the groove.

[0092] Furthermore, an insulating film and a metal film are formed on at least the first p-type semiconductor layer 320A, and a gate insulating layer 360 and a gate electrode layer 362 are formed by patterning using photolithography. Furthermore, a metal film is formed on at least the first n-type semiconductor layer 330A, and a source electrode layer 366 and a drain electrode layer 368 are formed by patterning using photolithography. The source electrode layer 366 contacts one of the two regions of the first n-type semiconductor layer 330A, and the drain electrode layer 368 contacts the other of the two regions of the first n-type semiconductor layer 330A. Furthermore, a metal film or a transparent conductive oxide film is formed on at least the second p-type semiconductor layer 420A, and a p-type electrode layer 464A is formed by patterning using photolithography. As a result, a transistor 21A is formed in the transistor formation region 300A, and an LED 22A is formed in the LED formation region 400A.

[0093] Finally, a planarization layer 502A is formed to cover the transistor 21A and the LED 22A and to have openings on the drain electrode layer 368 and the second conductive alignment layer 410A, and a wiring layer 504A is formed to electrically connect the drain electrode layer 368 and the second conductive alignment layer 410A, thereby completing the transistor formation region 300A and the LED formation region 400A of the display device 20A shown in FIG.

[0094] As described above, the display device 20A has the transistor 21A and the LED 22A directly provided on the amorphous substrate 500. Furthermore, in the display device 20A, the conductive alignment layer (first conductive alignment layer 310A or second conductive alignment layer 410A), the first semiconductor layer (first n-type semiconductor layer 330A or second n-type semiconductor layer 430A), and the second semiconductor layer (first p-type semiconductor layer 320A or second p-type semiconductor layer 420A) of each of the transistor 21A and the LED 22A are the same layer formed by patterning films formed in the same process. Therefore, the display device 20A can be manufactured inexpensively, reducing manufacturing costs.

[0095] <Third embodiment> A display device 30 according to one embodiment of the present invention will be described with reference to Fig. 9. In the following, when the configuration of the display device 30 is the same as that of the display device 10, the description of the configuration of the display device 30 may be omitted.

[0096] FIG. 9 is a schematic cross-sectional view showing the configuration of a transistor formation region 100B and an LED formation region 200B of a display device 30 according to one embodiment of the present invention.

[0097] In the display device 30, a transistor 31 and an LED 32 are provided on an amorphous substrate 500. That is, the transistor 31 is provided in the transistor formation region 100B, and the LED 32 is provided in the LED formation region 200B. The transistor 31 includes a first insulating orientation layer 115, a first p-type semiconductor layer 120, a first n-type semiconductor layer 130, a gate insulating layer 160, a gate electrode layer 162, an insulating layer 164, a source electrode layer 166, and a drain electrode layer 168. The LED 32 includes a second insulating orientation layer 215, a second p-type semiconductor layer 220, a second n-type semiconductor layer 230, a light-emitting layer 260, an n-type electrode layer 262, and a p-type electrode layer 266B. The first insulating orientation layer 115 and the second insulating orientation layer 215 are the same layer formed by patterning a film deposited in the same sputtering process. That is, in the display device 30, a first insulating alignment layer 115 and a second insulating alignment layer 215 are provided instead of the first conductive alignment layer 110 and the second conductive alignment layer 210 of the display device 10.

[0098] The first insulating orientation layer 115 and the second insulating orientation layer 215 can each be made of a conductive material having a hexagonal close-packed structure, a face-centered cubic structure, or a structure similar thereto. The first insulating orientation layer 115 and the second insulating orientation layer 215 are not conductive. In other words, the first insulating orientation layer 115 and the second insulating orientation layer 215 are insulating. Examples of insulating orientation films that can be used to form the first insulating orientation layer 115 and the second insulating orientation layer 215 include aluminum nitride (AlN), gallium oxide (GaO), aluminum oxide (Al2O3), lithium niobate (LiNbO), BiLaTiO, SrFeO, SrFeO, BiFeO, BaFeO, ZnFeO, PMnN-PZT, and biological apatite (BAp). It is particularly preferable to use aluminum nitride (AlN) as the insulating orientation film.

[0099] As described above, the second insulating orientation layer 215 does not have conductivity and therefore does not function as a p-type electrode. Therefore, in the LED 32, the p-type electrode layer 266B is provided in a region where the second p-type semiconductor layer 220 is exposed (a region where the second p-type semiconductor layer 220 does not overlap with the second n-type semiconductor layer 230, the light-emitting layer 260, and the n-type electrode layer 262).

[0100] The p-type electrode layer 266B can be made of a metal such as gold (Au) or platinum (Pt), or a transparent conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), or zinc oxide (ZnO). The p-type electrode layer 266B can be a single film or a stacked film. For example, the p-type electrode layer 266B can be a stacked film containing the above-mentioned metal and a transparent conductive oxide. The p-type electrode layer 266B is formed, for example, on the second p-type semiconductor layer 220 exposed by etching a portion of the stacked structure of the n-type electrode layer 262, the second n-type semiconductor layer 230, and the light-emitting layer 260.

[0101] As described above, the display device 30 has the transistor 31 and the LED 32 provided directly on the amorphous substrate 500. Furthermore, in the display device 30, the insulating orientation layer (first insulating orientation layer 115 or second insulating orientation layer 215), the first semiconductor layer (first p-type semiconductor layer 120 or second p-type semiconductor layer 220), and the second semiconductor layer (first n-type semiconductor layer 130 or second n-type semiconductor layer 230) of each of the transistor 31 and the LED 32 are the same layer formed by patterning films formed in the same process. Therefore, the display device 30 can be manufactured inexpensively, and manufacturing costs are reduced.

[0102] <Variation 1> A display device 30C according to a modified example of the third embodiment will be described with reference to Fig. 10. In the following, when the configuration of the display device 30C is the same as that of the display device 30, the description of the configuration of the display device 30C may be omitted.

[0103] FIG. 10 is a schematic cross-sectional view showing the configuration of a transistor formation region 100C and an LED formation region 200C of a display device 30C according to one embodiment of the present invention.

[0104] In the display device 30C, a transistor 31C and an LED 32C are provided on an amorphous substrate 500. That is, the transistor 31C is provided in a transistor formation region 100C, and the LED 32C is provided in an LED formation region 200C. The transistor 31C includes a first conductive orientation layer 110, a first insulating orientation layer 115, a first p-type semiconductor layer 120, a first n-type semiconductor layer 130, a gate insulating layer 160, a gate electrode layer 162, an insulating layer 164, a source electrode layer 166, and a drain electrode layer 168. The LED 32 includes a second conductive orientation layer 210, a second insulating orientation layer 215, a second p-type semiconductor layer 220, a second n-type semiconductor layer 230, a light-emitting layer 260, an n-type electrode layer 262, and a p-type electrode layer 266C. The first conductive alignment layer 110 and the second conductive alignment layer 210 are the same layer formed by patterning a film formed in the same sputtering process, and the first insulating alignment layer 115 and the second insulating alignment layer 215 are the same layer formed by patterning a film formed in the same sputtering process.

[0105] In the display device 30C, a laminated structure of a conductive orientation layer (first conductive orientation layer 110 or second conductive orientation layer 210) and an insulating orientation layer (first insulating orientation layer 115 or second insulating orientation layer 215) is used as an orientation layer to control the c-axis orientation of a p-type semiconductor film formed by sputtering. The insulating orientation layer formed on the conductive orientation layer is affected to some extent by the conductive orientation layer. Therefore, when the c-axis orientation of a p-type semiconductor film formed on a single insulating orientation layer is insufficient, the properties of the insulating orientation layer can be controlled by forming an insulating orientation layer in contact with the conductive orientation layer. In other words, the laminated structure of the conductive orientation layer and the insulating orientation layer can further improve the crystallinity of the p-type semiconductor film.

[0106] As described above, the display device 30C has the transistor 31C and the LED 32C directly provided on the amorphous substrate 500. Furthermore, the display device 30C has the conductive orientation layer (first conductive orientation layer 110 or second conductive orientation layer 210), the insulating orientation layer (first insulating orientation layer 115 or second insulating orientation layer 215), the first semiconductor layer (first p-type semiconductor layer 120 or second p-type semiconductor layer 220), and the second semiconductor layer (first n-type semiconductor layer 130 or second n-type semiconductor layer 230) of each of the transistor 31C and the LED 32C, which are the same layer formed by patterning films formed in the same process. Therefore, the display device 30C can be manufactured inexpensively, reducing manufacturing costs.

[0107] <Fourth embodiment> A display device 40 according to one embodiment of the present invention will be described with reference to Fig. 11. In the following, when the configuration of the display device 40 is the same as that of the display device 20 or the display device 30, the description of the configuration of the display device 40 may be omitted.

[0108] FIG. 11 is a schematic cross-sectional view showing the configuration of a transistor formation region 300D and an LED formation region 400D of a display device 40 according to one embodiment of the present invention.

[0109] In the display device 40, a transistor 41 and an LED 42 are provided on an amorphous substrate 500. That is, the transistor 41 is provided in a transistor formation region 300D, and the LED 42 is provided in an LED formation region 400D. The transistor 41 includes a first insulating orientation layer 315, a first p-type semiconductor layer 320, a first n-type semiconductor layer 330, a gate insulating layer 360, a gate electrode layer 362, a source electrode layer 366, and a drain electrode layer 368. The LED 42 includes a second insulating orientation layer 415, a second p-type semiconductor layer 420, a second n-type semiconductor layer 430, a light-emitting layer 460, an n-type electrode layer 462, and a p-type electrode layer 466D. The first insulating orientation layer 315 and the second insulating orientation layer 415 are the same layer formed by patterning a film deposited in the same sputtering process. That is, in the display device 40, a first insulating orientation layer 315 and a second insulating orientation layer 415 are provided instead of the first conductive orientation layer 110 and the second conductive orientation layer 210 of the display device 20. The first insulating orientation layer 315, the second insulating orientation layer 415, and the p-type electrode layer 464 are similar to the first insulating orientation layer 115, the second insulating orientation layer 215, and the p-type electrode layer 266B of the display device 30, respectively, and therefore will not be described here.

[0110] As described above, the display device 40 has the transistor 41 and the LED 42 provided directly on the amorphous substrate 500. Furthermore, in the display device 40, the insulating orientation layer (first insulating orientation layer 315 or second insulating orientation layer 415), the first semiconductor layer (first p-type semiconductor layer 320 or second p-type semiconductor layer 420), and the second semiconductor layer (first n-type semiconductor layer 330 or second n-type semiconductor layer 430) of each of the transistor 41 and the LED 42 are the same layer formed by patterning films formed in the same process. Therefore, the display device 40 can be manufactured inexpensively, and manufacturing costs are reduced.

[0111] The above-described embodiments of the present invention may be combined as appropriate as long as they are not mutually inconsistent. Furthermore, even if a person skilled in the art appropriately adds or deletes components or modifies the design based on each embodiment, or adds or omits steps or modifies conditions, such combinations are included within the scope of the present invention as long as they include the gist of the present invention.

[0112] Even if there are other effects and advantages different from those brought about by the above-mentioned embodiments, if they are clear from the description in this specification or can be easily predicted by a person skilled in the art, they are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0113] 10, 20, 20A, 30, 30C, 40: display device, 10a: display section, 10b: drive circuit section, 10c: terminal section, 10px: pixel, 11, 21, 21A, 31, 31C, 41: transistor, 12, 22, 22A, 32, 32C, 42: LED, 13: capacitance element, 100, 100B, 100C: transistor formation region, 110: first conductive orientation layer, 115: first insulating orientation layer, 120: first p-type semiconductor layer, 130: first n-type semiconductor layer, 160: gate insulating layer, 162: gate electrode layer, 164: insulating layer, 166: source electrode layer, 168: drain electrode layer, 200, 200B, 200C: LED formation region, 210: Second conductive alignment layer, 215: Second insulating alignment layer, 220: Second p-type semiconductor layer, 230: Second n-type semiconductor layer, 260: Light-emitting layer, 262: N-type electrode layer, 266B, 266C: P-type electrode layer, 300, 300A, 300D: Transistor formation region, 310, 310A: First conductive alignment layer, 315: First insulating alignment layer, 320, 320A: First p-type semiconductor layer, 330, 330A: First n-type semiconductor layer, 360: Gate insulating layer, 362: Gate electrode layer, 366: Source electrode layer, 368: Drain electrode layer, 400, 400A, 400D: LED formation region, 410, 410A: Second conductive alignment layer, 415: Second insulating alignment layer, 420, 420A: Second p-type semiconductor layer, 430, 430A: Second n-type semiconductor layer, 460: Light-emitting layer, 462: N-type electrode layer, 464A: P-type electrode layer, 466D: P-type electrode layer, 500: Amorphous substrate, 502, 502A: Planarization layer, 504, 504A: Wiring layer, 510: Conductive alignment film, 520: P-type semiconductor film, 530: N-type semiconductor film, 560: Multiple quantum well film, 562: N-type electrode film, 610: Scanning line, 620: Signal line, 630: Drive power line, 640: Reference power line

Claims

1. a transistor provided in a first region of the amorphous substrate; an LED provided in a second region of the amorphous substrate that is different from the first region; Each of the transistor and the LED is a conductive alignment layer; a first semiconductor layer on the conductive alignment layer; a second semiconductor layer on the first semiconductor layer; the conductive alignment layer, the first semiconductor layer, and the second semiconductor layer of the transistor are the same layers as the conductive alignment layer, the first semiconductor layer, and the second semiconductor layer of the LED, respectively; In the transistor, the first semiconductor layer is in contact with the second semiconductor layer, The display device, wherein a light-emitting layer is provided between the first semiconductor layer and the second semiconductor layer in the LED.

2. the first semiconductor layer includes a p-type semiconductor; The display device according to claim 1 , wherein the second semiconductor layer includes an n-type semiconductor.

3. a drain electrode is provided on the second semiconductor layer of the transistor; an n-type electrode is provided on the second semiconductor layer of the LED; The display device according to claim 2 , wherein the drain electrode is electrically connected to the n-type electrode.

4. the first semiconductor layer includes an n-type semiconductor; The display device according to claim 1 , wherein the second semiconductor layer includes a p-type semiconductor.

5. a drain electrode is provided on the second semiconductor layer of the transistor; The display device of claim 4 , wherein the drain electrode is electrically connected to the conductive alignment layer of the LED.

6. 6. The display device according to claim 1, wherein the conductive alignment layer of the transistor is divided into a plurality of parts.

7. 7. The display device according to claim 1, wherein the first semiconductor layer contains gallium nitride.

8. The display device according to claim 1 , wherein the conductive alignment layer contains at least one selected from the group consisting of titanium, aluminum, graphene, and zinc oxide.

9. 9. The display device according to claim 1, wherein the amorphous substrate is an amorphous glass substrate.

10. A conductive alignment film is formed on an amorphous substrate, forming a first semiconductor film on the conductive alignment film; forming a gate electrode in a first region of the amorphous substrate; forming a light-emitting film in a second region of the amorphous substrate that is different from the first region; forming a second semiconductor film on the gate electrode and the light-emitting film; A method for manufacturing a display device, comprising: patterning the first region and the second region to separate them; forming a transistor in the first region; and forming an LED in the second region.

11. A conductive alignment film is formed on an amorphous substrate, forming a conductive alignment layer in each of a first region and a second region different from the first region of the amorphous substrate by patterning the conductive alignment film; depositing a first semiconductor film on the conductive alignment layer; forming a first semiconductor layer on the conductive alignment layer in each of the first region and the second region by patterning the first semiconductor film; forming a light emitting layer on the first semiconductor layer in the second region; forming a second semiconductor film on the first semiconductor layer in the first region and the light emitting layer in the second region; forming a second semiconductor layer on each of the first semiconductor layer in the first region and the light emitting layer in the second region by patterning the second semiconductor film; forming an electrode layer on the second semiconductor layer in the second region.

12. The method for manufacturing a display device according to claim 11 , wherein the conductive alignment layer in the first region is divided into a plurality of parts.

13. 13. The method for manufacturing a display device according to claim 10, wherein the first semiconductor film contains gallium nitride.

14. 14. The method for manufacturing a display device according to claim 10, wherein the conductive alignment film contains at least one selected from titanium, aluminum, graphene, and zinc oxide.

15. 15. The method for manufacturing a display device according to claim 10, wherein the amorphous substrate is an amorphous glass substrate.

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