Test equipment, electrical margin test method, and margin tester

Abstract

Systems, devices, and methods for high-speed I / O margin testing can screen large volumes of prototype and production parts to identify cases where electrical characteristics have changed enough to affect operation. The disclosed margin tester is lower cost, easier to use, and faster than traditional BERTs and oscilloscopes, and can operate on complete multi-lane I / O links under standard operating conditions with full loading and crosstalk. The margin tester evaluates the receiver electrical margin of a commonly available multi-lane high-speed I / O link of a device under test in one or both directions simultaneously. In technology-specific configurations, margin tester embodiments may be implemented as add-in card margin testers that test motherboard slots on a motherboard under test, or as a motherboard with slots for testing add-in cards.

Description

[Technical Field]

[0001] The disclosed technology relates to test and measurement systems, and more particularly to systems and methods for performing high speed electrical margin testing on electrical devices under test (DUTs). [Background technology]

[0002] Designers and manufacturers of electrical devices require test and measurement equipment and appropriate test procedures to ensure that their devices function properly. Such testing may be performed, for example, during the engineering characterization stage of a new device design to compare the device's actual electrical performance with simulated performance to ensure the device is operating as designed. Such testing may also be performed in a production manufacturing environment after the engineering design is complete to uncover manufacturing defects in each manufactured device.

[0003] Many electrical devices are designed to include high-speed I / O signal paths or buses. For example, modern personal computer (PC) motherboards, along with other types of electrical devices, often include a high-speed serial PCI Express (PCIe or PCI-e) bus, which operates in accordance with the PCI Express high-speed serial computer expansion bus standard. The PCI Express standard format specification is maintained and developed by the PCI Special Interest Group (PCI-SIG). These buses are typically used for communication between the motherboard and add-in cards / daughter cards that are inserted into PCIe connector slots or ports on the motherboard. Many electrical devices other than motherboards also use PCIe buses and connectors for high-speed I / O. PCIe Generation 4 (Gen 4 or version 4) devices can achieve a bandwidth of up to 16 gigabit transfers per second (GT / s). PCIe Generation 5 (Gen 5 or version 5) devices can achieve a bandwidth of up to 32 GT / s.

[0004] PCIe devices communicate through a logical connection called an interconnect or link. A link is a point-to-point communication channel between two PCIe ports, allowing simultaneous bidirectional traffic. At the physical level, a link consists of one or more lanes. Low-speed PCIe devices use a single-lane (x1) link, while high-speed PCIe devices, such as graphics adapters, typically use a wider, faster 16-lane (x16) link. A lane consists of two differential signaling pairs: one pair for receiving data and the other for transmitting. Thus, each lane consists of four wires or signal traces. Traditionally, the performance of PCIe device lanes is tested using a bit error rate tester (BERT), a high-speed signal generator, and an oscilloscope.

[0005] During the engineering bench testing and engineering characterization phase of printed circuit board (PCB) development, high-speed routes (such as PCIe interconnects) of board designs are simulated, i.e., a design "recipe" or reference design is followed. However, testing every sample and lane of every high-speed I / O board with bit error rate test equipment (BERT) and oscilloscopes is impractical due to cost, time, and complexity constraints. Traditional BERTs and oscilloscopes, especially for testing high-speed I / O standards like PCIe, continue to increase in cost and complexity as data rates increase. A single Tx and Rx test station for testing one PCIe lane at a time can cost over $1 million. Furthermore, these devices are difficult to use for traditional Tx and Rx testing and calibration, and require expert (PhD-level) users and a significant amount of time to ensure accurate measurements and maintain the equipment in good working order. As a result of these limitations, traditional BERTs and oscilloscopes are rarely used for high-volume electrical testing of prototype silicon, boards, PCBs, and cables, and typically not at all for production testing. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] US Patent Application Publication No. 2008 / 0192814 Summary of the Invention [Problem to be solved by the invention]

[0007] However, as data rates for I / O links increase, such as PCI Express 5.0 at 32.0 GT / s, the risk that even small or subtle issues can significantly impact the performance of these I / O links increases. It is therefore increasingly important to implement some form of testing to flag electrical performance issues on every prototype sample, port, and lane before production begins, as well as to test the electrical performance of every unit on the production line to catch production-related issues (e.g., defective parts) and prevent them from resulting in customer issues and returns. Furthermore, traditional BERTs and oscilloscopes can only test one lane at a time, meaning that these tests are performed in an environment that differs from the actual operation of these I / O links. This typically involves multi-lane links, creating environments where severe crosstalk and loading issues can occur, and traditional BERTs and oscilloscope testing cannot handle these environments, if at all. Similarly, in a manufacturing test environment, when assembling and testing multiple PCBs of a given design, BERTs and oscilloscopes are typically not used on the production line for high speed I / O testing due to cost, time and complexity constraints.

[0008] This creates a need for new types of instruments that can screen large volumes of prototype and production parts and identify when their electrical characteristics change enough to affect operation. These instruments offer the greatest value compared to traditional BERTs and oscilloscopes: they are low-cost, extremely easy to use, and extremely fast, operating on fully formed multi-lane I / O links under typical operating conditions with full loading and crosstalk. Overall, knowing the electrical margin (a statistically valid operating margin) for each high-speed I / O lane in each direction is valuable because it increases the likelihood of finding both design (e.g., for all production samples, lane by lane) and assembly (e.g., specific board / lane causes) issues across all production samples.

[0009] Some traditional solutions rely only on functional testing as a best approximation (e.g., simply inserting a "golden" or reference device and testing the link at full speed). Other companies utilize on-die electrical margining in the silicon for their boards, but this only provides one-way information, and leaves the significant task of addressing and understanding the individual variations of add-in cards chosen for the purpose, rather than calibrated and characterized like test equipment.

[0010] The present application discloses a system, device and method for high-speed input / output (I / O) margin testing to solve the above technical problems.

[0011] The components in the drawings are not necessarily to scale relative to each other. Like reference numbers designate corresponding parts throughout the several views. [Brief explanation of the drawings]

[0012] [Figure 1] FIG. 1 is a schematic block diagram illustrating an example environment in which embodiments of systems, apparatuses, and methods for high-speed input / output (I / O) margin testing according to example embodiments may be implemented. [Figure 2] FIG. 2 is a block diagram illustrating an example of a technology-specific add-in card margin tester compliant with the PCI Express high-speed serial computer expansion bus standard for margin testing PCI Express motherboard slots according to an example embodiment. [Figure 3] FIG. 3 is a block diagram illustrating an example of a motherboard margin tester having slots compliant with the PCI Express high-speed serial computer expansion bus standard for margin testing PCI Express add-in cards according to an example embodiment. [Figure 4]FIG. 4 is a diagram illustrating exemplary margin test results of a device under test (DUT) performed by a high-speed I / O margin tester, and potential assembly or production issues for the DUT identified based on the margin test results, according to an example embodiment. [Figure 5] FIG. 5 is a diagram illustrating another exemplary margin test result of a device under test (DUT) performed by a high-speed I / O margin tester and potential assembly or production issues for the DUT identified based on the margin test results, according to an example embodiment. [Figure 6] FIG. 6 is a block diagram illustrating a generic margin tester according to an exemplary embodiment, where multiple interfaces are configured to be cabled to at least one test fixture to evaluate the electrical margin of a multi-lane high-speed I / O link of a DUT in both the transmit (Tx) and receive (Rx) directions. [Figure 7] FIG. 7 is a low-level block diagram of a margin tester according to an exemplary embodiment for testing the electrical margin of a multi-lane high-speed I / O link of a DUT in both the Tx and Rx directions. [Figure 8] FIG. 8 is a block diagram of an example field programmable gate array (FPGA) configured according to an example embodiment that can be utilized in a margin tester controller to test the electrical margin of a multi-lane high-speed I / O link of a DUT in one or both of the Tx and Rx directions. [Figure 9] FIG. 9 is a block diagram of example FPGA output drive options that may be utilized by a margin tester controller to test the electrical margin of a DUT's multi-lane high-speed I / O link in the Tx direction, according to an exemplary embodiment. [Figure 10] FIG. 10 is a flow diagram of an exemplary method 1000 for margin testing a DUT according to an example embodiment. [Figure 11]FIG. 11 is a flow diagram of an exemplary method according to one example embodiment for identifying potential DUT assembly or production issues based on margin testing the electrical margin of the DUT's multi-lane high-speed I / O link in one or both of the Tx and Rx directions. [Figure 12] FIG. 12 is a flow diagram of an exemplary method for a margin tester to initiate electrical margin evaluation operations based on user selectable options according to an example embodiment. [Figure 13] FIG. 13 is a flow diagram of an exemplary method 1300 for providing a calibrated margin tester according to an example embodiment. [Figure 14] FIG. 14 is a flow diagram of an exemplary method for configuring a DUT to perform margin testing according to an example embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0013] 1 is a schematic block diagram illustrating an example environment in which systems, devices, and methods for high-speed I / O margin testing, according to example embodiments, may be implemented. In one embodiment, the illustrated margin tester 102 evaluates the electrical receiver margin of operation for one or both of the Tx and Rx directions of a multi-lane high-speed I / O link 110 of an example DUT 104. The margin tester 102 of FIG. 1 represents one or more embodiments of the margin testers disclosed herein.

[0014] The margin tester 102 may be coupled to a test station, PC, terminal, or other display device 106 that can process, replicate, or display an eye pattern display or data eye diagram 108 that represents various aspects of the multi-lane high-speed I / O link 110. In some embodiments, the test station, PC, terminal, or other display device 106 may be integrated with or be part of the margin tester 102. The eye pattern display or data eye diagram 108 is a representation of a high-speed digital signal that allows key parameters of the signal's electrical quality to be quickly visualized and determined, so that data can be used to determine statistically valid operating margins for the DUT. The eye pattern display or data eye diagram 108 is composed of a digital waveform with signal amplitude on the vertical axis and time on the horizontal axis, with portions of the waveform corresponding to each individual bit collapsed onto a single graph. By repeating this configuration for many samples of the waveform, the resulting graph represents the average statistics of the signal and resembles an eye. The eye opening corresponds to one bit period and is commonly referred to as the unit interval (UI) width of the eye pattern display or data eye diagram 108. The bit period is the horizontal opening of the eye diagram at the eye crossing point and is typically measured in picoseconds for high-speed digital signals (e.g., 200 picoseconds is used for a 5 Gbps signal). The data rate is the inverse of the bit period (1 / bit period). The bit period is commonly referred to as the unit interval (UI) when describing eye diagrams. The advantage of using UI rather than actual time on the horizontal axis is that it is normalized, allowing eye diagrams of different data rates to be easily compared. Eye width is the horizontal opening of the eye diagram. It is calculated by measuring the difference in the statistical average of the eye crossing points. Rise time is the average transition time of the upward slope of the eye diagram data. It is usually measured at the 20% and 80% or 10% and 90% levels of the slope.Fall time is the average transition time of the downward slope of the data in an eye diagram. It is usually measured at the 20% and 80% or 10% and 90% levels of the slope. Jitter is the time deviation of data bit events from ideal timing and is an important characteristic of high-speed digital data signals. To calculate jitter, the time deviation at the intersection of the rising and falling edge transitions in the eye diagram is measured. Fluctuation can be random or deterministic. A time histogram of the deviations can be analyzed to determine the amount of jitter. Peak-to-peak (pp) jitter is defined as the full width of the histogram, which means all data points are present. Root-mean-square (RMS) jitter is defined as the standard deviation of the histogram. Jitter measurement for high-speed digital signals is usually in picoseconds.

[0015] Embodiments of margin tester 102 can take at least two forms: technology-specific and general-purpose. Margin tester 102 can be used with any high-speed I / O protocol link of any link width (number of lanes) and with any form of high-speed differential signaling, including, but not limited to, non-return-to-zero (NRZ), pulse amplitude modulation 3 (PAM-3), and pulse amplitude modulation 4 (PAM-4). PCI Express is used as an example of a specific embodiment for testing, although different high-speed serial bus standards, hardware, and protocols may be used.

[0016] FIG. 2 is a block diagram illustrating an exemplary technology-specific add-in card margin tester 202 compliant with the PCI Express high-speed serial computer expansion bus standard for margin testing PCI Express motherboard slots 206 according to an example embodiment.

[0017] In one technology-specific embodiment, a margin tester embodiment is implemented as a PCI Express add-in card margin tester 202 to test PCI Express motherboard slots 206 of a motherboard under test 204. For example, the PCI Express add-in card margin tester 202 may be a PCI Express x16 CEM (card electromechanical specification) form factor add-in card. In another technology-specific embodiment, a margin tester embodiment is implemented as a motherboard with PCI Express slots to test PCI Express add-in cards (as shown in FIG. 3).

[0018] PCI Express add-in card margin tester 202 may be in the form of a standard PCI Express compliant add-in card for a particular PCI Express form factor (e.g., CEM or M.2 (formerly known as Next Generation Form Factor (NGFF)) or U.2 (formerly known as SFF-8639)). PCI Express add-in card margin tester 202 may include PCB 212 and one or more components for each lane that implement compliant PCI Express physical and logical link layers. PCI Express add-in card margin tester 202 may include multiple interfaces (e.g., connectors 208) coupled to PCB 212 and controller 210. For example, such an interface may include a plurality of connectors 208 that connect to motherboard slots 206 and a margin tester transmitter, which, under the control of controller 210, may optionally have the ability to introduce controlled noise (e.g., voltage oscillations and sinusoidal jitter) to vary the expected eye margin at the receiver of motherboard under test 204 to a particular target for timing or voltage margin without the need to run software on motherboard under test 204. Controller 210 may also be coupled to memory 214, which may store instructions and other data that controller 210 may read, use, and execute to perform the functions described herein.

[0019] Various embodiments of margin tester 102 (including technology-specific PCI Express add-in card margin tester 202, technology-specific motherboard margin tester 302, and general-purpose margin tester 602) may or may not include noise injection capabilities. For cost-conscious production testing, the lack of noise injection capabilities may be more attractive. The margin tester receiver in a compliant physical layer embodiment may include the ability to margin the link as defined in the PCI Express 4.0 / 5.0 lane margin specification, but may also include additional, more sophisticated on-die margining capabilities. In one embodiment, the margin tester receiver may measure eye margin by running a separate error detector and comparing mismatches using a data sampler. In one embodiment, the controller 210 that enables the margin tester 102 (including technology-specific PCI Express add-in card margin tester 202, technology-specific motherboard margin tester 302, and general-purpose margin tester 602) to perform the functions described herein may be implemented with a field programmable gate array (FPGA) and FPGA I / O, as shown in more detail in Figures 7 through 9. However, other combinations of configurable controller hardware, firmware, and software may also be used.

[0020] FIG. 3 is a block diagram illustrating an exemplary technology-specific motherboard margin tester 302 having slots conforming to the PCI Express high-speed serial computer expansion bus standard for margin testing PCI Express add-in cards according to an example embodiment.

[0021] Motherboard margin tester 302 is another example of a technology-specific embodiment of margin tester 102 disclosed herein and is implemented as a motherboard margin tester 302 having one or more PCI Express slots 306 for testing PCI Express add-in cards, such as PCIe x16 add-in card DUT 304 shown in FIG. 3. Motherboard margin tester 302 may have multiple interfaces (e.g., one or more PCI Express slots 306) coupled to PCB 312 and controller 210. For example, such interfaces may include one or more PCI Express slots 306 into which PCIe x16 add-in card DUT 304 may be inserted for testing. The margin tester transmitter optionally has the ability to inject controlled noise, for example, voltage oscillations and sinusoidal jitter (discussed further below with respect to FIGS. 8 and 9 ), under the control of controller 210, to vary the expected eye margin at the receiver of PCIe x16 add-in card DUT 304 to a particular target for timing or voltage margin without requiring software to be executed on PCIe x16 add-in card DUT 304. For example, controller 210 may be configured to evaluate the electrical margin of a single-lane or multi-lane high-speed I / O link by configuring at least the margin test transmitter to inject jitter to reduce the eye width opening (or implement other eye width reduction methods), where the jitter injection can be applied simultaneously to all lanes of the single-lane or multi-lane high-speed I / O link or independently to each lane of the single-lane or multi-lane high-speed I / O link.The controller 210 may also be configured to evaluate the electrical margin of a single-lane or multi-lane high-speed I / O link by configuring it to introduce a reduction in eye-height opening by introducing jitter (or implementing other eye-height reduction methods) on at least a margin test transmitter, where the jitter introduction can be selectively applied to all lanes of the single-lane or multi-lane high-speed I / O link simultaneously or independently to each lane of the single-lane or multi-lane high-speed I / O link.

[0022] Controller 210 may be coupled to memory 214, which may store instructions and other data that may be read, used, and executed by controller 210 to perform the functions described herein.

[0023] Durability and insertion cycles are important considerations for technology-specific embodiments of margin tester 102, such as technology-specific PCI Express add-in card margin tester 202 and technology-specific motherboard margin tester 302. Therefore, PCB 212 and PCB 312 may be implemented to enable margin characterization using adapters that are configured to be replaced at low cost upon wear, without replacing the rest of the margin testing unit. For example, interchangeable adapters may be coupled to one or more PCI Express slots 306 or connectors 208 and configured to wear out after a specified amount of usage. In this case, the adapters may then be replaced upon wear, without replacing the rest of PCI Express add-in card margin tester 202 or motherboard margin tester 302.

[0024] FIG. 4 is a diagram 402 according to an example embodiment showing exemplary margin test results of several DUTs performed by the high-speed I / O margin tester 102 and potential assembly or production issues of the DUTs identified based on the margin test results.

[0025] In an example embodiment, margin testing may include evaluating, by margin tester 102, the timing of eye width margin for each of a plurality of devices under test (DUTs) in one or both of the Tx and Rx directions for each high-speed input / output (I / O) lane of the DUT's multi-lane high-speed I / O link. Margin tester 102 may then detect eye width margin timing measurements for some of the DUTs that are below a predetermined threshold for different lanes across the DUTs. Potential assembly or production issues of the DUTs may then be detected (visually or automatically by margin tester 102) based on detecting eye width margin timing measurements for some of the DUTs that are below a predetermined threshold for different lanes across the DUTs.

[0026] As an example, in one embodiment, an add-in card margin tester such as the add-in card margin tester 202 shown in FIG. 2 may be used to bench test / characterize a prototype sample of a motherboard with a PCIe x8 slot. The following exemplary test procedure may be performed using the add-in card margin tester 202, measuring the eye width margin (left + right) of the E-6 timing for each lane simultaneously over a few milliseconds, relative to the slot. This example only includes time measurements for simplicity, but other embodiments may include other measurements. Each measurement in this example is performed three times, but this may be user-programmable in various embodiments. The measurements shown in FIG. 402 are performed at the margin tester receiver in addition to the motherboard DUT receiver. The measurements are performed at the motherboard DUT receiver and can be performed in two ways. The first method may utilize the margin tester's jitter (Sj) and voltage swing sweep. A second method may utilize on-die margin testing at the motherboard receiver. For example, on-die margin testing at the motherboard receiver may be performed by software on a bootable drive connected to the motherboard DUT under the control of controller 210 of add-in card margin tester 202, or by basic input / output system (BIOS) software on the motherboard DUT to support speeds. In this example, measurements are performed at 16 GT / s, but this may be changed or made user configurable.

[0027] The above example test procedure can produce the exemplary results shown in diagram 402 for the average margin at the test receiver. As shown in diagram 402, the consistently low margin for lane 2 across all five DUTs, DUT#1 through DUT#5, may be an indicator of a potential design issue. In contrast, the low margin for lane 4 of DUT#1, lane 0 of DUT#3, and lane 6 of DUT#4 may be an indicator of a potential assembly or production issue with the specific lanes on these specific DUTs.

[0028] FIG. 5 is a diagram illustrating another exemplary margin test result of a DUT performed by a high-speed I / O margin tester and potential assembly or production issues for the DUT identified based on the margin test results, according to an example embodiment.

[0029] Similar indicators of potential design or assembly issues can be seen in the example results shown in diagram 502 of Figure 5 for voltage swing and Sj average margin at the DUT receiver. As shown in diagram 502, the consistently low margin for lane 1 across all five DUTs, DUT#1 through DUT#5, can be an indicator of a potential design issue. In contrast, the low margins for lane 0 of DUT#1, lane 5 of DUT#1, and lane 7 of DUT#2 can be an indicator of a potential assembly or production issue with the specific lanes on these specific DUTs.

[0030] Further features of embodiments of the disclosed technology may include the following functions that may be performed under the control of the controller 210 (e.g., by executing instructions according to a configured FPGA or by reading from another non-transitory computer-readable storage medium): Select one or more different high-speed I / O protocols and use them to perform margin testing based on the DUT's multi-lane high-speed I / O link; Test multiple ports of the DUT using miscellaneous protocols simultaneously; Output margin variation from run to run for any number of margin test runs of the margin tester for the multi-lane high-speed I / O link; Implement fixed Tx equalization (EQ) for the DUT to test how much margin varies due to Tx equalization training; and Test the impact of receiver equalization on the margin of the DUT's multi-lane high-speed I / O link using a fixed continuous time linear equalization (CTLE) in the margin tester's receiver. Ability to use decision feedback equalization (DFE) in the margin tester receiver to test the effect of receiver equalization on the margin of the DUT's multi-lane high-speed I / O link. Ability to calculate the margin tester's expected margin based on the target channel. Ability to automatically generate debug information when low margin is detected as a result of evaluating the electrical margin of the multi-lane high-speed I / O link. Ability to switch to using a variable inter-symbol interference (ISI) signal source to find the level of inter-symbol interference (ISI) required to cause a lane in the multi-lane high-speed I / O link to fail. Ability to test each lane individually to determine the amount of margin loss due to crosstalk in the DUT's multi-lane high-speed I / O link. Ability to turn off the DFE in the margin tester receiver to evaluate margin with and without the DFE, and the amount of nonlinear discontinuities in each channel associated with the multi-lane high-speed I / O link.The ability to indicate expected margin using a reference receiver and a representative channel, thereby flagging lower-than-expected margins even when the lower-than-expected margins are consistent across all lanes of a multi-lane high-speed I / O link for a single DUT and multiple DUTs. The ability to select from multiple speeds of a multi-lane high-speed I / O link and perform electrical margin evaluation on it. The ability to use protocol-specific knowledge to allow the margin tester to infer when an error occurs at the DUT's receiver based on traffic traveling in the opposite direction on the multi-lane high-speed I / O link, enabling margin testers to perform margin testing on the production line without software on the DUT. The ability to automatically capture time-domain reflectometry (TDR) values ​​of low-margin channels detected as a result of evaluating the electrical margin of a multi-lane high-speed I / O link. The ability to automatically connect to an oscilloscope and capture digitized waveforms when low margins are detected as a result of evaluating the electrical margin of a multi-lane high-speed I / O link. and providing a software plug-in to configure the silicon of the DUT to set one or more user-selectable options for the DUT and implement one or more user-selectable options. Portions of all of the above functionality may also be provided as user-selectable options for operating the margin tester 102 under the control of the controller 210.

[0031] FIG. 6 is a block diagram illustrating a generic margin tester 602 according to an example embodiment, where multiple interfaces 604 are configured to be connected to at least one test fixture, e.g., via one or more cables, to evaluate the electrical margin of a multi-lane high-speed I / O link of a DUT in one or both of the Tx and Rx directions.

[0032] Generic margin tester 602 includes controller 210 and associated memory 214, which may store instructions and other data that controller 210 can read, use, and execute to perform the functions described herein. Generic margin tester 602 has several lanes that can be connected (e.g., cabled) to a standard test fixture via interface 604, such as a standard PCI Express Compliance Load Board (CLB), and, under the control of controller 210, perform the same tests as technology-specific embodiments of the margin tester (e.g., add-in card margin tester 202 and motherboard margin tester 302). In addition, generic margin tester 602 supports multiple protocols, and generic margin tester 602 configuration software provides options for configuring lanes for various protocols and host / device roles. The generic margin tester 602 can also be used to test add-in cards by cabling it to a test fixture, such as a standard PCI Express Compliance Base Board (CBB) for testing add-in cards. The interface 604 of the generic margin tester 602 may have standard coaxial connectors and cables for each high-speed differential signal, or in various other embodiments, may have custom high-density connectors and fixtures to minimize cable count and make switching from one DUT to another more efficient.

[0033] FIG. 7 is a low-level block diagram of a margin tester 102 according to an exemplary embodiment for testing the electrical margin of a multi-lane high-speed I / O link of a DUT in one or both of the Tx and Rx directions.

[0034] Shown is an FPGA 714 operatively connected to a support unit 710 (which may have Ethernet or other communication capabilities), a timebase unit 708 that provides a reference clock for the system, a high speed I / O (HSIO) output unit 702, and an HSIO input unit 704. The margin tester 102 may also be powered by an AC / DC power supply unit 716. The HSIO output unit 702 and the HSIO input unit 704 are also operatively coupled to an I / O connector 706. The FPGA 714 is a semiconductor device based on a matrix of configurable logic blocks (CLBs) connected by programmable interconnects. In various embodiments, margin tester 102 may have fewer or more components than those shown, and some of the components or component functions shown may be located external to or separate from margin tester 102, or may be located within or integrated into FPGA 714, even though they are in operative communication with margin tester 102.

[0035] The FPGA 714 can be reprogrammed after manufacture for desired application or functional requirements, such as to perform the functions of the margin tester 102 described herein. For example, the firmware in the FPGA 714 may function as a standard PCI Express upstream port (for testing a motherboard, such as in the add-in card margin tester 202 embodiment) or a standard PCI Express root port (for testing an add-in card, such as in the motherboard margin tester 302 embodiment), including the link layer logic of the margin tester 102, to infer when an error began at the DUT's receiver based on traffic in the opposite direction, and to rapidly mitigate margin stress when an error occurs, preventing catastrophic link failure. In some embodiments, the FPGA 714 may be implemented using or otherwise include a system-on-module (SoM) architecture, which may incorporate memory, interfaces, and the like within the FPGA 714. SoMs can be implemented, for example, using advanced Reduced Instruction Set (RISC) machines (originally the Acorn RISC Machine (ARM) architecture).

[0036] A configuration application or script may be implemented via the FPGA 714 or stored in another accessible memory device or other non-transitory computer-readable storage medium to allow an end user to easily configure margin tester options for the margin tester 102, including multiple runs with one or more of the following options: In some embodiments, an option for a bit error rate (BER) target may be configured in terms of margin scans (milliseconds for E-6 type margins, minutes for E-12 type margins). For example, such targets may include, but are not limited to, margin, margin timing or voltage times, fixes for Tx equalization in the margin tester or DUT transmitter, and fixes for CTLE and DFE in the margin tester receiver Rx. In some embodiments, optional applications or scripts are provided that extract data from the margin tester 102 and provide visualization tools for users to view large margin data sets across multiple products / samples, view averages, run-to-run variations, trend over time, and compare margin across multiple runs of the same DUT with various configuration options (e.g., adjusted Tx equalization). In some embodiments, optional applications (which may be implemented on a bootable drive for installation on the motherboard under test) are provided that unlock additional options for motherboard testing, such as running in loopback and using specific patterns instead of L0, using on-die in-silicon margining capabilities of the DUT instead of voltage swing and Sj margining from the DUT's transmitter, and running both and comparing the results.

[0037] In some embodiments, optional plug-in models are provided that allow the margin tester's configuration application to also configure the Rx equalization settings on the specific DUT silicon, if a plug-in is provided for that DUT silicon. In some embodiments, optional IBIS-AMI (or similar) software models are provided for each individual margin test unit, which designers and system integrators can use to incorporate into their simulations and help establish test limits / methodologies for specific customer setups. IBIS-AMI is a serializer / deserializer (SerDes) physical layer (PHY) modeling standard that enables fast, accurate, and statistically significant simulation of multi-gigabit serial links. In some embodiments, optional IBIS-AMI models are provided for the margin test unit along with customer models (IBIS-AMI or S-parameters) that can be used in subsequent efforts to incorporate some level of the system, de-embedded for increased accuracy and repeatability.

[0038] FIG. 8 is a block diagram of an example field programmable gate array (FPGA) 714 configured, according to an example embodiment, that can be utilized in the controller 210 of the margin tester 102 to test the electrical margin of a multi-lane high-speed I / O link of a DUT in one or both of the Tx and Rx directions.

[0039] In various embodiments, FPGA 714 may include fewer or more components than those shown, and some of the components shown, or their functionality, may be located external to or separate from FPGA 714, even though they are in operative communication with FPGA 714. Shown is a register interface 804 operatively coupled to a local area network (LAN) connection 802, which may include a SerDes. Register interface 804 is also operatively coupled to a link training and status state machine (LTSSM) Rx controller 806. One of the processes at the physical layer of operation of margin tester 102 is the link initialization and training process. In PCI Express devices, this process establishes many important tasks, such as link width negotiation, link data rate negotiation, per-lane bit lock, and per-lane symbol lock / block alignment. All of these functions are performed by the LTSSM device, which observes stimuli from the remote link partner and the current state of the link and responds accordingly. The register interface 804 is also operably coupled to one or more additional LTSSM controller units, such as an LTSSM Universal Serial Bus (USB) controller 808 and an additional LTSSM USB controller 810. In the illustrated example embodiment, the LTSSM Rx controller 806 is operably coupled to a PCIe physical layer (PHY) 16x SerDes 812, and the LTSSM USB controller 808 is operably coupled to a USB / Thunderbolt / DisplayPort (USB / TBT / DP) PHY x4 unit 814. There is also a jitter control unit 816 as part of or operably coupled to FPGA 714 to control the jitter insertion unit so that the eye margin expected at the receiver of the DUT can be varied to specific targets in terms of timing or voltage margin without the need for software running on the DUT.

[0040] FIG. 9 is a block diagram of example output drive options of an FPGA (e.g., FPGA 714) according to an exemplary embodiment that may be utilized by a controller (e.g., controller 210) of a margin tester to test the electrical margin of a multi-lane high-speed I / O link of a DUT in one or both of the Tx and Rx directions.

[0041] The first output drive option is the FPGA direct drive option 818, which is unbuffered and does not introduce delay or jitter via varactors (variable capacitance diodes). The second output drive option is the buffered drive option 820, which includes a linear buffer amplifier or limiting amplifier 826 with a differential output voltage (Vod), but does not introduce varactor delay or jitter. The third output drive option is the varactor delay introduction option 822, which includes a linear buffer 826 and a varactor component 828, which result in some delay (which may be approximately 3-5 picoseconds, for example) in addition to inter-symbol interference (ISI). The fourth output drive option is the jitter introduction option 824, which in one embodiment includes a linear buffer 826 (which may or may not be present) and a delay ASIC (application specific integrated circuit) 830 (approximately 100 picoseconds at 32 GBd) (delay ASICs are also available from ADSANTEC). In some embodiments, the linear buffer 826 is not included. For example, in embodiments where the linear buffer 826 is not included, jitter injection may be performed by differential noise injection.

[0042] In various embodiments, margin tester 102 may utilize various types of stresses to identify a wide variety of corresponding failure modes, including, but not limited to, those related to assembly, interconnects (such as surface mount technology (SMT), packages, connectors, through-holes, and vias), defects, series resistance effects, ISI and baseline wander failure modes, eye closure effects, failure modes caused by causes other than width closure, functional test escapes, operator setting errors, novel materials, process variations, receiver bandwidth (which is analogous to interconnect variations), power supply rejection ratio (PSRR), vertical / horizontal eye closure, PLL stability, design, and lane-to-lane differences. Varactor-based jitter injection methods are particularly effective at exacerbating assembly-related defects.

[0043] FIG. 10 is a flow diagram of an exemplary method 1000 for margin testing a DUT according to an example embodiment.

[0044] At 1002, the margin tester 102 establishes a multi-lane high-speed I / O link with a device under test (DUT).

[0045] At 1004, the margin tester 102 evaluates electrical margin in one or both of the transmit (Tx) and receive (Rx) directions for each high-speed input / output (I / O) lane of the multi-lane high-speed I / O link. For example, evaluating the electrical margin may include injecting an adjustable stress into a margin test transmitter of the multi-lane high-speed I / O link. The adjustable stress may include injecting jitter and applying a voltage swing that is applied simultaneously to all lanes of the multi-lane high-speed I / O link. Evaluating the electrical margin may also include evaluating electrical margin in both the transmit (Tx) and receive (Rx) directions for each high-speed input / output (I / O) lane of the multi-lane high-speed I / O link simultaneously.

[0046] FIG. 11 is a flow diagram of an exemplary method 1100 according to one example embodiment for identifying potential assembly or production issues of a DUT based on margin testing the electrical margin of the DUT's multi-lane high-speed I / O link in one or both of the Tx and Rx directions.

[0047] At 1102, the margin tester 102 evaluates the timing of the eye width margin for each DUT among the plurality of DUTs in one or both of the Tx and Rx directions for each high-speed input / output (I / O) lane of the DUT's multi-lane high-speed I / O link.

[0048] At 1104, the margin tester 102 detects, for each DUT among the plurality of DUTs, timing eye width margin measurements that are consistently below a predetermined threshold for the same lane across the plurality of DUTs based on the evaluation.

[0049] In 1106, the margin tester 102 identifies potential issues in the DUT design based on detecting, for each DUT among the plurality of DUTs, timing eye width margin measurements that are consistently below a predetermined threshold for the same lane across the plurality of DUTs. The detection process may also or alternatively include detecting, for some of the plurality of DUTs, timing eye width margin measurements that are each below a predetermined threshold for different lanes across the plurality of DUTs based on the evaluation.

[0050] FIG. 12 is a flow diagram of an example method 1200 for margin tester 102 to initiate electrical margin evaluation operations based on user-selectable options according to an example embodiment.

[0051] In 1202, the margin tester 102 provides user-selectable options for the margin tester configured to establish a multi-lane high-speed input / output (I / O) link with a device under test (DUT) and evaluate the electrical margin of the multi-lane high-speed I / O link in one or both of the transmit (Tx) and receive (Rx) directions. The user-selectable options may include customization for evaluating the electrical margin of the multi-lane high-speed I / O link.

[0052] At 1204, the margin tester 102 receives instructions to select from among one or more user-selectable options for the margin tester 102.

[0053] In 1206, the margin tester 102 begins operation of evaluating the electrical margin of the multi-lane high-speed I / O link based on instructions to select from among one or more user-selectable options for the margin tester 102. The user-selectable options may include, but are not limited to, one or more of the following: Selectable option to select one or more different high-speed I / O protocols and use them to perform margin testing based on the DUT's multi-lane high-speed I / O link. Selectable option for testing multiple ports of a DUT using miscellaneous protocols simultaneously. For multi-lane high-speed I / O links, selectable option to output margin variation per run through any number of margin test runs in the margin tester. Selectable option to implement a fixed Tx equalization (EQ) in the DUT to test how much of the margin variation is due to variations in the Tx equalization (EQ) training. Selectable option to use adjusted CTLE at the receiver of the margin tester to test the impact of receiver equalization on the margin of the DUT's multi-lane high-speed I / O link. A selectable option to use a decision feedback equalizer (DFE) in the receiver of the margin tester to test the impact of receiver equalization on the margin of the DUT's multi-lane high-speed I / O link. Selectable option to calculate expected margin for Margin Tester based on target channel. Selectable option to automatically generate debug information when low margins are detected as a result of evaluating the electrical margins of multi-lane high-speed I / O links. A selectable option that switches the margin tester to use a variable inter-symbol interference (ISI) signal source to find how much ISI causes impairments in lanes of a multi-lane high-speed I / O link. Selectable option for the margin tester to test each lane individually to determine the amount of margin loss due to crosstalk in the DUT's multi-lane high-speed I / O link. A selectable option to turn off the DFE in the margin tester receiver to evaluate margin with and without the DFE and the amount of nonlinear discontinuities for each channel associated with a multi-lane high-speed I / O link. Selectable option for margin tester characterization data that allows flagging lower-than-expected margins, even if the lower-than-expected margins are consistent across all lanes of a multi-lane high-speed I / O link for one DUT among multiple DUTs. Selectable options for multi-lane high-speed I / O links, allowing you to choose between multiple speeds and evaluate electrical margins. A selectable option that allows the margin tester to use protocol-specific knowledge to infer when an error occurs at the DUT's receiver based on traffic traveling in the opposite direction of a multi-lane high-speed I / O link, enabling the margin tester to perform margin testing on the production line without software on the DUT. Selectable option to automatically capture time domain reflectometry (TDR) measurements of low-margin channels detected as a result of evaluating the electrical margin of multi-lane high-speed I / O links. Selectable option to automatically connect to an oscilloscope and automatically capture digitized waveforms when low margins are detected as a result of electrical margin evaluation of multi-lane high-speed I / O links. A selectable option for setting one or more user-selectable options on a DUT by configuring the silicon of the DUT to implement the one or more user-selectable options.

[0054] FIG. 13 is a flow diagram of an exemplary method 1300 for providing a calibrated margin tester according to an example embodiment.

[0055] In 1302, the margin tester 102 may provide an option to perform a calibration of the margin tester 102, or may perform a calibration, which allows the user to receive a set of expected margins on a series of reference channels.

[0056] In 1304, a calibrated margin tester is provided that is configured to measure electrical eye margin in one or both transmit (Tx) and receive (Rx) directions of a device under test (DUT) without special test modes and under full load conditions for the DUT's fully operational, normal operation link, capturing the full effects of loading and crosstalk. Individually calibrated models of the margin tester may also be provided that enable calculation of expected margin for one or more of the individualized system channels, receiver models, and transmitter models. Furthermore, the margin tester may provide the DUT's silicon with the capability to indicate, using a vendor-defined message or another protocol mechanism, that a margin test is about to be performed by the margin tester, allowing the DUT's silicon to disable logic that, in error, reduces the link width or speed for the duration of the margin test.

[0057] Margin tester software applications are also provided that enable the margin tester to perform testing of a channel component under test (e.g., a bare printed circuit board or cable) in a test configuration, with the margin tester being used on one or both ends of the channel component under test. In some embodiments, margin tester hardware is provided to companies that manufacture printed circuit boards (PCBs), and data related to the use of the margin tester is provided to silicon companies that provide the silicon used to manufacture the PCBs.

[0058] FIG. 14 is a flow diagram of an example method 1400 for configuring a DUT to perform margin testing according to an example embodiment.

[0059] At 1402, the margin tester 102 receives configuration settings for the device under test (DUT).

[0060] At 1404, the margin tester 102 configures the DUT to perform margin testing under various conditions on the DUT's silicon. The margin tester 102 may receive software plug-ins that enable configuration of the margin tester 102 to perform margin testing under various conditions on the DUT's silicon and DUT silicon parameters. The DUT silicon parameters may include, but are not limited to, one or more of parameters related to the receiver's continuous-time CTLE and parameters related to the DFE.

[0061] Advantages, benefits, and improvements of the disclosed embodiments include, but are not limited to, the following features: Some embodiments can be implemented almost entirely with off-the-shelf components, including standard FPGAs and sinusoidal jitter injection chips or delay lines, resulting in significantly lower cost compared to traditional BERTs and oscilloscopes. Example embodiments can be run on a complete multi-lane link operating under normal operating conditions without requiring specialized software, capturing any effects resulting from all lanes operating simultaneously. Another advantage is that embodiments of the disclosed technology can be tested in one or both directions (Tx and Rx) in a single, self-contained unit. Various embodiments can also be run in a production environment (e.g., motherboard production test environment) without requiring software on the DUT or modification to the DUT. Protocol-specific test logic may be provided in the silicon / firmware of the margin tester 102, allowing the device under test to very quickly recognize when an error is occurring in the DUT receiver based on the data the device under test sends back to the margin tester. In some exemplary embodiments, the DUT silicon may have the capability to recognize, through PCI Express vendor-specific messaging or other standard protocol features, that a margin test is about to occur and place the DUT silicon in a state that would not normally cause an error to degrade the link width or speed. This is useful for ensuring that the process of setting margins in the DUT receiver using noise injection or voltage swing adjustments can occur without the risk of degrading the link width or speed through normal protocol mechanisms. This is an alternative to special logic that can quickly infer when an error has started and reduce stress before link or speed degradation occurs.

[0062] Another improvement provided by the described embodiments is that because each margin tester unit in the plurality of margin tester units is individually calibrated and characterized, the user knows the expected margin value for each particular unit and can flag even the smallest deviations from the expected value across the user's prototype and production units. As part of this individual characterization and calibration, a model, such as an IBIS-AMI model, can be provided to each individual margin tester 102, allowing the end user to calculate the expected margin for a particular channel model based on simulated or measured S-parameters.

[0063] This disclosure describes an inventive margin tester that is extremely fast and extremely easy to use. Convenient and efficient configuration software is provided for length margin measurements and a variety of user-configurable options. Once configured, the margin tester 102 calls the link as any standard device and then automatically performs measurements on the working link. Testing is performed on all lanes simultaneously, allowing for rapid electrical margin scanning in milliseconds. This allows for high-volume testing, including full testing of all high-speed I / O ports and lanes. Various embodiments provide various margin testing modes that allow a level of problem characterization without the need for conventional equipment, including, but not limited to: The number of iterations and analysis of the variability per run of margin, the selected Tx equalization process (for both the DUT and the margin tester), the selected Rx equalization process (for the receiver of the margin tester), and the likelihood of training problems in the DUT's Tx or Rx training algorithm under test; adjusting the transmitter equalization in either way and observing the effect on margin; The process of adjusting (fixing) the number of taps (including zero) in the receiver equalization (CTLE) and DFE in the margin tester receiver and observing the effect on the margin value. For example, a significant change in margin when the DFE is off indicates a significant discontinuity in a particular channel.

[0064] Another advantage provided by various embodiments of margin tester 102 is the ability to test the electrical margins of all high-speed I / O ports and lanes of a particular DUT, across all prototype units and in actual production, creating an unprecedented ability to flag problems and potential problems before they reach production or the customer. Various embodiments also enable analysis of margins before and after various link events, such as power state transitions (possibly using software on the DUT).

[0065] Previous solutions include very general-purpose, highly sophisticated jitter and noise injection methods. Various embodiments of the present disclosure have advantages over these solutions by significantly simplifying (but not eliminating) the necessary tasks of jitter / amplitude stress. This simplicity translates into reduced operational costs, faster results, and improved product reliability (through the collection of large data sets) compared to what is required using existing methods.

[0066] Aspects of the disclosed technology may operate on specially created hardware, firmware, digital signal processors, or specially programmed general-purpose computers, including processors that operate according to programmed instructions. The terms "controller" or "processor" herein contemplate microprocessors, microcomputers, ASICs, and dedicated hardware controllers, among others. Aspects of the disclosed technology may be implemented as computer-usable data and computer-executable instructions, such as one or more program modules, executed by one or more computers (including a monitoring module) or other devices. Generally, program modules include routines, programs, objects, components, data structures, etc., which, when executed by a processor in a computer or other device, perform particular tasks or implement particular abstract data formats. Computer-executable instructions may be stored in computer-readable storage media, such as hard disks, optical disks, removable storage media, solid-state memory, RAM, etc. Those skilled in the art will appreciate that the functionality of the program modules may be combined or distributed as desired in various embodiments. Furthermore, such functionality may be embodied in whole or in part in firmware or hardware equivalents, such as integrated circuits, field programmable gate arrays (FPGAs), etc. Certain data structures may be used to more effectively implement one or more aspects of the disclosed technology, and such data structures are considered within the scope of the computer-executable instructions and computer-usable data described herein.

[0067] The disclosed aspects may, in some cases, be implemented in hardware, firmware, software, or any combination thereof. The disclosed aspects may also be implemented as instructions carried by or stored on one or more computer-readable media, which may be read and executed by one or more processors. Such instructions may be referred to as a computer program product. As used herein, computer-readable media refers to any medium that can be accessed by a computing device. By way of example, and not limitation, computer-readable media may include computer storage media and communication media.

[0068] "Computer storage media" means any medium that can be used to store computer-readable information. By way of example and not limitation, computer storage media may include random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory and other memory technologies, compact disc read-only memory (CD-ROM), digital video disc (DVD) and other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage and other magnetic storage devices, and any other volatile or nonvolatile, removable or non-removable medium implemented in any technology. "Computer storage media" excludes signals themselves and transitory forms of signal transmission.

[0069] A communication medium means any medium usable for communicating computer-readable information. By way of example, and not limitation, communication media may include coaxial cable, fiber optic cable, air, or any other medium suitable for communicating electrical, optical, radio frequency (RF), infrared, acoustic, or other types of signals.

[0070] Additionally, the description herein refers to specific features. It should be understood that the disclosure herein includes all possible combinations of these specific features. When a specific feature is disclosed in connection with a particular aspect or embodiment, that feature can also be used in connection with other aspects and embodiments, to the extent possible.

[0071] Furthermore, when this application refers to a method having two or more defined steps or processes, these defined steps or processes may be performed in any order or simultaneously, unless the circumstances do not preclude this possibility.

[0072] Although specific embodiments of the invention have been illustrated and described for purposes of illustration, it will be appreciated that various modifications can be made therein without departing from the spirit and scope of the invention. Accordingly, the invention should not be limited except as by the appended claims.

Claims

1. A test apparatus comprising: one or more printed circuit boards (PCBs); at least one interface coupled to the one or more PCBs; margin test circuitry on said one or more PCBs; Equipped with the margin test circuitry comprising: a controller coupled to the at least one interface; a margin test transmitter and a margin test receiver controlled by the controller; and The above controller is implementing a physical layer and a logical link layer via the at least one interface that communicatively connect the margin test circuitry of the test apparatus to a device under test (DUT) to establish a multi-lane high-speed I / O link with the DUT; and evaluating the electrical margin of multiple lanes of the multi-lane high-speed I / O link based on an indication of a selection of one or more user-selectable options in one or both of the transmit (Tx) and receive (Rx) directions. In the Tx direction, the controller causes the calibrated margin test transmitter to transmit data to the DUT, and in the Rx direction, the calibrated margin test receiver receives data from the DUT; The above user selectable options are: a selectable option for selecting and using one or more different high speed I / O protocols to perform margin testing based on the multi-lane high speed I / O link of the DUT; A selectable option for testing multiple ports of the DUT using a variety of protocols simultaneously; a selectable option for outputting margin variation for the multi-lane high speed I / O link from run to run through any number of runs of the tester's margin test; a selectable option to implement a fixed Tx equalization (EQ) on the DUT to test how much of the margin variation is due to variations in Tx EQ training; a selectable option for using a tuned continuous time linear equalizer (CTLE) in the tester receiver to test the impact of receiver equalization on the margin of the multi-lane high speed I / O link of the DUT; a selectable option for using a decision feedback equalizer (DFE) in the receiver of the tester to test the impact of receiver equalization on the margin of the multi-lane high speed I / O link of the DUT; a selectable option for calculating an expected margin for the test device based on a target channel; a selectable option for automatically generating debug information when low margin is detected as a result of evaluating the electrical margin of the multi-lane high speed I / O link; a selectable option for switching the tester to use a variable inter-symbol interference (ISI) signal source to find out how much ISI is causing impairments in lanes of the multi-lane high speed I / O link; a selectable option for the tester to test each lane individually to determine the amount of margin loss due to crosstalk in the multi-lane high speed I / O link of the DUT; a selectable option to turn off the DFE in the tester receiver to evaluate the margin with and without the DFE and the amount of nonlinear discontinuity for each channel associated with the multi-lane high speed I / O link; a selectable option for the tester's characterization data that allows the tester to flag lower-than-expected margins, even if the lower-than-expected margins are consistent across all lanes of the multi-lane high-speed I / O link for one of the DUTs; and a selectable option for selecting among multiple speeds of the multi-lane high speed I / O link for which to evaluate the electrical margin; a selectable option for the test equipment to use protocol-specific knowledge to infer when an error occurs at the receiver of the DUT based on traffic traveling in opposite directions on the multi-lane high-speed I / O link, allowing the test equipment to perform margin testing on a production line without software on the DUT; a selectable option for automatically capturing time domain reflectometry (TDR) measurements of low margin channels detected as a result of the electrical margin assessment of the multi-lane high speed I / O link; a selectable option for automatically connecting to an oscilloscope and automatically capturing a digitized waveform when a low margin is detected as a result of evaluating the electrical margin of the multi-lane high speed I / O link; Selectable options for setting one or more user selectable options on the DUT by configuring the silicon of the DUT to implement one or more user selectable options. A test device including one or more of the following:

2. 2. The test apparatus of claim 1, wherein the one or more PCBs include an add-in card PCB, the DUT is a motherboard, and the add-in card is configured to be plugged into a connector on the motherboard and to implement a physical layer and a logical link layer of the multi-lane high-speed I / O link.

3. 1. A method for testing the electrical margin of a device under test (DUT), comprising: establishing a multi-lane high speed I / O link between the DUT and a test apparatus having margin test circuitry with margin test transmitters and margin test receivers and a controller coupled to the at least one interface via the at least one interface; evaluating electrical margins for a plurality of lanes of the multi-lane high speed I / O link in one or both of the transmit (Tx) and receive (Rx) directions based on indication of selection of one or more user-selectable options by the controller of the test equipment controlling the margin test transmitter and the margin test receiver; Equipped with In the transmit (Tx) direction, the controller causes the calibrated margin test transmitter to transmit data to the DUT, and in the receive (Rx) direction, the calibrated margin test receiver receives data from the DUT; The above user selectable options are: a selectable option for selecting and using one or more different high speed I / O protocols to perform margin testing based on the multi-lane high speed I / O link of the DUT; A selectable option for testing multiple ports of the DUT using a variety of protocols simultaneously; a selectable option for outputting margin variation for the multi-lane high speed I / O link from run to run through any number of runs of the tester's margin test; a selectable option to implement a fixed Tx equalization (EQ) on the DUT to test how much of the margin variation is due to variations in Tx EQ training; a selectable option for using a tuned continuous time linear equalizer (CTLE) in the tester receiver to test the impact of receiver equalization on the margin of the multi-lane high speed I / O link of the DUT; a selectable option for using a decision feedback equalizer (DFE) in the receiver of the tester to test the impact of receiver equalization on the margin of the multi-lane high speed I / O link of the DUT; a selectable option for calculating an expected margin for the test device based on a target channel; a selectable option for automatically generating debug information when low margin is detected as a result of evaluating the electrical margin of the multi-lane high speed I / O link; a selectable option for switching the tester to use a variable inter-symbol interference (ISI) signal source to find out how much ISI is causing impairments in lanes of the multi-lane high speed I / O link; a selectable option for the tester to test each lane individually to determine the amount of margin loss due to crosstalk in the multi-lane high speed I / O link of the DUT; a selectable option to turn off the DFE in the tester receiver to evaluate the margin with and without the DFE and the amount of nonlinear discontinuity for each channel associated with the multi-lane high speed I / O link; a selectable option for the tester's characterization data that allows the tester to flag lower-than-expected margins, even if the lower-than-expected margins are consistent across all lanes of the multi-lane high-speed I / O link for one of the DUTs; and a selectable option for selecting among multiple speeds of the multi-lane high speed I / O link for which to evaluate the electrical margin; a selectable option for the test equipment to use protocol-specific knowledge to infer when an error occurs at the receiver of the DUT based on traffic traveling in opposite directions on the multi-lane high-speed I / O link, allowing the test equipment to perform margin testing on a production line without software on the DUT; a selectable option for automatically capturing time domain reflectometry (TDR) measurements of low margin channels detected as a result of the electrical margin assessment of the multi-lane high speed I / O link; a selectable option for automatically connecting to an oscilloscope and automatically capturing a digitized waveform when a low margin is detected as a result of evaluating the electrical margin of the multi-lane high speed I / O link; Selectable options for setting one or more user selectable options on the DUT by configuring the silicon of the DUT to implement one or more user selectable options. A method for testing electrical margins of a DUT, the method comprising one or more of the following:

4. A computer program that, when executed, causes at least one processor to: providing a test apparatus configured to establish a multi-lane high-speed input / output (I / O) link with a device under test (DUT) and evaluate electrical margins of multiple lanes of the multi-lane high-speed I / O link in one or both of a transmit (Tx) and a receive (Rx) direction with user-selectable options including customization of evaluation of the electrical margins of the multiple lanes of the multi-lane high-speed I / O link; receiving instructions to select one or more of the user-selectable options for the test device; and initiating, upon indication of selection of one or more of the user-selectable options for the tester, the tester to evaluate the electrical margins of a plurality of lanes of the multi-lane high-speed I / O link. Let them do this, The operation of evaluating the electrical margin is as follows: a controller coupled to at least one interface of the test equipment implementing a physical layer and a logical link layer via the at least one interface to communicatively connect a margin test transmitter and a margin test receiver of the test equipment to the DUT, whereby the test equipment establishes the multi-lane high speed I / O link with the DUT; causing the margin test transmitter and the margin test receiver to transmit and receive data between the DUT and the test equipment via the multi-lane high-speed I / O link under the control of the controller, and evaluating electrical margins of multiple lanes of the multi-lane high-speed I / O link in one or both of the Tx and Rx directions; in the Tx direction, the controller causes the calibrated margin test transmitter to transmit data to the DUT, and in the Rx direction, the calibrated margin test receiver receives data from the DUT; The above user selectable options are: a selectable option for selecting and using one or more different high speed I / O protocols to perform margin testing based on the multi-lane high speed I / O link of the DUT; A selectable option for testing multiple ports of the DUT using a variety of protocols simultaneously; a selectable option for outputting margin variation for the multi-lane high speed I / O link from run to run through any number of runs of the tester's margin test; a selectable option to implement a fixed Tx equalization (EQ) on the DUT to test how much of the margin variation is due to variations in Tx EQ training; a selectable option for using a tuned continuous time linear equalizer (CTLE) in the tester receiver to test the impact of receiver equalization on the margin of the multi-lane high speed I / O link of the DUT; a selectable option for using a decision feedback equalizer (DFE) in the receiver of the tester to test the impact of receiver equalization on the margin of the multi-lane high speed I / O link of the DUT; a selectable option for calculating an expected margin for the test device based on a target channel; a selectable option for automatically generating debug information when low margin is detected as a result of evaluating the electrical margin of the multi-lane high speed I / O link; a selectable option for switching the tester to use a variable inter-symbol interference (ISI) signal source to find out how much ISI is causing impairments in lanes of the multi-lane high speed I / O link; a selectable option for the tester to test each lane individually to determine the amount of margin loss due to crosstalk in the multi-lane high speed I / O link of the DUT; a selectable option to turn off the DFE in the tester receiver to evaluate the margin with and without the DFE and the amount of nonlinear discontinuity for each channel associated with the multi-lane high speed I / O link; a selectable option for the tester's characterization data that allows the tester to flag lower-than-expected margins, even if the lower-than-expected margins are consistent across all lanes of the multi-lane high-speed I / O link for one of the DUTs; and a selectable option for selecting among multiple speeds of the multi-lane high speed I / O link for which to evaluate the electrical margin; a selectable option for the test equipment to use protocol-specific knowledge to infer when an error occurs at the receiver of the DUT based on traffic traveling in opposite directions on the multi-lane high-speed I / O link, allowing the test equipment to perform margin testing on a production line without software on the DUT; a selectable option for automatically capturing time domain reflectometry (TDR) measurements of low margin channels detected as a result of the electrical margin assessment of the multi-lane high speed I / O link; a selectable option for automatically connecting to an oscilloscope and automatically capturing a digitized waveform when a low margin is detected as a result of evaluating the electrical margin of the multi-lane high speed I / O link; Selectable options for setting one or more user selectable options on the DUT by configuring the silicon of the DUT to implement one or more user selectable options. A computer program including one or more of the following:

5. a test fixture that is a motherboard including a printed circuit board having a plurality of slots; at least one slot among the plurality of slots into which at least one add-in card device under test (DUT) is inserted; a margin test transmitter on the tester that transmits data to the DUT via the at least one slot; a margin test receiver on the tester that receives data from the DUT via the at least one slot; a controller on the tester configured to control the margin test transmitter and the margin test receiver to margin test the DUT; Equipped with a controller on the test apparatus configured to evaluate electrical margins of multiple lanes of a multi-lane high-speed input / output (I / O) link of the DUT in one or both transmit (Tx) and receive (Rx) directions based on indication of selection of one or more user-selectable options after inserting the DUT into the at least one slot; In the Tx direction, the controller causes the calibrated margin test transmitter to transmit data to the DUT, and in the Rx direction, the calibrated margin test receiver receives data from the DUT; The above user selectable options are: a selectable option for selecting and using one or more different high speed I / O protocols to perform margin testing based on the multi-lane high speed I / O link of the DUT; A selectable option for testing multiple ports of the DUT using a variety of protocols simultaneously; a selectable option for outputting margin variation for the multi-lane high speed I / O link from run to run through any number of runs of the tester's margin test; a selectable option to implement a fixed Tx equalization (EQ) on the DUT to test how much of the margin variation is due to variations in Tx EQ training; a selectable option for using a tuned continuous time linear equalizer (CTLE) in the tester receiver to test the impact of receiver equalization on the margin of the multi-lane high speed I / O link of the DUT; a selectable option for using a decision feedback equalizer (DFE) in the receiver of the tester to test the impact of receiver equalization on the margin of the multi-lane high speed I / O link of the DUT; a selectable option for calculating an expected margin for the test device based on a target channel; a selectable option for automatically generating debug information when low margin is detected as a result of evaluating the electrical margin of the multi-lane high speed I / O link; a selectable option for switching the tester to use a variable inter-symbol interference (ISI) signal source to find out how much ISI is causing impairments in lanes of the multi-lane high speed I / O link; a selectable option for the tester to test each lane individually to determine the amount of margin loss due to crosstalk in the multi-lane high speed I / O link of the DUT; a selectable option to turn off the DFE in the tester receiver to evaluate the margin with and without the DFE and the amount of nonlinear discontinuity for each channel associated with the multi-lane high speed I / O link; a selectable option for the tester's characterization data that allows the tester to flag lower-than-expected margins, even if the lower-than-expected margins are consistent across all lanes of the multi-lane high-speed I / O link for one of the DUTs; and a selectable option for selecting among multiple speeds of the multi-lane high speed I / O link for which to evaluate the electrical margin; a selectable option for the test equipment to use protocol-specific knowledge to infer when an error occurs at the receiver of the DUT based on traffic traveling in opposite directions on the multi-lane high-speed I / O link, allowing the test equipment to perform margin testing on a production line without software on the DUT; a selectable option for automatically capturing time domain reflectometry (TDR) measurements of low margin channels detected as a result of the electrical margin assessment of the multi-lane high speed I / O link; a selectable option for automatically connecting to an oscilloscope and automatically capturing a digitized waveform when a low margin is detected as a result of evaluating the electrical margin of the multi-lane high speed I / O link; Selectable options for setting one or more user selectable options on the DUT by configuring the silicon of the DUT to implement one or more user selectable options. A margin tester including one or more of the following:

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