Variable capacitance element unit and manufacturing method thereof

Abstract

To provide a variable capacitance element unit with a high capacitance variable ratio and linearity.SOLUTION: A variable capacitance element unit includes at least one first variable capacitance element and at least one second variable capacitance element with a capacitance variable ratio different from that of the first variable capacitance element, which are formed on the same semiconductor substrate. The semiconductor substrate includes a flat region including a part of a main surface of the semiconductor substrate, and a concave region including a concave part provided on the main surface of the semiconductor substrate. The first variable capacitance element includes, in the flat region, a first semiconductor layer with a first conductivity type formed along the main surface of the semiconductor substrate, and a second semiconductor layer with a second conductivity type formed on the first semiconductor layer. The second variable capacitance element includes, in the concave region, the first semiconductor layer with the first conductivity type formed along a surface in the concave part, and the second semiconductor layer with the second conductivity type formed on the first semiconductor layer.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a variable capacitance element unit and a manufacturing method thereof. [Background technology]

[0002] A variable capacitance diode is a diode known as a variable capacitance element. A configuration such as that shown in Patent Document 1 is known as a variable capacitance diode. A variable capacitance diode utilizes the fact that when a reverse voltage is applied to a variable capacitance, the depletion layer of the pn junction acts as a capacitor. When the magnitude of the reverse voltage applied to the variable capacitance diode is changed, the width of the depletion layer of the pn junction of the variable capacitance diode changes, and therefore the capacitance changes.

[0003] Variable capacitance diodes are used in, for example, high frequency filters, TV tuners, and voltage controlled variable oscillators (VCOs) such as VCXOs (Voltage Controlled Crystal Oscillators) that use a quartz crystal resonator as a resonator.

[0004] It is known that the capacitance of a variable capacitance element can be more easily controlled when the graph of the change in capacitance relative to the change in the magnitude of the applied reverse voltage is more linear.

[0005] When multiple types of variable capacitance elements are required, multiple variable capacitance elements are used in combination. For example, Patent Document 2 discloses a method for combining multiple variable capacitance elements with different variable capacitance elements. In the method disclosed in Patent Document 2, a different mask is used for each variable capacitance element, and ion implantation is performed sequentially to create multiple variable capacitance elements with different variable capacitance elements.

[0006] In addition, in Patent Document 3, a buried electrode portion having an oxide film formed on its surface is buried in an impurity region formed in a semiconductor substrate portion, and a voltage application portion applies an arbitrary DC voltage between the buried electrode portion and the semiconductor substrate portion, and a charge accumulation portion formed inside the oxide film accumulates an amount of charge according to the applied DC voltage, thereby forming a variable capacitance semiconductor element. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Japanese Patent Application Publication No. 3-147375 [Patent Document 2] Japanese Patent Application Laid-Open No. 2010-003987 [Patent Document 3] Japanese Patent Application Laid-Open No. 2016-134432 Summary of the Invention [Problem to be solved by the invention]

[0008] However, with Patent Documents 1 to 3, it is difficult to obtain a variable capacitance element unit that has a high capacitance variable ratio and a highly linear profile of the capacitance variable ratio relative to the magnitude of the reverse voltage.

[0009] Furthermore, in the method disclosed in Patent Document 2, a mask must be formed for each variable capacitance element in order to manufacture the respective variable capacitance elements. Therefore, a mask formation step is required for each desired variable capacitance characteristic, which complicates the manufacturing process and increases manufacturing costs. Another known method is to use thermal diffusion to adjust the variable capacitance characteristics by implantation and thermal diffusion, but this method is difficult to fabricate, and is therefore not a practical solution.

[0010] The present invention has been made in view of the above circumstances, and aims to provide a method for easily manufacturing a variable capacitance element unit having a high capacitance variable ratio and a highly linear profile of the capacitance variable ratio versus the magnitude of the reverse voltage, and a variable capacitance element unit having a high capacitance variable ratio and linearity. [Means for solving the problem]

[0011] (1) A variable capacitance element unit according to a first aspect of the present invention comprises at least one first variable capacitance element and at least one second variable capacitance element having a capacitance variable ratio different from that of the first variable capacitance element, both formed on a semiconductor substrate, wherein the semiconductor substrate has a flat region including a part of a main surface of the semiconductor substrate and in which the at least one first variable capacitance element is formed, and a recessed region including a recess provided in the main surface of the semiconductor substrate and in which the at least one second variable capacitance element is formed, the first variable capacitance element having a first semiconductor layer of a first conductivity type formed along the main surface of the semiconductor substrate in the flat region of the semiconductor substrate and a second semiconductor layer of a second conductivity type formed on the first semiconductor layer, and the second variable capacitance element having a first semiconductor layer of a first conductivity type formed along a surface in the recess in the recessed region of the semiconductor substrate and a second semiconductor layer of a second conductivity type formed on the first semiconductor layer.

[0012] (2) In the variable capacitance element unit according to the above aspect, the recess may have an inclined surface that reduces the cross-sectional area of ​​the recess perpendicular to the stacking direction with increasing distance from the main surface of the semiconductor substrate, and the first semiconductor layer and the second semiconductor layer of the second variable capacitance element may be formed on the inclined surface of the recess.

[0013] (3) In the variable capacitance element unit according to the above aspect, the recess may be a groove having a substantially V-shaped cross section.

[0014] (4) In the variable capacitance element unit according to the above aspect, the thickness of the second semiconductor layer in the second variable capacitance element in the stacking direction may be smaller than the thickness of the second semiconductor layer in the first variable capacitance element in the stacking direction.

[0015] (5) In the variable capacitance element unit according to the above aspect, the first variable capacitance element may further include an insulating film formed on the second semiconductor layer of the first variable capacitance element, and the second variable capacitance element may further include an insulating film formed on the second semiconductor layer of the second variable capacitance element.

[0016] (6) In the variable capacitance element unit according to the above aspect, the insulating film in the first variable capacitance element and the insulating film in the second variable capacitance element may be thermal oxide films, and the thickness of the insulating film in the second variable capacitance element in the stacking direction may be greater than the thickness of the insulating film in the first variable capacitance element in the stacking direction.

[0017] (7) In the variable capacitance element unit according to the above aspect, the insulating film in the first variable capacitance element and the insulating film in the second variable capacitance element may be a vapor-deposited film, and the thickness of the insulating film in the second variable capacitance element in the stacking direction may be the same as the thickness of the insulating film in the first variable capacitance element in the stacking direction.

[0018] (8) In the variable capacitance element unit according to the above aspect, the at least one first variable capacitance element and the at least one second variable capacitance element may be arranged in a line or a matrix on the semiconductor substrate, and the ratio (A1:A2) of a total area A1 of the at least one first variable capacitance element to a total area A2 of the at least one second variable capacitance element when the semiconductor substrate is viewed in a plane may be 1:9 to 9:1.

[0019] (9) A method for manufacturing a variable capacitance element unit according to a second aspect of the present invention includes a first step of forming at least one recess in a part of a main surface of a semiconductor substrate to provide a flat region and a recess region in the semiconductor substrate; a second step of forming an insulating film in the flat region and the recess region of the semiconductor substrate; a third step of implanting ions into the semiconductor substrate via the insulating film to form a first semiconductor layer of a first conductivity type in the flat region and the recess region of the semiconductor substrate; and a fourth step of implanting ions into the semiconductor substrate via the insulating film to form a second semiconductor layer of a second conductivity type on the first semiconductor layer in the flat region and the recess region of the semiconductor substrate.

[0020] (10) In the method for manufacturing a variable capacitance element unit according to the above aspect, in the first step, the recess may be formed to have an inclined surface whose cross-sectional area parallel to the main surface of the semiconductor substrate decreases with increasing distance from the main surface of the semiconductor substrate; in the third step, the first semiconductor layer may be formed on the inclined surface in the recess region; and in the fourth step, the second semiconductor layer may be formed on the first semiconductor layer.

[0021] (11) In the method for manufacturing a variable capacitance element unit according to the above aspect, in the second step, a surface layer portion of the semiconductor substrate may be thermally oxidized to form a thermal oxide film in the flat region and the recessed region.

[0022] (12) In the method for manufacturing a variable capacitance element unit according to the above aspect, in the second step, an insulating film made of an oxide or nitride of a semiconductor material may be formed in the flat region and the recessed region by chemical vapor deposition or physical vapor deposition.

[0023] (13) In the method for manufacturing a variable capacitance element unit according to the above aspect, in the first step, the at least one recess may be formed in plurality so that the flat regions and recess regions are arranged in a linear or matrix pattern. [Effects of the Invention]

[0024] According to the present invention, it is possible to provide a method for easily manufacturing a variable capacitance element unit having a high capacitance variable ratio and a highly linear profile of the capacitance variable ratio versus the magnitude of the reverse voltage, as well as a variable capacitance element unit having a high capacitance variable ratio and linearity. [Brief explanation of the drawings]

[0025] [Figure 1] FIG. 2 is a cross-sectional view schematically illustrating an example of a variable capacitance element unit according to the present embodiment. [Figure 2] 3 is a plan view showing an example of the arrangement of first and second variable capacitance elements that form a unit of variable capacitance elements according to the present embodiment. FIG. [Figure 3] 10 is a plan view showing another example of the arrangement of the first and second variable capacitance elements that configure the variable capacitance element unit according to the present embodiment. FIG. [Figure 4] FIG. 10 is a schematic cross-sectional view showing another example of the variable capacitance element unit according to the embodiment. [Figure 5] 5A to 5C are diagrams illustrating an example of a method for manufacturing the variable capacitance element unit according to the embodiment. [Figure 6] 5A and 5B are views for explaining a first step of the method for manufacturing the variable capacitance element unit according to the embodiment. [Figure 7] FIG. 10 is a view for explaining a second step of the method for manufacturing the variable capacitance element unit. [Figure 8] FIG. 10 is a diagram illustrating a third step in the method for manufacturing the variable capacitance element unit. [Figure 9] FIG. 10 is a view for explaining a fourth step of the method for manufacturing the variable capacitance element unit. [Figure 10] FIG. 8 is a diagram for explaining a modified example of the second step in FIG. 7. [Figure 11] 9 is a diagram for explaining a modified example of the third step in FIG. 8. FIG. [Figure 12] 10 is a diagram for explaining a modified example of the fourth step in FIG. 9. FIG. [Figure 13] 2 is an example of a circuit diagram of a voltage-controlled crystal oscillator including the variable capacitance element of FIG. 1. [Figure 14]1 is a diagram showing the rate at which a thermal oxide film SiO 2 is formed on the (100) and (111) surfaces of a silicon substrate in Production Examples 1 and 2. FIG. [Figure 15] 10 is a diagram showing the relationship between the substrate depth and the impurity concentration of the variable capacitance element obtained in Production Examples 3 and 4. FIG. [Figure 16] 10 is a cross-sectional view showing the distribution of impurity concentrations in the variable capacitance elements obtained in Production Examples 3 and 4. FIG. [Figure 17] 10 is a diagram showing a change in capacitance variable ratio (C / C0) when a reverse bias voltage applied to the variable capacitance element units of Example 1, Comparative Example 1, and Comparative Example 2 is changed. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0026] An example of an embodiment of the present invention will be described in detail below with reference to the drawings. Note that the drawings used in the following description may show characteristic parts enlarged for the sake of convenience in order to make the features of the present invention easier to understand. Therefore, the dimensional ratios of each component may differ from the actual ones.

[0027] [Variable capacitance element] First Embodiment FIG. 1 is a diagram schematically showing a cross-sectional structure of a variable capacitance element unit 100 according to this embodiment. As shown in Fig. 1, variable capacitance element unit 100 includes at least one first variable capacitance element 1A and at least one second variable capacitance element 1B having a capacitance variable ratio different from that of first variable capacitance element 1A, which are formed on the same semiconductor substrate 10. In Fig. 1, first variable capacitance element 1A and second variable capacitance element 1B of variable capacitance element unit 100 are connected to anode electrode terminal 65 and cathode electrode terminal 60, respectively, and share a common cathode electrode. To facilitate understanding of the present invention, Fig. 1 also shows an example of a circuit diagram of variable capacitance element unit 100.

[0028] The variable capacitance element unit 100 includes, for example, a semiconductor substrate 10, an insulating film 20, a cathode electrode structure 30, a cathode electrode body 31, a cathode contact 32, an anode electrode structure 35, an anode electrode body 36, an anode contact 37, an element isolation oxide film 40, and an insulating layer 50. The semiconductor substrate 10 is, for example, a semiconductor containing silicon, and includes a base substrate 11 of a first conductivity type, a first semiconductor layer 12 of the first conductivity type, and a second semiconductor layer 13 of a second conductivity type.

[0029] The semiconductor substrate 10 has a flat region RA including a portion of the main surface S of the semiconductor substrate 10 and in which at least one first variable capacitance element 1A is formed, and a recessed region RB including a recessed portion PB provided in the main surface S of the semiconductor substrate 10 and in which at least one second variable capacitance element 1B is formed.

[0030] First variable capacitance element 1A includes a first semiconductor layer 12A of a first conductivity type formed along a main surface S of semiconductor substrate 10 in flat region RA of the semiconductor substrate, and a second semiconductor layer 13A of a second conductivity type formed on the first semiconductor layer. Here, the crystal plane of main surface S of semiconductor substrate 10 is, for example, the (100) plane. First semiconductor layer 12A is formed on, for example, base substrate 11 of semiconductor substrate 10. First variable capacitance element 1A further includes, for example, an insulating film 20A formed on second semiconductor layer 13A.

[0031] Base substrate 11 is a p-type semiconductor containing a uniform impurity element, such as a low concentration of boron. First semiconductor layer 12A is a p-type semiconductor layer containing an impurity element, such as boron. Second semiconductor layer 13A is an n-type semiconductor layer containing an impurity element, such as arsenic. First variable capacitance element 1A includes first semiconductor layer 12A and second semiconductor layer 13A forming a p-n junction (p-n junction surface 19). p-n junction surface 19 is the interface between first semiconductor layer 12A and second semiconductor layer 13A and is a coordinate plane where the impurity concentration has a minimum value. In the p-n junction, first semiconductor layer 12A has a structure in which the impurity concentration increases with increasing distance from p-n junction surface 19, reaches a maximum value at a certain coordinate, and decreases with increasing distance from the maximum value. That is, first semiconductor layer 12A has a first region in which the impurity concentration increases with increasing distance from pn junction surface 19, and a second region that is farther away from pn junction surface 19 than the first region and in which the impurity concentration decreases with increasing distance from pn junction surface 19. That is, first variable capacitance element 1A is, for example, a hyperabrupt junction type. If the pn junction is a hyperabrupt junction in which the concentration decreases from a maximum value near the pn junction surface toward the depth direction inside the substrate, the depletion layer expands in the stacking direction in response to voltage application according to a principle described below, thereby increasing the capacitance variable ratio.

[0032] The first semiconductor layer 12 is provided, for example, over the entire in-plane surface of the semiconductor substrate 10. The second semiconductor layer 13A is, for example, a region defined by adjacent element isolation oxide films 40, 40, and a part of it is in contact with the cathode contact 32.

[0033] The thicknesses of the first semiconductor layer 12A, the second semiconductor layer 13A, and the insulating film 20A in the stacking direction are respectively T 12A , T 13A ,T 20A (FIG. 1). Here, the thickness in the stacking direction is the thickness in the direction in which the first semiconductor layer 12A, the second semiconductor layer 13A, and the insulating film 20A are stacked, and is the thickness in the direction perpendicular to the main surface S of the semiconductor substrate 10. The thickness T of the first semiconductor layer 12A in the stacking direction is 12A is the thickness T of the first semiconductor layer 12B in the stacking direction, which will be described later.12B The thickness T 13A is the thickness T of the second semiconductor layer 13B in the stacking direction, which will be described later. 13B It is preferable that the thickness T 20A is the thickness T of the insulating film 20B in the stacking direction, which will be described later. 20B With this configuration, the degree of freedom of the variable capacitance element unit 100 can be increased.

[0034] The concentration of the impurity element in the base substrate 11 is, for example, 10 15 / cm 3 ~10 16 / cm 3 The concentration of the impurity element in the first semiconductor layer 12A is, for example, 10 16 / cm 3 ~10 18 / cm 3 The concentration of the impurity element in the second semiconductor layer 13A is, for example, 10 17 / cm 3 ~10 21 / cm 3 is.

[0035] In the first semiconductor layer 12A, in a region slightly away from the pn junction surface 19, the impurity concentration increases steeply with increasing distance from the pn junction surface 19, and once it reaches a maximum value, the impurity concentration decreases steeply with increasing distance from the pn junction surface. In the region from the pn junction surface 19 to the maximum value of the impurity concentration, the impurity concentration gradient in the thickness direction of the first semiconductor layer 12A is, for example, -2.0 19 ~+5.0 19 (pcs / cm 3 ·μm) and -1.0 19 ~+3.0 19 (pcs / cm 3 In the first semiconductor layer 12A, the concentration gradient of the impurity in a region farther from the pn junction surface 19 than the maximum value of the impurity concentration is preferably −1.0 μm. 19 ~+1.0 17 (pcs / cm 3 ·μm) and -1.0 19 ~+1.0 16(pcs / cm 3 Preferably, the impurity concentration gradient in the thickness direction of the first semiconductor layer 12A is calculated by averaging the impurity concentration profiles at 10 arbitrary equally spaced locations in the stacking direction of the first semiconductor layer 12A, differentiated with respect to the stacking direction position. 19 (pcs / cm 3 10 μm) the impurity concentration decreases from 1×10 19 (pcs / cm 3 0 (μm) reduction 3 μm) indicates that the impurity concentration does not change, 19 (pcs / cm 3 μm) is 1×10 19 (pcs / cm 3 This means that the particle size (μm) increases.

[0036] The insulating film 20A is, for example, a thermal oxide film, or a film made of an oxide or nitride of a semiconductor material such as a silicon oxide film or a silicon nitride film, and is deposited by a vapor deposition method. The insulating film 20A is, for example, a vapor deposition film.

[0037] Second variable capacitance element 1B includes a first semiconductor layer 12B of a first conductivity type formed along a surface SB of recess PB in recess region RB of semiconductor substrate 10, and a second semiconductor layer 13B of a second conductivity type formed on first semiconductor layer 12B. Second semiconductor layer 13B is, for example, a region defined by adjacent element isolation oxide films 40, 40, and a portion thereof is in contact with cathode contact 32. First semiconductor layer 12B is, for example, formed on base substrate 11 of semiconductor substrate 10. Second variable capacitance element 1B further includes, for example, an insulating film 20B formed on second semiconductor layer 13B.

[0038] The recess PB is recessed in the thickness direction of the semiconductor substrate 10. For example, the recess PB has an inclined surface 10 whose cross-sectional area perpendicular to the thickness direction of the semiconductor substrate 10 decreases with increasing distance from the main surface S of the semiconductor substrate 10. T Inclined surface 10 T The recess PB shown in FIG. T1, the recess PB is substantially V-shaped in cross section perpendicular to the main surface S of the semiconductor substrate 10. Here, the main surface S is, for example, the (100) surface of the silicon substrate, and the inclined surface 10 T The crystal plane is, for example, the (111) plane of a silicon substrate.

[0039] The recesses PB may be provided in the form of spots or lines when viewed from above in the thickness direction of the semiconductor substrate 10. The recesses PB may also be grooves that are provided continuously or intermittently along the in-plane direction of the semiconductor substrate 10.

[0040] The thicknesses of the first semiconductor layer 12B, the second semiconductor layer 13B, and the insulating film 20B in the stacking direction are respectively T 12B ,T 13B , and T 20B Here, the thicknesses of the first semiconductor layer 12B, the second semiconductor layer 13B, and the insulating film 20B in the stacking direction are the thicknesses in the direction in which the first semiconductor layer 12B, the second semiconductor layer 13B, and the insulating film 20B are stacked, respectively, and are the thicknesses of the inclined surface 10B. T The thickness is measured along the inclined surface 10 with respect to the main surface S of the semiconductor substrate 10. T The angle is, for example, 15° to 75°, and preferably 50° to 60°. T When the crystal plane is the (111) plane of the silicon substrate, the angle of the inclined plane 10T with respect to the main surface S of the semiconductor substrate 10 is 54.7°.

[0041] Thickness T of the first semiconductor layer 12B in the stacking direction 12B is, for example, the thickness T of the first semiconductor layer 12A in the stacking direction. 12A The thickness T of the first semiconductor layer 12A in the stacking direction is 12A It can be arbitrarily designed according to a desired capacitance variable ratio, but the thickness T 12B is the thickness T of the first semiconductor layer 12A in the stacking direction. 12AIt is more preferable that the ratio is 1.1 times or more, and even more preferable that the ratio is 1.3 times or more. The thickness T of the second semiconductor layer 13B in the stacking direction 13B is, for example, the thickness T of the second semiconductor layer 13A in the stacking direction. 13A The thickness T 13A It can be arbitrarily designed according to a desired capacitance variable ratio, but the thickness T 13B is the thickness T of the second semiconductor layer 13A in the stacking direction. 13A It is more preferable that the ratio is 0.8 times or less, and even more preferable that the ratio is 0.5 times or less.

[0042] The thickness T of the second semiconductor layer 13B in the stacking direction 13B is the thickness T of the second semiconductor layer 13A in the stacking direction 13A When the thickness T 13B is the thickness T of the second semiconductor layer 13A in the stacking direction 13A , the impurity concentration profile of the first semiconductor layer 12B can be made different from that of the first semiconductor layer 12A. Specifically, the impurity concentration profile of the first semiconductor layer 12A can be made steeper than the impurity concentration profile of the first semiconductor layer 12B, and a hyperabrupt junction can be formed, for example.

[0043] The concentration profiles of impurity elements in the first semiconductor layer 12B and the second semiconductor layer 13B are different from the concentration profiles of impurity elements in the first semiconductor layer 12A and the second semiconductor layer 13A. Specifically, the impurity concentration in the first semiconductor layer 12A changes more steeply than in the first semiconductor layer 12B with increasing distance from the pn junction surface 19, while the impurity concentration in the first semiconductor layer 12B changes more gradually than in the first semiconductor layer 12A with increasing distance from the pn junction surface 19. In the first semiconductor layer 12B, in a region slightly away from the pn junction surface 19, the impurity concentration gradually increases with increasing distance from the pn junction surface, and after reaching a maximum value, the impurity concentration gradually decreases with increasing distance from the pn junction surface. That is, like the first semiconductor layer 12A, the first semiconductor layer 12B also has a first region and a second region. In the first semiconductor layer 12B, the concentration gradient of the impurity in the thickness direction in the region from the pn junction surface 19 to the maximum value of the impurity concentration is, for example, 1×10 18 ~+5×10 19 (pcs / cm 3 μm), and +5×10 18 ~+2×10 19 (pcs / cm 3 In the first semiconductor layer 12B, the concentration gradient of the impurity in a region farther from the pn junction surface 19 than the maximum value of the impurity concentration is preferably −5×10 19 ~-5×10 16 (pcs / cm 3 μm), and -1×10 19 ~-1×10 17 (pcs / cm 3 where -1×10 19 (pcs / cm 3 1 μm away from the pn junction surface 19, the impurity concentration decreases by 1×10 19 (pcs / cm 3 ) decrease to 0 (pieces / cm 3 ) indicates that the impurity concentration does not change, and 19 (pcs / cm 3 ) is 1×10 19 (pcs / cm 3) increases. The difference between the impurity concentration gradient in the thickness direction of the first semiconductor layer 12B and the impurity concentration gradient in the thickness direction of the first semiconductor layer 12A is 2×10 18 (pcs / cm 3 The concentration profile gradient (atoms / cm 3 ) of the impurity element in the first semiconductor layer 12A at a position deeper than the position of the pn junction surface 19 by the depletion layer width W at a reverse bias voltage V=0 V is preferably 1 / cm 3 . 3 It is preferable that the concentration profile starts from a positive value or zero.

[0044] In first variable capacitance element 1A, the impurity concentration of first semiconductor layer 12A, which is located farther from main surface S of the semiconductor substrate than junction surface 19, rises sharply at first and then drops sharply as the depth increases, resulting in a sharper capacitance-voltage change and a sharper capacitance-voltage curve. Therefore, the capacitance reaches its lower limit at a low reverse bias voltage. Meanwhile, in second variable capacitance element 1B, the impurity concentration of first semiconductor layer 12A, which is located farther from main surface S of the semiconductor substrate than junction surface 19, rises gradually at first and then drops gradually as the depth increases, resulting in a more gradual capacitance-voltage change and a more gradual capacitance-voltage curve. Therefore, the capacitance reaches its lower limit at a high reverse bias voltage. The lower limit of capacitance is determined substantially by the impurity concentration of semiconductor substrate 10, as shown in the following equations (1) and (2):

[0045]

number

[0046]

number

[0047] When the gradient of the impurity concentration profile in the thickness direction of first semiconductor layer 12B is within the above range, the capacitance variable ratio can be easily adjusted by combining first variable capacitance element 1A and second variable capacitance element 1B.

[0048] The concentration of the impurity element in the first semiconductor layer 12B is, for example, 10 15 / cm 3 ~10 18 / cm 3 The concentration of the impurity element in the second semiconductor layer 13B is, for example, 5.0×10 16 / cm 3 ~1.0×10 21 / cm 3 The maximum value of the impurity concentration of the second semiconductor layer 13B is higher than the maximum value of the impurity concentration of the first semiconductor layer 12B. Similarly, the maximum value of the impurity concentration of the second semiconductor layer 13A is higher than the maximum value of the impurity concentration of the first semiconductor layer 12A.

[0049] The insulating film 20B is, for example, a thermal oxide film or a CVD film such as a silicon oxide film or a silicon nitride film. 20B is the thickness T of the insulating film 20A in the stacking direction. 20A It is preferable that the thickness T 20A Specifically, the thickness T of the insulating film 20B in the stacking direction may be the same as 20B is the thickness T of the insulating film 20A in the stacking direction. 20A It is preferable that the ratio is 1.2 to 2.0 times.

[0050] As described above, the variable capacitance element unit 100 has different impurity concentration profiles in the flat region RA and the recessed region RB of the semiconductor substrate 10.

[0051] When a reverse voltage is applied to first variable capacitance element 1A and second variable capacitance element 1B from cathode electrode terminal 60 to anode electrode terminal 65, almost no current flows and a depletion layer is formed near pn junction surface 19. When the reverse voltage applied to first variable capacitance element 1A and second variable capacitance element 1B is increased, the depletion layer expands in the stacking direction. In other words, the capacitance of first variable capacitance element 1A and second variable capacitance element 1B can be changed by changing the magnitude of the reverse voltage.

[0052] The way in which the capacitance of a varactor changes with the magnitude of the reverse voltage differs for each varactor. Generally, when the reverse voltage is small, the capacitance of the varactor changes greatly with the change in reverse voltage, and when the reverse voltage is large, the capacitance of the varactor changes little with the change in reverse voltage. On the other hand, a varactor whose capacitance changes uniformly regardless of the magnitude of the reverse voltage is preferable because it is easy to control the capacitance variable ratio. In other words, a varactor whose capacitance variable ratio profile with respect to the magnitude of the reverse voltage has a high linearity is desirable.

[0053] The capacitance variable ratio of a variable capacitance element and the linearity of its profile with respect to the magnitude of the reverse voltage depend on the impurity concentration profile of the semiconductor layer constituting the variable capacitance element. Therefore, the first variable capacitance element 1A and the second variable capacitance element 1B, which have different impurity concentration profiles, have different capacitance variable ratios and linearity of their profile with respect to the magnitude of the reverse voltage. Specifically, the capacitance variable ratio of the first variable capacitance element 1A is greater than that of the second variable capacitance element 1B. Furthermore, the linearity of the profile with respect to the reverse voltage of the second variable capacitance element 1B is greater than that of the first variable capacitance element 1A. Therefore, by combining the first variable capacitance element 1A and the second variable capacitance element 1B, a variable capacitance element unit 100 can be obtained that has a higher capacitance variable ratio than the second variable capacitance element 1B and a more linear profile with respect to the change in reverse voltage than the first variable capacitance element 1A.

[0054] 2 and 3 are plan views showing an example of the arrangement of first variable capacitance element 1A and second variable capacitance element 1B that constitute a unit of variable capacitance elements according to this embodiment. 2 and 3, in variable capacitance element units 100A and 100B, for example, at least one first variable capacitance element 1A and at least one second variable capacitance element 1B are arranged linearly or in a matrix on semiconductor substrate 10. In variable capacitance element units 100, 100A, and 100B, first variable capacitance element 1A and second variable capacitance element 1B are connected in parallel, for example. When semiconductor substrate 10 is viewed in plan, the ratio (A1:A2) of total area A1 of first variable capacitance element 1A to total area A2 of second variable capacitance element 1B is preferably 1:9 to 9:1. Here, the areas of first variable capacitance element 1A and second variable capacitance element 1B refer to the areas of second semiconductor layers 13A and 13B, respectively, when semiconductor substrate 10 is viewed in plan.

[0055] If the ratio of the total area of ​​first variable capacitance element 1A to second variable capacitance element 1B is within the above range, the capacitance variable ratio and linearity can be set within a preferable range.

[0056] The number and area ratio of the first variable capacitance elements 1A and the second variable capacitance elements 1B in the variable capacitance element unit are not limited to the examples shown in Figures 2 and 3, and can be selected arbitrarily depending on the desired capacitance variable ratio and linearity.

[0057] As described above, according to this embodiment, the variable capacitance element unit 100 is configured to include the first variable capacitance element 1A having the flat region RA and the second variable capacitance element 1B having the recessed region RB and having a capacitance variable ratio different from that of the first variable capacitance element 1A. Therefore, by combining the first variable capacitance element 1A and the second variable capacitance element 1B having different capacitance variable ratios, it is possible to easily realize a variable capacitance element unit 100 having a high capacitance variable ratio and a highly linear profile of the capacitance variable ratio with respect to the magnitude of the reverse voltage.

[0058] In the above embodiment, the base substrate 11 has a structure in which the impurity concentration is uniform, but the present invention is not limited to this. The impurity elements may be various within the base substrate 11, and the impurity concentration may be lower in regions farther from the first semiconductor layer 12A. In addition, in the above embodiment, an example was shown in which the shape of the recess PB in the cross section perpendicular to the main surface S of the semiconductor substrate 10 is V-shaped, but the shape of the recess PB may be U-shaped or trapezoidal. In addition, the inclined surface 10 T The angle with respect to the main surface S is not limited to a linear shape, but may be a curved shape.

[0059] Furthermore, although the hyperabrupt junction structure in which the impurity concentration is lower in the region where the first semiconductor layer 12A and the base substrate 11 are farther away from the pn junction surface 19 has been described, the structure is not limited as long as it is a variable capacitance element that utilizes a pn junction. Furthermore, in this embodiment, a variable capacitance element in which the first conductivity type is N-type and the second conductivity type is P-type has been described, but this is not limited thereto, and the first conductivity type may be P-type and the second conductivity type may be N-type. The first variable capacitance element 1A and the second variable capacitance element 1B may further have an anti-inversion layer between the anode contact 37 and the first semiconductor layer 12, the anti-inversion layer being of the first conductivity type and having a higher impurity element concentration than the first semiconductor layer 12. The recessed portion 10 is formed along the main surface S of the semiconductor substrate 10. T The term "formed along" refers to the main surface S to the inclined surface 10 of the recess. T It is sufficient that the surface is approximately parallel to the main surface S or the inclined surface 10 of the recess. T The present invention is not limited to a configuration in which the semiconductor device is exposed to the external environment.

[0060] 1 shows a configuration including a cathode electrode structure 30 and an element isolation oxide film 40 located directly below the cathode electrode structure 30 and connected together, but the present invention is not limited to this example. For example, the present invention may also be a variable capacitance element unit 100′ as shown in FIG. 4. The variable capacitance element unit 100′ differs from the variable capacitance element unit 100 in that it does not include an anode electrode structure 35 (anode electrode body 36 and anode contact 37), a cathode electrode structure 30 (cathode electrode body 31 and cathode contact 32), or an element isolation oxide film 40 that separates the first variable capacitance element 1A and the second variable capacitance element 1B, and the second semiconductor layer 13X and the insulating film 20X are not separated by the element isolation oxide film 40. In the variable capacitance element unit 100′, components similar to those in the variable capacitance element unit 100 are designated by the same reference numerals, and descriptions thereof will be omitted. In variable capacitance element unit 100', first semiconductor layer 12A of first variable capacitance element 1A is connected to first semiconductor layer 12B of second variable capacitance element 1B, and second semiconductor layer 13A of first variable capacitance element 1A is connected to second semiconductor layer 13B of second variable capacitance element 1B. According to variable capacitance element unit 100' of this modification, it is possible to realize variable capacitance element unit 100' having a high capacitance variable ratio and a highly linear profile of the capacitance variable ratio with respect to the magnitude of the reverse voltage, and further, since semiconductor layers of the same type are connected without providing an anode electrode structure and a cathode electrode structure, it is possible to simplify the structure.

[0061] [Manufacturing method of variable capacitance element unit] Next, an example of a method for manufacturing the variable capacitance element unit according to this embodiment will be described, focusing on the process of forming the flat region RA of the first variable capacitance element 1A and the recessed region RB of the second variable capacitance element 1B.

[0062] The method for manufacturing a variable capacitance element unit according to this embodiment includes a first step of providing a flat region and a recessed region on a semiconductor substrate, a second step of forming an insulating film in the flat region and the recessed region, a third step of forming a first semiconductor layer of a first conductivity type in the flat region and the recessed region, and a fourth step of forming a second semiconductor layer of a second conductivity type on the first semiconductor layer in the flat region and the recessed region.

[0063] In the method for manufacturing a variable capacitance element unit according to this embodiment, first, a semiconductor substrate as shown in FIG. 5 is prepared. The semiconductor substrate to be prepared is a semiconductor substrate containing a known semiconductor element such as Si as a main component, and may be a semiconductor substrate of a first conductivity type doped with an impurity element. When doped with an impurity element, it is preferable that the concentration of the impurity element is lower in a region farther from the main surface S. The crystal plane of the main surface S of the semiconductor substrate is, for example, a (100) plane. Hereinafter, when the semiconductor substrate is a p-type <100> A method for manufacturing a variable capacitance element unit according to this embodiment will be described using a silicon crystal substrate as an example.

[0064] (1st step) Then, as shown in FIG. - At least one recess PB is formed in a part of the main surface S of the semiconductor substrate, and a flat region RA and a recess region RB are provided in the semiconductor substrate. In the first step, the recess PB is formed by forming an inclined surface 10 whose cross-sectional area parallel to the main surface of the semiconductor substrate becomes smaller with increasing distance from the main surface S of the semiconductor substrate. T In this first step, a plurality of recesses PB are formed in the semiconductor substrate so that the flat regions RA and the recessed regions RB are arranged in a linear or matrix pattern. In the first step, the recesses may be formed in a spot pattern on the main surface S of the semiconductor substrate, or may be formed in a groove pattern.

[0065] The recesses are formed in the first step by etching, for example. The recesses may be formed by anisotropic etching such as alkaline etching, or by isotropic etching. By performing the first step by anisotropic etching, a linear inclined surface 10 as shown in FIG. 6 is formed. T The cross section is roughly V-shaped and the slope is 10 T The inclined surface 10 can form a recess having a substantially trapezoidal cross section with a surface parallel to the main surface S. T The crystal plane of this is, for example, a (111) plane, different from the crystal plane of the main surface S. Furthermore, if the first step is performed by isotropic etching, a recess having a substantially U-shaped cross section can be formed.

[0066] (2nd process) 7, the surface layer of the semiconductor substrate is thermally oxidized to form an insulating film 20 in the flat region RA and the recessed region RB. In the second step, for example, the semiconductor substrate is heated in an air atmosphere to form a thermal oxide film SiO2 as the insulating film 20 in the flat region RA and the recessed region RB.

[0067] The main surface S of the semiconductor substrate in the flat region RA and the surface SB of the recess in the recess region RB have different crystal planes. The crystal plane of the main surface S of the semiconductor substrate is the (100) plane, and the crystal plane of the surface SB of the recess is the (111) plane. Due to the anisotropy of thermal oxidation, the thickness T of the insulating film 20B in the recess region RB in the stacking direction 20B is the thickness T of the insulating film 20A in the stacking direction in the flat region RA. 20A It is formed to be larger than

[0068] (3rd step) Next, as shown in FIG. 8, ions are implanted into the semiconductor substrate via an insulating film 20 and a single mask (not shown) having a predetermined pattern, to form a p-type first semiconductor layer 12A along the main surface S in the flat region RA of the semiconductor substrate, and a p-type first semiconductor layer 12B along the surface SB of the recess region RB.

[0069] In the third step, the impurity element to be ion-implanted is, for example, boron. In this embodiment, the mask pattern corresponds to the region where the first semiconductor layer is to be formed in a plan view of the semiconductor substrate. T Therefore, in the third step, the inclined surface 10 T The first semiconductor layer 12B is formed on the first semiconductor layer 12B.

[0070] (4th step) Next, as shown in FIG. 9, ions are implanted into the semiconductor substrate through an insulating film 20 and a single mask having a predetermined pattern, to implant n-type (N +) second semiconductor layer 13A, and an n-type second semiconductor layer 13B is formed on the first semiconductor layer 12B in the recessed region RB. That is, the second semiconductor layer 13A and the second semiconductor layer 13B are formed between the first semiconductor layer 12A and the insulating film 20A, and between the first semiconductor layer 12B and the insulating film 20B, respectively. Here, the mask pattern corresponds to the region where the second semiconductor layer is to be formed, when the semiconductor substrate is viewed from above. In the fourth step, the impurity element ion-implanted is, for example, arsenic.

[0071] The acceleration energy of the ion implantation in the fourth step is preferably greater than that of the ion implantation in the third step. For example, the ion implantation energy in the fourth step is preferably 25 KeV, and the acceleration energy of the ion implantation in the third step is preferably 15 KeV. The amount of ion implantation in the fourth step is preferably greater than that in the third step. This allows the first semiconductor layer and the second semiconductor layer to form a hyperabrupt junction.

[0072] The thickness T of the second semiconductor layer 13B in the stacking direction 13B When ions are implanted in a direction perpendicular to the main surface S of the flat region RA, the influence of channeling and the thickness of the insulating film 20 in the stacking direction are different between the flat region RA and the recessed region RB. Therefore, in the recessed region RB, the distance through which the impurity ions pass through the insulating film 20 is relatively long. Therefore, the thickness T 13A As the second semiconductor layers 13A and 13B are formed, the thickness T12B of the first semiconductor layer 12B becomes larger than the thickness T12A of the first semiconductor layer 12A.

[0073] Next, peripheral components for the flat region RA and the recessed region RB are provided, for example, by the following method. First, an insulating layer is formed on the insulating film 20. Next, necessary windows are opened in the insulating film 20 and the insulating layer, as well as in the first semiconductor layer 12 and the second semiconductor layer 13, by etching. Next, an element isolation oxide film as shown in FIG. 1 is formed. Next, a cathode contact 32 and an anode contact 37 are formed. Next, metal films such as copper and aluminum are stacked to form a cathode electrode body 31 in contact with the cathode contact 32 and an anode electrode body 36 in contact with the anode contact 37. The cathode electrode body 31 and anode electrode body 36 correspond to the cathode terminal 60 and the anode electrode terminal 65, respectively. Next, etching is performed to adjust the shapes of the cathode electrode structure 30 and the anode electrode structure 35, and an insulator is provided to insulate them, forming an insulating layer 50. This completes the manufacture of the variable capacitance element unit 100.

[0074] According to the method for manufacturing a variable capacitance element unit of this embodiment, flat and recessed regions are formed in a semiconductor substrate, and ions are implanted into the semiconductor substrate including the flat and recessed regions. This allows the ion flight distance to be adjusted by the recessed regions. Furthermore, regions with different crystal planes can be formed on the surface of the semiconductor substrate, and regions with different crystal planes can be formed on the main surface S of the semiconductor substrate. This allows the first semiconductor layer 12 or the second semiconductor layer 13 with different impurity element concentration profiles to be formed in a single process, without the need for multiple separate ion implantations by adjusting the angle or energy. This allows the variable capacitance element unit 100 including the first variable capacitance element 1A and the second variable capacitance element 1B to be easily manufactured. Furthermore, since the first variable capacitance element 1A and the second variable capacitance element 1B can be implanted simultaneously using a common mask, the manufacturing process can be simplified and costs can be reduced. The first semiconductor layer 12 has a smaller difference in impurity concentration profile between the flat and recessed regions than the second semiconductor layer 13, which will be described later. This is due to the atomic weight of the ions implanted when forming the first semiconductor layer. Since the ions of boron and the like implanted when forming the first semiconductor layer are ions of light elements, the blocking power of the insulating film and silicon substrate against boron is small, and the influence thereof is small. Therefore, the impurity concentration profile of the first semiconductor layer 12 tends to have smaller differences between the flat region and the recessed region compared to the impurity concentration profile of the second semiconductor layer 13.

[0075] Furthermore, the manufacturing method of the variable capacitance element unit according to this embodiment is not limited to the above example and can be modified as appropriate. For example, the p-type region and the n-type region may be reversed. That is, the impurity elements ion-implanted in the third and fourth steps may be interchanged.

[0076] Further, for example, after the first step is performed in the same manner as in the above example, the second step may be performed by a method different from that of the above example. FIG. 10 is a diagram for explaining a modification of the second step of FIG. 7. As shown in FIG. 10, in the second step of this modification, an insulating film is formed by depositing oxide SiO2, nitride SiN, or the like by chemical vapor deposition as the insulating film 20' in the flat region RA and the recessed region RB. Since the chemical vapor deposition method is an isotropic film formation method, the insulating film 20' in the recessed region RB has a thickness T in the stacking direction of the insulating film 20A in the flat region RA. 20A That is, the insulating film 20'B has a thickness T 20´B is the thickness T of the insulating film 20A in the stacking direction. 20A is the same size as

[0077] Next, a third step is performed in the same manner as in the above embodiment. That is, as shown in Fig. 11, ions are implanted into the semiconductor substrate via an insulating film 20 and a mask having a predetermined pattern to form a first semiconductor layer 12'. Specifically, a p-type first semiconductor layer 12A is formed along the main surface S in the flat region RA of the semiconductor substrate, and a p-type first semiconductor layer 12'B is formed in the recessed region RB.

[0078] Next, a fourth step is performed using a method similar to that of the above embodiment. That is, as shown in FIG. 12 , ions are implanted into the semiconductor substrate through the insulating film 20 and a mask having a predetermined pattern to form a second semiconductor layer 13A on the first semiconductor layer 12A in the flat region RA of the semiconductor substrate, and an n-type second semiconductor layer 13′B on the first semiconductor layer 12′B in the recessed region RB. That is, the second semiconductor layer 13A and the second semiconductor layer 13′B are formed between the first semiconductor layer 12A and the insulating film 20A, and between the first semiconductor layer 12′B and the insulating film 20′B, respectively. Even in the manufacturing method of the variable capacitance element unit according to the modified example, the second semiconductor layer 13′B in the recessed region RB has a different impurity concentration profile from the second semiconductor layer 13A in the flat region RA. The difference in impurity concentration profiles between the second semiconductor layer 13A in the flat region RA and the second semiconductor layer 13′B in the recessed region RB is due to the large atomic weight of ions such as arsenic implanted when forming the second semiconductor layer. Specifically, the insulating film and silicon substrate have a large ion nucleus stopping power against arsenic. Therefore, the flight distance of arsenic due to collision scattering with silicon is greatly affected by the insulating films 20A and 20'B through which it passes and the implantation angle. As described above, due to the difference in structure and the type of ions implanted, the second semiconductor layer 13A has a steeper impurity concentration gradient than the second semiconductor layer 13'B. Also, the thickness T of the second semiconductor layer 13'B in the stacking direction 13´B is the thickness T of the second semiconductor layer 13A in the stacking direction. 13A In the manufacturing method of the variable capacitance element unit according to the modified example, the thickness T 13´B and the thickness T of the second semiconductor layer 13A in the stacking direction 13A The difference is the thickness T 13´B and the thickness T of the second semiconductor layer 13A in the stacking direction 13A Furthermore, by forming second semiconductor layers 13A and 13'B with different profiles, first semiconductor layers 12A and 12'B also tend to have different thicknesses and profiles.

[0079] Next, an element isolation oxide film, an insulating layer, an anode electrode, a cathode electrode, etc. are formed using the same method as in the above embodiment to manufacture a variable capacitance element unit. Thus, even with the manufacturing method for a variable capacitance element unit according to the modified example, the projection distance of the doping ions can be adjusted using the recesses. Therefore, it is not necessary to provide separate masks for the flat region RA and the recessed region RB for ion implantation. This makes it possible to form the first semiconductor layer 12' or the second semiconductor layer 13' with different impurity element concentration profiles in a single process. Therefore, a variable capacitance element unit having a first variable capacitance element and a second variable capacitance element can be easily manufactured. Note that the difference in the impurity element concentration profiles between the first variable capacitance element and the second variable capacitance element in the variable capacitance element unit manufactured according to the modified example is smaller than the difference in the impurity element concentration profiles between the first variable capacitance element and the second variable capacitance element manufactured by the manufacturing method for a variable capacitance element unit according to the above embodiment. Therefore, by selecting a manufacturing method according to specifications and applications, a variable capacitance element unit with desired characteristics can be manufactured.

[0080] FIG. 13 is an example of a circuit diagram of a voltage-controlled oscillator 200 including the variable capacitance element unit 100 of the above embodiment. The voltage-controlled oscillator 200 includes, for example, an internal circuit 71, a resistor 72, a protection diode 73, a VDD terminal 74, an input terminal 75, a VSS terminal 76, and the variable capacitance element unit 100. The voltage at the VDD terminal is the ground voltage, and the voltage at the VSS terminal is the power supply voltage. In the voltage-controlled oscillator 200, the internal circuit 71 is provided between the VDD terminal 74 and the VSS terminal 76. This internal circuit 71 is configured with a general oscillator circuit, such as an inverting amplifier and a feedback resistor. The input terminal 75 is a terminal to which a piezoelectric resonator such as a crystal is connected to the internal circuit 71 via a resistor 72, and the variable capacitance element unit 100 is provided between this input terminal 75 and the VSS terminal 76. Although not shown, a control voltage is applied to input terminal 75 of first variable capacitance element 1A and second variable capacitance element 1B of variable capacitance element unit 100 via another terminal, thereby adjusting the capacitance value. Furthermore, a protection diode 73 is provided as a protection element between VDD terminal 74 and VSS terminal 76. Terminals a and b shown in FIG. 13 correspond to cathode electrode terminal 60 and anode terminal 65 shown in FIG. 1, respectively.

[0081] So far, the variable capacitance element unit, the manufacturing method thereof, and the voltage controlled oscillator using the variable capacitance element unit have been described, but the characteristic configurations of the above-described embodiments and modifications may be combined with each other. [Example]

[0082] Examples of the present invention will be described below, but the present invention is not limited to the following examples.

[0083] [Manufacturing Example 1] In Manufacturing Example 1, a silicon substrate was heated in a nitrogen-diluted dry oxygen atmosphere to form a thermal oxide film on the (100) surface of the silicon substrate, and the change in thickness over time in the stacking direction was simulated using Silvaco's TCAD "ATHENA." In Manufacturing Example 1, the simulation was performed under the condition that the heating temperature was 900°C.

[0084] [Manufacturing Example 2] The same procedures as in Production Example 1 were carried out except that a simulation was performed to see how the thickness in the stacking direction changes over time when a thermal oxide film is formed on the (111) plane of a silicon substrate.

[0085] The results of Production Examples 1 and 2 are shown in Figure 14. In Figure 14, the time when the temperature inside the furnace reached 900°C corresponds to 0 minutes in the film formation time. As shown in Figure 14, the thickness of the thermal oxide film increases in proportion to the film formation time, i.e., the diffusion time. Production Examples 1 and 2 confirmed that when the (100) and (111) surfaces of a silicon substrate are heated in air for the same time, the thickness of the thermal oxide film formed on the (111) surface is greater than the thickness of the thermal oxide film formed on the (100) surface.

[0086] [Manufacturing Example 3] As Manufacturing Example 3, the same simulation software as in Manufacturing Example 1 was used to determine the impurity concentration profile in the substrate depth direction of a variable capacitance element manufactured under the following conditions.

[0087] A recess with a roughly V-shaped cross section was formed in a silicon substrate, a thermal oxide film was formed on the (111) surface of the substrate, and ion implantation was performed to form a p- first semiconductor layer and an n+ second semiconductor layer between the silicon substrate and the thermal oxide film. Specifically, anisotropic etching was first performed on the silicon substrate using an alkaline solution to form a recess with a depth of 5 μm, with the (111) surface as the inclined surface. Next, the substrate was heated in a diffusion furnace in an atmosphere containing dry oxygen to form a thermal oxide film with a thickness of 345 Å. Next, B ions were implanted onto the silicon substrate through the thermal oxide film at a dose of 5.0 × 10 with an acceleration energy of 15 keV. 13 pieces / cm 2 Then, As ions were implanted into the silicon substrate through the thermal oxide film at a dose of 5.0 × 10 with an acceleration energy of 20 keV. 15 pieces / cm 2 The second semiconductor layer was formed on the first semiconductor layer by ion implantation.

[0088] [Manufacturing Example 4] In Manufacturing Example 4, the same simulation software as in Manufacturing Example 1 was used to determine the impurity concentration profile in the substrate depth direction of a variable capacitance element manufactured under the following conditions. The same procedure as in Production Example 3 was carried out except that a thermal oxide film was formed on the (100) surface of the silicon substrate, which is the surface on which no recesses were formed. Production Examples 4 and 3 were carried out using the same substrate, and the flat region on which no recesses were formed was designated Production Example 4. That is, a thermal oxide film with a thickness of 250 Å was formed on the (100) surface of the silicon substrate, which is the surface on which no recesses were formed, by the same method as in Production Example 3. Next, ion implantation was carried out through the thermal oxide film under the same conditions as in Production Example 3, to form a first semiconductor layer and a second semiconductor layer between the silicon substrate and the thermal oxide film.

[0089] FIG. 15 shows the simulation results of the relationship between the substrate depth and the impurity concentration of the variable capacitance element obtained in Manufacturing Examples 3 and 4, and FIG. 16 shows the simulation results of the distribution of the impurity concentration of the variable capacitance element obtained in Manufacturing Examples 3 and 4.

[0090] In Manufacturing Example 3, the impurity concentration in the second semiconductor layer, which is approximately 0.03 μm thick, decreases continuously, and a pn junction surface is formed at a depth of approximately 0.035 μm (symbol xj in FIG. 15). The impurity concentration of the first semiconductor layer in Manufacturing Example 3 increases sharply in a region up to a depth of 0.085 μm, which is a region (first region) slightly separated from the pn junction surface in a direction away from the thermal oxide film, and reaches its highest (maximum value) at a depth of approximately 0.085 μm. The impurity concentration in the first semiconductor layer decreases in a region from 0.085 μm to 0.30 μm deep (second region). The impurity concentration gradient in the first region (depth 0.035 μm to 0.085 μm) in Manufacturing Example 3 is 2.5×10 19 (pcs / cm 3 ·μm), and the impurity concentration gradient in the second region (depth 0.085μm to 0.30μm) is -5.8×10 18 (pcs / cm 3 The particle size was 1 μm.

[0091] In FIG. 15, the interface between the second semiconductor layer and the thermal oxide film is set to a depth of 0 μm. In Manufacturing Example 4, the impurity concentration in the second semiconductor layer, which is approximately 0.1 μm thick, decreases continuously, and a pn junction surface is formed at a depth of approximately 0.1 μm (symbol xj in FIG. 15). The impurity concentration of the first semiconductor layer in Manufacturing Example 4 increases sharply in a region (first region) that is approximately 0.12 μm from the pn junction surface and is spaced away from the thermal oxide film, reaches its highest position at a depth of approximately 0.12 μm in the first semiconductor layer, and then decreases sharply toward a region (second region) from a depth of approximately 0.12 μm to 0.28 μm. The concentration gradient of the impurity concentration in the first region (depth 0.10 μm to 0.12 μm) in Manufacturing Example 4 is 3.2×10 19 (pcs / cm 3 ·μm), and the concentration gradient of the impurity concentration in the second region (depth 0.12μm to 0.28μm) is -4.0×10 18 / cm 3 The thickness was 1 μm.

[0092] 15 and 16, it was confirmed that the first semiconductor layer of Production Example 4 had a steeper impurity concentration gradient than the first semiconductor layer of Production Example 3. Furthermore, the impurity concentration of the second semiconductor layer was lower in Production Example 3, and the position of the pn junction surface was shallower in Production Example 3. As such, it can be seen that Production Example 4 and Production Example 3 have different impurity concentration profiles.

[0093] [Example 1] In Example 1, a variable capacitance element unit was manufactured in which four first variable capacitance elements and one second variable capacitance element were connected in parallel. Specifically, a portion of a silicon substrate was etched to form one recess with a substantially V-shaped cross section, and flat regions and one recess with a substantially V-shaped cross section arranged in a matrix were formed. The silicon substrate was then heated in a diffusion furnace in an atmosphere containing dry oxygen to form thermal oxide films in the flat and recessed regions. Next, ions were implanted into the silicon substrate through the thermal oxide film to form a first semiconductor layer on the silicon substrate, and a second semiconductor layer on the first semiconductor layer. The flat and recessed regions were formed under the same conditions as in Comparative Example 2 and Example 2, respectively. Next, an insulating layer, an element isolation oxide film, a cathode electrode, and an anode electrode were formed, and the four first variable capacitance elements and one second variable capacitance element formed in the flat region were wired in parallel.

[0094] In Example 1, when the silicon substrate is viewed from above, the ratio A1:A2 of the total area A1 of the four first variable capacitance elements to the total area A2 of one second variable capacitance element is set to 1:4.

[0095] [Comparative Example 1] The manufacturing process was the same as in Example 1, except that a variable capacitance element unit in which five second variable capacitance elements were connected in parallel was manufactured. That is, the variable capacitance element unit of Comparative Example 1 was composed only of variable capacitance elements having recessed regions, and each variable capacitance element was manufactured by the same method as in Manufacturing Example 3.

[0096] Comparative Example 2 The manufacturing process was the same as in Example 1, except that a variable capacitance element unit in which five first variable capacitance elements were connected in parallel was manufactured. That is, the variable capacitance element unit of Comparative Example 2 was composed only of variable capacitance elements having flat regions, and each variable capacitance element was manufactured by the same method as in Manufacturing Example 4.

[0097] A reverse bias voltage was applied to the varactor capacitance element units of Example 1, Comparative Example 1, and Comparative Example 2, and the capacitance variable ratio (C / C0) of the varactor capacitance element units was determined by changing the reverse bias voltage. The changes in the capacitance variable ratio of the varactor capacitance element units of Example 1, Comparative Example 1, and Comparative Example 2 are shown in Fig. 17. In Fig. 17, C0 represents the capacitance when no bias voltage is applied, and C represents the capacitance when a reverse bias voltage is applied.

[0098] 17, it was found that the variable capacitance element unit of Comparative Example 1 had a small capacitance variable ratio, and that the variable capacitance element unit of Comparative Example 2 had low linearity in the profile of the capacitance variable ratio with respect to changes in the reverse bias voltage. In contrast, it was found that the variable capacitance element unit of Example 1 had a large capacitance variable ratio and high linearity in the profile of the capacitance variable ratio with respect to changes in the bias voltage. [Explanation of symbols]

[0099] 10: semiconductor substrate, 10 T : inclined surface, 11: base substrate, 12, 12', 12A, 12B, 12'B: first semiconductor layer, 13, 13', 13A, 13B, 13'B: second semiconductor layer, 19: pn junction surface, 20: insulating film, 30: cathode electrode structure, 31: cathode electrode body, 32: cathode contact, 35: anode electrode structure, 36: anode electrode body, 37: anode contact, 40: element isolation oxide film, 50: insulating layer, 60: cathode electrode terminal, 65: anode electrode terminal, 100: variable capacitance element unit, PB: recess, RA: flat region, RB: recessed region, S: main surface of semiconductor substrate, SB: surface of recessed region

Claims

1. At least one first variable capacitance element and at least one second variable capacitance element having a capacitance variable ratio different from that of the first variable capacitance element, both formed on the same semiconductor substrate; the semiconductor substrate has a flat region including a part of a main surface of the semiconductor substrate and in which the at least one first variable capacitance element is formed, and a recessed region including a recess provided in the main surface of the semiconductor substrate and in which the at least one second variable capacitance element is formed, the first variable capacitance element includes a first semiconductor layer of a first conductivity type formed along a major surface of the semiconductor substrate in the flat region of the semiconductor substrate, and a second semiconductor layer of a second conductivity type formed on the first semiconductor layer; The second variable capacitance element is a variable capacitance element unit having a first semiconductor layer of a first conductivity type formed along a surface within the recess in the recess region of the semiconductor substrate, and a second semiconductor layer of a second conductivity type formed on the first semiconductor layer.

2. the recess has an inclined surface that reduces a cross-sectional area of ​​the recess perpendicular to a stacking direction with increasing distance from the main surface of the semiconductor substrate, The variable capacitance element unit according to claim 1 , wherein the first semiconductor layer and the second semiconductor layer of the second variable capacitance element are formed on an inclined surface of the recess.

3. The variable capacitance element unit according to claim 2 , wherein the recess is a groove having a substantially V-shaped cross section.

4. 4. The variable capacitance element unit according to claim 1, wherein a thickness in a stacking direction of the second semiconductor layer in the second variable capacitance element is smaller than a thickness in a stacking direction of the second semiconductor layer in the first variable capacitance element.

5. the first variable capacitance element further includes an insulating film formed on the second semiconductor layer of the first variable capacitance element, 5. The variable capacitance element unit according to claim 1, wherein the second variable capacitance element further comprises an insulating film formed on the second semiconductor layer of the second variable capacitance element.

6. the insulating film in the first variable capacitance element and the insulating film in the second variable capacitance element are thermal oxide films; The variable capacitance element unit according to claim 5 , wherein the thickness of the insulating film in the stacking direction of the second variable capacitance element is greater than the thickness of the insulating film in the stacking direction of the first variable capacitance element.

7. 6. The variable capacitance element unit according to claim 5, wherein the insulating film in the first variable capacitance element and the insulating film in the second variable capacitance element are vapor-deposited films, and the thickness of the insulating film in the second variable capacitance element in the stacking direction is the same as the thickness of the insulating film in the first variable capacitance element in the stacking direction.

8. the at least one first variable capacitance element and the at least one second variable capacitance element are arranged in a line or a matrix on the semiconductor substrate; The variable capacitance element unit according to any one of claims 1 to 7, wherein when the semiconductor substrate is viewed in a plane, the ratio (A1:A2) of the total area A1 of the at least one first variable capacitance element to the total area A2 of the at least one second variable capacitance element is 1:9 to 9:

1.

9. a first step of forming at least one recess in a portion of a main surface of a semiconductor substrate to provide a flat region and a recessed region in the semiconductor substrate; a second step of forming an insulating film in the flat region and the recessed region of the semiconductor substrate; a third step of implanting ions into the semiconductor substrate through the insulating film to form a first semiconductor layer of a first conductivity type in the flat region and the recessed region of the semiconductor substrate; and a fourth step of implanting ions into the semiconductor substrate via the insulating film to form a second semiconductor layer of a second conductivity type on the first semiconductor layer in the flat region and the recessed region of the semiconductor substrate.

10. In the first step, the recess is formed to have an inclined surface whose cross-sectional area parallel to the main surface of the semiconductor substrate decreases with increasing distance from the main surface of the semiconductor substrate; and in the third step, the first semiconductor layer is formed on the inclined surface in the recess region.

10. The method for manufacturing a variable capacitance element unit according to claim 9, wherein in the fourth step, the second semiconductor layer is formed on the first semiconductor layer.

11. 11. The method for manufacturing a variable capacitance element unit according to claim 9, wherein in the second step, a surface layer portion of the semiconductor substrate is thermally oxidized to form a thermal oxide film in the flat region and the recessed region.

12. 11. The method for manufacturing a variable capacitance element unit according to claim 9, wherein in the second step, an insulating film made of an oxide or nitride of a semiconductor material is formed in the flat region and the recessed region by vapor phase growth.

13. 13. The method for manufacturing a variable capacitance element unit according to claim 9, wherein in the first step, the at least one recess is formed in plurality so that the flat region and the recess region are arranged in a linear or matrix pattern.

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