Semiconductor device and manufacturing method thereof

Abstract

To provide a semiconductor device with a configuration suitable for miniaturization and a method for manufacturing the semiconductor device.SOLUTION: A semiconductor device comprises a transistor including a gate insulating film formed on a semiconductor substrate, a gate electrode formed on the gate insulating film and containing germanium at least in its upper portion, a source region formed on the semiconductor substrate, and a drain region formed on the semiconductor substrate.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present embodiment relates to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] It is desirable for transistors to have small variations in threshold voltage. Patent Document 1 discloses a transistor in which the positional relationship between the source / drain regions and contacts of the transistor is specified to suppress variations in threshold voltage. Patent Document 2 also discloses a transistor in which the source / drain regions are selectively pre-amorphized, but the gate electrode is not pre-amorphized, thereby suppressing variations in threshold voltage that occur with miniaturization. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2020-027865 [Patent Document 2] Special Publication No. 2010-532572 Summary of the Invention [Problem to be solved by the invention]

[0004] According to the present embodiment, a semiconductor device having a configuration suitable for miniaturization and a method for manufacturing the semiconductor device are provided. [Means for solving the problem]

[0005] This embodiment provides a semiconductor device including a transistor including a gate insulating film formed on a semiconductor substrate, a gate electrode formed on the gate insulating film and containing germanium in at least a portion of an upper part thereof, a source region formed in the semiconductor substrate, and a drain region formed in the semiconductor substrate.

[0006] The present embodiment provides a method for manufacturing a semiconductor device, which includes forming a gate insulating film having a first thickness in a first region on a semiconductor substrate, forming an insulating film having a second thickness larger than the first thickness and partially including the second gate insulating film in a second region on the semiconductor substrate, forming a gate electrode on the gate insulating film, forming a second gate electrode on the second gate insulating film, forming spacer insulating films on the semiconductor substrate and the gate electrode in the first region and on the insulating film and the second gate electrode in the second region, and injecting germanium through the spacer insulating film to form an amorphous structure in an upper portion of the semiconductor substrate and an upper portion of the gate electrode in the first region, and to form an amorphous structure in an upper portion of the second gate electrode in the second region.

[0007] The present embodiment provides a method for manufacturing a semiconductor device, including forming a gate insulating film in a first region on a semiconductor substrate, forming a second gate insulating film in a second region on the semiconductor substrate, forming a gate electrode on the gate insulating film, forming a second gate electrode on the second gate insulating film, forming first and second sidewalls on side surfaces of the gate electrode and forming third and fourth sidewalls on side surfaces of the second gate electrode, forming a first resist film on the gate electrode in the first region to cover the second sidewalls and expose a first upper end portion close to the first sidewall, forming a second resist film on the second gate electrode in the second region to cover the third and fourth sidewalls and expose an intermediate portion of an upper portion of the second gate electrode, and implanting germanium through the first resist film and the second resist film to amorphize the first upper end portion of the gate electrode in the first region and the intermediate portion of the second gate electrode in the second region.

[0008] The steps described in the above method for manufacturing a semiconductor device are not in any particular order and can be modified within the scope that can be reasonably conceived by a person skilled in the art. [Brief explanation of the drawings]

[0009] [Figure 1]FIG. 1 is a cross-sectional view schematically illustrating the configuration of a transistor included in a semiconductor device according to an embodiment. [Figure 2] FIG. 2 is a schematic diagram showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 3] FIG. 3 is a schematic diagram showing a method for manufacturing a semiconductor device according to an embodiment. [Figure 4] FIG. 4 is a cross-sectional view schematically showing the configuration of a transistor included in a semiconductor device according to another embodiment. [Figure 5] FIG. 5 is a schematic diagram showing a method for manufacturing a semiconductor device according to another embodiment. [Figure 6] FIG. 6 is a schematic diagram showing a method for manufacturing a semiconductor device according to another embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, the present embodiment will be described with reference to the accompanying drawings. To facilitate understanding of the description, the same components in the drawings will be denoted by the same reference numerals as much as possible, and duplicated descriptions will be omitted.

[0011] [First embodiment]

[0012] FIG. 1 is a cross-sectional view schematically illustrating the configuration of a transistor included in a semiconductor device 100 according to the first embodiment. As shown in the figure, the semiconductor device 100 includes two types of transistors. One of the transistors is a VLV (Very Low Voltage) transistor 10. The other is an HV (High Voltage) transistor 20. The VLV transistor 10 and the HV transistor 20 constitute transistors of a CMOS logic circuit formed on the same semiconductor substrate W, for example. However, the VLV transistor 10 and the HV transistor 20 may be formed on different semiconductor substrates.

[0013] The HV transistor 20 can be used at a higher voltage than the VLV transistor 10. Therefore, the HV transistor 20 can be formed in an area AR2 (sometimes called the "second area AR2") on the semiconductor substrate W where circuits operating at a relatively high voltage are provided, and the VLV transistor 10 can be formed in another area (sometimes called the "first area AR1"). The second area AR2 where the HV transistor 20 is provided and the first area AR1 where the VLV transistor 10 is provided are separated by, for example, STI or the like. The configuration of each transistor will be described below.

[0014] [VLV transistor]

[0015] The VLV transistor includes a first gate insulating film 10GI formed on a semiconductor substrate W, a first gate electrode 10GC (sometimes referred to as a "gate contact") formed on the first gate insulating film 10GI, and a first source region 10S and a first drain region 10D formed in the semiconductor substrate W. The VLV transistor further includes a first sidewall 11S provided opposite one side of the first gate electrode 10GC and a second sidewall 12S provided opposite the other side of the first gate electrode 10GC. The semiconductor device 100 further includes a source contact, a drain contact, and a gate contact electrically connected to the first source region 10S, the first drain region 10D, and the first gate electrode 10GC, respectively, as well as an insulating layer for insulating the VLV transistor and other transistors. The present invention is applicable to both N-type and P-type transistors.

[0016] The semiconductor substrate W is, for example, a P-type or N-type silicon wafer.

[0017] The first gate insulating film 10GI has a film thickness T1 (an example of a "first film thickness") of, for example, 0.5 nm to 1 nm (e.g., 0.8 nm). The gate length of the first gate insulating film 10GI is, for example, 50 nm to 100 nm (e.g., 50 nm). The gate insulating film including the first gate insulating film 10GI is formed of, for example, SiO2 or SiN.

[0018] A first gate electrode 10GC is formed on the first gate insulating film 10GI. The first gate electrode 10GC has a height of, for example, 50 to 150 nm (e.g., 100 nm). The first gate electrode 10GC and other gate electrodes are formed of, for example, polysilicon. An upper region 10GCU of the first gate electrode 10GC is implanted with germanium (Ge) and made amorphous by pre-amorphization implants (hereinafter, sometimes referred to as "PAI"), as will be described later. Note that a lower region of the first gate electrode 10GC is substantially free of germanium because it is only affected by, or is not affected by, PAI.

[0019] The first source region 10S is a P-type diffusion region in which, for example, boron (B) is implanted and diffused. Of the first source region 10S, an upper source region 10SU provided near the surface of the semiconductor substrate W is implanted with germanium (Ge) by PAI and made amorphous. Of the first source region 10S, a lower source region 10SL provided at a position farther from the semiconductor substrate surface than the upper source region 10SU is either only partially affected by PAI or is not affected by PAI, and therefore does not substantially contain germanium.

[0020] In this way, the upper source region 10SU of the first source region 10S is made amorphous, and therefore it is possible to suppress the diffusion of impurities (boron in this embodiment) and to suppress variations in the characteristics of the transistor.

[0021] The first drain region 10D is a P-type diffusion region in which, for example, boron (B) is implanted and diffused. Of the first drain region 10D, an upper drain region 10DU provided near the surface of the semiconductor substrate W is implanted with germanium (Ge) and made amorphous by PAI. Of the first drain region 10D, a lower drain region 10DL provided at a position farther from the surface of the semiconductor substrate W than the upper drain region 10DU is affected by PAI to a limited extent or is not affected by PAI, and therefore does not substantially contain germanium.

[0022] In this way, the upper drain region 10DU of the first drain region 10D is made amorphous, and therefore it is possible to suppress the diffusion of impurities (boron in this embodiment) and to suppress variations in the characteristics of the transistor.

[0023] [HV transistor]

[0024] The HV transistor 20 is formed in the second region AR2 of the semiconductor substrate W where the VLV transistor 10 is formed. The HV transistor 20 includes a second gate insulating film 20GI, a second gate electrode 20GC formed on the second gate insulating film 20GI and containing germanium at least in an upper portion thereof, a second source region 20S formed in the semiconductor substrate W, and a second drain region 20D formed in the semiconductor substrate W. The HV transistor 20 further includes a third sidewall 23S provided opposite one side surface of the second gate electrode 20GC, and a fourth sidewall 24S provided opposite the other side surface of the second gate electrode 20GC. The semiconductor device 100 further includes a source contact, a drain contact, and a gate contact electrically connected to the second source region 20S, the second drain region 20D, and the second gate electrode 20GC, respectively, and an insulating layer or the like stacked on the semiconductor substrate W to insulate the HV transistor 20 and other transistors. The HV transistor 20 has a different configuration from the VLV transistor 10 in that the third sidewall 23S and the fourth sidewall 24S are formed on the second gate insulating film 20GI, in that the HV transistor 20 has a different configuration from the VLV transistor 10 in which the first gate insulating film 10GI is formed between the first sidewall and the second sidewall. The second gate insulating film 20GI has a thickness greater than that of the first gate insulating film 10GI, and has a thickness T2 (an example of "second film thickness") of, for example, 1 nm to 5 nm (e.g., 3 nm). The gate length of the second gate insulating film 20GI may be greater than that of the first gate insulating film 10GI, and is, for example, 10 nm to 100 nm (e.g., 50 nm).

[0025] A second gate electrode 20GC is formed on the second gate insulating film 20GI. The second gate electrode 20GC may be formed to have the same height as the first gate electrode 10GC, and as an example, has a height of 50 to 150 nm (e.g., 100 nm). An upper region 20GCU of the second gate electrode 20GC is implanted with germanium (Ge) by PAI and is made amorphous. Note that a lower region of the second gate electrode 20GC is substantially free of germanium because the influence of PAI is limited or not affected by PAI.

[0026] The second source region 20S is a P-type diffusion region in which, for example, boron (B) is implanted and diffused. Unlike the first source region 10S, the entire region including the upper region of the second source region 20S is substantially free of germanium because the influence of PAI is limited or not affected by PAI. An LDD (Lightly Doped Drain) is formed around the periphery of the second source region 20S.

[0027] The second drain region 20D is a P-type diffusion region in which, for example, boron (B) is implanted and diffused. Unlike the first drain region 10D, the entire region including the upper region of the second drain region 20D is substantially free of germanium because the influence of PAI is limited or not affected by PAI. An LDD (Lightly Doped Drain) is formed around the periphery of the second drain region 20D.

[0028] In the HV transistor 20 configured as described above, at least a portion of the upper region of the second gate electrode 20GC is implanted with germanium (Ge) and made amorphous by PAI. Therefore, during implantation to form an LDD (Lightly Doped Drain), it is possible to suppress the dopant from passing through the second gate electrode 20GC and being implanted into the channel region of the semiconductor substrate W, which would otherwise cause fluctuations in the threshold voltage.

[0029] That is, the inventors of the present application noticed that, in order to suppress transistor miniaturization, it is necessary to reduce the height of the gate electrode as the gate length is miniaturized in order to improve the aspect ratio, particularly of VLV transistors, but when the height of the gate electrode is reduced, dopants pass through the gate electrode and are implanted into the channel region of the semiconductor substrate, causing a problem of threshold voltage fluctuation, particularly when forming an LDD in an HV transistor. Therefore, they came up with a configuration that can suppress the situation where dopants pass through the gate electrode by applying PAI to the gate electrode (particularly the second gate electrode of an HV transistor) to implant germanium (Ge) and amorphizing at least a portion of the upper part of the gate electrode.

[0030] This configuration makes it possible to prevent the dopant from passing through the gate electrode and being implanted into the channel region of the semiconductor substrate, thereby making it possible to provide a semiconductor device that can suppress threshold fluctuations during miniaturization.

[0031] Unlike the gate electrode (second gate electrode 20GC), PAI is not applied to the diffusion layers (second source region 20S and second drain region 20D) of the HV transistor 20. This makes it possible to suppress GIDL (Gate-Induced-Drain-Leakage current).

[0032] As described above, the semiconductor device according to this embodiment includes two types of transistors. For transistors with relatively thin gate insulating films (VLV transistors), PAI is applied to the diffusion layers (source and drain regions) to suppress impurity diffusion, thereby improving the characteristics. On the other hand, for transistors with relatively thick gate insulating films (HV transistors), GIDL can be suppressed by not applying PAI to the diffusion layers (source and drain regions). In addition, applying PAI to the gate electrode makes it possible to suppress threshold voltage fluctuations associated with LDL formation.

[0033] [Manufacturing method]

[0034] A method for manufacturing the semiconductor device 100 according to this embodiment will now be described. Figures 2 and 3 are schematic diagrams illustrating a method for manufacturing the semiconductor device 100 according to this embodiment. As shown in Figure 2(A), first, an insulating film that will become the first gate insulating film 10GI is formed in a first region AR1 on the semiconductor substrate W by oxidizing the surface of the semiconductor substrate W or the like. Similarly, an insulating film that will become the second gate insulating film 20GI having a thickness T2 that is larger than the thickness T1 of the first gate insulating film 10GI is formed in a second region AR2 on the semiconductor substrate W.

[0035] Next, a polysilicon film that will later become the first gate electrode 10GC and the second gate electrode 20GC is formed on each of the insulating films in the first region AR1 and the second region AR2 by, for example, CVD. Then, by patterning and removing a portion of the polysilicon film, a first gate insulating film 10GI having a thickness T1 and a first gate electrode 10GC on the first gate insulating film 10GI are formed in the first region AR1.

[0036] Furthermore, by patterning and removing a portion of the polysilicon film, a second gate electrode 20GC is formed on the insulating film that will become the second gate insulating film 20GI. Here, by leaving the second gate insulating film 20GI on the semiconductor substrate W without removing it, it is possible to form an insulating film with a thickness T2 that partially encompasses the second gate insulating film 20GI in the second region AR2, as shown in FIG.

[0037] Next, as shown in Fig. 1B, a spacer insulating film SI, which will later form sidewalls, is formed in the first region AR1 and the second region AR2 of the semiconductor substrate W. Specifically, the spacer insulating film SI is deposited by, for example, CVD on the semiconductor substrate W and the first gate electrode 10GC in the first region AR1, and on the insulating film and the second gate electrode 20GC in the second region AR2.

[0038] Next, as shown in FIG. 1C, PAI is performed on the semiconductor device 100 covered with the spacer insulating film SI. Specifically, germanium is implanted through the spacer insulating film SI to cause germanium to be contained in the upper part of the semiconductor substrate W in the first region AR1 (regions corresponding to the upper source region 10SU and the upper drain region 10DU later) and to make this portion amorphous. Also, germanium is implanted into the region 10GCU above the first gate electrode 10GC to make this portion amorphous.

[0039] At the same time, germanium is implanted into the region 20GCU above the second gate electrode 20GC in the second region AR2 to amorphize this portion. However, at this time, the upper portion of the semiconductor substrate W in the second region AR2 (the portion corresponding to the upper portion of the second source region 20S and the upper portion of the second drain region 20D) is covered with a thick insulating film provided below the spacer insulating film SI, so germanium is not implanted and the region is not amorphized. In other words, by performing PAI to implant germanium at an acceleration voltage that penetrates the spacer insulating film SI but does not penetrate the insulating film below it, it is possible to manufacture a transistor having the configuration shown in FIG. 1.

[0040] As a result of the above process, it is possible to form two or more types of transistors on the same semiconductor substrate W: a transistor containing germanium in the upper part of the gate electrode and in the upper part of the diffusion layer (source and drain regions) (VLV transistor), and a transistor containing germanium in the upper part of the gate electrode but not in the diffusion layer (HV transistor).

[0041] Thereafter, as shown in FIG. 3A, for example, the spacer insulating film SI formed on the entire surface is etched back by anisotropic etching such as RIE, thereby removing the spacer insulating film so that portions corresponding to the sidewalls remain.

[0042] Then, as shown in FIG. 1B, a dopant (e.g., phosphorus) is implanted to form an LDD. At this time, since the upper portion of the second gate electrode 20GC is made amorphous, at least a portion of the dopant is blocked by the second gate electrode 20GC. This makes it possible to prevent the threshold voltage from fluctuating due to the dopant being implanted into the channel region.

[0043] Thereafter, a diffusion layer and the like are formed in accordance with a known method, thereby making it possible to provide the transistor shown in FIG.

[0044] [Second embodiment]

[0045] The second embodiment will be described below. Explanations of parts that will be understood by those skilled in the art to have the same configuration as the first embodiment will be omitted or simplified, and the description will focus on parts that are different from the first embodiment.

[0046] 4A and 4B are cross-sectional views schematically illustrating the configuration of an HV transistor included in a semiconductor device 200 according to the second embodiment. The HV transistor 30 shown in FIG. 4A and the HV transistor 40 shown in FIG. 4B may be formed on the same semiconductor substrate W, or on different semiconductor substrates. For example, the HV transistor 30 shown in FIG. 4A may be provided in a periphery constituting a peripheral circuit of a semiconductor memory, and the HV transistor 40 shown in FIG. 4B may be provided in a core portion of the semiconductor memory on the same semiconductor substrate W. Furthermore, the VLV transistor 10 shown in the first embodiment may also be provided on the same semiconductor substrate W.

[0047] The transistor according to this embodiment has a configuration in which only a portion of the upper portion of the gate electrode is amorphous and contains germanium, and the other portion is polycrystalline and contains substantially no germanium.

[0048] Also, the HV transistor 30 shown in FIG. 1B has a source and a drain arranged symmetrically, whereas the HV transistor 40 shown in FIG. 1A has a source and a drain arranged asymmetrically.

[0049] The HV transistor 30 shown in FIG. 2B includes a first gate insulating film 30GI formed on a semiconductor substrate W, a first gate electrode 30GC formed on the first gate insulating film 30GI, and a first source region 30S and a first drain region 30D formed in the semiconductor substrate W. The HV transistor 30 further includes a first sidewall 31S provided opposite one side of the first gate electrode 30GC, and a second sidewall 32S provided opposite the other side of the first gate electrode 30GC. The semiconductor device 200 further includes a source contact, a drain contact, and a gate contact electrically connected to the first source region 30S, the first drain region 30D, and the first gate electrode 30GC, respectively, as well as an insulating layer for insulating the HV transistor and other transistors.

[0050] Of the region 30U above the first gate electrode 30GC, an intermediate portion 30UM corresponding to an intermediate region between the first sidewall 31S and the second sidewall 32S is made of an amorphous material containing germanium.

[0051] On the other hand, in the region 30U above the first gate electrode 30GC, the first upper end portion 30U1, which is closer to the first sidewall than the intermediate portion 30UM, is polycrystalline and does not substantially contain germanium.

[0052] Similarly, in the region 30U above the first gate electrode 30GC, a second upper end portion 30U2 closer to the second sidewall 32S than the intermediate portion 30UM is polycrystalline and does not substantially contain germanium.

[0053] Furthermore, in the semiconductor substrate W, an LDD (source LDD) is formed in a region below the first upper end portion 30U1, and an LDD (drain LDD) is formed in a region below the second upper end portion 30U2.

[0054] According to the HV transistor 30 configured as described above, the middle portion 30UM of the upper portion 30U of the first gate electrode 30GC is amorphous, so that it is possible to prevent dopants (e.g., phosphorus) from passing through the middle portion 30UM and being implanted into the channel region during LDD formation.

[0055] In addition, since it is possible to form an LDD below the end of the first gate insulating film 30GI, it is possible to suppress GIDL.

[0056] On the other hand, the HV transistor 40 shown in FIG. 1A includes a first gate insulating film 40GI formed on a semiconductor substrate W, a first gate electrode 40 formed on the first gate insulating film, and a first source region 40S and a first drain region 40D formed in the semiconductor substrate. The HV transistor 40 further includes a first sidewall 41S provided opposite one side of the first gate electrode 40GC and a second sidewall 42S provided opposite the other side of the first gate electrode 40GC. The semiconductor device 200 further includes a source contact, a drain contact, and a gate contact electrically connected to the first source region 40S, the first drain region 40D, and the first gate electrode 40GC, respectively, as well as an insulating layer for insulating the HV transistor 40 and other transistors.

[0057] In the region 40U above the first gate electrode 40GC, an intermediate portion 40UM corresponding to an intermediate region between the first sidewall 41S and the second sidewall 42S is made of an amorphous material containing germanium.

[0058] In addition, in the region 40U above the first gate electrode 40GC, the first upper end portion 40U1, which is closer to the first sidewall 41S than the intermediate portion 40UM, is also made of an amorphous material containing germanium.

[0059] On the other hand, in the upper portion 40U of the first gate electrode 40GC, a second upper end portion 40U2 that is closer to the second sidewall 42S than the intermediate portion 40UM is polycrystalline and does not substantially contain germanium.

[0060] In addition, in the semiconductor substrate W, an LDD (source LDD) is not formed in the region below the first upper end 40U1, while an LDD (drain LDD) is formed in the region below the second upper end 42US.

[0061] In addition, the upper source region 40SU of the first source region 40S near the surface of the semiconductor substrate W is implanted with germanium (Ge) by PAI and made amorphous, and therefore forms a shallow LDD.

[0062] On the other hand, unlike the first source region, the first drain region 40D does not contain substantially germanium throughout its entire region. Furthermore, the first drain region is formed deeper than the first source region.

[0063] In the HV transistor 40 configured as described above, a relatively shallow LDD is formed in the first source region 40S, which makes it possible to suppress the short channel effect (SCE). Also, a relatively deep LDD is formed in the first drain region 40D, which makes it possible to suppress GIDL. This makes it possible to apply the HV transistor 40 to circuits (e.g., core parts) that require high amplification.

[0064] A method for manufacturing the semiconductor device 200 according to this embodiment will now be described. Figures 5 and 6 are schematic diagrams illustrating the method for manufacturing the semiconductor device 200 according to this embodiment. Note that the HV transistor 30 having symmetric diffusion layers and the HV transistor 40 having asymmetric diffusion layers may be formed simultaneously on the same semiconductor substrate W. In this embodiment, the symmetric HV transistor 30 is formed in a predetermined region (hereinafter sometimes referred to as a "first region") of the same semiconductor substrate W, and the asymmetric HV transistor 40 is formed in a different predetermined region (hereinafter sometimes referred to as a "second region").

[0065] As shown in the same figure (A), first gate insulating films 30GI, 40GI, first gate electrodes 30GC, 40GC, and first sidewalls 31S, 41S and second sidewalls 32S, 42S respectively facing two side surfaces of each gate electrode are formed in a first region and a second region on a semiconductor substrate W, respectively.

[0066] Next, as shown in Fig. 1B, a resist film R is formed in the first region of the semiconductor substrate W, covering the first sidewall 31S and the second sidewall 32S and exposing at least the middle portion 30UM of the upper region 30U of the first gate electrode 30GC. In the second region of the semiconductor substrate W, a resist film R is formed, covering the second sidewall 42S and exposing at least the middle portion 40UM and the first sidewall 41S of the upper region 40U of the first gate electrode 40GC. Then, germanium is implanted through the resist film R to perform PAI.

[0067] As a result, in the first region, the intermediate portion 30UM of the first gate electrode 30GU that is not covered with the resist film R is implanted with germanium and made amorphous.

[0068] In the second region, the upper portion of the first gate electrode 40U, including the intermediate portion 40UM of the first gate electrode 40GC that is not covered with the resist film R and the first upper end portion 40U1 that is closer to the first sidewall 41S than the intermediate portion 40UM, is implanted with germanium and made amorphous.

[0069] 6A, a dopant (e.g., phosphorus) is implanted while the resist film R remains to form an LDD. At this time, germanium is implanted into the first gate electrode 40GC in the second region by PAI and the first gate electrode 40GC is made amorphous. Therefore, during the implantation to form the LDD, the dopant is prevented from passing through the first gate electrode 40GC and being implanted into the semiconductor substrate W. As a result, an LDD is formed in the region of the second region that will become the first source region 40S and is not covered with the resist film R.

[0070] 6(B), after removing the resist film R, a resist film R2 is formed in the second region to cover the second sidewall 42S and expose at least the intermediate portion 40UM above the first gate electrode 40GU and the first sidewall 41S. In this state, a dopant (e.g., phosphorus) is implanted through the resist film R2 to form an LDD.

[0071] At this time, since the first upper end 30U1 and the second upper end 30U2 in the first region are not amorphous but polycrystalline, the dopant easily passes through the first upper end 30U1 and the second upper end 30U2, which makes it possible to form a source LDD region below the source-side end of the first gate insulating film 30GI and a drain LDD region below the drain-side end.

[0072] On the other hand, the second upper end 40U2 of the second region is not amorphous but polycrystalline. Therefore, the dopant passes through the second upper end 40U2, and an LDD is formed in the drain region. Here, by increasing the acceleration voltage of the dopant in the LDD formation shown in FIG. 6B compared to the acceleration voltage of the dopant in the LDD formation shown in FIG. 6A, it is possible to form a relatively deep LDD on the drain side.

[0073] Thereafter, by forming a diffusion layer and the like in accordance with a known method, it becomes possible to manufacture the semiconductor device 200 having a transistor having the configuration shown in FIG.

[0074] The present embodiment has been described above with reference to specific examples. However, the present disclosure is not limited to these specific examples. Design modifications to these specific examples made by a person skilled in the art as appropriate are also included within the scope of the present disclosure as long as they comprise the features of the present disclosure. The elements of the above-described specific examples, as well as their arrangement, conditions, shape, etc., are not limited to those exemplified and can be modified as appropriate. The elements of the above-described specific examples can be combined in various ways as appropriate, as long as no technical contradictions arise.

[0075] For example, the upper end of the upper part of the gate electrode may be configured not only to contain no germanium, but also to contain germanium at a concentration lower than the germanium concentration in the intermediate part (an example of a "first concentration") by diffusing germanium from the intermediate part containing germanium. [Explanation of symbols]

[0076] W semiconductor substrate AR1 1st area AR2 2nd area 10 VLV transistor 10I First gate insulating film 10GC First gate electrode 10S First Source Region 10D First drain region 20 HV transistors 20I First gate insulating film 20GC First gate electrode 20S First Source Region 20D First drain region 100 Semiconductor device

Claims

1. a gate insulating film formed on a semiconductor substrate; a gate electrode formed on the gate insulating film and containing germanium in at least a portion of an upper portion thereof; a source region formed in the semiconductor substrate; a drain region formed in the semiconductor substrate; a transistor comprising: the gate insulating film has a first thickness; the source region contains germanium; the drain region contains germanium; a second gate insulating film formed on the semiconductor substrate and having a second thickness greater than the first thickness; a second gate electrode formed on the second gate insulating film and containing germanium at least in an upper portion thereof; a second source region formed in the semiconductor substrate and not containing germanium; a second drain region formed in the semiconductor substrate and not containing germanium; a second transistor configured as:

2. The source region is an upper source region containing germanium and located on the surface side of the semiconductor substrate; a lower source region that does not contain germanium and is spaced further from the surface of the semiconductor substrate than the upper source region; The drain region is an upper drain region containing germanium and located on the surface side of the semiconductor substrate; a lower drain region that does not contain germanium and is spaced further from the surface of the semiconductor substrate than the upper drain region; The semiconductor device according to claim 1 .

3. The transistor is a first sidewall provided opposite to one side surface of the gate electrode; a second sidewall provided opposite to the other side surface of the gate electrode, The second transistor is a third sidewall provided opposite to one side surface of the second gate electrode; a fourth sidewall provided opposite to the other side surface of the second gate electrode, The semiconductor device according to claim 1 , wherein the third sidewall and the fourth sidewall are formed on the second gate insulating film.

4. The transistor is a first sidewall provided opposite to one side surface of the gate electrode; a second sidewall provided opposite to the other side surface of the gate electrode, The upper portion of the gate electrode is an intermediate portion provided in an intermediate region between the first sidewall and the second sidewall and containing germanium at a first concentration; a first upper end portion that is closer to the first sidewall than the intermediate portion and that contains germanium at a concentration lower than the first concentration or that does not contain germanium; a second upper end portion that is closer to the second sidewall than the intermediate portion and that contains germanium at a concentration lower than the first concentration or does not contain germanium; The semiconductor device according to claim 1 , comprising:

5. The transistor is a source LDD region formed in a region of the semiconductor substrate corresponding to a region below the first upper end portion; a drain LDD region formed in a region of the semiconductor substrate corresponding to a region below the second upper end portion; The semiconductor device according to claim 4 , further comprising:

6. The transistor is a first sidewall provided opposite to one side surface of the gate electrode; a second sidewall provided opposite to the other side surface of the gate electrode, The upper portion of the gate electrode is an intermediate portion provided in an intermediate region between the first sidewall and the second sidewall and containing germanium at a first concentration; a first upper end portion closer to the first sidewall than the intermediate region and containing germanium at a second concentration; a second upper end portion that is closer to the second sidewall than the intermediate region and that contains germanium at a concentration lower than the first concentration and the second concentration, or that does not contain germanium; The semiconductor device according to claim 1 , comprising:

7. The source region of the transistor is an upper source region containing germanium and including the semiconductor substrate surface; a lower source region that does not contain germanium and is deeper than the upper source region; The drain region of the transistor is Does not contain germanium The semiconductor device according to claim 6.

8. The transistor according to claim 3 formed on the semiconductor substrate; The transistor according to claim 5 formed on the semiconductor substrate. A semiconductor device comprising:

9. forming a gate insulating film having a first thickness in a first region on a semiconductor substrate; forming an insulating film having a second film thickness greater than the first film thickness in a second region on the semiconductor substrate and including a second gate insulating film in a part thereof; forming a gate electrode on the gate insulating film; forming a second gate electrode on the second gate insulating film; forming a spacer insulating film on the semiconductor substrate and the gate electrode in the first region and on the insulating film and the second gate electrode in the second region; germanium is injected through the spacer insulating film to form an amorphous region on an upper portion of the semiconductor substrate and an upper portion of the gate electrode in the first region, and an amorphous region on an upper portion of the second gate electrode in the second region; A method for manufacturing a semiconductor device.

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