Semiconductor Devices

Abstract

To provide a semiconductor device which offers stable characteristics.SOLUTION: According to an embodiment, a semiconductor device includes a first electrode, a second electrode, a third electrode, a first semiconductor region, a second semiconductor region, a first layer, a second layer, and a first insulation layer. The first layer includes Al and N. The second layer includes Al, Si, O, and N. The second layer includes a first intermediate region. The first intermediate region includes a second position. The second position is at a center of the first intermediate region in the second direction. A first ratio of second-position nitrogen concentration in the second position to second-position nitrogen oxygen concentration in the second position is in a range of 0.1 to 0.2, both inclusive.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor device. [Background technology]

[0002] For example, stable characteristics are desired in semiconductor devices such as transistors. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2019-96720 Summary of the Invention [Problem to be solved by the invention]

[0004] The embodiments of the present invention provide a semiconductor device that can obtain stable characteristics. [Means for solving the problem]

[0005] According to an embodiment of the present invention, a semiconductor device includes a first electrode, a second electrode, a third electrode, a first semiconductor region, a second semiconductor region, a first layer, a second layer, and a first insulating layer. A direction from the first electrode to the second electrode is along a first direction. The third electrode includes a first electrode portion. A position of the first electrode portion in the first direction is between a position of the first electrode in the first direction and a position of the second electrode in the first direction. The first semiconductor region is Al x1 Ga 1-x1N (0≦x1<1). The first semiconductor region includes a first partial region, a second partial region, a third partial region, a fourth partial region, and a fifth partial region. A direction from the first partial region to the first electrode is along a second direction intersecting with the first direction. A direction from the second partial region to the second electrode is along the second direction. A direction from the third partial region to the first electrode is along the second direction. A position of the fourth partial region in the first direction is between a position of the first partial region in the first direction and a position of the third partial region in the first direction. A position of the fifth partial region in the first direction is between the position of the third partial region in the first direction and a position of the second partial region in the first direction. The second semiconductor region is Al x2 Ga 1-x2It includes N(x1 < x2 ≦ 1). The second semiconductor region includes a first semiconductor portion and a second semiconductor portion. The direction from the fourth partial region to the first semiconductor portion is along the second direction. The direction from the fifth partial region to the second semiconductor portion is along the second direction. The first layer includes Al and N. The first layer includes a first compound region. The first compound region is provided between the third partial region and the first electrode portion in the second direction. The first compound region does not contain oxygen. Or, the concentration of oxygen in the first compound region is lower than the concentration of nitrogen in the first compound region. The first compound region does not contain Ga. Or, the Ga concentration in the first compound region is lower than the Al concentration in the first compound region in the first compound region. The Al concentration in the first compound region is higher than the Al concentration in the third partial region in the third partial region. At least a part of the first compound region is crystalline. The first compound region includes a first position. The first position is the center of the first compound region in the second direction. The second layer includes Al, Si, O, and N. The second layer includes a first intermediate region. The first intermediate region is provided between the first compound region and the first electrode portion in the second direction. The concentration of Si in the first intermediate region is lower than the concentration of Al in the first intermediate region. The concentration of oxygen in the first intermediate region is higher than the concentration of nitrogen in the first intermediate region. The first intermediate region includes a second position. The second position is the center of the first intermediate region in the second direction. The Al concentration at the second position is lower than the Al concentration at the first position. The first ratio of the nitrogen concentration at the second position to the oxygen concentration at the second position at the second position is 0.1 or more and 0.2 or less. The first insulating layer includes Si and O. The first insulating layer includes a first insulating region. The first insulating region is provided between the first intermediate region and the first electrode portion in the second direction.

Brief Description of the Drawings

[0006] [Figure 1] FIG. 1 is a schematic cross-sectional view illustrating a semiconductor device according to the first embodiment. [Figure 2] FIG. 2 is a graph illustrating the semiconductor device according to the first embodiment. [Figure 3] FIG. 3 is a graph illustrating the experimental results. [Figure 4] FIG. 4 is a schematic cross-sectional view illustrating the semiconductor device according to the first embodiment. [Figure 5] FIG. 5 is a schematic cross-sectional view illustrating the semiconductor device according to the first embodiment. [Figure 6] FIG. 6 is a schematic cross-sectional view illustrating the semiconductor device according to the first embodiment. [Figure 7] FIG. 7 is a schematic cross-sectional view illustrating the semiconductor device according to the first embodiment. [Figure 8] FIG. 8 is a schematic cross-sectional view illustrating the semiconductor device according to the first embodiment. [Figure 9] FIG. 9 is a schematic cross-sectional view illustrating the semiconductor device according to the second embodiment. [Figure 10] 10(a) to 10(d) are schematic cross-sectional views illustrating the method for manufacturing the semiconductor device according to the embodiment. [Figure 11] 11(a) to 11(c) are schematic cross-sectional views illustrating the method for manufacturing the semiconductor device according to the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments of the present invention will be described with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc. are not necessarily the same as those in reality. Even when the same part is shown, the dimensions and ratios may be different depending on the drawing. In this specification and in each drawing, elements similar to those previously described with reference to the previous drawings are designated by the same reference numerals, and detailed descriptions thereof will be omitted where appropriate.

[0008] (First embodiment) FIG. 1 is a schematic cross-sectional view illustrating the semiconductor device according to the first embodiment. As shown in FIG. 1, the semiconductor device 110 according to the embodiment includes a first electrode 51, a second electrode 52, a third electrode 53, a first semiconductor region 11, a second semiconductor region 12, a first layer 31, a second layer 32, and a first insulating layer 41.

[0009] The direction from the first electrode 51 to the second electrode 52 is along the first direction D1. The first direction D1 is, for example, the X-axis direction. A direction perpendicular to the X-axis direction is defined as the Z-axis direction. A direction perpendicular to the X-axis and Z-axis directions is defined as the Y-axis direction.

[0010] The third electrode 53 includes a first electrode portion 53a. The position of the first electrode portion 53a in the first direction D1 is between the position of the first electrode 51 in the first direction D1 and the position of the second electrode 52 in the first direction D1. For example, the third electrode 53 is between the first electrode 51 and the second electrode 52 in the first direction D1.

[0011] The first semiconductor region 11 is Al x1 Ga 1-x1 N (0≦x1<1). In one example, the Al composition ratio x1 in the first semiconductor region 11 is, for example, equal to or greater than 0 and less than 0.1. The first semiconductor region 11 includes, for example, GaN. The first semiconductor region 11 includes a crystal.

[0012] The first semiconductor region 11 includes a first partial region 11a, a second partial region 11b, a third partial region 11c, a fourth partial region 11d, and a fifth partial region 11e. The direction from the first partial region 11a to the first electrode 51 is along a second direction D2. The second direction D2 intersects with the first direction D1. The second direction D2 is, for example, the Z-axis direction.

[0013] The direction from the second partial region 11b to the second electrode 52 is along the second direction D2. The direction from the third partial region 11c to the third electrode 53 is along the second direction D2. For example, the region overlapping with the first electrode 51 in the second direction D2 corresponds to the first partial region 11a. For example, the region overlapping with the second electrode 52 in the second direction D2 corresponds to the second partial region 11b. For example, the region overlapping with the third electrode 53 in the second direction D2 corresponds to the third partial region 11c.

[0014] The position of the fourth partial region 11d in the first direction D1 is between the position of the first partial region 11a in the first direction D1 and the position of the third partial region 11c in the first direction D1. The position of the fifth partial region 11e in the first direction D1 is between the position of the third partial region 11c in the first direction D1 and the position of the second partial region 11b in the first direction D1. The boundaries between these partial regions may be unclear or clear.

[0015] The second semiconductor region 12 contains Al x2 Ga 1-x2 N (x1 < x2 ≦ 1). In one example, the composition ratio x1 of Al in the second semiconductor region 12 is, for example, 0.1 or more and 0.35 or less. The second semiconductor region 12 contains, for example, AlGaN. The second semiconductor region 12 contains crystals.

[0016] The second semiconductor region 12 contains the first semiconductor portion 12a and the second semiconductor portion 12b. The direction from the fourth partial region 11d to the first semiconductor portion 12a is along the second direction D2. The direction from the fifth partial region 11e to the second semiconductor portion 12b is along the second direction D2.

[0017] The first layer 31 contains Al and N. The first layer 31 contains the first compound region 31a. The first compound region 31a is provided between the third partial region 11c and the first electrode portion 53a in the second direction D2. At least a part of the first compound region 31a is crystalline. At least a part of the first compound region 31a may contain single crystals.

[0018] The second layer 32 contains Al, Si, O, and N. The second layer 32 includes a first intermediate region 32a. The first intermediate region 32a is provided between the first compound region 31a and the first electrode portion 53a in the second direction D2.

[0019] The first insulating layer 41 includes Si and O. The first insulating layer 41 includes, for example, SiO2. The first insulating layer 41 includes a first insulating region 41a. The first insulating region 41a is provided between the first intermediate region 32a and the first electrode portion 53a in the second direction D2.

[0020] The current flowing between the first electrode 51 and the second electrode 52 can be controlled by the potential of the third electrode 53. The potential of the third electrode 53 may be, for example, a potential based on the potential of the first electrode 51. The first electrode 51 functions as, for example, a source electrode. The second electrode 52 functions as, for example, a drain electrode. The third electrode 53 functions as, for example, a gate electrode. The semiconductor device 110 is, for example, a transistor. The first insulating region 41a functions as at least a part of a gate insulating film.

[0021] The first semiconductor region 11 includes a portion facing the second semiconductor region 12. The facing portion includes a carrier region 10c. The carrier region 10c is, for example, a two-dimensional electron gas. The semiconductor device 110 is, for example, a HEMT (High Electron Mobility Transistor).

[0022] For example, the distance in the first direction D1 between the first electrode 51 and the first electrode portion 53a is shorter than the distance in the first direction D1 between the first electrode portion 53a and the second electrode 52. The first electrode 51 functions stably as a source electrode. The second electrode 52 functions stably as a drain electrode. For example, the semiconductor device is less likely to be destroyed. For example, it is easier to obtain a semiconductor device with small current collapse and stable characteristics.

[0023] For example, the first electrode 51, the second electrode 52, and the third electrode 53 may extend in a third direction D3. The third direction D3 intersects with a plane including the first direction D1 and the second direction D2. The third direction D3 is, for example, the Y-axis direction.

[0024] 1, the semiconductor device 110 may further include a nitride layer 14. The nitride layer 14 is, for example, a GaN layer containing C. The first semiconductor region 11, the second semiconductor region 12, and the nitride layer 14 are included in a semiconductor member 10M.

[0025] The semiconductor device 110 may further include a base 18s and a buffer layer 18b. The base 18s may include, for example, a silicon substrate, a SiC substrate, or a GaN substrate. The buffer layer 18b is provided on the base 18s. The buffer layer 18b may include Al, Ga, N, or the like. The semiconductor member 10M is provided on the buffer layer 18b.

[0026] FIG. 2 is a graph illustrating the semiconductor device according to the first embodiment. FIG. 2 illustrates element profiles in a first sample SP1, which is an example of the semiconductor device 110. FIG. 2 shows the results of a transmission electron microscope (TEM)-energy dispersive X-ray spectroscopy (EDX) analysis of a portion including the third partial region 11c, the first compound region 31a, the first intermediate region 32a, and the first insulating region 41a. The horizontal axis of FIG. 2 represents the position pZ in the Z-axis direction (second direction D2). The vertical axis represents the element concentration (atomic percent). FIG. 2 shows profiles of Ga, Al, N, O, and Si.

[0027] The third partial region 11c contains Ga and N.

[0028] The first compound region 31a does not contain Ga. Alternatively, the Ga concentration in the first compound region 31a (first compound region Ga concentration) is lower than the Al concentration in the first compound region 31a (first compound region Al concentration). This makes it easier to obtain high electron mobility and low on-resistance. The region where the Ga concentration is higher than the Al concentration corresponds to the third partial region 11c. The region where the Al concentration is higher than the Ga concentration corresponds to the first compound region 31a. For example, the position pZ where the Al concentration is the same as the Ga concentration may be considered to be the boundary between the third partial region 11c and the first compound region 31a.

[0029] The Al concentration in the first compound region 31a (first compound region Al concentration) is higher than the Al concentration in the third partial region 11c (third partial Al concentration). The first compound region 31a does not contain oxygen. Alternatively, the oxygen concentration in the first compound region 31a is lower than the nitrogen concentration in the first compound region 31a. This makes it easier to obtain a film with high crystallinity.

[0030] The oxygen concentration in the first intermediate region 32a is higher than the nitrogen concentration in the first intermediate region 32a. This makes it easier to obtain a film with fewer traps, for example. It also makes it easier to obtain stable characteristics. The region where the oxygen concentration is higher than the nitrogen concentration corresponds to the first intermediate region 32a. The region where the nitrogen concentration is higher than the oxygen concentration corresponds to the first compound region 31a. For example, the position pZ where the oxygen concentration is the same as the nitrogen concentration can be considered to be the boundary between the first compound region 31a and the first intermediate region 32a.

[0031] The concentration of Si in the first intermediate region 32a is lower than the concentration of Al in the first intermediate region 32a.

[0032] The Si concentration in the first insulating region 41a is higher than the Si concentration in the first intermediate region 32a. The first insulating region 41a does not contain Al. Alternatively, the Al concentration in the first insulating region 41a is lower than the Si concentration in the first insulating region 41a. The region where the Si concentration is higher than the Al concentration corresponds to the first insulating region 41a. The region where the Al concentration is higher than the Si concentration corresponds to the first intermediate region 32a. The position pZ where the Si concentration is the same as the Al concentration can be considered to be the boundary between the first insulating region 41a and the first intermediate region 32a.

[0033] The first compound region 31a includes a first position p1. The first position p1 is the center of the first compound region 31a in the second direction D2. Meanwhile, the first intermediate region 32a includes a second position p2. The second position p2 is the center of the first intermediate region 32a in the second direction D2. The Al concentration at the second position p2 (second position Al concentration CA1p2) is lower than the Al concentration at the first position p1 (first position Al concentration CA1p1).

[0034] The Al concentration in the first compound region 31a is higher than the Al concentration in the first intermediate region 32a. This results in a low on-resistance. For example, by providing the first compound region 31a, a stronger piezoelectric charge is generated in, for example, the third partial region 11c compared to when the first compound region 31a is not provided. This results in a steep electron potential well. For example, electron scattering is suppressed. For example, high electron mobility is obtained in the third partial region 11c.

[0035] For example, the higher the Al concentration in the first compound region 31a, the more likely it is that a strong piezoelectric charge will be generated, and a steep electron potential well will be formed in the third partial region 11c. Higher electron mobility will be obtained in the third partial region 11c. For example, the higher the crystallinity of the first compound region 31a, the more likely it is that a strong piezoelectric charge will be generated, and a steep electron potential well will be formed in the third partial region 11c. Higher electron mobility will be obtained in the third partial region 11c.

[0036] For example, the higher the Al concentration in the first compound region 31a, the easier it is to obtain high electron mobility in the third partial region 11c even if the thickness of the first compound region 31a is thin. The ALD (Atomic Layer Deposition) method, which has good coverage, may be used to form the first compound region 31a. The high Al concentration in the first compound region 31a allows the thickness of the first compound region 31a to be thin, and the process time can be shortened.

[0037] For example, the Al concentration at the first position p1 is preferably five times or more the Ga concentration at the first position p1. This makes it easier to obtain high electron mobility, the thickness of the first compound region 31a can be reduced, and the process time can be shortened.

[0038] The concentration of nitrogen at the second position p2 is defined as the second-position nitrogen concentration CNp2. The concentration of oxygen at the second position p2 is defined as the second-position oxygen concentration COp2. The ratio of the second-position nitrogen concentration CNp2 to the second-position oxygen concentration COp2 (CNp2 / COp2) is defined as the first ratio. In this embodiment, the first ratio is equal to or greater than 0.1 and equal to or less than 0.2. It has been found that this allows stable characteristics to be obtained.

[0039] The results of experiments conducted by the inventors are described below. In the experiments, samples were prepared by changing the conditions for forming the second layer 32. In this example, AlN films and Al2O3 films were alternately and repeatedly formed and heat-treated. This caused interdiffusion between the AlN films and the Al2O3 films, resulting in the second layer 32. The first ratio was changed by changing the thickness of the AlN film and the Al2O3 film during the repeated lamination. For example, if the thickness of the AlN film was made thinner relative to the thickness of the Al2O3 film, the first ratio (N concentration) decreased. For example, if the thickness of the AlN film was made thicker relative to the thickness of the Al2O3 film, the first ratio (nitrogen concentration) increased. For these samples, changes in threshold voltage were measured in an accelerated test in which a voltage was applied to the gate electrode.

[0040] 3(a) and 3(b) are graphs illustrating the experimental results. The horizontal axis of Figure 3(a) is the first ratio R1. The vertical axis of Figure 3(a) is the change in threshold voltage ΔV. In Figure 3(a), the change ΔV in the reference sample SPx, which does not have the second layer 32 (first intermediate region 32a), is shown by a dashed line. In addition to the first sample SP1, Figure 3(a) also shows the change ΔV in other samples in which the formation conditions of the second layer 32 were changed.

[0041] As shown in FIG. 3(a), the absolute value of the change ΔV is large in the reference sample SPx. In other samples, including the first sample SP1, the absolute value of the change ΔV is large when the first ratio R1 changes. As can be seen from FIG. 3(a), when the first ratio R1 is 0.1 or more and 0.2 or less, the absolute value of the change ΔV is small. When the first ratio R1 is 0.125 or more and 0.175 or less, a particularly small absolute value of the change ΔV is obtained. For example, when the first ratio R1 is less than 0.1, the absolute value of the change ΔV is large. For example, when the first ratio R1 is 0.05, the change ΔV is approximately -1.

[0042] When the first ratio R1 is equal to or greater than 0.1 and equal to or less than 0.2, it is believed that trap generation is suppressed, for example, in the first intermediate region 32a. For example, it is believed that trap generation is suppressed at the interface between the first intermediate region 32a and the first insulating region 41a. For example, it is believed that trap generation is suppressed at the interface between the first intermediate region 32a and the first compound region 31a. It is believed that suppressing trap generation can reduce the absolute value of the threshold voltage change ΔV.

[0043] The horizontal axis of Fig. 3(b) is the first ratio R1. The vertical axis of Fig. 3(b) is the electron mobility μ1. The electron mobility μ1 is normalized with the electron mobility of the reference sample SPx, which does not have the second layer 32 (first intermediate region 32a), set to 1. It is preferable that the electron mobility μ1 is high.

[0044] As can be seen from FIG. 3(b), the other samples, including the first sample SP1, exhibit higher electron mobility μ1 than the reference sample SPx. As can be seen from FIG. 3(b), a particularly high electron mobility μ1 is obtained when the first ratio R1 is 0.1 or greater and 0.2 or less. An even higher electron mobility μ1 is obtained when the first ratio R1 is 0.1 or greater and 0.175 or less. For example, when the first ratio R1 is less than 0.1, the electron mobility μ1 is low. For example, when the first ratio R1 is 0.05, the electron mobility μ1 is approximately 1.7.

[0045] When the first intermediate region 32a is provided, the electron mobility μ1 in the third partial region 11c is higher than when the first intermediate region 32a is not provided. For example, when the first ratio R1 is 0.15, the electron mobility μ1 in the third partial region 11c is approximately 1.9 times higher than when the first intermediate region 32a is not provided.

[0046] By providing the first intermediate region 32a, the interface with the first compound region 31a is improved. For example, a first compound region 31a with higher crystallinity can be obtained. In a first compound region 31a with higher crystallinity, there is less polycrystalline layer and less amorphous layer. This makes it easier to form a steep electron potential well in the third partial region 11c. This is thought to make it easier to obtain a higher electron mobility μ1 in the third partial region 11c. When the first ratio R1 is 0.1 or more and 0.2 or less, particularly high mobility can be obtained. A semiconductor device with low on-resistance can be obtained. When the first ratio R1 is 0.1 or more and 0.175 or less, particularly high mobility can be obtained. A semiconductor device with lower on-resistance can be obtained.

[0047] In the embodiment, the first ratio R1 is preferably 0.1 or more and 0.2 or less. A small absolute value of the change ΔV can be obtained. A high electron mobility μ1 can be obtained. The first ratio R1 may be 0.125 or more and 0.175 or less. An even smaller absolute value of the change ΔV can be obtained. A high electron mobility μ1 can be obtained. According to the embodiment, a semiconductor device with stable characteristics can be provided.

[0048] In the embodiment, it is preferable that at least a part of the first intermediate region 32a is amorphous. This makes it possible to suppress, for example, leakage current. In the embodiment, it is preferable that at least a part of the first insulating region 41a is amorphous. This makes it possible to suppress, for example, leakage current.

[0049] On the other hand, the first compound region 31a preferably contains crystals, which makes it easier to obtain, for example, a low on-resistance.

[0050] The thickness of the first compound region 31a along the second direction D2 is defined as the first thickness t1 (see FIG. 2). In this embodiment, the first thickness t1 is preferably 1 nm or more and 10 nm or less. When the first thickness t1 is 1 nm or more, a high electron mobility μ1 is easily obtained. When the first thickness t1 is 10 nm or less, for example, a crystal with fewer cracks is easily obtained. For example, the gate leakage current caused by cracks can be reduced. When the first thickness t1 is 10 nm or less, for example, the Al concentration of the first compound region 31a can be increased. This makes it easy to obtain high electron mobility. It is more preferable that the first thickness t1 is 1.5 nm or more and 5 nm or less. A film with high electron mobility μ1 and low leakage current can be obtained.

[0051] The thickness of the first intermediate region 32a along the second direction D2 is defined as the second thickness t2 (see FIG. 2). In this embodiment, the second thickness t2 is preferably 0.5 nm or more and 7 nm or less. This allows a semiconductor device with stable characteristics to be obtained. The second thickness t2 is more preferably 1 nm or more and 3 nm or less. This makes it easier to obtain stable characteristics with little change in threshold voltage.

[0052] 1, in this example, at least a portion of the first electrode portion 53a is located between the fourth partial region 11d and the fifth partial region 11e in the first direction D1. The third electrode 53 is, for example, a recessed gate electrode. For example, a normally-off operation is obtained.

[0053] In a normally-off operation, it is particularly desirable that the threshold voltage be stable. By providing the first compound region 31a and the first intermediate region 32a, a normally-off operation in which the change ΔV in the threshold voltage is suppressed can be achieved.

[0054] FIG. 4 is a schematic cross-sectional view illustrating the semiconductor device according to the first embodiment. 4, in the semiconductor device 110 according to the embodiment, the first layer 31 may further include a second compound region 31b, the second layer 32 may further include a second intermediate region 32b, and the first insulating layer 41 may further include a second insulating region 41b.

[0055] The second insulating region 41b is located between the first electrode portion 53a and the second semiconductor portion 12b in the first direction D1. The second intermediate region 32b is located between the second insulating region 41b and the second semiconductor portion 12b in the first direction D1. The second compound region 31b is located between the second intermediate region 32b and the second semiconductor portion 12b in the first direction D1. For example, the second compound region 31b may be single crystal. For example, stable normally-off operation can be obtained.

[0056] In this manner, the stacked film SL1 including the first layer 31, the second layer 32, and the first insulating layer 41 may be provided between the first electrode portion 53a and the second semiconductor portion 12b. The stacked film SL1 may be provided between the first semiconductor portion 12a and the first electrode portion 53a.

[0057] 4, the first layer 31 may further include a third compound region 31c. The second layer 32 may further include a third intermediate region 32c. The first insulating layer 41 may further include a third insulating region 41c. The third compound region 31c may be amorphous. This makes it easier to suppress leakage current.

[0058] The second semiconductor portion 12b is located between the fifth portion region 11e and the third insulating region 41c in the second direction D2. The third compound region 31c is located between the second semiconductor portion 12b and the third insulating region 41c in the second direction D2. The third intermediate region 32c is located between the third compound region 31c and the third insulating region 41c in the second direction D2.

[0059] In this way, the stacked film SL1 may be provided in at least a part of the region between the third electrode 53 and the second electrode 52.

[0060] The first layer 31 may further include a fourth compound region 31d. The second layer 32 may further include a fourth intermediate region 32d. The first insulating layer 41 may further include a fourth insulating region 41d.

[0061] The first semiconductor portion 12a is located between the fourth portion region 11d and the fourth insulating region 41d in the second direction D2. The fourth compound region 31d is located between the first semiconductor portion 12a and the fourth insulating region 41d in the second direction D2. The fourth intermediate region 32d is located between the fourth compound region 31d and the fourth insulating region 41d in the second direction D2.

[0062] In this way, the stacked film SL1 may be provided in at least a part of the region between the first electrode 51 and the third electrode 53.

[0063] 4, the semiconductor device 110 may further include a second insulating layer 42. The second insulating layer 42 includes at least one selected from the group consisting of oxygen and nitrogen, and at least one selected from the group consisting of Si and Al. In one example, the second insulating layer 42 includes, for example, SiN. In one example, the second insulating layer 42 includes, for example, AlN. The second insulating layer 42 includes, for example, an amorphous material.

[0064] The second insulating layer 42 includes a first insulating portion 42a. The first insulating portion 42a is located between the second semiconductor portion 12b and the third compound region 31c. By providing the second insulating layer 42, the semiconductor member 10M is protected. For example, stable characteristics are easily obtained. Leakage current is easily suppressed. Current collapse is easily suppressed.

[0065] The second insulating layer 42 may include a second insulating portion 42b. The second insulating portion 42b is located between the first semiconductor portion 12a and the fourth compound region 31d.

[0066] As shown in FIG. 4, the first compound region 31a includes a first surface F1. The first surface F1 faces the third partial region 11c. The third compound region 31c includes a second surface F2. The second surface F2 faces the first insulating portion 42a. The distance along the second direction D2 between a position of the first surface F1 in the second direction D2 and a position of the second surface F2 in the second direction D2 is defined as a first distance d1. In this embodiment, the first distance d1 is preferably 100 nm or more and 400 nm or less. This makes it easier to obtain an appropriate threshold voltage. The first distance d1 corresponds to, for example, the depth of the recess.

[0067] The position of the first face F1 in the second direction D2 is preferably between the position of the second semiconductor region 12 in the second direction D2 and the position of the nitride layer 14 in the second direction D2. For example, high electron mobility is easily obtained. Stable characteristics are easily obtained. Threshold voltage fluctuations are easily suppressed.

[0068] 4, the third electrode 53 may further include a second electrode portion 53b. The position of the second electrode portion 53b in the first direction D1 is between the position of the first electrode portion 53a in the first direction D1 and the position of the second electrode 52 in the first direction D1. The second electrode portion 53b is continuous with the first electrode portion 53a. A portion of the second semiconductor portion 12b is provided between the fifth portion region 11e and the second electrode portion 53b in the second direction D2. A portion of the third compound region 31c, a portion of the third intermediate region 32c, and a portion of the third insulating region 41c are located between the first insulating portion 42a and the second electrode portion 53b in the second direction D2.

[0069] A high electric field is likely to occur at the end of the second electrode portion 53b. This may result in breakdown or the like. By providing the first insulating portion 42a below the second electrode portion 53b, the electric field is alleviated. For example, a higher breakdown voltage can be obtained. Breakdown or the like can be suppressed. By providing the stacked film SL1 below the second electrode portion 53b, a higher breakdown voltage can be obtained.

[0070] FIG. 5 is a schematic cross-sectional view illustrating the semiconductor device according to the first embodiment. 5, in the semiconductor device 111 according to the embodiment, the structure of the portion below the second electrode portion 53b is different from the structure in the semiconductor device 110. Except for this, the configuration of the semiconductor device 111 may be the same as the configuration of the semiconductor device 110.

[0071] In the semiconductor device 111, the third electrode 53 includes a first electrode portion 53a, a second electrode portion 53b, and a third electrode portion 53c. As already described, the position of the second electrode portion 53b in the first direction D1 is between the position of the first electrode portion 53a in the first direction D1 and the position of the second electrode 52 in the first direction D1. The second electrode portion 53b is continuous with the first electrode portion 53a.

[0072] The third electrode portion 53c is located between the first electrode portion 53a and the second electrode portion 53b. The third electrode portion 53c is continuous with the first electrode portion 53a and the second electrode portion 53b. A part of the second semiconductor portion 12b is provided between the fifth partial region 11e and the third electrode portion 53c in the second direction D2. A part of the second semiconductor portion 12b is also provided between the fifth partial region 11e and the second electrode portion 53b in the second direction D2.

[0073] 5, in the semiconductor device 111, another portion 31cP of the third compound region 31c is located between the first electrode portion 53a and the first insulating portion 42a in the first direction D1. For example, the another portion 31cP of the third compound region 31c is in contact with the second semiconductor portion 12b.

[0074] In the example of the semiconductor device 111, the first insulating portion 42a is provided below the second electrode portion 53b (the end portion of the third electrode 53). The first insulating portion 42a is omitted below the portion (third electrode portion 53c) between the first electrode portion 53a and the second electrode portion 53b. By providing the first insulating portion 42a below the second electrode portion 53b, it is possible to suppress the concentration of the electric field, as described above. A high breakdown voltage is obtained. By omitting the first insulating portion 42a below the third electrode portion 53c, for example, a high carrier concentration is obtained in the carrier region 10c below another portion 31cP of the third compound region 31c. For example, a low on-resistance is easily obtained.

[0075] FIG. 6 is a schematic cross-sectional view illustrating the semiconductor device according to the first embodiment. 6, in the semiconductor device 112 according to the embodiment, the fourth compound region 31d, the fourth intermediate region 32d, and the fourth insulating region 41d are omitted. The remaining configuration of the semiconductor device 112 may be the same as that of the semiconductor device 110. In the semiconductor device 112, a high carrier concentration is obtained in the carrier region 10c between the first electrode 51 and the third electrode 53. A low on-resistance is easily obtained.

[0076] FIG. 7 is a schematic cross-sectional view illustrating the semiconductor device according to the first embodiment. 7, in a semiconductor device 113 according to the embodiment, the first insulating portion 42a is omitted near the second electrode 52. Except for this, the configuration of the semiconductor device 113 may be similar to the configuration of the semiconductor device 110.

[0077] In the semiconductor device 113, a portion of the third compound region 31c is located between the first insulating portion 42a and the second electrode 52 in the first direction D1. For example, a portion of the third compound region 31c contacts the second semiconductor portion 12b. In the semiconductor device 113, a high carrier concentration is obtained in the carrier region 10c corresponding to the region where the third compound region 31c and the second semiconductor portion 12b contact. A low on-resistance is easily obtained. Current collapse is less likely to occur. Stable characteristics are easily obtained.

[0078] FIG. 8 is a schematic cross-sectional view illustrating the semiconductor device according to the first embodiment. As shown in FIG. 8, the configurations described for the semiconductor device 111, the semiconductor device 112, and the semiconductor device 113 are applied to a semiconductor device 114 according to the embodiment.

[0079] In the semiconductor devices 110 to 114, the first ratio is set to be equal to or greater than 0.1 and equal to or less than 0.2. For example, the change ΔV in the threshold voltage can be suppressed. A semiconductor device with stable characteristics can be provided.

[0080] (Second embodiment) FIG. 9 is a schematic cross-sectional view illustrating the semiconductor device according to the second embodiment. 9 illustrates a portion of the semiconductor device 120 according to the embodiment. Fig. 9 illustrates a portion including the third partial region 11c, the first compound region 31a, the first intermediate region 32a, the first insulating region 41a, and the first electrode portion 53a. The semiconductor device 120 includes a third layer 43. The remaining configuration of the semiconductor device 120 may be the same as that of any semiconductor device according to the first embodiment.

[0081] At least a portion of the third layer 43 is located between the first intermediate region 32a and the first insulating region 41a. The third layer 43 includes SiN or SiON. At least a portion of the third layer 43 has a third thickness t3 along the second direction D2 of 0.1 nm or more and 2 nm or less. By providing the third layer 43, for example, during the manufacturing process (particularly the heat treatment process), it is possible to suppress the diffusion of impurities generated from the third partial region 11c, the first compound region 31a, and the first intermediate region 32a into the first insulating region 41a. It is possible to reduce impurities in the first insulating region 41a. It is possible to reduce the diffusion of at least one of Al and Ga into the first insulating region 41a. Good gate reliability is easily obtained. Gate breakdown is less likely to occur. Stable characteristics are easily obtained.

[0082] An example of a method for manufacturing a semiconductor device according to an embodiment will be described below. 10(a) to 10(d) and 11(a) to 11(c) are schematic cross-sectional views illustrating the method for manufacturing the semiconductor device according to the embodiment. As shown in FIG. 10(a), a first semiconductor film 11F is provided on the nitride layer 14. A second semiconductor film 12F is provided on the first semiconductor film 11F. A second insulating film 42F is provided on the second semiconductor film 12F. The first semiconductor film 11F becomes the first semiconductor region 11. The second semiconductor film 12F becomes the second semiconductor region 12. The second insulating film 42F becomes the second insulating layer 42.

[0083] 10(b), a portion of the first semiconductor film 11F, a portion of the second semiconductor film 12F, and a portion of the second insulating film 42F are removed. As a result, a trench 10R is formed. A first semiconductor region 11, a second semiconductor region 12, and a second insulating layer 42 are obtained.

[0084] As shown in FIG. 10(c), the first layer 31 is formed.

[0085] 10(d), the second layer 32 is formed. For example, the second layer 32 may be formed by oxidizing a portion of the first layer 31.

[0086] As shown in FIG. 11(a), a first insulating layer 41 is formed.

[0087] 11(b), the remaining space in the trench 10R is filled with a conductive material, thereby obtaining the third electrode 53.

[0088] 11(c), a first electrode 51 and a second electrode 52 are formed. In this way, for example, a semiconductor device 110 is formed.

[0089] In the embodiment, at least one of the first electrode 51 and the second electrode 52 includes, for example, at least one selected from the group consisting of Al and Ti. The third electrode 53 may include, for example, at least one selected from the group consisting of TiN, polysilicon, polyAlGaN, and polyGaN.

[0090] In an embodiment, information about the length and thickness can be obtained by electron microscopy, etc. Information about the composition of the material can be obtained by SIMS (Secondary Ion Mass Spectrometry) or EDX (Energy Dispersive X-ray spectroscopy), etc.

[0091] The embodiment may include the following configurations (e.g., technical solutions). (Configuration 1) A first electrode; a second electrode, the direction from the first electrode to the second electrode being along a first direction; a third electrode including a first electrode portion, wherein a position of the first electrode portion in the first direction is between a position of the first electrode in the first direction and a position of the second electrode in the first direction; Al x1 Ga 1-x1 a first semiconductor region including N (0≦x1<1), the first semiconductor region including a first partial region, a second partial region, a third partial region, a fourth partial region, and a fifth partial region, a direction from the first partial region to the first electrode along a second direction intersecting the first direction, a direction from the second partial region to the second electrode along the second direction, a direction from the third partial region to the first electrode along the second direction, a position of the fourth partial region in the first direction between a position of the first partial region in the first direction and a position of the third partial region in the first direction, and a position of the fifth partial region in the first direction between the position of the third partial region in the first direction and a position of the second partial region in the first direction; Al x2 Ga 1-x2A second semiconductor region including N(x1 < x2 ≦ 1), wherein the second semiconductor region includes a first semiconductor portion and a second semiconductor portion, the direction from the fourth partial region to the first semiconductor portion is along the second direction, and the direction from the fifth partial region to the second semiconductor portion is along the second direction, the second semiconductor region, A first layer including Al and N, wherein the first layer includes a first compound region provided between the third partial region and the first electrode portion in the second direction, the first compound region does not contain oxygen or the oxygen concentration in the first compound region is lower than the nitrogen concentration in the first compound region, the first compound region does not contain Ga or the Ga concentration in the first compound region is lower than the Al concentration in the first compound region, the Al concentration in the first compound region is higher than the Al concentration in the third partial region in the third partial region, at least a part of the first compound region is crystalline, the first compound region includes a first position, and the first position is the center of the first compound region in the second direction, the first layer, A second layer including Al, Si, O and N, wherein the second layer includes a first intermediate region provided between the first compound region and the first electrode portion in the second direction, the Si concentration in the first intermediate region is lower than the Al concentration in the first intermediate region, the oxygen concentration in the first intermediate region is higher than the nitrogen concentration in the first intermediate region, the first intermediate region includes a second position, and the second position is the center of the first intermediate region in the second direction, the Al concentration at the second position is lower than the Al concentration at the first position, and the first ratio of the nitrogen concentration at the second position to the oxygen concentration at the second position at the second position is 0.1 or more and 0.2 or less, the second layer, A first insulating layer including Si and O, wherein the first insulating layer includes a first insulating region provided between the first intermediate region and the first electrode portion in the second direction, the first insulating layer, A semiconductor device provided with

[0092] (Configuration 2) 2. The semiconductor device according to configuration 1, wherein the first ratio is equal to or greater than 0.125 and equal to or less than 0.175.

[0093] (Configuration 3) 3. The semiconductor device according to claim 1, wherein the concentration of Si in the first insulating region is higher than the concentration of Si in the first intermediate region.

[0094] (Configuration 4) the first insulating region does not contain Al, or 4. The semiconductor device according to any one of configurations 1 to 3, wherein the concentration of Al in the first insulating region is lower than the concentration of Si in the first insulating region.

[0095] (Configuration 5) 5. The semiconductor device according to any one of configurations 1 to 4, wherein at least a portion of the first intermediate region is amorphous.

[0096] (Configuration 6) 6. The semiconductor device according to any one of configurations 1 to 5, wherein at least a portion of the first insulating region is amorphous.

[0097] (Configuration 7) 7. The semiconductor device according to any one of configurations 1 to 6, wherein the thickness of the first compound region along the second direction is 1 nm or more and 10 nm or less.

[0098] (Configuration 8) 8. The semiconductor device according to any one of configurations 1 to 7, wherein the thickness of the first intermediate region along the second direction is 0.5 nm or more and 7 nm or less.

[0099] (Configuration 9) 9. The semiconductor device according to any one of configurations 1 to 8, wherein at least a part of the first electrode portion is located between the fourth partial region and the fifth partial region in the first direction.

[0100] (Configuration 10) the first layer further comprises a second compound region; the second layer further comprises a second intermediate region; the first insulating layer further includes a second insulating region; the second insulating region is between the first electrode portion and the second semiconductor portion in the first direction; the second intermediate region is located between the second insulating region and the second semiconductor portion in the first direction; 10. The semiconductor device of claim 9, wherein the second compound region is between the second intermediate region and the second semiconductor portion in the first direction.

[0101] (Configuration 11) the first layer further comprises a third compound region; the second layer further comprises a third intermediate region; the first insulating layer further includes a third insulating region; the second semiconductor portion is located between the fifth portion region and the third insulating region in the second direction; the third compound region is located between the second semiconductor portion and the third insulating region in the second direction; 11. The semiconductor device according to any one of configurations 1 to 10, wherein the third intermediate region is located between the third compound region and the third insulating region in the second direction.

[0102] (Configuration 12) Further comprising a second insulating layer; the second insulating layer includes at least one selected from the group consisting of oxygen and nitrogen, and at least one selected from the group consisting of Si and Al; 12. The semiconductor device of claim 11, wherein the second insulating layer includes a first insulating portion, the first insulating portion being between the second semiconductor portion and the third compound region.

[0103] (Configuration 13) the third electrode further includes a second electrode portion; a position of the second electrode portion in the first direction is between the position of the first electrode portion in the first direction and the position of the second electrode in the first direction; the second electrode portion is continuous with the first electrode portion, a portion of the second semiconductor portion is provided between the fifth portion region and the second electrode portion in the second direction, A semiconductor device as described in structure 12, wherein a portion of the third compound region, a portion of the third intermediate region, and a portion of the third insulating region are located between the first insulating portion and the second electrode portion in the second direction.

[0104] (Configuration 14) the third electrode further includes a third electrode portion; the third electrode portion is located between the first electrode portion and the second electrode portion; the third electrode portion is continuous with the first electrode portion and the second electrode portion, the part of the second semiconductor portion is further provided between the fifth portion region and the third electrode portion in the second direction, 14. The semiconductor device of claim 13, wherein another portion of the third compound region is between the first electrode portion and the first insulating portion in the first direction.

[0105] (Configuration 15) 15. The semiconductor device of claim 14, wherein the other portion of the third compound region is in contact with the second semiconductor portion.

[0106] (Configuration 16) 13. The semiconductor device of claim 12, wherein a portion of the third compound region is between the first insulating portion and the second electrode in the first direction.

[0107] (Configuration 17) 17. The semiconductor device of claim 16, wherein the portion of the third compound region contacts the second semiconductor portion.

[0108] (Configuration 18) the first compound region includes a first surface facing the third partial region, the third compound region includes a second surface facing the first insulating portion; The semiconductor device according to any one of structures 12 to 17, wherein the distance along the second direction between the position of the first surface in the second direction and the position of the second surface in the second direction is 100 nm or more and 400 nm or less.

[0109] (Configuration 19) A semiconductor device described in any one of configurations 10 to 18, wherein the distance along the first direction between the first electrode and the first electrode portion is shorter than the distance along the first direction between the first electrode portion and the second electrode.

[0110] (Configuration 20) Further comprising a third layer, at least a portion of the third layer is between the first intermediate region and the first insulating region; the third layer includes SiN or SiON; 20. The semiconductor device according to any one of configurations 1 to 19, wherein the third thickness of the at least part of the third layer along the second direction is not less than 0.1 nm and not more than 2 nm.

[0111] According to the embodiment, a semiconductor device that can obtain stable characteristics can be provided.

[0112] The embodiments of the present invention have been described above with reference to specific examples. However, the present invention is not limited to these specific examples. For example, the specific configurations of the elements included in the semiconductor device, such as electrodes, semiconductor regions, layers, and insulating layers, are within the scope of the present invention as long as a person skilled in the art can implement the present invention in a similar manner and obtain similar effects by appropriately selecting them from known ranges.

[0113] Furthermore, any combination of two or more elements of each specific example within the scope of technical feasibility is also included within the scope of the present invention as long as it includes the gist of the present invention.

[0114] In addition, all semiconductor devices that can be implemented by a person skilled in the art by appropriately modifying the design based on the semiconductor device described above as an embodiment of the present invention also fall within the scope of the present invention as long as they include the gist of the present invention.

[0115] In addition, within the scope of the concept of the present invention, a person skilled in the art may come up with various modifications and alterations, and it will be understood that these modifications and alterations also fall within the scope of the present invention.

[0116] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0117] 10M...semiconductor member, 10c...carrier region, 11, 12...first and second semiconductor regions, 11a-11e...first to fifth partial regions, 12...second semiconductor region, 12a, 12b...first and second semiconductor portions, 14...nitride layer, 18b...buffer layer, 18s...substrate, 31...first layer, 31a-32d...first to fourth compound regions, 31cP...part, 32...second layer, 32a-32d...first to fourth intermediate regions, 41...first insulating layer, 41a-41d...first to fourth insulating regions, 42...second insulating layer, 42a, 42b...first and second insulating portions, 43...third layer, 51-53...first to third electrodes, 53a to 53c...first to third electrode portions, ΔV...change, μ1...electron mobility, 110 to 114, 120...semiconductor device, CA1p1, CA1p2...Al concentration at first and second positions, CNp2...nitrogen concentration at second position, COp2...oxygen concentration at first position, D1 to D3...first to third directions, F1, F2...first and second surfaces, R1...first ratio, SL1...laminated film, SP1...first sample, d1...first distance, p1, p2...first and second positions, pZ...position, t1 to t3...first to third thicknesses

Claims

1. A first electrode; a second electrode, the direction from the first electrode to the second electrode being along a first direction; a third electrode including a first electrode portion, wherein a position of the first electrode portion in the first direction is between a position of the first electrode in the first direction and a position of the second electrode in the first direction; Al ｘ１ Ga １－ｘ１ a first semiconductor region including N (0≦x1<1), the first semiconductor region including a first partial region, a second partial region, a third partial region, a fourth partial region, and a fifth partial region, a direction from the first partial region to the first electrode along a second direction intersecting the first direction, a direction from the second partial region to the second electrode along the second direction, a direction from the third partial region to the first electrode along the second direction, a position of the fourth partial region in the first direction between a position of the first partial region in the first direction and a position of the third partial region in the first direction, and a position of the fifth partial region in the first direction between the position of the third partial region in the first direction and a position of the second partial region in the first direction; Al ｘ２ Ga １－ｘ２ N (x1<x2≦1), the second semiconductor region including a first semiconductor portion and a second semiconductor portion, the direction from the fourth sub-region to the first semiconductor portion being along the second direction, and the direction from the fifth sub-region to the second semiconductor portion being along the second direction; a first layer containing Al and N, the first layer including a first compound region, the first compound region being provided between the third partial region and the first electrode portion in the second direction, the first compound region not containing oxygen, or an oxygen concentration in the first compound region being lower than a nitrogen concentration in the first compound region, the first compound region not containing Ga, or a first compound region Ga concentration in the first compound region being lower than a first compound region Al concentration in the first compound region and the first compound region Al concentration being higher than a third partial Al concentration in the third partial region, at least a portion of the first compound region being crystalline, the first compound region including a first position, the first position being a center of the first compound region in the second direction; a second layer including Al, Si, O, and N, the second layer including a first intermediate region, the first intermediate region being provided between the first compound region and the first electrode portion in the second direction, a Si concentration in the first intermediate region being lower than an Al concentration in the first intermediate region, an oxygen concentration in the first intermediate region being higher than a nitrogen concentration in the first intermediate region, the first intermediate region including a second position, the second position being a center of the first intermediate region in the second direction, an Al concentration at the second position being lower than a first Al concentration at the first position, and a first ratio of a second nitrogen concentration at the second position to a second oxygen concentration at the second position being 0.1 or more and 0.2 or less; a first insulating layer including Si and O, the first insulating layer including a first insulating region, the first insulating region being provided between the first intermediate region and the first electrode portion in the second direction; The third layer, Equipped with at least a portion of the third layer is between the first intermediate region and the first insulating region; the third layer includes SiN or SiON; a third thickness of the at least part of the third layer along the second direction is not less than 0.1 nm and not more than 2 nm.

2. The semiconductor device according to claim 1 , wherein the first ratio is equal to or greater than 0.125 and equal to or less than 0.

175.

3. The semiconductor device according to claim 1 , wherein a concentration of Si in said first insulating region is higher than said concentration of Si in said first intermediate region.

4. the first insulating region does not contain Al, or 2. The semiconductor device according to claim 1, wherein a concentration of Al in said first insulating region is lower than a concentration of Si in said first insulating region.

5. The semiconductor device according to claim 1 , wherein at least a portion of said first intermediate region is amorphous.

6. The semiconductor device according to claim 1 , wherein at least a portion of said first insulating region is amorphous.

7. The semiconductor device according to claim 1 , wherein the thickness of the first compound region along the second direction is not less than 1 nm and not more than 10 nm.

8. The semiconductor device according to claim 1 , wherein the thickness of said first intermediate region along said second direction is not less than 0.5 nm and not more than 7 nm.

9. The semiconductor device according to claim 1 , wherein at least a part of said first electrode portion is located between said fourth partial region and said fifth partial region in said first direction.

10. the first layer further comprises a second compound region; the second layer further comprises a second intermediate region; the first insulating layer further includes a second insulating region; the second insulating region is located between the first electrode portion and the second semiconductor portion in the first direction; the second intermediate region is located between the second insulating region and the second semiconductor portion in the first direction; The semiconductor device according to claim 9 , wherein the second compound region is located between the second intermediate region and the second semiconductor portion in the first direction.

11. the first layer further includes a third compound region; the second layer further includes a third intermediate region; the first insulating layer further includes a third insulating region; the second semiconductor portion is located between the fifth portion region and the third insulating region in the second direction; the third compound region is located between the second semiconductor portion and the third insulating region in the second direction, 11. The semiconductor device according to claim 1, wherein the third intermediate region is located between the third compound region and the third insulating region in the second direction.

12. Further comprising a second insulating layer; the second insulating layer includes at least one selected from the group consisting of oxygen and nitrogen, and at least one selected from the group consisting of Si and Al; The semiconductor device according to claim 11 , wherein the second insulating layer includes a first insulating portion, and the first insulating portion is between the second semiconductor portion and the third compound region.

13. the third electrode further includes a second electrode portion; a position of the second electrode portion in the first direction is between the position of the first electrode portion in the first direction and the position of the second electrode portion in the first direction; the second electrode portion is continuous with the first electrode portion; a portion of the second semiconductor portion is provided between the fifth portion region and the second electrode portion in the second direction, 13. The semiconductor device according to claim 12, wherein a portion of the third compound region, a portion of the third intermediate region, and a portion of the third insulating region are located between the first insulating portion and the second electrode portion in the second direction.

14. the third electrode further includes a third electrode portion; the third electrode portion is between the first electrode portion and the second electrode portion; the third electrode portion is continuous with the first electrode portion and the second electrode portion, the part of the second semiconductor portion is further provided between the fifth portion region and the third electrode portion in the second direction, The semiconductor device according to claim 13 , wherein another part of the third compound region is located between the first electrode portion and the first insulating portion in the first direction.

15. The semiconductor device according to claim 14 , wherein the other part of the third compound region is in contact with the second semiconductor portion.

16. The semiconductor device according to claim 12 , wherein a portion of the third compound region is located between the first insulating portion and the second electrode in the first direction.

17. The semiconductor device according to claim 16 , wherein the portion of the third compound region is in contact with the second semiconductor portion.

18. the first compound region includes a first surface facing the third partial region, the third compound region includes a second surface facing the first insulating portion, 13. The semiconductor device according to claim 12, wherein a distance along the second direction between a position of the first surface in the second direction and a position of the second surface in the second direction is not less than 100 nm and not more than 400 nm.

19. 11. The semiconductor device according to claim 10, wherein a distance along the first direction between the first electrode and the first electrode portion is shorter than a distance along the first direction between the first electrode portion and the second electrode.

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