Semiconductor device and manufacturing method thereof

Abstract

A semiconductor device 1 comprises: a substrate 3 including a p-type substrate 4 and an n-type semiconductor layer 5 formed in the p-type substrate 4, and including an element region 2 having a transistor 40 having a drain of the n-type semiconductor layer; a p-type element isolating region 7 formed in an upper-layer portion of the substrate so as to define the element region; and an electrically conductive wire 25B disposed over a peripheral portion of the element region and electrically connected to the n-type semiconductor layer. The transistor in the peripheral portion of the element region includes an n+-type drain contact region 14 formed in an upper-layer portion of the n-type semiconductor layer. The electrically conductive wire is disposed so as to cover at least part of an element terminal region 30 between the n+-type drain contact region and the p-type element isolating region.

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device including a transistor such as a DMOS (Diffused Metal Oxide Semiconductor) transistor, and a method for manufacturing the same. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device including a p-type element isolation region (p-type well) that isolates an element region and a DMOS transistor formed in the element region. The semiconductor device includes a source region and a drain region selectively formed on the surface of an n-type epitaxial layer (n-type well) of a p-type substrate, and a gate electrode formed on a silicon substrate via a gate oxide film. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2012-156205 Summary of the Invention [Problem to be solved by the invention]

[0004] In a semiconductor device having an element isolation structure as in Patent Document 1, a DMOS transistor may be mounted together with other elements. In such a semiconductor device, not only a wiring electrically connected to the DMOS transistor but also a plurality of wirings (hereinafter referred to as "other wirings") electrically connected to elements other than the DMOS transistor (hereinafter referred to as "other elements") are formed. Various voltages according to the corresponding other elements are applied to the plurality of other wirings.

[0005] Therefore, in the DMOS transistor described in Patent Document 1, when a reverse voltage is applied to a parasitic diode existing between the n-type epitaxial layer and the p-type element isolation region, the equipotential distribution is disturbed due to the influence of potential from other wiring, and there is a risk of a decrease in breakdown voltage.

[0006] An object of the present invention is to provide a semiconductor device capable of suppressing a decrease in breakdown voltage due to the influence of the potential of other wiring. [Means for solving the problem]

[0007] One embodiment of the present invention provides a semiconductor device comprising: a base including a p-type substrate and an n-type semiconductor layer formed on the p-type substrate, the base including an element region having a transistor with the n-type semiconductor layer as a drain; a p-type element isolation region formed in a surface layer portion of the base so as to partition the element region; and conductive wiring arranged on a periphery of the element region and electrically connected to the n-type semiconductor layer, the transistor including an n-type drain contact region formed in a surface layer portion of the n-type semiconductor layer, at the periphery of the element region, and the conductive wiring arranged so as to cover at least a portion of an element termination region between the n-type drain contact region and the p-type element isolation region.

[0008] In this configuration, it is possible to suppress a decrease in breakdown voltage due to the influence of the potential of other wiring.

[0009] In one embodiment of the present invention, the device includes a drain wiring electrically connected to the n-type drain contact region, and the drain wiring has, in a planar view, an extension portion that extends into the element termination region, and the conductive wiring is composed of the extension portion.

[0010] In one embodiment of the present invention, the n-type drain contact region and the drain wiring are each formed endlessly in a planar view, and the extension portion is formed over the entire length of the drain wiring so as to surround the n-type drain contact region in a planar view.

[0011] In one embodiment of the present invention, in the element termination region, an n-type contact region for the conductive wiring is formed in the surface layer portion of the n-type semiconductor layer, and the conductive wiring is electrically connected to the n-type contact region via a conductive member.

[0012] In one embodiment of the present invention, the n-type drain contact region is formed endlessly in a planar view, and the n-type contact region and the conductive wiring are each formed endlessly so as to surround the n-type drain contact region in a planar view.

[0013] In one embodiment of the present invention, the semiconductor device further includes a drain wiring electrically connected to the n-type drain contact region, and the conductive wiring is electrically connected to the drain wiring via a conductive member.

[0014] In one embodiment of the present invention, the conductive wiring is formed on the n-type semiconductor layer within the element termination region via an insulating layer, and the drain wiring has an overlapping portion that overlaps a part of the conductive wiring in a planar view, and the lower surface of the overlapping portion and the upper surface of the conductive wiring are electrically connected by the conductive member.

[0015] In one embodiment of the present invention, the n-type drain contact region and the drain wiring are formed endlessly in a planar view, the conductive wiring is formed endlessly so as to surround the n-type drain contact region in a planar view, the drain wiring has the overlapping portion on its outer periphery, and the lower surface of the overlapping portion and the inner periphery of the upper surface of the conductive wiring are electrically connected by the conductive member.

[0016] In one embodiment of the present invention, the conductive wiring is made of polysilicon.

[0017] In one embodiment of the present invention, an n-type buried layer is formed in the center of the element region in a plan view so as to straddle the boundary between the p-type substrate and the n-type semiconductor layer.

[0018] In one embodiment of the present invention, the p-type element isolation well is formed endlessly in a planar view so as to surround the element region, and the n-type drain contact region is formed endlessly along the p-type element isolation well in a planar view.

[0019] In one embodiment of the present invention, the transistor includes a p-type well region formed in a surface layer portion of the n-type semiconductor layer, an n-type source region formed in a surface layer portion of the p-type well region, an n-type source contact region formed in the surface layer portion of the n-type source region and having a higher n-type impurity concentration than the n-type source region, and an n-type drain region formed endlessly in the surface layer portion of the n-type semiconductor layer so as to surround the p-type well region, and the n-type drain contact region is formed in the surface layer portion of the n-type drain region so as to surround the p-type well region and has a higher n-type impurity concentration than the n-type drain region.

[0020] In one embodiment of the present invention, the transistor further includes a gate insulating film formed to cover a channel region between the source contact region and the drain contact region, and a gate electrode formed on the gate insulating film and facing the channel region with the gate insulating film interposed therebetween.

[0021] In one embodiment of the present invention, the semiconductor device further includes a source wiring electrically connected to the n-type source contact region.

[0022] The above and other objects, features and advantages of the present invention will become apparent from the following description of the embodiments with reference to the accompanying drawings. [Brief explanation of the drawings]

[0023] [Figure 1] FIG. 1 is a schematic plan view for explaining the configuration of a semiconductor device according to a first embodiment of the present invention. [Figure 2] FIG. 2 is a schematic cross-sectional view taken along line II-II in FIG. [Figure 3] FIG. 3 is a schematic cross-sectional view showing an example of a simulation model relating to a comparative example. [Figure 4] FIG. 4 is a graph showing the simulation results for the comparative example. [Figure 5]FIG. 5 is a graph showing the simulation results for this embodiment. [Figure 6A] FIG. 6A is a cross-sectional view showing an example of a manufacturing process for the semiconductor device shown in FIGS. 1 and 2, and corresponds to the cross section of FIG. [Figure 6B] FIG. 6B is a cross-sectional view showing the next step of FIG. 6A. [Figure 6C] FIG. 6C is a cross-sectional view showing the step subsequent to FIG. 6B. [Figure 6D] FIG. 6D is a cross-sectional view showing the next step of FIG. 6C. [Figure 6E] FIG. 6E is a cross-sectional view showing the step subsequent to FIG. 6D. [Figure 6F] FIG. 6F is a cross-sectional view showing the step subsequent to FIG. 6E. [Figure 6G] FIG. 6G is a cross-sectional view showing the step subsequent to FIG. 6F. [Figure 7] FIG. 7 is a schematic plan view for explaining the configuration of a semiconductor device according to a second embodiment of the present invention. [Figure 8] FIG. 8 is a schematic cross-sectional view taken along line VIII-VIII in FIG. [Figure 9A] FIG. 9A is a cross-sectional view showing an example of a manufacturing process for the semiconductor device shown in FIGS. 7 and 8, and corresponds to the cross section of FIG. [Figure 9B] FIG. 9B is a cross-sectional view showing the next step of FIG. 9A. [Figure 9C] FIG. 9C is a cross-sectional view showing the step subsequent to FIG. 9B. [Figure 9D] FIG. 9D is a cross-sectional view showing the step subsequent to FIG. 9C. [Figure 9E] FIG. 9E is a cross-sectional view showing the step subsequent to FIG. 9D. [Figure 10] FIG. 10 is a schematic plan view for explaining the configuration of a semiconductor device according to a third embodiment of the present invention. [Figure 11] FIG. 11 is a schematic cross-sectional view taken along line X1-X1 in FIG. [Figure 12A]12A is a cross-sectional view showing an example of a manufacturing process of the semiconductor device shown in FIGS. 10 and 11, and is a cross-sectional view corresponding to the cross section of FIG. [Figure 12B] FIG. 12B is a cross-sectional view showing the next step of FIG. 12A. [Figure 12C] FIG. 12C is a cross-sectional view showing the next step of FIG. 12B. DETAILED DESCRIPTION OF THE INVENTION

[0024] Fig. 1 is a schematic plan view for explaining the configuration of a semiconductor device according to a first embodiment of the present invention. Fig. 2 is a schematic cross-sectional view taken along line II-II in Fig. 1. The interlayer insulating film 21 and source wiring 26 shown in Fig. 2 are omitted in Fig. 1. However, the drain wiring 25 shown in Fig. 2 is shown in Fig. 1.

[0025] In the following description, the left-right direction on the plane of FIG. 1 will be referred to as the horizontal direction, and the up-down direction on the plane of FIG. 1 will be referred to as the vertical direction.

[0026] The semiconductor device 1 includes a base 3. The base 3 includes a p-type semiconductor substrate 4 and an n-type semiconductor layer formed on the p-type semiconductor substrate 4. - In this embodiment, the p-type semiconductor substrate 4 is a silicon substrate. The p-type semiconductor substrate 4 is an example of the "p-type substrate" of the present invention, and is an n-type epitaxial layer 5. - The n-type epitaxial layer 5 is an example of the "n-type semiconductor layer" of the present invention.

[0027] n - The thickness of the p-type epitaxial layer 5 is, for example, about 3.0 μm to 10 μm. A p-type element isolation region 7 that partitions the element region 2 is formed in the surface layer portion of the base 3. In this embodiment, the element region 2 has a rectangular shape that is elongated in the vertical direction in a plan view. The element region 2 has n - A DMOS transistor 40 is formed using the epitaxial layer 5 as a drain.

[0028] The p-type element isolation region film 7 has an endless shape in plan view. In this embodiment, the p-type element isolation region 7 has a rectangular ring shape in plan view, but it may have an endless shape such as a circular ring or an elliptical ring. The p-type element isolation region 7 includes a lower isolation region 8 connected to the p-type semiconductor substrate and an upper isolation region 9 formed on the lower isolation region 8.

[0029] As a result, the base 3 has an n-type semiconductor substrate 4 surrounded by a p-type element isolation region 7. - An element region 2 made of a part of the p-type epitaxial layer 5 is defined in the p-type epitaxial layer 5. Although not shown, the p-type element isolation region 7 and the p-type semiconductor substrate 4 are grounded.

[0030] In the element region 2, a p-type semiconductor substrate 4 and an n - At the boundary of the p-type epitaxial layer 5, the p-type semiconductor substrate 4 and the n-type epitaxial layer 5 are - The n-type epitaxial layer 5 is formed across the n-type epitaxial layer 5. - The n-type epitaxial layer 5 has a higher impurity concentration than the n-type epitaxial layer 5. + A buried layer 6 is selectively formed. + The buried layer 6 is formed in a central region surrounded by the peripheral edge of the element region 2 in plan view. + The thickness of the mold-buried layer 6 is, for example, about 2.0 μm to 10.0 μm.

[0031] In addition, in the base 3, an element region (not shown) in which elements different from the DMOS transistor 40 in the element region 2 are formed is defined in the peripheral region of the element region 2.

[0032] A field insulating film 11 that is endless in plan view is formed on the surface of the p-type element isolation region 7. The field insulating film 11 is formed in a quadrangular ring shape in plan view so as to surround the region surrounded by the peripheral edge of the element region 2. The field insulating film 11 is wider than the p-type element isolation region 7 and is formed so as to completely cover the p-type element isolation region 7. The field insulating film 11 is, for example, - The LOCOS film is formed by selectively oxidizing the surface of the epitaxial layer 5 .

[0033] The DMOS transistor 40 is - The device region 2 includes an n-type drain region 13 and a p-type well region 15 formed at an interval from each other in a surface layer portion of the epitaxial layer 5. In this embodiment, the p-type well region 15 has a rectangular shape that is elongated in the vertical direction in a plan view, and is formed in the center of the device region 2 in the horizontal direction.

[0034] The n-type drain region 13 is - The n-type drain region 13 has a higher impurity concentration than the p-type epitaxial layer 5. The n-type drain region 13 is formed endlessly so as to surround the p-type well region 15 in plan view. In this embodiment, the n-type drain region 13 is formed in a square ring shape along the field insulating film 11 in plan view. The surface layer of the n-type drain region 13 has an n-type epitaxial layer 13 having a higher impurity concentration than the n-type drain region 13. + A type drain contact region 14 is formed.

[0035] The surface layer of the p-type well region 15 is - An n-type source region 16 having a higher impurity concentration than the n-type epitaxial layer 5 is formed in the surface layer of the n-type source region 16. + A source contact region 17 is formed.

[0036] The n-type source region 16 is formed to, for example, the same concentration and the same depth as the n-type drain region 13. + The outer periphery of the n-type source contact region 17 is spaced inward from the outer periphery of the p-type well region 15. + The source contact region 17 is, for example, an n + It is formed to the same concentration and depth as the type drain contact region 14 .

[0037] n - The surface of the n-type epitaxial layer 5 +A field insulating film 12 having a rectangular ring shape in plan view is formed between the p-type drain contact region 14 and the p-type well region 15. The field insulating film 12 is a LOCOS film formed in the same process as the above-mentioned field insulating film 11. In FIG. 1, the inner peripheral edge of the field insulating film 12 is indicated by the reference symbol 12a.

[0038] The inner periphery 12a of the field insulating film 12 is spaced outward from the outer periphery of the p-type well region 15, and the outer periphery of the field insulating film 12 is + The n-type drain contact region 14 is disposed on the inner periphery thereof. + The type drain contact region 14 is formed in a region sandwiched between the outer periphery of the field insulating film 12 and the inner periphery of the field insulating film 11 .

[0039] Also, n - The surface of the n-type epitaxial layer 5 - A gate insulating film 18 is formed across the n-type epitaxial layer 5 and the p-type well region 15. The gate insulating film 18 has a thickness of 100 nm in plan view. + The gate insulating film 18 is formed in a rectangular ring shape so as to surround the n-type source contact region 17. A gate electrode 19 is formed on the gate insulating film 18. The gate electrode 19 is formed in a rectangular ring shape so as to surround the n-type source region 16 in a plan view. The gate electrode 19 is formed so as to selectively cover a part of the gate insulating film 18 and a part of the field insulating film 12.

[0040] The gate electrode 19 is made of, for example, polysilicon. The gate insulating film 18 is made of, for example, n - The silicon oxide film is formed by oxidizing the surface of the silicon epitaxial layer 5.

[0041] The region where the gate electrode 19 faces the p-type well region 15 via the gate insulating film 18 is the channel region 20 of the DMOS transistor 40. The formation of the channel in the channel region 20 is controlled by the gate electrode 19.

[0042] An interlayer insulating film 21 is formed so as to cover the entire element region 2. The interlayer insulating film 21 is formed of an insulating film such as an oxide film or a nitride film.

[0043] A drain contact plug 22, a source contact plug 23, and a gate contact plug 24 are buried in the interlayer insulating film 21. The lower end of the drain contact plug 22 is + The lower end of the source contact plug 23 is electrically connected to the n-type drain contact region 14. + The gate contact plug 24 is electrically connected to the gate electrode 19.

[0044] A drain wiring 25, a source wiring 26, and a gate wiring (not shown) are formed on the interlayer insulating film 21. In FIG. 1, the region of the drain wiring 25 is shown as a hatched region with dots. The drain wiring 25 is connected to n-channel MOS transistors via a plurality of drain contact plugs 22. + The source wiring 26 is electrically connected to the n-type drain contact region 14 via a plurality of source contact plugs 23. + The gate wiring is electrically connected to the gate electrode 19 via a plurality of gate contact plugs 24.

[0045] Although not shown in FIG. 1, the source wiring 26 has a rectangular shape that is long in the vertical direction in plan view, and covers the intermediate portion of the length between both ends of the gate electrode 19. A plurality of points in the widthwise center of the source wiring 26 are connected to the n-type semiconductor layer 14 via a plurality of source contact plugs 23. + The gate electrode 19 is electrically connected to the source contact region 17. The gate wiring is electrically connected to both ends of the gate electrode 19 via a plurality of gate contact plugs 24.

[0046] The drain wiring 25 is formed in a quadrangular ring shape in plan view so as to surround the field insulating film 12. The inner periphery of the drain wiring 25 is +The outer periphery of the drain wiring 25 is located almost directly above the inner periphery of the n-type drain contact region 14. + The drain wiring 25 is located outside the outer periphery of the n-type drain contact region 14. + The wiring is made up of a main wiring portion 25A disposed directly above the type drain contact region 14, and an extension portion 25B extending outward from the outer periphery of the main wiring portion 25A. In the first embodiment, this extension portion 25B constitutes the "conductive wiring" of the present invention (hereinafter, sometimes referred to as "voltage-resistance-improved wiring").

[0047] The extension portion (voltage resistance improvement wiring) 25B has a rectangular ring shape in a plan view. + The extension 25B extends from the outer periphery of the n-type drain contact region 14 toward the p-type element isolation region 7 located outside the n-type drain contact region 14. In this embodiment, the extension 25B has a length of n-type + From the outer periphery of the n-type drain contact region 14 + The insulating layer 14 extends to approximately the center of the width between the outer periphery of the p-type drain contact region 14 and the inner periphery of the p-type element isolation region 7 outside it.

[0048] That is, the extension (withstand voltage improvement wiring) 25B is a peripheral region of the element region 2, and n + The insulating film 12 is disposed so as to cover a part of the element termination region 30 between the outer periphery of the p-type drain contact region 14 and the inner periphery of the p-type element isolation region 7 outside the outer periphery.

[0049] The extension portion 25B has a length of n in plan view. + It is sufficient that the extension 25B extends outward beyond the outer periphery of the n-type drain contact region 14. Therefore, in a plan view, the extension 25B has a width of, for example, n + From the outer periphery of the n-type drain contact region 14 + It may extend to any position between the outer periphery of the p-type drain contact region 14 and the inner periphery of the p-type element isolation region 7 outside it, or it may extend outward beyond the inner periphery of the p-type element isolation region 7.

[0050] If wiring for elements other than the DMOS transistor 40 (hereinafter referred to as "other wiring") runs above the element region 2, the potential of the other wiring may affect the n - When a reverse voltage is applied to the parasitic diode present between the p-type epitaxial layer 5 and the p-type element isolation region 7, the equipotential distribution is disturbed, which may result in a decrease in breakdown voltage. If the potential of the other wiring is the same as the potential (drain voltage) of the element region 2, the equipotential distribution is not disturbed, but if the potential of the other wiring is the ground potential, the equipotential distribution is disturbed.

[0051] In this embodiment, an extension (voltage-improving wiring) 25B that covers at least a portion of the device termination region 30 is formed on the drain wiring 25. This results in a configuration in which wiring (voltage-improving wiring) with the same potential as the device region 2 is arranged above the device termination region 30, so that even when the potential of the other wiring is at ground potential, the influence of the potential of the other wiring can be suppressed. This makes it possible to suppress the disruption of the equipotential distribution when the potential of the other wiring is at ground potential, and to suppress a decrease in the breakdown voltage of the DMOS transistor 40 or to improve the breakdown voltage.

[0052] 1 and 2 will be referred to as "this embodiment," and a configuration in which the drain wiring 25 does not have the extension portion 25B in the semiconductor device 1 of Figures 1 and 2 will be referred to as "comparative example." That is, in the comparative example, the drain wiring 25 is composed only of the main wiring portion 25A of this embodiment.

[0053] First, as shown in Figure 3, the breakdown voltage of the comparative example was calculated using a first simulation model 101 in which other wiring 50 (hereinafter referred to as "GND wiring") with a ground potential was placed on the device termination region 30. In Figure 3, the same reference numerals as in Figure 2 are used to denote the components corresponding to those in Figure 2. Furthermore, the breakdown voltage of the comparative example was calculated using a second simulation model in which no GND wiring was placed on the device termination region 30.

[0054] Specifically, n - Type epitaxial layer 5(n +The reverse voltage applied to the parasitic diode existing between the p-type drain contact region 14 and the p-type element isolation region 7 is V epi [V]. Also, the reverse current flowing through the parasitic diode is I epi [A]. Reverse voltage V epi When the reverse current I epi was calculated by simulation.

[0055] Similarly, with respect to this embodiment, the breakdown voltage of this embodiment was calculated using a third simulation model in which GND wiring was arranged on the element termination region 30. Also, with respect to this embodiment, the breakdown voltage of this embodiment was calculated using a fourth simulation model in which GND wiring was not arranged.

[0056] 4 is a graph showing the simulation results for the comparative example, in which the dashed line indicates the simulation results when the GND wiring is present, and the solid line indicates the simulation results when the GND wiring is not present.

[0057] Fig. 5 is a graph showing the simulation results for this embodiment, in which the dashed line indicates the simulation results when the GND wiring is present, and the solid line indicates the simulation results when the GND wiring is not present.

[0058] 4, in the comparative example, the breakdown voltage is lower when the GND wiring is present than when the GND wiring is not present. Also, in the comparative example, the absolute difference between the breakdown voltage when the GND wiring is present and the breakdown voltage when the GND wiring is not present is relatively large.

[0059] 5, in this embodiment, the breakdown voltage when the GND wiring is present is approximately equal to the breakdown voltage when the GND wiring is not present. Moreover, the breakdown voltage when the GND wiring is not present in this embodiment is higher than the breakdown voltage when the GND wiring is not present in the comparative example.

[0060] In other words, in this embodiment, the breakdown voltage when other wiring at ground potential exists is approximately equal to the breakdown voltage when other wiring at ground potential does not exist. In other words, in this embodiment, the breakdown voltage of the DMOS transistor does not decrease significantly even when other wiring at ground potential exists.

[0061] In addition, in this embodiment, the breakdown voltage when other wiring at ground potential exists is higher than that of the comparative example. Furthermore, in this embodiment, the breakdown voltage when other wiring at ground potential does not exist is also higher than that of the comparative example.

[0062] In addition, as a result of carrying out a similar simulation by changing the outward protrusion amount of the extension portion (withstand voltage improvement wiring) 25B of this embodiment, in all cases, the absolute value difference of the breakdown voltage between the case where the GND wiring is present and the case where it is not present is smaller than that of the comparative example. + If the distance from the outer edge of the p-type drain contact region 14 to the inner edge of the p-type element isolation region 7 outside it is L, the breakdown voltage becomes the largest when the outward protrusion amount of the extension portion (breakdown voltage improvement wiring) 25B is about half of L (about 0.5L).

[0063] 6A to 6G, a manufacturing process of the semiconductor device 1 will be described. Figures 6A to 6G are cross-sectional views for explaining an example of a manufacturing process of the semiconductor device 1, and are cross-sectional views corresponding to the cross section of Figure 2.

[0064] To manufacture the semiconductor device 1, a p-type semiconductor substrate 4 is prepared as shown in FIG. 6A. Next, n-type impurities and p-type impurities are selectively implanted into the surface of the p-type semiconductor substrate 4. Then, under a heated condition of, for example, 1100° C. or higher, silicon is epitaxially grown on the p-type semiconductor substrate 4 while the n-type impurities are being added. As a result, as shown in FIG. 6B, the p-type semiconductor substrate 4 and the n-type impurities are epitaxially grown on the p-type semiconductor substrate 4. - A substrate 3 is formed that includes a silicon-doped epitaxial layer 5 .

[0065] During epitaxial growth, the n-type impurities and p-type impurities implanted into the p-type semiconductor substrate 4 are - The n-type epitaxial layer 5 is then diffused in the growth direction of the p-type semiconductor substrate 4. - The n-type epitaxial layer 5 straddles the boundary + A p-type buried layer 6 and a p-type lower isolation region 8 are formed. Examples of p-type impurities include B (boron) and Al (aluminum), and examples of n-type impurities include P (phosphorus) and As (arsenic).

[0066] Next, as shown in FIG. 6C, an ion implantation mask (not shown) having selective openings in regions where p-type upper isolation regions 9 are to be formed is implanted into n-type silicon. - The p-type epitaxial layer 5 is then implanted with p-type impurities through the ion implantation mask. - The ions are implanted into the p-type epitaxial layer 5. As a result, the p-type element isolation region 7 is formed, which has a two-layer structure consisting of a lower isolation region 8 and an upper isolation region 9. After this, the ion implantation mask is removed.

[0067] Next, a hard mask 51 having selective openings in regions where the field insulating films 11 and 12 are to be formed is formed on the n - The n-type epitaxial layer 5 is then formed on the n-type epitaxial layer 5 through a hard mask 51. - The surface of the type epitaxial layer 5 is subjected to thermal oxidation treatment to form field insulating films 11 and 12. Thereafter, the hard mask 51 is removed.

[0068] Next, as shown in Figure 6D,- The surface of the type epitaxial layer 5 is subjected to thermal oxidation treatment to form a gate insulating film 18. At this time, the gate insulating film 18 is formed so as to be continuous with the field insulating films 11 and 12. Next, polysilicon for a gate electrode 19 is formed in the n-type epitaxial layer 5. - A polysilicon layer 52 is deposited on the epitaxial layer 5 .

[0069] 6E, a resist mask (not shown) having selective openings in regions where gate electrodes 19 are to be formed is formed on polysilicon layer 52. Then, unnecessary portions of polysilicon layer 52 are removed by etching through the resist mask, thereby forming gate electrodes 19. Thereafter, the resist mask is removed.

[0070] Next, in order to remove unnecessary portions of the gate insulating film 18, a hard mask (not shown) having selective openings is formed on the n - The hard mask is formed on the first epitaxial layer 5. Then, unnecessary portions of the gate insulating film 18 are etched through the hard mask. This forms the desired gate insulating film 18. Thereafter, the hard mask is removed. Note that the step of selectively etching the gate insulating film 18 may be omitted.

[0071] Next, as shown in Figure 6F, - A p-type well region 15 is formed in the surface layer of the n-type epitaxial layer 5. To form the p-type well region 15, first, an ion implantation mask (not shown) having openings selectively in the region where the p-type well region 15 is to be formed is formed. Then, p-type impurities are implanted through the ion implantation mask. - The p-type impurities are implanted into the p-type epitaxial layer 5. Thereafter, the p-type impurities are thermally diffused at a temperature of, for example, 900° C. to 1100° C. This forms the p-type well region 15. Thereafter, the ion implantation mask is removed.

[0072] Before the gate insulating film 18 and the gate electrode 19 are formed (FIG. 6C), the p-type impurity is introduced into the n -The p-type well region 15 may be formed by selectively implanting the p-type epitaxial layer 5 .

[0073] Next, n - An n-type drain region 13 is formed in the surface layer portion of the p-type epitaxial layer 5, and at the same time, an n-type source region 16 is formed in the inner region (surface layer portion) of the p-type well region 15. To form the n-type drain region 13 and the n-type source region 16, first, an ion implantation mask (not shown) having openings selectively in the region where the n-type drain region 13 and the n-type source region 16 are to be formed is formed. Then, n-type impurities are implanted through the ion implantation mask to form n - The ions are implanted into the n-type epitaxial layer 5. This forms the n-type drain region 13 and the n-type source region 16. After this, the ion implantation mask is removed.

[0074] Next, the n-type drain region 13 and the n-type source region 16 are respectively provided with n + type drain contact region 14 and n + The n-type source contact regions 17 are selectively formed. + type drain contact region 14 and n + To form the n-type source contact region 17, first + type drain contact region 14 and n + An ion implantation mask (not shown) having selective openings in the regions where the n-type source contact regions 17 are to be formed is formed. Then, n-type impurities are implanted into the n-type drain region 13 and the n-type source region 16 through the ion implantation mask. + type drain contact region 14 and n + The source contact regions 17 are formed, after which the ion implantation mask is removed.

[0075] Next, as shown in FIG. 6G, an insulating material is deposited to cover the gate electrode 19, thereby forming an interlayer insulating film 21. Next, a drain contact plug 22, a source contact plug 23, and a gate contact plug 24 are formed so as to penetrate the interlayer insulating film 21. The drain contact plug 22, the source contact plug 23, and the gate contact plug 24 are each formed of n + n-type drain contact region 14 + The gate electrode 19 is electrically connected to the source contact region 17 and the gate electrode 19, respectively.

[0076] Finally, drain wiring 25, source wiring 26, and gate wiring (not shown), which are electrically connected to drain contact plug 22, source contact plug 23, and gate contact plug 24, respectively, are selectively formed on interlayer insulating film 21. To form drain wiring 25, source wiring 26, and gate wiring, for example, a wiring material layer is formed on interlayer insulating film 21. Then, by selectively removing the wiring material layer by photolithography and etching, drain wiring 25, source wiring 26, and gate wiring are formed. Through the above steps, the semiconductor device 1 according to the first embodiment is manufactured.

[0077] Next, a semiconductor device 1A according to a second embodiment of the present invention will be described with reference to FIGS. 7 and 8. FIG. 7 is a schematic plan view illustrating the configuration of the semiconductor device according to the second embodiment of the present invention. FIG. 8 is a schematic cross-sectional view taken along line VIII-VIII in FIG. 7. The interlayer insulating film 21, drain wiring 25, and source wiring 26 shown in FIG. 8 are omitted in FIG. 7. However, the breakdown voltage improvement wiring 65 shown in FIG. 8 is shown in FIG. 7.

[0078] In Fig. 7, parts corresponding to the parts in Fig. 1 are denoted by the same reference numerals as in Fig. 1. In Fig. 8, parts corresponding to the parts in Fig. 2 are denoted by the same reference numerals as in Fig. 2.

[0079] The semiconductor device 1A according to the second embodiment has a different configuration of breakdown voltage improvement wiring compared to the semiconductor device 1 according to the first embodiment. In the semiconductor device 1 according to the first embodiment, the breakdown voltage improvement wiring is formed by an extension 25B of the drain wiring 25. In the semiconductor device 1A according to the second embodiment, a breakdown voltage improvement wiring is provided independently of the drain wiring 25.

[0080] In the second embodiment, the inner periphery of the field insulating film 11 covering the surface of the p-type element isolation region 7 is n-type in plan view. + It is located at a position spaced a certain distance outward from the outer periphery of the mold drain contact region 14 .

[0081] In a plan view, in the region between the n-type drain region 13 and the field insulating film 11, - In the epitaxial layer 5, an n-type region 61 is formed at a distance from the n-type drain region 13.

[0082] The n-type region 61 is formed in a rectangular ring shape along the field insulating film 11 in a plan view so as to surround the n-type drain region 13. The impurity concentration of the n-type region 61 is approximately equal to the impurity concentration of the n-type drain region 13. The surface layer of the n-type region 61 is provided with an n-type wiring for improving breakdown voltage, which has a higher impurity concentration than the n-type region 61. + A contact region 62 is formed. + The impurity concentration of the n-type contact region 62 is + The impurity concentration is approximately equal to that of the type drain contact region 14 .

[0083] n - The surface of the n-type epitaxial layer 5 + type contact region 62 and n + A field insulating film 63 having a rectangular ring shape in plan view is formed in the portion between the type drain contact region 14. The field insulating film 63 is a LOCOS film formed in the same process as the field insulating films 11 and 12 described above.

[0084] In addition to the drain contact plug 22, the source contact plug 23, and the gate contact plug 24, a contact plug 64 for a breakdown voltage improvement wiring is buried in the interlayer insulating film 21. The lower end of the contact plug 64 is + It is electrically connected to the mold contact region 62 .

[0085] On the interlayer insulating film 21, in addition to the drain wiring 25, the source wiring 26, and the gate wiring (not shown), a breakdown voltage improvement wiring 65 is formed. In FIG. 7, the region of the breakdown voltage improvement wiring 65 is shown as a hatched region with dots. In the second embodiment, the drain wiring 25 is composed of only the main wiring portion 25A of the drain wiring 25 of the first embodiment. The breakdown voltage improvement wiring 65 is connected to n-channel MOS transistors via a plurality of contact plugs 64. + The metal contact region 62 is electrically connected to the metal contact region 62 .

[0086] The breakdown voltage improvement wiring 65 is formed in a quadrangular ring shape in plan view so as to surround the field insulating film 63. In this embodiment, the inner periphery of the breakdown voltage improvement wiring 65 is n + The inner periphery of the breakdown voltage improvement wiring 65 is located almost directly above the inner periphery of the n-type contact region 62. + The outer periphery of the breakdown voltage improvement wiring 65 may be closer to the outer periphery of the n-type drain contact region 14. + In this embodiment, the outer periphery of the breakdown voltage improvement wiring 65 is located outside the outer periphery of the n-type contact region 62. + The contact region 62 is located between the outer periphery of the contact region 62 and the inner periphery of the p-type element isolation region 7 located outside the contact region 62 .

[0087] That is, the breakdown voltage improvement wiring 65 is in the peripheral region of the element region 2, and n + It is arranged so as to cover a part (in this example, the middle part in width) of the element termination region 30 between the outer periphery of the p-type drain contact region 14 and the inner periphery of the p-type element isolation region 7 outside it.

[0088] In this embodiment, a breakdown voltage improvement wiring 65 is provided that covers at least a part of the element termination region 30. This provides a configuration in which the breakdown voltage improvement wiring 65, which has the same potential as the element region 2, is arranged on the element termination region 30, so that even if the potential of the other wiring is at ground potential, the influence of the potential of the other wiring can be suppressed. As a result, when the potential of the other wiring is at ground potential, n - This can suppress the disturbance of the equipotential distribution when a reverse voltage is applied to the parasitic diode present between the p-type epitaxial layer and the p-type element isolation region 7. As a result, it is possible to suppress a decrease in the breakdown voltage of the DMOS transistor 40 or to improve the breakdown voltage.

[0089] Next, a manufacturing process of the semiconductor device 1A will be described with reference to Figures 9A to 9E. Figures 9A to 9E are cross-sectional views for explaining an example of a manufacturing process of the semiconductor device 1A, and are cross-sectional views corresponding to the cross section of Figure 8.

[0090] In the manufacturing method of this semiconductor device 1A, as in the manufacturing method of the semiconductor device 1 described above, a p-type semiconductor substrate 4 is prepared as shown in Fig. 6A. Then, n-type impurities and p-type impurities are selectively implanted into the surface of the p-type semiconductor substrate 4, and then silicon is epitaxially grown on the p-type semiconductor substrate 4 while adding the n-type impurities in a heated environment of, for example, 1100°C or higher. As a result, as shown in Fig. 6B, the p-type semiconductor substrate 4 and the n-type impurities are formed. - The substrate 3 includes the p-type epitaxial layer 5. This also forms a p-type semiconductor substrate 4 and an n-type epitaxial layer 5. - The n-type epitaxial layer 5 straddles the boundary + A p-type buried layer 6 and a p-type lower isolation region 8 are formed.

[0091] Next, as shown in FIG. 9A, an ion implantation mask (not shown) having selective openings in regions where p-type upper isolation regions 9 are to be formed is implanted into n - The p-type epitaxial layer 5 is then implanted with p-type impurities through the ion implantation mask. -The ions are implanted into the p-type epitaxial layer 5. As a result, the p-type element isolation region 7 is formed, which has a two-layer structure consisting of a lower isolation region 8 and an upper isolation region 9. After this, the ion implantation mask is removed.

[0092] Next, a hard mask 71 having selective openings in regions where the field insulating films 11, 12, and 63 are to be formed is formed. - The n-type epitaxial layer 5 is then formed on the n-type epitaxial layer 5 via a hard mask 71. - The surface of the type epitaxial layer 5 is subjected to thermal oxidation treatment to form field insulating films 11, 12, and 63. Thereafter, the hard mask 71 is removed.

[0093] Next, as shown in Figure 9B, - The surface of the type epitaxial layer 5 is subjected to thermal oxidation treatment to form a gate insulating film 18. At this time, the gate insulating film 18 is formed so as to be continuous with the field insulating films 11, 63, and 12. Next, polysilicon for the gate electrode 19 is formed in the n-type epitaxial layer 5. - A polysilicon layer 72 is deposited on the epitaxial layer 5 .

[0094] 9C, a resist mask (not shown) having selective openings in regions where gate electrodes 19 are to be formed is formed on polysilicon layer 72. Then, unnecessary portions of polysilicon layer 72 are removed by etching through the resist mask, thereby forming gate electrodes 19. Thereafter, the resist mask is removed.

[0095] Next, in order to remove unnecessary portions of the gate insulating film 18, a hard mask (not shown) having selective openings is formed on the n - The hard mask is formed on the first epitaxial layer 5. Then, unnecessary portions of the gate insulating film 18 are etched through the hard mask. This forms the desired gate insulating film 18. Thereafter, the hard mask is removed. Note that the step of selectively etching the gate insulating film 18 may be omitted.

[0096] Next, as shown in Figure 9D,- A p-type well region 15 is formed in the surface layer of the n-type epitaxial layer 5. To form the p-type well region 15, first, an ion implantation mask (not shown) having openings selectively in the region where the p-type well region 15 is to be formed is formed. Then, p-type impurities are implanted through the ion implantation mask. - The p-type impurities are implanted into the p-type epitaxial layer 5. Thereafter, the p-type impurities are thermally diffused at a temperature of, for example, 900° C. to 1100° C. This forms the p-type well region 15. Thereafter, the ion implantation mask is removed.

[0097] Before the gate insulating film 18 and the gate electrode 19 are formed (FIG. 9A), the p-type impurity is introduced into the n - The p-type well region 15 may be formed by selectively implanting the p-type epitaxial layer 5 .

[0098] Next, n - At the same time that the n-type drain region 13 and the n-type region 61 are formed in the surface layer portion of the p-type epitaxial layer 5, the n-type source region 16 is formed in the inner region (surface layer portion) of the p-type well region 15. The n-type drain region 13, the n-type region 61, and the n-type source region 16 are formed, for example, as follows.

[0099] That is, first, an ion implantation mask (not shown) having selective openings is formed in the region where the n-type drain region 13, the region where the n-type region 61, and the region where the n-type source region 16 are to be formed. Then, n-type impurities are implanted through the ion implantation mask to form n - The ions are implanted into the n-type epitaxial layer 5. This forms the n-type drain region 13, the n-type region 61, and the n-type source region 16. After this, the ion implantation mask is removed.

[0100] Next, the n-type drain region 13, the n-type region 61, and the n-type source region 16 are respectively provided in their inner regions (surface layers) with n + n-type drain contact region 14 + type contact region 62 and n +The n-type source contact regions 17 are selectively formed. + n-type drain contact region 14 + type contact region 62 and n + The source contact region 17 is formed, for example, as follows.

[0101] That is, first, n + n-type drain contact region 14 + type contact region 62 and n + An ion implantation mask (not shown) having selective openings in the regions where the n-type source contact regions 17 are to be formed is formed. Then, n-type impurities are implanted into the n-type drain region 13, the n-type region 61, and the n-type source region 16 through the ion implantation mask. + n-type drain contact region 14 + type contact region 62 and n + The source contact regions 17 are formed, after which the ion implantation mask is removed.

[0102] 9E, an insulating material is deposited to cover the gate electrode 19, thereby forming an interlayer insulating film 21. Next, a contact plug 64, a drain contact plug 22, a source contact plug 23, and a gate contact plug 24 are formed so as to penetrate the interlayer insulating film 21. The contact plug 64, the drain contact plug 22, the source contact plug 23, and the gate contact plug 24 are each formed of n + type contact region 62, n + n-type drain contact region 14 + The gate electrode 19 is electrically connected to the source contact region 17 and the gate electrode 19, respectively.

[0103] Finally, breakdown voltage improvement wiring 65, drain wiring 25, source wiring 26, and gate wiring (not shown), which are electrically connected to the contact plug 64, drain contact plug 22, source contact plug 23, and gate contact plug 24, respectively, are selectively formed on the interlayer insulating film 21. To form the breakdown voltage improvement wiring 65, drain wiring 25, source wiring 26, and gate wiring, for example, a wiring material layer is formed on the interlayer insulating film 21. Then, the wiring material layer is selectively removed by photolithography and etching, thereby forming the breakdown voltage improvement wiring 65, drain wiring 25, source wiring 26, and gate wiring. Through the above steps, the semiconductor device 1A according to the second embodiment is manufactured.

[0104] Next, a semiconductor device 1B according to a third embodiment of the present invention will be described with reference to FIGS. 10 and 11. FIG. 10 is a schematic plan view illustrating the configuration of the semiconductor device according to the third embodiment of the present invention. FIG. 11 is a schematic cross-sectional view taken along line XI-XI in FIG. 10. The interlayer insulating film 21, drain wiring 25, and source wiring 26 shown in FIG. 11 are omitted in FIG. 10. However, the breakdown voltage improvement wiring 81 shown in FIG. 11 is shown in FIG.

[0105] In Fig. 10, parts corresponding to those in Fig. 1 are denoted by the same reference numerals as in Fig. 1. In Fig. 11, parts corresponding to those in Fig. 2 are denoted by the same reference numerals as in Fig. 2.

[0106] The semiconductor device 1B according to the third embodiment has a different configuration of breakdown voltage improvement wiring compared to the semiconductor device 1 according to the first embodiment. In the semiconductor device 1 according to the first embodiment, the breakdown voltage improvement wiring is formed by an extension 25B of the drain wiring 25. In the semiconductor device 1B according to the third embodiment, a breakdown voltage improvement wiring is provided independently of the drain wiring 25. However, in the third embodiment, the drain wiring 25 has an extension 25B similar to the first embodiment, and this extension 25B also functions as a breakdown voltage improvement wiring.

[0107] In the third embodiment, a breakdown voltage improvement wiring 81 is formed on the field insulating film 11. In FIG. 10, the region of the breakdown voltage improvement wiring 81 is shown as a hatched region with dots. The breakdown voltage improvement wiring 81 has n + The wiring 81 for improving breakdown voltage is formed in a rectangular ring shape along the p-type element isolation region 7 so as to surround the p-type drain contact region 14. In this embodiment, the wiring 81 for improving breakdown voltage is made of polysilicon. The wiring 81 for improving breakdown voltage is covered with the interlayer insulating film 21.

[0108] The withstand voltage improvement wiring 81 is, in plan view, + The wiring 81 for improving breakdown voltage is formed on the outer side of the n-type drain contact region 14. In this embodiment, the inner periphery of the wiring 81 for improving breakdown voltage is + The wiring 81 is located at a position spaced a certain distance outward from the n-type drain contact region 14. + The outer periphery of the breakdown voltage improvement wiring 81 may be located directly above the outer periphery of the p-type drain contact region 14. On the other hand, the outer periphery of the breakdown voltage improvement wiring 81 is located inside the inner periphery of the p-type element isolation region 7.

[0109] That is, the breakdown voltage improvement wiring 81 is in the peripheral region of the element region 2, and + It is arranged so as to cover a part (in this example, the middle part in width) of the element termination region 30 between the outer periphery of the p-type drain contact region 14 and the inner periphery of the p-type element isolation region 7 outside it.

[0110] The drain wiring 25 is + The wiring 81 is made up of a main wiring portion 25A disposed directly above the drain contact region 14 and an extension portion 25B extending outward from the outer periphery of the main wiring portion 25A. In plan view, the extension portion 25B has an overlapping portion that overlaps the surface of the breakdown voltage improvement wiring 81. In the interlayer insulating film 21, a plurality of contact plugs 82 are embedded to electrically connect the overlapping portions of the extension portion 25B and the breakdown voltage improvement wiring 81.

[0111] The breakdown voltage improvement wiring 81 is electrically connected to the drain wiring 25 via a plurality of contact plugs 82. Therefore, the breakdown voltage improvement wiring 81 is electrically connected to the n-type wiring 25 via the contact plugs 82, the drain wiring 25, and the drain contact plug 22. - The epitaxial layer 5 is electrically connected to the silicon substrate 1 .

[0112] In this embodiment, a breakdown voltage improvement wiring 81 is provided that covers at least a part of the element termination region 30. This provides a configuration in which the breakdown voltage improvement wiring 81, which has the same potential as the element region 2, is arranged on the element termination region 30, so that even if the potential of the other wiring is at ground potential, the influence of the potential of the other wiring can be suppressed. As a result, when the potential of the other wiring is at ground potential, n - This can suppress the disturbance of the equipotential distribution when a reverse voltage is applied to the parasitic diode present between the p-type epitaxial layer and the p-type element isolation region 7. As a result, it is possible to suppress a decrease in the breakdown voltage of the DMOS transistor 40 or to improve the breakdown voltage.

[0113] Next, a manufacturing process of the semiconductor device 1B will be described with reference to Figures 12A to 12C. Figures 12A to 12C are cross-sectional views for explaining an example of a manufacturing process of the semiconductor device 1B, and are cross-sectional views corresponding to the cross section of Figure 11.

[0114] The above-described steps of FIGS. 6A to 6D are also applicable to the manufacturing method of the semiconductor device 1B. - 12A, a resist mask (not shown) having selective openings in regions where gate electrode 19 and breakdown voltage improvement wiring 81 are to be formed is formed on polysilicon layer 52. Then, unnecessary portions of polysilicon layer 52 are removed by etching through the resist mask. As a result, gate electrode 19 and breakdown voltage improvement wiring 81 are simultaneously formed. Thereafter, the resist mask is removed.

[0115] Next, in order to remove unnecessary portions of the gate insulating film 18, a hard mask (not shown) having selective openings is formed on the n - The hard mask is formed on the first epitaxial layer 5. Then, unnecessary portions of the gate insulating film 18 are etched through the hard mask. This forms the desired gate insulating film 18. Thereafter, the hard mask is removed. Note that the step of selectively etching the gate insulating film 18 may be omitted.

[0116] Next, as shown in FIG. 12B, - A p-type well region 15 is formed in the surface layer of the n-type epitaxial layer 5. To form the p-type well region 15, first, an ion implantation mask (not shown) having openings selectively in the region where the p-type well region 15 is to be formed is formed. Then, p-type impurities are implanted through the ion implantation mask. - The p-type impurities are implanted into the p-type epitaxial layer 5. Thereafter, the p-type impurities are thermally diffused at a temperature of, for example, 900° C. to 1100° C. This forms the p-type well region 15. Thereafter, the ion implantation mask is removed.

[0117] Before the gate insulating film 18 and the gate electrode 19 are formed (FIG. 6C), the p-type impurity is introduced into the n - The p-type well region 15 may be formed by selectively implanting the p-type epitaxial layer 5 .

[0118] Next, n - An n-type drain region 13 is formed in the surface layer portion of the p-type epitaxial layer 5, and at the same time, an n-type source region 16 is formed in the inner region (surface layer portion) of the p-type well region 15. To form the n-type drain region 13 and the n-type source region 16, first, an ion implantation mask (not shown) having openings selectively in the region where the n-type drain region 13 and the n-type source region 16 are to be formed is formed. Then, n-type impurities are implanted through the ion implantation mask to form n - The ions are implanted into the n-type epitaxial layer 5. This forms the n-type drain region 13 and the n-type source region 16. After this, the ion implantation mask is removed.

[0119] Next, the n-type drain region 13 and the n-type source region 16 are respectively provided with n + type drain contact region 14 and n + The n-type source contact regions 17 are selectively formed. + type drain contact region 14 and n + To form the n-type source contact region 17, first + type drain contact region 14 and n + An ion implantation mask (not shown) having selective openings in the regions where the n-type source contact regions 17 are to be formed is formed. Then, n-type impurities are implanted into the n-type drain region 13 and the n-type source region 16 through the ion implantation mask. + type drain contact region 14 and n + The source contact regions 17 are formed, after which the ion implantation mask is removed.

[0120] 12C, an insulating material is deposited so as to cover the gate electrode 19 and the breakdown voltage improvement wiring 81, thereby forming an interlayer insulating film 21. Next, a drain contact plug 22, a source contact plug 23, a gate contact plug 24, and a contact plug 82 are formed so as to penetrate the interlayer insulating film 21. The drain contact plug 22, the source contact plug 23, the gate contact plug 24, and the contact plug 82 are each formed of n + n-type drain contact region 14 + The source contact region 17, the gate electrode 19 and the breakdown voltage improvement wiring 81 are electrically connected to each other.

[0121] Finally, drain wiring 25, source wiring 26, and gate wiring (not shown) are selectively formed on the interlayer insulating film 21. The drain wiring 25 is electrically connected to the drain contact plug 22 and the breakdown voltage improvement wiring contact plug 82. The source wiring 26 and gate wiring are electrically connected to the source contact plug 23 and the gate contact plug 24, respectively. Through the above steps, the semiconductor device 1B according to the third embodiment is manufactured.

[0122] Although the embodiments of the present invention have been described in detail, these are merely examples used to clarify the technical contents of the present invention, and the present invention should not be construed as being limited to these examples, and the scope of the present invention is limited only by the appended claims.

[0123] This application corresponds to Patent Application No. 2020-44368 filed with the Japan Patent Office on March 13, 2020, the entire disclosure of which is incorporated herein by reference. [Explanation of symbols]

[0124] 1, 1A, 1B Semiconductor device 2. Element area 3 Base 4 p-type semiconductor substrate 5n - Type epitaxial layer 6n + Mold-embedding layer 7 p-type element isolation region 8 Lower separation area 9 Upper separation area 11 Field insulating film 12 Field insulating film 13 n-type drain region 14n + Type drain contact region 15 p-type well region 16 n-type source region 17n + Source contact region 18 Gate insulating film 19 Gate electrode 20 channel region 21 Interlayer insulating film 22 Drain contact plug 23 Source contact plug 24 Gate contact plug 25 Drain wiring 25A main wiring section 25B extension (voltage-resistant wiring) 26 Source wiring 30 Device termination area 40 DMOS transistors 51,71 Hard Mask 52,72 Polysilicon layer 61 n-type region 62n + Mold contact area 63 Field insulating film 64,82 Contact plug 65,81 Improved voltage resistance wiring

Claims

1. a base including a p-type substrate and an n-type semiconductor layer formed on the p-type substrate, the base including an element region having a transistor with the n-type semiconductor layer as a drain; a p-type element isolation region formed in a surface layer portion of the base body so as to partition the element region; a conductive wiring disposed on a periphery of the element region and electrically connected to the n-type semiconductor layer, the transistor includes an n-type drain contact region formed in a surface layer portion of the n-type semiconductor layer in a peripheral portion of the element region, the conductive wiring is disposed so as to cover at least a portion of a device termination region between the n-type drain contact region and the p-type device isolation region; a drain wiring electrically connected to the n-type drain contact region; the drain wiring has an extension portion that extends into the element termination region in a plan view, the conductive wiring is composed of the extension portion, The extension portion surrounds the n-type drain contact region in a plan view. The semiconductor device is formed over the entire length of the drain wiring.

2. 2. The semiconductor device according to claim 1, wherein said n-type drain contact region and said drain wiring are each formed endlessly in a plan view.

3. A substrate including a p-type substrate and an n-type semiconductor layer formed on the p-type substrate, the substrate including an element region having a transistor with the n-type semiconductor layer as a drain; a p-type element isolation region formed in a surface layer portion of the base body so as to partition the element region; a conductive wiring disposed on a periphery of the element region and electrically connected to the n-type semiconductor layer, the transistor includes an n-type drain contact region formed in a surface layer portion of the n-type semiconductor layer in a peripheral portion of the element region, the conductive wiring is disposed so as to cover at least a portion of a device termination region between the n-type drain contact region and the p-type device isolation region; an n-type contact region for the conductive wiring is formed in a surface layer portion of the n-type semiconductor layer in the element termination region; The conductive wiring is electrically connected to the n-type contact region via a conductive member.

4. the n-type drain contact region is formed endlessly in a plan view, 4. The semiconductor device according to claim 3, wherein said n-type contact region and said conductive wiring are each formed endlessly so as to surround said n-type drain contact region in a plan view.

5. A substrate including a p-type substrate and an n-type semiconductor layer formed on the p-type substrate, the substrate including an element region having a transistor with the n-type semiconductor layer as a drain; a p-type element isolation region formed in a surface layer portion of the base body so as to partition the element region; a conductive wiring disposed on a periphery of the element region and electrically connected to the n-type semiconductor layer, the transistor includes an n-type drain contact region formed in a surface layer portion of the n-type semiconductor layer in a peripheral portion of the element region, the conductive wiring is disposed so as to cover at least a portion of a device termination region between the n-type drain contact region and the p-type device isolation region; a drain wiring electrically connected to the n-type drain contact region; the conductive wiring is electrically connected to the drain wiring via a conductive member; the conductive wiring is formed on the n-type semiconductor layer via an insulating layer in the element termination region, the drain wiring has an overlapping portion that overlaps a part of the conductive wiring in a plan view, the n-type drain contact region and the drain wiring are formed endlessly in a plan view, the conductive wiring is formed endlessly in a plan view so as to surround the n-type drain contact region, the drain wiring has the overlapping portion at its outer periphery, The lower surface of the overlapping portion and the inner peripheral edge of the upper surface of the conductive wiring are electrically connected by the conductive member.

6. 6. The semiconductor device according to claim 5, wherein said conductive wiring is made of polysilicon.

7. 7. The semiconductor device according to claim 1, wherein an n-type buried layer is formed in a central portion of the element region in a plan view so as to straddle a boundary between the p-type substrate and the n-type semiconductor layer.

8. the p-type element isolation region is formed endlessly to surround the element region in plan view, 8. The semiconductor device according to claim 1, wherein the n-type drain contact region is formed endlessly along the p-type element isolation region in a plan view.

9. The transistor is a p-type well region formed in a surface layer portion of the n-type semiconductor layer; an n-type source region formed in a surface layer portion of the p-type well region; an n-type source contact region formed in a surface layer portion of the n-type source region and having a higher n-type impurity concentration than the n-type source region; an n-type drain region formed endlessly in a surface layer portion of the n-type semiconductor layer so as to surround the p-type well region, the n-type drain contact region is formed in a surface layer portion of the n-type drain region so as to surround the p-type well region, and has an n-type impurity concentration higher than that of the n-type drain region; The semiconductor device according to any one of claims 1 to 8.

10. The transistor is a gate insulating film formed to cover a channel region between the n-type source contact region and the n-type drain contact region; 10. The semiconductor device according to claim 9, further comprising: a gate electrode formed on said gate insulating film and facing said channel region via said gate insulating film.

11. 11. The semiconductor device according to claim 9, further comprising a source wiring electrically connected to said n-type source contact region.

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