Method for forming a bipolar transistor including a vertical collector contact

Abstract

A method for forming a bipolar transistor including a vertical collector contact involves providing a transistor comprising multiple epitaxial semiconductor layers on a first substrate and providing a host substrate. A metal collector contact is patterned on the top surface of the host substrate, and the multiple epitaxial semiconductor layers are transferred from the first substrate onto the metal collector contact on the host substrate. The first substrate is preferably a growth substrate for the multiple epitaxial semiconductor layers. The host substrate preferably has a higher thermal conductivity than the first substrate, which improves the heat dissipation characteristics of the transistor and allows the transistor to operate at a higher power density. Multiple transistors can be transferred onto a common host substrate to form a multi-finger transistor.

Description

[Technical Field]

[0001] The present invention relates generally to bipolar transistors, and more particularly to methods of forming bipolar transistors that include vertical collector contacts. [Background technology]

[0002] Thermal management is a continuing problem for integrated bipolar transistors, especially when used as part of power amplifiers. For example, power density (W / cm) in heterojunction bipolar transistor (HBT)-based power amplifiers and mixed-signal circuits is 2 ) are often limited by thermal considerations, with HBT junction temperatures typically required to remain below a certain temperature for reliable operation or to meet specified performance criteria.

[0003]

[0003] Conventional HBTs typically use a structure in which lateral base contacts are located on either side of the emitter contact and lateral collector contacts are located outside the base contact. This configuration results in a large footprint, and the active semiconductor device area must be reduced to support these lateral contacts. Furthermore, the collector resistance to the contact through the subcollector semiconductor layer (known as "collector access resistance") adversely affects the RF performance and efficiency of multi-finger HBTs. Summary of the Invention [Means for solving the problem]

[0004] A method is presented for forming a bipolar transistor that includes a vertical collector contact that allows operation at higher power densities with a compact device footprint.

[0005] The method involves providing a transistor comprising a plurality of epitaxial semiconductor layers on a first substrate and providing a host substrate. Metal collector contacts are patterned on the top surface of the host substrate, and then the plurality of epitaxial semiconductor layers are transferred from the first substrate onto the metal collector contacts on the host substrate. In a preferred embodiment, the plurality of epitaxial semiconductor layers form a heterojunction bipolar transistor (HBT).

[0005]

[0006] The first substrate is preferably a growth substrate for the plurality of epitaxial semiconductor layers. The host substrate preferably has a higher thermal conductivity than the first substrate, which improves the heat dissipation characteristics of the transistor when compared to conventional designs and allows the transistor to operate at higher power densities.

[0006]

[0007] A plurality of transistor fingers with an array of emitter and base contacts can be transferred onto a common host substrate to form a multi-finger transistor. The transistors can be transferred onto a common metal collector contact patterned on the top surface of the host substrate.

[0007]

[0008] In one embodiment, the metal collector contact is embedded in an opening patterned and etched in an electrically insulating dielectric layer at the surface of the host substrate such that the surface of the collector contact is approximately flush with the top surface of the dielectric layer. In another embodiment, an opening is etched into the top surface of the host substrate and the metal collector contact is formed in the opening.

[0008]

[0009] These and other features, aspects, and advantages of the present invention will become better understood with reference to the following drawings, description, and claims. [Brief explanation of the drawings]

[0009] [Figure 1]

[0010] FIG. 1 is a flow diagram illustrating one possible embodiment of the method. [Figure 2A]

[0011] 1 is a cross-sectional view of multiple epitaxial semiconductor layers on a first substrate. [Figure 2B]

[0012] 2B is a cross-sectional view of the plurality of epitaxial semiconductor layers of FIG. 2A after being transferred to a host substrate according to the present method. [Figure 2C]

[0013] 2B is a cross-sectional view of the plurality of epitaxial semiconductor layers of FIG. 2A after being transferred to a host substrate using another embodiment of the present method. [Figure 3A]

[0014] 1 is a cross-sectional view of multiple epitaxial semiconductor layers including a subcollector layer on a first substrate. [Figure 3B]

[0015] 3B is a cross-sectional view of the plurality of epitaxial semiconductor layers of FIG. 3A after being transferred to a host substrate according to the present method. [Figure 4A]

[0016] 1 is a cross-sectional view of multiple transistors each comprising multiple epitaxial semiconductor layers after being transferred to a common host substrate including a common metal collector contact. [Figure 5A]

[0017] 1A-1C illustrate one possible sequence of steps that can be used to form a multi-finger transistor, preferably an HBT, according to the present method. [Figure 5B] 1A-1C illustrate one possible sequence of steps that can be used to form a multi-finger transistor, preferably an HBT, according to the present method. [Figure 5C] 1A-1C illustrate one possible sequence of steps that can be used to form a multi-finger transistor, preferably an HBT, according to the present method. [Figure 5D] 1A-1C illustrate one possible sequence of steps that can be used to form a multi-finger transistor, preferably an HBT, according to the present method. [Figure 5E] 1A-1C illustrate one possible sequence of steps that can be used to form a multi-finger transistor, preferably an HBT, according to the present method. [Figure 5F]1A-1C illustrate one possible sequence of steps that can be used to form a multi-finger transistor, preferably an HBT, according to the present method. [Figure 5G] 1A-1C illustrate one possible sequence of steps that can be used to form a multi-finger transistor, preferably an HBT, according to the present method. [Figure 5H] 1A-1C illustrate one possible sequence of steps that can be used to form a multi-finger transistor, preferably an HBT, according to the present method. DETAILED DESCRIPTION OF THE INVENTION

[0010]

[0018] One embodiment of the present method for forming a bipolar transistor including a vertical collector contact is shown in Figure 1. A transistor is provided (Step 10) comprising a plurality of epitaxial semiconductor layers (also referred to herein as "epilayers") on a first substrate. A host substrate is also provided (Step 12). A metal collector contact is patterned on the top surface of the host substrate (Step 14), and the plurality of epitaxial semiconductor layers from the first substrate are transferred directly onto the metal collector contact on the host substrate (Step 16). In this manner, the metal collector contact serves as the vertical collector contact for the transistor.

[0011]

[0019] This process can be beneficially used to maximize semiconductor utilization in the first substrate. Discrete transistors or multi-finger transistor structures can be fabricated on the first substrate with high integration density. These transistors can be transferred onto a host substrate containing patterned metal collector contacts at a lower density for a given integrated circuit design. For circuit designs such as high-frequency RF power amplifiers, active device arrays can occupy <1% of the total circuit area. With proper design, multiple host substrates can be populated with transistors from a single initial substrate containing epitaxial layers. Because epitaxy growth and transistor fabrication costs account for a large portion of integrated circuit manufacturing costs, this approach offers the potential for significant cost reduction. Furthermore, the performance of the transferred transistors can be improved. For example, if the host substrate is appropriately selected, heterojunction bipolar transistors (HBTs) transferred to a host substrate containing patterned metal collector contacts on its top surface have improved thermal performance.

[0012]

[0020] There are several ways in which a metal collector contact may be formed on the top surface of a preferably planar host substrate (step 14). For example, as shown in step 18, an electrically insulating dielectric layer may be formed on the surface of the host substrate. The metal collector contact may then be embedded in the dielectric layer (step 20), preferably so that the surface of the contact is generally flush with the top surface of the dielectric layer. In this example, the electrically insulating dielectric layer is preferably patterned and etched to form openings, and metal is deposited in the openings to form the metal collector contacts. Alternatively, openings may be etched into the top surface of the host substrate (step 22), and metal collector contacts are formed in the openings (step 24).

[0013]

[0021] The method may also be used to form multi-finger transistors. For example, as shown in step 26, multiple transistors can be transferred onto a common metal collector contact patterned on the top surface of a host substrate to form a multi-finger transistor.

[0014]

[0022] Exemplary devices fabricated according to various embodiments of the present method are now discussed. For example, in FIG. 2A, multiple epitaxial semiconductor layers are shown on a first substrate 36, including an emitter layer 30, a base layer 32, and a collector layer 34, and electrical contacts to the emitter and base layers, such as contacts 38, may also be present. According to the present method, the epilayers 30, 32, and 34 are transferred to a host substrate 40 on which a metal collector contact 42 is formed; this structure is shown in FIG. 2B. Note that contact 38 may be formed before or after the transfer of the epitaxial semiconductor layers to the host substrate 40.

[0015]

[0023] In the example shown in Figure 2B, an electrically insulating dielectric layer 44 is formed on the top surface of the host substrate 40, and a metal collector contact 42 is embedded in the dielectric layer, preferably so that the surface of the contact is generally flush with the top surface of the layer. For this embodiment, the dielectric layer 44 is preferably patterned and etched to form openings, and metal is deposited in the openings to form the metal collector contacts 42. Alternatively, as shown in Figure 2C, openings may be etched into the top surface of the host substrate 40, and the metal collector contacts 42 formed in the openings. The collector layer 34 is preferably N - The placement of the collector layer comprising the material and directly on the metal collector contact 42 forms a Schottky contact at their interface.

[0016]

[0024] Another embodiment is shown in Figures 3A and 3B. In Figure 3A, multiple epitaxial semiconductor layers are formed on a first substrate 58, including an emitter layer 50, a base layer 52, a collector layer 54, and a subcollector layer 56, and electrical contacts to the emitter and base layers, such as contact 60, may also be present. According to this method, layers 50, 52, 54, and 56 are transferred to a host substrate 62 on which a metal collector contact 64 is formed. This structure is shown in Figure 3B. In this example, the collector contact 64 is formed in an opening etched in the top surface of the host substrate 62, although the collector contact may alternatively be buried in an electrically insulating dielectric layer, as previously described with reference to Figure 2B. The subcollector layer 56 is preferably N ++ The placement of the sub-collector layer directly on the metal collector contact 42, including the material, forms an ohmic contact at their interface.

[0017] The host substrate preferably has a higher thermal conductivity than the first substrate, which improves the heat dissipation characteristics of the transistor. A metal collector contact on a high thermal conductivity substrate can significantly improve heat dissipation near the junction of a transistor, such as an HBT, allowing for higher power densities (W / cm) when compared to conventional designs. 2 ) This allows devices produced according to the present method to occupy a smaller footprint than existing designs or to provide higher performance (output power or functionality) in a constrained area. Suitable materials for the host substrate include silicon (Si), silicon carbide (SiC), aluminum nitride (AlN), or diamond.

[0018]

[0025] The epitaxial semiconductor layers referenced in step 10 of Figure 1 preferably comprise III-V materials. For example, the epitaxial semiconductor layers may include a combination of indium phosphide (InP), indium gallium arsenide (InGaAs), indium aluminum arsenide (InAlAs), indium arsenide (InAs), and gallium arsenide antimonide (GaAsSb). The first substrate containing such epitaxial layers is typically InP, which has poor thermal properties, although many other materials may be used.

[0019]

[0026] While this method is useful for transferring a single transistor from a first substrate to a host substrate, it is more practical to transfer multiple transistors onto a common host substrate. This technique can be used to form discrete, isolated transistors or to form the multi-finger transistors often used in power amplifier designs. This can be achieved in several ways. For example, in FIG. 4A , multiple transistors 70 comprising multiple epitaxial semiconductor layers on a first substrate—in this example, consisting of emitter 72, common base layer 74, common collector layer 76, emitter contact 78, and base contact 80—are transferred onto a common metal collector contact 82 formed in an opening etched in the top surface of host substrate 84, thereby forming multi-finger transistor 86. The collector contact so formed is preferably planarized before transfer. In this example, collector contact 82 is formed in an opening etched in the top surface of host substrate 84, but the collector contact may alternatively be embedded in an electrically insulating dielectric layer, as previously described with reference to FIG. 2B . Similarly, although FIG. 4A shows transistor 70 including emitter, base, and collector layers, a transistor including a sub-collector layer may also be used.

[0020]

[0027] One possible process sequence that can be used to form a multi-finger transistor, preferably an HBT, according to the present method is shown in Figures 5A-5H. In Figure 5A, a structure is provided or formed that includes a plurality of emitters 110, a common base layer 112, and a common collector layer 114 epitaxially grown on a first substrate 116. Emitter contacts 118 are preferably provided or formed on each emitter 110. To simplify the subsequent step of removing first substrate 116 from layers 110, 112, and 114 (described below), a sacrificial etch layer 120 is preferably provided between first substrate 116 and common collector layer 114.

[0021]

[0028] In FIG. 5B, base contacts 122 are defined on common base layer 112, and in FIG. 5C, layer 112 is patterned and etched to provide base mesa isolation, if desired.

[0022]

[0029] In Figure 5D, a layer, such as a BCB dielectric layer 124, is typically provided and interconnects 126 may be formed on the device. Next, in Figure 5E, the BCB layer 124 may be patterned, a mesa etch performed, and the remaining structure - mesa 128 - is then encapsulated using, for example, a polymer (polymer strap) 130.

[0023]

[0030] In FIG. 5F, a stamp 132 is preferably attached to the top surface of the polymer strap 130, and the transistor mesa 128 is separated from the first substrate 116—preferably by performing an etch release using a sacrificial etchant layer, such as layer 120.

[0024]

[0031] In Figure 5G, a host substrate 134 is provided that includes a metal collector contact 136 formed on the top surface of the host substrate. In the example shown, the collector contact 136 is embedded in an opening formed in a dielectric layer 138, preferably made of SiO2. As mentioned above, the collector contact 136 may alternatively be formed in an opening etched into the top surface of the host substrate 134. It will be apparent that the host substrate can be prepared independently of the other steps in the process shown; i.e., it is not required that the host substrate be prepared during the steps shown in Figures 5F and 5H.

[0025]

[0032] In Figure 5H, the mesa 128 is transferred onto the metal collector contact 136 on the host substrate 134, and the polymer encapsulant 130 is removed. Assuming the host substrate 134 has a higher thermal conductivity than the first substrate 116, the heat dissipation characteristics of the device are improved. As mentioned above, this allows the transistor to have a higher power density (W / cm) when compared to conventional designs. 2 ), which allows the device to occupy a smaller footprint than existing designs or to provide higher performance (output power or functionality) in a constrained area.

[0026]

[0033] The method further allows multi-finger transistors to be designed without the need for lateral collector contacts, which can significantly increase unit power cell power density without the penalty in collector access resistance that would otherwise affect efficiency. Furthermore, by eliminating the lateral collector contact, the transistor footprint can be significantly reduced.

[0027]

[0034] The transfer of the epitaxial layer from the first substrate to the host substrate can be achieved by many different techniques. One way transfer can be achieved is through the use of microtransfer printing. In one example of this process, a polydimethylsiloxane (PDMS) stamp is used to lift an HBT epitaxy prepared by the technique of Figure 5F. The HBT epitaxy can then be placed on the host substrate. The microtransfer printing process relies on the rate-sensitive adhesion of the stamp head to the device to achieve device lift and placement. This dependence stems from the viscoelastic behavior of the PDMS polymer. The microtransfer printing process can be used to lift a single HBT or an array of HBTs, eliminating the planarity requirement of the entire wafer bonding process. The process allows for the efficient use of HBT epitaxy from a donor substrate in a batch manufacturing process.

[0028]

[0035] The patterned collector contact preferably has a large thickness. Thick, patterned collector contact metal can be achieved using a chemical-mechanical polishing (CMP) process while maintaining wafer planarity. Thick metal is preferred because it improves current handling and heat dissipation. This process, with the addition of one or more sacrificial etch layers below the epilayer, is compatible with existing HBT process flows and epitaxy designs.

[0029]

[0036] This process can be used, for example, to improve output power and efficiency in microwave and millimeter-wave power amplifiers. It can also be used to improve transistor density in mixed-signal circuits to provide improvements in speed, bandwidth, and dynamic range.

[0030]

[0037] Note that it is possible to obtain multiple one-finger transistors (e.g., as shown in Figures 2B, 2C, and 3B) and multi-finger transistors (e.g., as shown in Figure 4A) deposited on a host substrate on separate collector contacts. This can be done in a single transfer step or in multiple steps. Thus, integrated circuits of different functions can be realized by wiring the transistors together.

[0031]

[0038] The embodiments of the invention described herein are exemplary, and many modifications, variations, and rearrangements may readily be envisioned to achieve substantially equivalent results, all of which are intended to be within the spirit and scope of the invention as defined in the appended claims.

Claims

1. providing a transistor comprising a plurality of epitaxial semiconductor layers on a first substrate; providing a host substrate; patterning a metal collector contact on the top surface of the host substrate; transferring the plurality of epitaxial semiconductor layers from the first substrate directly onto the metal collector contact on the host substrate such that one of the plurality of epitaxial semiconductor layers is in direct contact with the metal collector contact; 1. A method for forming a bipolar transistor including a vertical collector contact, comprising:

2. the plurality of epitaxial semiconductor layers comprising an emitter layer, a base layer, and a collector layer, the collector layer overlying the metal collector contact such that a Schottky contact is formed; The method of claim 1.

3. The collector layer is N － Materials include, The method of claim 2.

4. the plurality of epitaxial semiconductor layers comprising an emitter layer, a base layer, a collector layer, and a sub-collector layer, the sub-collector layer being on the metal collector contact such that an ohmic contact is formed; The method of claim 1.

5. The sub-collector layer is N ＋＋ Materials include, The method of claim 4.

6. the plurality of epitaxial semiconductor layers form a heterojunction bipolar transistor (HBT); The method of claim 1.

7. the transferring step includes transferring a localized region of epitaxy from the first substrate to the host substrate; The method of claim 1.

8. The plurality of epitaxial semiconductor layers on the first substrate further comprises a sacrificial etching layer between the epitaxial semiconductor layers and the first substrate, and the transferring step comprises: encapsulating the epitaxial semiconductor layer and the sacrificial etch layer in a polymer; Etching the sacrificial etch layer to release the epitaxial semiconductor layer from the first substrate; using a stamp to transfer the detached and encapsulated epitaxial semiconductor layer onto the metal collector contact on the host substrate; removing the polymer encapsulating the epitaxial semiconductor layer and the sacrificial etch layer; Including, The method of claim 1.

9. the step of providing a transistor comprises providing a plurality of the transistors, and the step of transferring comprises transferring a plurality of the transistors onto a common host substrate. The method of claim 1.

10. transferring the plurality of transistors onto a common metal collector contact patterned on the top surface of the host substrate to form a multi-finger transistor.

10. The method of claim 9.

11. transferring the plurality of transistors onto respective metal collector contacts patterned on the top surface of the host substrate to form a multi-finger transistor; 10. The method of claim 9.

12. the host substrate has a higher thermal conductivity than the first substrate; The method of claim 1.

13. the host substrate comprises silicon (Si), silicon carbide (SiC), aluminum nitride (AlN), or diamond; The method of claim 12.

14. the plurality of epitaxial semiconductor layers comprising a III-V material; The method of claim 1.

15. the plurality of epitaxial semiconductor layers comprising a combination of indium phosphide (InP), indium gallium arsenide (InGaAs), indium aluminum arsenide (InAlAs), indium arsenide (InAs), and gallium arsenide antimonide (GaAsSb); The method of claim 1.

16. the metal collector contact is embedded in the electrically insulating dielectric layer at the surface of the host substrate such that the surface of the metal collector contact is approximately flush with the upper surface of the electrically insulating dielectric layer; The method of claim 1.

17. patterning and etching the electrically insulating dielectric layer to form openings; depositing metal in the opening to form the metal collector contact; 17. The method of claim 16, further comprising:

18. further comprising planarizing the metal collector contact using chemical mechanical polishing (CMP).

18. The method of claim 17.

19. the plurality of epitaxial semiconductor layers comprising an emitter layer, a base layer, and a collector layer, the method further comprising the step of fabricating electrical contacts to the emitter layer and the base layer after the step of transferring the plurality of epitaxial semiconductor layers from the first substrate onto the metal collector contact on the host substrate. The method of claim 1.

20. the plurality of epitaxial semiconductor layers comprising an emitter layer, a base layer, and a collector layer, the method further comprising the step of fabricating electrical contacts to the emitter layer and the base layer prior to the step of transferring the plurality of epitaxial semiconductor layers from the first substrate onto the metal collector contact on the host substrate. The method of claim 1.

21. the first substrate is a growth substrate for the plurality of epitaxial semiconductor layers; The method of claim 1.

22. etching an opening in the top surface of the host substrate; and forming the metal collector contact in the opening. The method of claim 1.

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