Process for transferring a thin layer onto a carrier substrate provided with a charge trapping layer

Abstract

The present invention relates to a process for transferring a thin layer (5) to a carrier substrate (1), comprising the steps of preparing the carrier substrate (1) using a fabrication process including providing a base substrate (3) having a charge trapping layer (2) on a major surface thereof and forming a dielectric layer (4) on the charge trapping layer (2) with a thickness of more than 200 nm. The dielectric layer (4) is formed by simultaneous dielectric layer deposition and ion sputtering. The transfer process also includes bonding a donor substrate to the dielectric layer (4) of the carrier substrate (1) by molecular bonding without creating a free surface of the dielectric layer (4) by polishing, where the donor substrate is characterized by a weakened plane that defines the thin layer (5). The process finally includes splitting the donor substrate at the weakened plane, thereby releasing and transferring the thin layer (5) to the carrier substrate (1).

Description

[Technical Field]

[0001] FIELD OF THE INVENTION The present invention relates to a process for transferring thin layers onto carrier substrates provided with charge trapping layers. These substrates are particularly applicable in the field of radio frequency integrated devices, i.e. electronic devices handling signals in the frequency range of approximately 3 kHz to 300 GHz, for example in the field of telecommunications (telephone, Wi-Fi, Bluetooth, etc.). These substrates are also applicable in the field of photonics. Description of the Prior Art

[0002] (Technical Background of the Invention) To prevent or limit the effects of electromagnetic coupling between an electronic or photonic device and a carrier substrate of a silicon-on-insulator (SOI) substrate on which the device is formed, it is known to insert a charge trapping layer between the buried dielectric layer and the SOI carrier, directly below the dielectric layer. This layer can consist of, for example, a 1-10 micron layer of polycrystalline silicon. The boundaries of the polycrystalline grains form traps for charge carriers, which may originate from the trapping layer itself or from the underlying substrate. This prevents the formation of a conductive plane below the insulating layer. The production of known SOI substrates of this type is described, for example, in documents such as French Patent Application Publication No. 2860341, French Patent Application Publication No. 2933233, French Patent Application Publication No. 2953640, US Patent Application Publication No. 2015115480, US Patent No. 7268060, US Patent No. 6544656, US Patent Application Publication No. 20200020520 or WO 2020 / 008116.

[0003] To construct an SOI substrate featuring such a trapping layer, a carrier substrate is created by forming a charge trapping layer on a base substrate. A thin layer is then transferred to the carrier substrate using a layer transfer process (e.g., Smart Cut® technology). According to this technique, a donor substrate featuring a weakened plane defining the thin layer to be transferred at its exposed surface is bonded to the carrier substrate, usually by molecular bonding. The donor substrate is then split at the weakened plane, thereby transferring the thin layer to the carrier substrate. A dielectric layer is inserted between the carrier substrate and the thin layer, for example, by oxidizing one or both of the substrates prior to bonding.

[0004] According to the Smart-Cut® technology, a weakened plane is obtained by introducing light species (e.g., hydrogen and / or helium) into the donor substrate, typically by implantation through a dielectric layer (if present). The energy and dose of the implanted species are determined by the thickness of the thin layer to be transferred; the greater the thickness, the higher the energy and dose. High-energy, high-dose implantations are industrially undesirable. Therefore, to avoid this problem, it is preferable to form at least a part of this dielectric layer on a carrier substrate rather than on the donor substrate, especially if the dielectric layer is selected to be relatively thick (e.g., greater than 200 nm). In the field of photonics, this thickness can reach one or even several microns, exacerbating all the problems associated with the presence of a dielectric layer of considerable thickness.

[0005] Thus, the applicant's experiments have revealed that forming a dielectric layer by oxidizing a charge trapping layer composed of polycrystalline silicon poses a number of problems. This oxidation tends to roughen the surface of the carrier substrate, requiring preparation, for example by polishing, prior to the bonding step, thus complicating the process. Furthermore, the buried interface between the silicon oxide and the remaining polysilicon layer is also rough, which can present problems when optically inspecting the SOI substrate during device fabrication. It should be noted that this interface cannot be polished and is necessarily maintained inside the substrate, which can adversely affect the operation of devices, particularly photonic devices, formed in or on such a carrier substrate. Furthermore, the oxidation step tends to deform the carrier substrate, resulting in significant warpage. This warpage complicates subsequent bonding steps and, more generally, handling the carrier substrate in a manufacturing line using conventional equipment.

[0006] It should be noted that similar problems arise when forming the dielectric layer by deposition on the carrier, instead of by oxidation of the carrier substrate: in particular, conventional techniques such as PECVD (Plasma Enhanced Chemical Vapor Deposition) or LPCVD (Low Pressure Chemical Vapor Deposition) result in significant warping and generally produce very rough layers that require preparation by polishing before bonding can be considered.

[0007] References such as Pye et al., "High density plasma CVD and CMP for 0.25 M intermetal dielectric processing," Solid State Technology, Penwell Corporation, vol. 38, no. 12, 1995, and Machida et al., "New planarization technology using bias ECR plasma deposition," Japanese Journal of Applied Physics, pp. 329-332 (1985), teach techniques for depositing intermetal dielectric films that are located roughly between two metal levels in functional semiconductor structures. These films are intended to fill topological patterns exhibiting significant aspect ratios, and their deposition is followed by a polishing step. Summary of the Invention

[0008] (Problem of the Invention) The present invention aims to overcome all or some of the above-mentioned drawbacks.

[0009] (Brief Description of the Invention) To achieve one of the above objects, the subject of the present invention is a process for transferring a thin layer onto a carrier substrate, comprising: preparing a carrier substrate using a preparation process including: providing a base substrate having a charge trapping layer on a major surface thereof; and forming a dielectric layer having a thickness of greater than 200 nm on the charge trapping layer, wherein the formation of the dielectric layer comprises simultaneous deposition of the dielectric layer and ion sputtering; bonding a donor substrate characterized by a weakened plane defining a thin layer to a dielectric layer of a carrier substrate by molecular bonding without creating a free surface of the dielectric layer by polishing; - splitting the donor substrate at the weakened plane to release and transfer the thin layer to a carrier substrate; The present invention relates to a process including:

[0010] According to other advantageous and non-limiting features of the present invention, the following are provided, taken alone or in any technically feasible combination:

[0011] The fabrication process includes forming a warp compensation layer on the back surface of the base substrate opposite the main surface.

[0012] The warpage compensation layer has a thickness of 500 nm to 1000 nm.

[0013] The base substrate is a single crystal silicon substrate exhibiting a resistivity lower than 1000 Ω·cm.

[0014] The base substrate is a single crystal silicon substrate exhibiting a resistivity higher than 600 Ω·cm.

[0015] The charge trapping layer includes polycrystalline silicon.

[0016] The charge trapping layer includes carbon.

[0017] The charge trapping layer has a thickness of 1 micron to 20 microns.

[0018] The dielectric layer is made of silicon oxide.

[0019] The dielectric layer comprises a barrier layer composed of silicon nitride or silicon oxynitride.

[0020] The dielectric layer has a thickness of 200 nm to 10 microns, preferably 600 nm to 10 microns.

[0021] The deposition / sputtering ratio is 1-10, preferably 2-5.

[0022] The dielectric layer is formed at a temperature of 300°C to 450°C, preferably 350°C to 400°C.

[0023] The dielectric layer is formed in an atmosphere exhibiting a pressure below atmospheric pressure.

[0024] The process further comprises annealing the dielectric layer in a neutral atmosphere at a temperature above the formation temperature of the dielectric layer, preferably below 950°C.

[0025] The free surface of the dielectric layer exhibits a roughness of less than 0.5 nm in terms of RMS (root mean square) value over a measurement area of ​​10 microns by 10 microns.

[0026] The donor substrate does not have a dielectric surface layer.

[0027] Other features and advantages of the present invention will become apparent from the following detailed description of the invention, which proceeds with reference to the accompanying drawings. [Brief explanation of the drawings]

[0028] [Figure 1] 1 illustrates a carrier substrate for a layer transfer process according to the present invention; [Figure 2] 1 illustrates the final substrate obtained upon completion of the layer transfer process according to the present invention. [Figure 3] FIG. 1 illustrates one embodiment of a carrier substrate. [Figure 4] FIG. 1 illustrates the final substrate obtained upon completion of the layer transfer process of one embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0029] (Detailed Description of the Invention) Presentation of the final board 2 , the final substrate S of one embodiment comprises a base substrate 3, a charge trapping layer 2 disposed on the base substrate 3, a dielectric layer 4 disposed in direct contact with the charge trapping layer 2, and a thin layer 5 disposed on the dielectric layer 4. The base substrate 3 provided with the charge trapping layer and the dielectric layer 4 constitutes the carrier substrate 1 of the final substrate S.

[0030] 4, the carrier substrate 1 of the final substrate S comprises a base substrate 3 provided with a charge trapping layer 2 and a warpage compensation layer 32. The function of this layer is to deform the base substrate 3 in order to at least partially compensate for future deformations that the base substrate 3 and the final substrate S will undergo in particular during the various steps of the process that constitutes the subject of this description. This means in particular compensating for the stresses exerted by the dielectric layer 4 when it is formed on the base substrate 3, and to a lesser extent by the charge trapping layer 2.

[0031] The charge trapping layer 2 is disposed on a major surface 31 of the base substrate 3, and the compensation layer 32 is disposed on a back surface 33 of the base substrate 3 opposite the major surface 31. The compensation layer 32 is preferably made of silicon oxide or silicon nitride. Its thickness is preferably greater than 200 nm, more preferably 500 to 1000 nm.

[0032] The final substrate S (and thus the carrier substrate 1) in the embodiments of Figures 2 and 4 may be in the form of a circular wafer of standard size (e.g. 200 mm, 300 mm or 450 mm diameter), especially if the final substrate S, and in particular the thin layer 5, still does not carry any devices, although the invention is in no way limited to these dimensions or to this form.

[0033] The base substrate 3 has a thickness of several hundred microns. The base substrate 3 preferably exhibits a resistivity higher than 100 or 1000 Ω·cm, and even more preferably higher than 3000 Ω·cm. In this way, the density of charges, i.e., holes or electrons, that tend to migrate in the base substrate 3 and thereby degrade the RF performance of the final substrate S is limited. However, the present invention is not limited to the base substrate 3 exhibiting such a resistivity. It is also advantageous in terms of RF performance if the base substrate 3 exhibits a resistivity lower than 1000 Ω·cm, on the order of several hundred Ω·cm, or more typically 100 Ω·cm or less.

[0034] For reasons of availability and cost, the base substrate 3 is preferably made of silicon, in particular monocrystalline silicon. It may, for example, be a CZ substrate containing a small amount of interstitial oxygen, which, as is well known per se, may have a resistivity higher than 1000 Ω·cm. Alternatively, the base substrate 3 may be made of another material, for example sapphire, silicon carbide, silicon germanium, III-V materials, glass, etc. Alternatively, it may be a more standard CZ monocrystalline substrate with a resistivity lower than 1000 Ω·cm, or a CZ substrate containing a large or medium amount of interstitial oxygen, which may result in a resistivity higher than 1000 Ω·cm. - Dope or p - It may be doped and have a resistivity on the order of 500 Ω·cm or less.

[0035] The carrier substrate 1 of the various embodiments of the present invention may optionally be provided with a thin dielectric layer, arranged in direct contact with the base substrate 3 and made of, for example, silicon dioxide or silicon nitride. The thin dielectric layer (not shown in FIGS. 1 and 2) has a thickness of more than a few nanometers (for example, 5 nm to 500 nm). This layer can be obtained by oxidation of the base substrate 3 or by deposition on this substrate. In order to limit the time and costs required for the formation of this thin layer, its thickness can be chosen to be between 5 nm and 200 nm (for example, 145 nm, etc.). The thin dielectric layer can prevent or limit recrystallization of the charge trapping layer 3 when the carrier substrate 1 or the final substrate S is exposed to high temperatures.

[0036] The carrier substrate 1 also comprises a charge trapping layer 2 arranged in direct contact with the base substrate 3 (or the thin dielectric layer, if present). The trapping layer 2 has a resistivity higher than 500 Ω·cm, preferably higher than 1000 Ω·cm, more preferably higher than 10 kΩ·cm. As mentioned above in the introduction to this application, the function of the trapping layer is to capture any charge carriers present in the carrier 1 and limit their respective movement. This is especially the case when the final substrate S comprises a semiconductor structure which, penetrating the carrier substrate 1, emits an electromagnetic field which interacts with these charges and tends to move them. The charge trapping layer 2 typically has a thickness of 1 micron to 15 microns, or even 20 microns.

[0037] The trapping layer 2 may generally be formed of a non-single-crystalline semiconductor layer having structural defects such as dislocations, grain boundaries, amorphous regions, gaps, inclusions, pores, etc. These structural defects, for example at the sites of imperfect chemical bonds or dangling bonds, act as traps for any charges flowing through the material, thereby inhibiting conduction in the trapping layer and resulting in high resistivity.

[0038] For the same reasons of availability and cost as mentioned above, the trapping layer 2 is preferably made of polycrystalline silicon. However, it may also be made of or include other polycrystalline semiconductor materials. Naturally, the charge trapping layer 2 may be formed by techniques other than those requiring a layer made of polycrystalline silicon. This layer may also contain carbon, for example, in the form of an intermediate layer inserted into the thickness of the polycrystalline silicon, or may be made of silicon carbide or an alloy of silicon and carbon, or may include silicon carbide or an alloy of silicon and carbon. When the trapping layer 2 is made of silicon carbide or an alloy of silicon and carbon, its thickness is preferably several nanometers (e.g., 2 nm) to several tens of nanometers (e.g., 50 nm). Alternatively, electric traps may be formed in the layer 2 by ion bombardment of the surface of the base substrate 3 with a relatively heavy species (e.g., argon) to generate crystalline defects capable of trapping charges. It is also conceivable to form the charge trapping layer 2 from a porous material, for example, by making the surface of the base substrate 3 porous when the base substrate 3 is made of silicon.

[0039] In any case, the trapping layer 2 exhibits a high resistivity higher than 500 Ω·cm. For this reason, the trapping layer 2 is not intentionally doped. 14 It has a charge carrier dopant concentration of less than atoms per cubic centimeter and may be nitrogen- or carbon-rich to improve resistivity characteristics.

[0040] Returning to the general description of FIGS. 1 and 4, the carrier substrate 1 also comprises a dielectric layer 4 disposed directly on the trapping layer 2. By way of example, the dielectric layer 4 may consist of or contain silicon dioxide or silicon nitride, or may be a laminate of these materials. The thickness of the dielectric layer 4 may be between 10 nm and 10 microns, although in the context of this specification, this layer preferably has a relatively large thickness (e.g., greater than 200 nm), preferably between 200 nm and 10 microns or between 200 nm and 1 micron. This is particularly the case when the final substrate is intended for applications in the field of photonics, in which case a thick dielectric layer 4 is required, the thickness of which is typically greater than 600 nm and may even reach 10 microns.

[0041] The final substrate S comprises a thin layer 5 in contact with the dielectric layer 4 of the carrier substrate 1. The thin layer is typically made of monocrystalline silicon, but may also comprise any other material (semiconductor or not), depending on the nature of the device intended to be formed in or on it. If the final substrate S is intended to receive semiconductor integrated components, the thin layer 5 may be made of monocrystalline silicon or of any other semiconductor material, such as germanium, silicon germanium or silicon carbide.

[0042] The semiconductor integrated components may in particular be of a photonic nature and may be passive or active components, for example waveguides, ring resonators or Mach-Zehnder interferometers, etc. Devices of this kind, in particular optical phase shifters and switches, must be able to efficiently transmit large amounts of signals whilst respecting specifications in terms of miniaturization, low power consumption, suppression of electromagnetic coupling effects and switching speed, and can advantageously be provided by high performance substrates such as the final substrate S.

[0043] The photonic device 51 (shown by way of example in FIG. 4) advantageously constitutes a switch, a waveguide, a phase shifter, a modulator, a laser oscillator, an amplifier, a directional coupler, a filter, and / or a multiplexer.

[0044] If the final substrate S is intended to receive a surface acoustic wave filter, the thin layer 5 may consist of a piezoelectric and / or ferroelectric material, such as lithium tantalate or lithium niobate. The thin layer 5 may also comprise finished or semi-finished integrated components formed on a donor substrate and transferred to the carrier substrate 1 during the manufacture of the final substrate S. Typically, the thin layer 5 may have a thickness of 10 nm to 10 microns.

[0045] Creating the carrier substrate The process for producing the carrier substrate 1 shown in FIG. 1 is presented below. In a first step, a base substrate 3 is provided, which exhibits a charge trapping layer 2 on its main surface. If this trapping layer 2 is made of polycrystalline silicon, it may be manufactured using industry-standard deposition equipment. This may include RPCVD (remote plasma-enhanced chemical vapor deposition) or PECVD (plasma-enhanced chemical vapor deposition). It may also include LPCVD (low-pressure chemical vapor deposition). However, as mentioned above, the formation of the trapping layer on or in the base substrate 3 may also be achieved by many other methods, such as implanting heavy species or porosifying the surface layer of the base substrate 3.

[0046] Optionally, the base substrate 3 may be provided with a thin dielectric layer prior to the formation of the charge trapping layer 2, for example by oxidation or deposition of a thickness of oxide.

[0047] For embodiments providing a warpage compensation layer, this first step includes a first subsequent sub-step of forming a compensation layer on all exposed surfaces of the base substrate prior to the formation of the trapping layer (FIGS. 3A and 3B). For the same reasons of availability and cost discussed above, the compensation layer 32 may be comprised of silicon oxide formed by thermal oxidation of the silicon base substrate 3, for example, at temperatures between 800 and 1100°C.

[0048] 3C, the compensation layer 32 is at least partially removed from the front surface 31 prior to the formation of the trapping layer 2 and the dielectric layer 4. This substep may in particular be carried out by polishing the front surface 31. It is also conceivable to retain part of the compensation layer 32 on the front surface 31 of the base substrate in order to constitute a thin dielectric layer on which the charge trapping layer is formed.

[0049] The presence of this layer on each of the major surface 31 and rear surface 33 of the base substrate 3 balances the stress present in the compensation layer 32. The substep of removing the layer 32 from the major surface 31 while retaining the compensation layer 32 at least on the rear surface 33 will result in an imbalance of this balance and a bowing of the base substrate 3. Thus, when the compensation layer 32 is under compressive strain, the base substrate 3 will exhibit a negative curvature that gives it a slightly concave shape.

[0050] Thus, as an example, if the base substrate 3 is made of silicon and has a conventional thickness on the order of 650 microns, then a compensation layer 32 made of thermal silicon oxide and having a thickness of approximately 600 nm on the back surface 33 alone will result in a concave curvature on the order of −110 μm, which can compensate for at least part of the deformation caused by the trapping layer and the dielectric layer.

[0051] The thickness of the compensation layer 32 is therefore determined according to the target thicknesses of the charge trapping layer 2 and the dielectric layer 4 so that the carrier substrate exhibits a predetermined tolerable curvature after the formation of these layers. This tolerable curvature may be up to 100 microns (preferably up to 60 microns or 40 microns) for a substrate with a diameter of 300 mm, which allows handling and processing of the carrier substrate using conventional equipment. The thickness of the compensation layer 32 is typically between 500 nm and 1000 nm.

[0052] FIG. 3D shows the carrier substrate of this embodiment at the completion of this first step, ie after the formation of the charge trapping layer 2.

[0053] In the second step of the process of making the carrier substrate 1, whether or not the base substrate is provided with a compensation layer, a dielectric layer 4 is formed on the charge trapping layer 2. According to an important aspect of this process, the formation of the dielectric layer 4 is performed by simultaneous deposition and ion sputtering of this dielectric layer 4.

[0054] The technique for forming such a dielectric layer may be performed by placing the base substrate 3 provided with the trapping layer 2 and possibly the compensation layer 32 in the chamber of an HDP CVD (High Density Plasma Chemical Vapour Deposition) apparatus.

[0055] Such a chamber can be excited by an RF source (e.g., with a frequency of approximately 13 MHz) located above the chamber, generating a 10 10 ~10 12 pieces / cm 3A plasma source is provided to form a plasma from which electrons and ions present at very high densities (on the order of 1000 to 10,000 mTorr) can be extracted. A substrate introduced into the chamber is placed on a carrier comprising a second electrode connected to a second RF source (e.g., with a frequency of approximately 2 MHz), often referred to in the art as a "bias source." Ions and electrons are projected onto the exposed surface of the substrate, resulting in a mild etching (sputtering) of the surface. The first and second RF sources are typically operated with a power of 1,000 to 10,000 watts (for an apparatus intended to receive substrates in the form of 300 mm diameter circular wafers). Precursor gases are introduced into the chamber, and their interaction on the exposed surface of the substrate gradually forms a dielectric layer thereon. The chamber is maintained at a very low pressure, on the order of 1 mTorr or tens of mTorr, using a vacuum pump that circulates and extracts the injected gas and residual reactant species from the chamber. The chamber is also maintained at a relatively low temperature, typically between 200°C and 450°C. Thus, to form a silicon oxide layer, a silicon-containing gas, an oxygen-containing gas, and an inert gas (e.g., argon or helium) are introduced into the chamber. By controlling the chamber parameters, particularly the inlet gas flow and RF source power, the simultaneous deposition and sputtering effects occurring in the chamber during the formation of the dielectric layer can be controlled, with a deposition / sputtering ratio of 1 to 10, preferably 2 to 5. This combined effect compensates for any topology that may be present on the substrate surface and tends to result in the formation of a particularly uniform and smooth layer. In this regard, it is recalled that to obtain a surface that can be bonded by molecular bonding, this surface must exhibit a roughness of less than 0.5 nm RMS (root mean square) over a 10 micron × 10 micron measurement area. It is particularly surprising that such a formation process can meet this low roughness requirement, especially for relatively thick dielectric layers exceeding 200 nm. It is recalled in particular that in the normal use of HDP CVD equipment, the formed layers are intended to fill topological patterns exhibiting a significant aspect ratio, and their deposition is necessarily followed by a polishing step.Therefore, it was not believed that forming a dielectric layer on a charge trapping layer would result in a layer exhibiting a surface roughness as low as 0.5 nm RMS over a 10 micron x 10 micron measurement area.

[0056] Returning therefore to the process for preparing the carrier substrate 1, this process involves the formation of a dielectric layer 4 by implementing such simultaneous deposition and ion sputtering techniques. In a preferred embodiment, the dielectric layer 4 is made of silicon oxide. In this case, for a carrier substrate 1 having a size of 300 mm, the gas introduced into the chamber may comprise silane (SiH4), oxygen, and argon (or another inert gas, such as helium), with a mass flow rate of 20-80 sccm (standard cubic centimeters per minute). The power of the RF source may be selected to be 1000 W-5000 W. The dielectric layer 4 is formed at a temperature of 300°C-450°C, preferably 350°C-400°C, and the chamber pressure is maintained below atmospheric pressure, preferably below 5 mTorr. These parameters may be controlled to define a deposition / sputtering ratio, preferably between 2 and 5.

[0057] Of course, by modifying the nature of the gas introduced into the chamber (in this example, N, NH, or NO instead of oxygen) and adjusting other parameters of the process, one can choose to form a dielectric layer 4 other than a silicon oxide layer (e.g., a silicon nitride layer or a silicon oxynitride layer).

[0058] In particular, the gas flow into the chamber can be controlled to form a dielectric layer 4 comprising at least one alternating layer formed of a first elementary layer of silicon oxide and a second elementary layer of silicon oxynitride or silicon nitride. Thus, in a particular embodiment, a layer of silicon oxynitride or silicon nitride can be embedded within the thickness of a dielectric layer formed primarily of silicon oxide. In this way, a barrier layer is formed within the dielectric layer 4, which can limit the diffusion of certain species, such as hydrogen, through the depth of the dielectric layer, particularly during subsequent steps in the fabrication of the final substrate. Advantageously, the silicon oxynitride or silicon nitride barrier is located near the free surface of the dielectric layer (e.g., 10 nm to 50 nm below the surface layer of silicon oxide).

[0059] In any event, regardless of the exact nature of the dielectric layer 4, the deposition chamber will continue to operate long enough to form a selected thickness of the dielectric layer 4. In the context of this specification, this thickness will be relatively large (e.g., greater than 200 nm), advantageously between 200 nm and 1 micron or 10 microns. As a further example, forming a 400 nm thick dielectric layer 4 may be problematic.

[0060] Tests carried out by the applicant have shown that forming such a 400 nm silicon oxide layer on a trapping layer 2 of polycrystalline silicon in the form of a circular wafer with a diameter of 300 mm makes it possible to create a carrier substrate 1 having properties that are particularly suitable for forming the final substrate S.

[0061] Thus, it was particularly surprising that, as mentioned above, the exposed surface of the carrier substrate 1, i.e., the free surface of the dielectric layer 4 made of silicon oxide, exhibited a surface roughness of less than 2 Å RMS (root mean square) over a 10 micron × 10 micron measurement area and a 30 micron × 30 micron measurement area. This roughness is similar to the roughness obtained by oxidizing a trapping layer made of polycrystalline silicon after polishing to reduce the roughness. This low roughness is sufficiently suitable for the step of bonding by molecular bonding. Thus, the proposed process for forming the dielectric layer 4 is highly advantageous in that it can omit the polishing step, thereby simplifying the process of making the carrier substrate 1.

[0062] Also, the interface between the silicon oxide dielectric layer 4 and the polysilicon trapping layer exhibited a roughness of less than 2 Angstroms RMS (over the same 10 micron x 10 micron and 30 micron x 30 micron measurement areas), while the same 400 nm thick silicon oxide dielectric layer formed by oxidation of the polysilicon trapping layer exhibited a roughness on the order of 50 Angstroms RMS.

[0063] The process for forming the dielectric layer 4 is carried out at a relatively low temperature of around 380° C., below 400° C., to form a silicon oxide dielectric layer, thus avoiding recrystallization of the charge trapping layer 2 and loss of electrical traps, which may occur if this layer is subjected to high temperatures by solid phase repita- tion .

[0064] Furthermore, the formation of the dielectric layer 4 according to the proposed technology results in significantly less deformation of the carrier substrate 1 (of the order of 100 microns for a 300 mm carrier substrate 1 provided with a 400 nm silicon oxide layer) compared to deformation due to oxidation of a trapping layer of polycrystalline silicon (of the order of 150 microns). Again, this property makes the carrier substrate 1 obtained by the process according to the invention much more compatible with the bonding step by molecular bonding. This property is further improved if the carrier substrate is provided with a compensation layer, the thickness of which can be chosen to closely compensate for the deformations caused by the dielectric layer 4 and, to a lesser extent, by the charge trapping layer. This embodiment is particularly useful when the dielectric layer exhibits a considerable thickness (more than 600 nm).

[0065] It should also be noted that the process for producing the carrier substrate 1 may include a step of annealing the dielectric layer 4. This annealing, called degassing or densification annealing, is advantageously carried out in a neutral atmosphere. It is carried out at a temperature higher than the deposition temperature of the dielectric layer 4, preferably below 950°C, for a relatively short time of less than one hour (e.g., 30 minutes). The time and temperature of this annealing will be chosen to avoid or at least limit recrystallization of the trapping layer 2. This annealing step may affect the curvature of the carrier substrate, and will therefore be taken into account in determining the thickness of the compensation layer.

[0066] Final board manufacturing Upon completion of the fabrication process presented above, a carrier substrate 1 is obtained, which comprises at least one trapping layer 2 and one dielectric layer 4 successively arranged on a base substrate 3. The carrier substrate may also comprise a compensation layer 32, which allows the curvature of this substrate to be kept below 100 microns (e.g., 100-60 microns), even in the presence of a thick dielectric layer, e.g., 600 nm.

[0067] As mentioned above, the carrier substrate 1 is intended to receive, by transfer, a thin layer 5 to constitute the final substrate S. The carrier substrate 1 exhibits properties (in particular with regard to surface roughness and deformation) that are suitable for receiving such a thin layer 5.

[0068] As is well known per se, this transfer is typically achieved by bonding the free surface of the donor substrate to the carrier substrate 1, preferably by molecular bonding. Since the dielectric layer 4 is already formed on the carrier substrate 1, the donor substrate itself does not need to be provided with such a dielectric layer. Nevertheless, the donor substrate may be provided with a thin dielectric layer (for example, thinner than 150 nm). However, in any case, this thickness will always be much smaller than the thickness of the dielectric layer 4 of the final substrate S, since part of this thickness will be contributed by the dielectric layer 4 formed on the carrier substrate 1. Therefore, the donor substrate preferably does not have a purposefully formed dielectric surface layer. As described in the previous sections of this specification, the properties of the donor substrate are selected according to the desired properties of the thin layer 5. The donor substrate may therefore be a substrate made of a monocrystalline semiconductor (for example, silicon) or a substrate made of a piezoelectric material or provided with a surface layer of such a piezoelectric material.

[0069] After this bonding step, the thickness of the donor substrate is reduced to form the thin layer 5. This reduction step may be carried out by mechanical or chemical thinning. However, in the context of this specification, in order to make the most of the advantageous properties of the carrier substrate 1, the thickness of the donor substrate is reduced by splitting at a previously introduced weakened plane, for example according to the principles of the SmartCut™ technology, as explained in the introduction to this application. This weakened plane, together with the free surface of the donor substrate, defines the thin layer 5.

[0070] It should be noted that since the donor substrate preferably does not have a surface dielectric layer (or has a layer with a relatively small thickness), the dose and energy of the species implanted to form the weakened plane can be kept to reasonable values ​​even if the final substrate S exhibits a thick dielectric layer 4 of 200 nm or more.

[0071] The transfer of the thin layer does not alter the stress balance, so that at this stage the final substrate exhibits a curvature very similar to that of the carrier substrate.

[0072] After this thinning step, preferably the splitting step, finishing steps for the thin layer 5, such as polishing steps, heat treatment in a reducing or inert atmosphere, and sacrificial oxidation, may be carried out after the thickness reduction step.

[0073] If the donor substrate is simply a substrate, i.e. does not contain integrated devices, an "on-insulator" final substrate S is thus formed, with the thin layer 5 being the raw material layer constituting the carrier substrate 1 according to the invention. This final substrate S may then be adapted to be used for the construction of integrated or photonic devices, as shown in Figure 4. If the donor substrate has been previously processed to form integrated devices on its surface, at the end of this process a thin layer 5 is obtained with these devices.

[0074] Naturally, the invention is not limited to the described embodiments and modifications are possible without departing from the scope of the invention as defined by the claims.

Claims

1. A process for transferring a thin layer (5) onto a carrier substrate (1), comprising: a step of preparing a carrier substrate (1) using a preparation process including: providing a base substrate (3) having a charge trapping layer (2) on a main surface thereof; and forming a dielectric layer (4) having a thickness of more than 200 nm on the charge trapping layer (2), wherein the formation of the dielectric layer (4) is performed by simultaneously depositing the dielectric layer and ion sputtering; bonding a donor substrate characterized by a weakened plane defining said thin layer (5) to said dielectric layer (4) of said carrier substrate (1) by molecular bonding, without creating a free surface of said dielectric layer (4) by polishing; - splitting the donor substrate at the weakened plane, thereby releasing and transferring the thin layer (5) to the carrier substrate (1); The process includes:

2. The process of claim 1 , wherein the fabrication process includes forming a warp compensation layer (32) on a back surface of the base substrate (3) opposite the main surface.

3. The process of claim 2, wherein the warp compensation layer (32) has a thickness of between 500 nm and 1000 nm.

4. The process according to any one of claims 1 to 3, wherein the base substrate (3) is a monocrystalline silicon substrate exhibiting a resistivity higher than 600 Ω·cm.

5. The process of any one of claims 1 to 4, wherein the charge trapping layer (2) comprises polycrystalline silicon.

6. The process of any one of claims 1 to 5, wherein the charge trapping layer (2) comprises carbon.

7. The process of any one of claims 1 to 6, wherein the charge trapping layer (2) has a thickness of between 1 micron and 20 microns.

8. The process according to any one of claims 1 to 7, wherein the dielectric layer (4) consists of silicon oxide.

9. The process according to any one of claims 1 to 8, wherein the dielectric layer (4) comprises a barrier layer made of silicon nitride or silicon oxynitride.

10. The process according to any one of the preceding claims, wherein the dielectric layer (4) has a thickness of between 200 nm and 10 microns, preferably between 600 nm and 10 microns.

11. The process according to any one of claims 1 to 10, further comprising annealing said dielectric layer (4) in a neutral atmosphere at a temperature above the formation temperature of said dielectric layer, preferably below 950°C.

12. A process according to any one of the preceding claims, wherein the free surface of the dielectric layer (4) exhibits a roughness of less than 0.5 nm in terms of RMS value over a measurement area of ​​10 microns by 10 microns.

13. The process of any one of claims 1 to 12, wherein the donor substrate does not have a dielectric surface layer.

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