Semiconductor Devices

Abstract

To obtain a semiconductor device that can prevent cracks from forming on semiconductor chips.SOLUTION: A first semiconductor chip 2 is bonded to a substrate 1 by a bonding material 3. A second semiconductor chip 4 is bonded to the junction on the top surface of the first semiconductor chip 2 and has an external shape with a recess 6 formed in the same external shape as the first semiconductor chip 2 in plan view. A pad 7 is formed on an exposed portion of the top surface of the first semiconductor chip 2 exposed in the recess 6. A wire 8 is bonded to the pad 7.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] A semiconductor device has been disclosed in which a second semiconductor chip is soldered to the top surface of a first semiconductor chip such as an infrared emitting element as a cap made of an infrared-transparent material (see, for example, Patent Document 1). The second semiconductor chip has a rectangular shape that is smaller than the first semiconductor chip, and a step is formed between the two chips. The top surface of the first semiconductor chip has a bonding portion to which the second semiconductor chip is bonded and an exposed portion where the second semiconductor chip is not bonded. Wire bonding pads are formed on the exposed portion. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Special Publication No. 9-506712 Summary of the Invention [Problem to be solved by the invention]

[0004] The first semiconductor chip is bonded to the substrate with a bonding material. Temperature changes during bonding or during use of the semiconductor device cause the substrate to warp due to differences in thermal expansion between the substrate and the first semiconductor chip, resulting in bending stress being applied to the first semiconductor chip. In conventional technology, the boundary between the exposed portion and the bonding portion extends in a straight line from one end of the chip to the other in a plan view, which causes stress to concentrate at this boundary, making the first semiconductor chip prone to cracking.

[0005] The present disclosure has been made to solve the above-mentioned problems, and its object is to obtain a semiconductor device that can prevent cracks from occurring in a semiconductor chip. [Means for solving the problem]

[0006] The semiconductor device according to the present disclosure includes: A semiconductor device comprising: a substrate; a first semiconductor chip bonded to the substrate with a bonding material; a second semiconductor chip bonded to a bonding portion on the upper surface of the first semiconductor chip and having an outer shape smaller than that of the first semiconductor chip; pads formed on an exposed portion on the upper surface of the first semiconductor chip exposed from the second semiconductor chip; and wires bonded to the pads; wherein the lower surface of the first semiconductor chip is recessed directly below the boundary between the bonding portion and the exposed portion, and a portion of the first semiconductor chip that is not bonded to the substrate with the bonding material is recessed. It is characterized by: [Effects of the Invention]

[0007] In the present disclosure, the second semiconductor chip has an outer shape that is the same as the first semiconductor chip in a plan view, but with a recess formed therein. Therefore, the boundary between the exposed portion and the bonded portion on the top surface of the first semiconductor chip is not a straight line but is bent along the recess. Therefore, even if bending stress is applied to the first semiconductor chip, stress does not concentrate at the boundary between the exposed portion and the bonded portion, preventing cracks from occurring in the first semiconductor chip. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a plan view showing a semiconductor device according to a first embodiment. [Figure 2] FIG. 2 is a cross-sectional view taken along line I-II in FIG. [Figure 3] FIG. 2 is a cross-sectional view taken along the line III-IV in FIG. [Figure 4] FIG. 10 is a plan view showing a semiconductor device according to a comparative example. [Figure 5] FIG. 5 is a cross-sectional view taken along line I-II in FIG. [Figure 6] FIG. 10 is a plan view showing a modified example of the semiconductor device according to the first embodiment. [Figure 7] FIG. 7 is a cross-sectional view taken along line I-II in FIG. 6. [Figure 8] FIG. 10 is a plan view showing a semiconductor device according to a second embodiment. [Figure 9] FIG. 9 is a cross-sectional view taken along line I-II in FIG. 8. [Figure 10] FIG. 10 is a plan view showing a semiconductor device according to a third embodiment. [Figure 11] FIG. 11 is a cross-sectional view taken along line I-II in FIG. [Figure 12] FIG. 10 is a plan view showing a semiconductor device according to a fourth embodiment. [Figure 13] FIG. 13 is a cross-sectional view taken along line I-II in FIG. DETAILED DESCRIPTION OF THE INVENTION

[0009] A semiconductor device according to an embodiment will be described with reference to the drawings. The same or corresponding components are denoted by the same reference numerals, and repeated description may be omitted.

[0010] Embodiment 1 FIG. 1 is a plan view showing a semiconductor device according to a first embodiment. FIG. 2 is a cross-sectional view taken along line I-II in FIG. 1. FIG. 3 is a cross-sectional view taken along line III-IV in FIG. 1. A first semiconductor chip 2 is bonded to a substrate 1, such as a glass epoxy substrate, with a bonding material 3. The bonding material 3 is an epoxy-based bonding material, an acrylic-based bonding material, a silicone-based bonding material, or the like. The first semiconductor chip 2 is an infrared emitting element made of, for example, silicon. A second semiconductor chip 4 is bonded to a bonding portion on the upper surface of the first semiconductor chip 2 with solder 5. The second semiconductor chip 4 is a cap made of an infrared-transparent material, such as silicon. A vacuum gap is secured between the first semiconductor chip 2 and the second semiconductor chip 4.

[0011] The outer shape of the first semiconductor chip 2 is rectangular in plan view. The second semiconductor chip 4 has a U-shaped outer shape with a recess 6 formed on one side of a rectangle whose vertical and horizontal lengths are the same as those of the first semiconductor chip 2 in plan view. Pads 7 are formed on the exposed portions of the top surface of the first semiconductor chip 2 exposed in the recess 6.

[0012] Gold wires 8 are bonded to pads 7 of the first semiconductor chip 2, electrically connecting the pads 7 to wiring 9 on the substrate 1. The gold wires 8 are made up of one or more wires. A sufficient gap is secured between the recesses 6 and the pads 7 so that the capillary does not come into contact with the second semiconductor chip 4 when wire-bonding the gold wires 8 to the pads 7.

[0013] Next, the effects of this embodiment will be explained in comparison with a comparative example. FIG. 4 is a plan view showing a semiconductor device according to the comparative example. FIG. 5 is a cross-sectional view taken along line I-II in FIG. 4. The outer shape of the second semiconductor chip 4 is a rectangle smaller than that of the first semiconductor chip 2, and a step is formed between the two chips. Stress on the substrate 1 or a difference in thermal expansion between the substrate 1 and the first semiconductor chip 2 causes warping of the substrate 1, which in turn applies bending stress to the first semiconductor chip 2. In the comparative example, the boundary between the exposed portion and the bonding portion of the first semiconductor chip 2 extends in a straight line from one end of the chip to the other in a plan view, so stress concentrates at this boundary, making it easy for cracks 10 to form in the first semiconductor chip 2.

[0014] In contrast, in this embodiment, the second semiconductor chip 4 has an outer shape that is the same as the first semiconductor chip 2 in a plan view, but with a recess 6 formed therein. Therefore, the boundary between the exposed portion and the bonding portion on the top surface of the first semiconductor chip 2 is not a straight line in a plan view, but is bent along the recess 6. Therefore, even if a bending stress is applied to the first semiconductor chip 2, the stress does not concentrate at the boundary between the exposed portion and the bonding portion, and it is possible to prevent cracks from occurring in the first semiconductor chip 2.

[0015] Fig. 6 is a plan view showing a modified example of the semiconductor device according to the first embodiment. Fig. 7 is a cross-sectional view taken along line I-II in Fig. 6. After the gold wires 8 are bonded to the pads 7, an underfill 11 made of epoxy resin is applied to the exposed portions of the upper surface of the first semiconductor chip 2 exposed in the recesses 6 of the second semiconductor chip 4. This further reduces the bending stress applied to the first semiconductor chip 2, preventing cracks from occurring in the first semiconductor chip 2.

[0016] Embodiment 2 Figure 8 is a plan view showing a semiconductor device according to embodiment 2. Figure 9 is a cross-sectional view taken along line I-II in Figure 8. The outer shape of the second semiconductor chip 4 is a rectangle whose vertical length is the same as that of the first semiconductor chip 2 and whose horizontal length is shorter in plan view. The boundary between the exposed portion and the bonding portion of the first semiconductor chip 2 extends in a straight line from one end of the chip to the other in plan view.

[0017] A portion of the underside of the first semiconductor chip 2 is removed by etching to form a recess 12. The recess 12 extends from below the exposed portion of the first semiconductor chip 2, beyond the boundary, to below a portion of the bonding portion. Except for the recess 12, the underside of the first semiconductor chip 2 is bonded to the substrate 1 by the bonding material 3. The recess 12 is not bonded to the substrate 1 by the bonding material 3. The recess 12 is provided so that the bonding material 3 does not reach the bottom of the recess 12 even if it wets and spreads. The other configurations are the same as those of the first embodiment.

[0018] As described above, in this embodiment, the underside of first semiconductor chip 2 is recessed directly below the boundary between the bonding portion and the exposed portion of first semiconductor chip 2, and is not bonded to substrate 1 by bonding material 3, and is not restrained in a floating state. Therefore, even if bending stress is applied to first semiconductor chip 2, stress does not concentrate at the boundary between the exposed portion and the bonding portion, and it is possible to prevent cracks from occurring in first semiconductor chip 2.

[0019] Although the exposed portion of the first semiconductor chip 2 where wire bonding is performed is raised, the stress during wire bonding is small, so that the first semiconductor chip 2 does not crack.

[0020] Embodiment 3 FIG. 10 is a plan view showing a semiconductor device according to a third embodiment. FIG. 11 is a cross-sectional view taken along line I-II in FIG. 10. Unlike the second embodiment, the bottom surface of the first semiconductor chip 2 is flat. A groove 13 is formed in the top surface of the substrate 1 directly below the boundary between the bonding portion and the exposed portion of the first semiconductor chip 2. A bonding material 3 is applied onto the substrate 1 so as not to fill the groove 13. The other configurations are the same as those of the second embodiment.

[0021] Even if the bonding material 3 gets wet and spreads, it is stopped by the groove 13. Therefore, the first semiconductor chip 2 is not bonded to the substrate 1 by the bonding material 3 directly below the boundary, and is not restrained in a floating state. Therefore, even if bending stress is applied to the first semiconductor chip 2, the stress does not concentrate at the boundary between the exposed portion and the bonding portion, and it is possible to prevent cracks from occurring in the first semiconductor chip 2.

[0022] Embodiment 4 Figure 12 is a plan view showing a semiconductor device according to embodiment 4. Figure 13 is a cross-sectional view taken along line I-II in Figure 12. The outer shape of the second semiconductor chip 4 is a rectangle whose vertical length is the same as that of the first semiconductor chip 2 in plan view, but is shorter in length. The boundary between the exposed portion and the bonding portion of the first semiconductor chip 2 extends in a straight line from one end of the chip to the other in plan view.

[0023] The difference in thermal expansion between the substrate 1 and the first semiconductor chip 2 causes warping of the substrate 1, which places a bending stress on the first semiconductor chip 2. Stress concentrates on the boundary that extends in a straight line, making it easy for cracks to occur in the first semiconductor chip 2. Therefore, in this embodiment, an underfill 11 made of epoxy resin is applied to the entire exposed portion of the first semiconductor chip 2. The other configurations are the same as those of the first embodiment.

[0024] By applying underfill 11, bending stress applied to first semiconductor chip 2 due to stress on substrate 1 or thermal history can be alleviated, and cracks can be prevented from occurring in first semiconductor chip 2. [Explanation of symbols]

[0025] REFERENCE SIGNS LIST 1 substrate, 2 first semiconductor chip, 3 bonding material, 4 second semiconductor chip, 6 recess, 7 pad, 8 gold wire, 11 underfill, 13 groove

Claims

1. A substrate; a first semiconductor chip bonded onto the substrate by a bonding material; a second semiconductor chip bonded to a bonding portion on the top surface of the first semiconductor chip and having an outer shape smaller than that of the first semiconductor chip; a pad formed on an exposed portion of the top surface of the first semiconductor chip exposed from the second semiconductor chip; a wire bonded to the pad; a first semiconductor chip having a recessed lower surface directly below the boundary between the bonding portion and the exposed portion, the first semiconductor chip not being bonded to the substrate by the bonding material;

2. A substrate; a first semiconductor chip bonded onto the substrate by a bonding material; a second semiconductor chip bonded to a bonding portion on the top surface of the first semiconductor chip and having an outer shape smaller than that of the first semiconductor chip; a pad formed on an exposed portion of the top surface of the first semiconductor chip exposed from the second semiconductor chip; a wire bonded to the pad; A semiconductor device characterized in that a groove is formed on the top surface of the substrate directly below the boundary between the bonding portion and the exposed portion, and the first semiconductor chip is not bonded to the substrate by the bonding material.

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