Chip manufacturing method, system, and chip

Abstract

A chip manufacturing method, system, and chip, which relates to the technical field of micro-nano processing, includes the steps of: (201) manufacturing a first bottom circuit of an impedance Josephson parametric amplifier and a second bottom circuit used for testing by a laser direct writing exposure method to obtain a first chip product; (202) generating a photoresist structure used for manufacturing a Josephson junction on the first chip product by a laser direct writing exposure method; (203) cutting a second chip product having a second bottom circuit and a third chip product having a first bottom circuit from the first chip product; (204) fabricating a Josephson junction sample based on the photoresist structure corresponding to the second bottom circuit and obtaining an oxidation condition; (205) manufacturing a Josephson junction based on the photoresist structure corresponding to the first bottom circuit according to the oxidation condition to obtain a fourth chip product; and (206) obtaining a target chip product based on the fourth chip product.

Description

[Technical Field]

[0001] The present application relates to the technical field of micro-nano fabrication, and in particular to a chip manufacturing method, system, and chip.

[0002] This application claims priority to a Chinese patent application filed on October 21, 2022, bearing application number 202211295833.6 and entitled "Chip manufacturing method, system, and chip," the entire contents of which are incorporated herein by reference. [Background technology]

[0003] Impedance-matched Josephson parametric amplifiers are key components of superconducting quantum computing measurement circuits, which can fulfill the task of multi-bit measurements.

[0004] In the related art, impedance-matched Josephson parametric amplifiers have relatively high processing accuracy requirements for components, especially Josephson junctions, so they are usually manufactured using electron beam exposure processing.

[0005] However, the fabrication process of electron beam exposure requires fabricating an additional metal layer as an electron beam overlay mark, which introduces an additional exposure-coating-peeling process, making the fabrication process of the impedance-matched Josephson parametric amplifier relatively complicated and affecting the manufacturing efficiency. Summary of the Invention [Problem to be solved by the invention]

[0006] The embodiments of the present application provide a chip manufacturing method, a system, and a chip, which can improve the performance of chip products.

[0007] In one aspect, a method of manufacturing a chip is provided, the method comprising: Fabricating a first bottom layer circuit of an impedance Josephson parametric amplifier on a substrate by laser direct writing exposure, and fabricating a second bottom layer circuit of a Josephson junction used for testing on the substrate, to obtain a first chip product; generating a photoresist structure used to fabricate the Josephson junction on the first chip product by laser direct writing exposure; Dividing the first bottom layer circuit and the second bottom layer circuit of the first chip product to obtain a second chip product including the second bottom layer circuit after division, and a third chip product including the first bottom layer circuit after division; determining oxidation conditions used to fabricate an oxide layer in a Josephson junction by fabricating a Josephson junction sample on the second chip product based on the photoresist structure covering the second bottom layer circuit; According to the oxidation condition, fabricating the Josephson junction on the third chip product based on the photoresist structure covering the first bottom layer circuit, and fabricating the third chip product as a fourth chip product; and obtaining a target chip product including the impedance Josephson parametric amplifier based on the fourth chip product.

[0008] In another aspect, a chip manufacturing system is provided, the system including a coating machine, a photolithography machine, a deposition machine, an etching machine, an oxidation chamber, a cleaning machine, and a cutting machine; the coating machine, the photolithography machine, the deposition machine, the etching machine, and the cleaning machine are used to fabricate a first bottom layer circuit of an impedance Josephson parametric amplifier on a substrate, and fabricate a second bottom layer circuit of a Josephson junction used for testing on the substrate, thereby obtaining a first chip product; the coating machine and the photolithography machine are used to generate photoresist structures used to fabricate the Josephson junctions on the first chip product; the cutting machine is used to separate the first bottom layer circuit and the second bottom layer circuit of the first chip product, and obtain a second chip product including the second bottom layer circuit after separation, and a third chip product including the first bottom layer circuit after separation; the deposition machine and the oxidation chamber are used to fabricate a Josephson junction sample on the second chip product based on the photoresist structure covering the second bottom layer circuit, thereby determining oxidation conditions used to fabricate an oxide layer in the Josephson junction; The deposition machine and the oxidation chamber are further used to fabricate the Josephson junction on the third chip product according to the oxidation conditions based on the photoresist structure covering the first bottom layer circuit, and fabricate the third chip product as a fourth chip product; The coating machine, the photolithography machine, the deposition machine, the etching machine, and the cleaning machine are further used to obtain a target chip product including the impedance Josephson parametric amplifier based on the fourth chip product.

[0009] In one possible implementation, the first bottom layer circuit includes a capacitor portion of a nonlinear inductor-capacitor (LC) resonator of the Josephson parametric amplifier; The capacitor portion is a planar stub of a coplanar waveguide structure.

[0010] In one possible implementation, the coating machine, the photolithography machine, the deposition machine, the etching machine, and the cleaning machine are used to manufacture an air bridge at the root of the planar stub of the fourth chip product and manufacture the fourth chip product as the target chip product.

[0011] In one possible implementation, the step of fabricating an air bridge at the root of the planar stub of the fourth chip product to obtain the target chip product includes: the coating machine is used to apply a first photoresist layer on the fourth chip product; using the photolithography machine to expose and develop the first photoresist layer in a region corresponding to the base of the planar stub, thereby forming a pier region of the air bridge; performing a reflow process on the first photoresist layer to obtain an arched first photoresist layer; the deposition machine is used to deposit a bridge body material of an air bridge on the arch-shaped first photoresist layer; The coating machine is used to apply a second photoresist layer on the bridge body material; the photolithography machine is used to expose and develop the second photoresist layer in areas other than the air bridge body; the etching machine is used to remove bridge body materials other than the bridge body of the air bridge by etching; The cleaning machine is used to clean the photoresist of the fourth chip product to obtain the target chip product.

[0012] In one possible implementation, in the oxidizing condition, the resistance of the Josephson junction sample is less than the design resistance of the Josephson junction, and the resistance difference between the resistance of the Josephson junction sample and the design resistance of the Josephson junction matches the resistance increment of the air bridge to the Josephson junction.

[0013] In one possible implementation, the deposition machine is used to deposit a bottom layer circuit material on the substrate; the coating machine is used to apply a third photoresist layer on the bottom layer circuit material; The photolithography machine is used to expose and develop the third photoresist layer by a laser direct writing exposure method to form etching areas corresponding to the first bottom layer circuit and the second bottom layer circuit; the etching machine is used to perform an etching process on the third photoresist layer to remove the bottom-layer circuit material in the etching area; The cleaning machine is used to clean the photoresist on the substrate to obtain the first chip product.

[0014] In one possible embodiment, the photolithography machine is used to define the circuit patterns of the first bottom layer circuit and the second bottom layer circuit in a third photoresist layer by laser direct writing, and develop the etching areas corresponding to the first bottom layer circuit and the second bottom layer circuit by placing the substrate in a developer and developing it.

[0015] In one possible implementation, the first bottom layer circuit includes an impedance converter of the Josephson parametric amplifier; A compensation deviation exists between the line width in the layout of the impedance converter and the design line width of the impedance converter, and the compensation deviation is determined based on an etching deviation when etching the third photoresist layer.

[0016] In one possible implementation, a Josephson junction sample array is included on the second bottom layer circuit, the Josephson junction sample array including at least two Josephson junction sample port circuits, each of the port circuits corresponding to a set of the photoresist structures; the deposition machine and the oxidation chamber are configured to fabricate the Josephson junction sample corresponding to the first port circuit based on the photoresist structure covering the first port circuit under a first oxidation condition, the first port circuit being one port circuit of at least two Josephson junction sample port circuits in which the Josephson junction sample is not fabricated; determining the first oxidation conditions as oxidation conditions for manufacturing an oxide layer in a Josephson junction when a first resistance value satisfies a design requirement, and the first resistance value is obtained by measuring the Josephson junction sample corresponding to the first port circuit based on the first port circuit.

[0017] In one possible implementation, the oxidation chamber further comprises: In the situation where the first resistance value does not meet the design requirement, the second oxidation condition and the first port circuit are used to update and test.

[0018] In one possible implementation, the photoresist structure is a Dolan bridge structure; the deposition machine is used to obliquely deposit a first superconducting layer of the Josephson junction sample corresponding to the first port circuit based on the photoresist structure covering the first port circuit; the oxidation chamber is used to perform an oxidation treatment on the first superconducting layer according to the first oxidation conditions to obtain an oxide insulating layer on the surface of the first superconducting layer; The deposition machine is used to vertically deposit a second superconducting layer of the Josephson junction sample corresponding to the first port circuit based on the photoresist structure covering the first port circuit, thereby obtaining the Josephson junction sample corresponding to the first port circuit.

[0019] In one possible implementation, the first oxidation conditions are: The information includes at least one of the gas flow rate of oxygen gas, the atmospheric pressure, and the oxidation time.

[0020] In another aspect, a chip is provided, the chip comprising: a substrate; and an impedance Josephson parametric amplifier located on the substrate; Here, the capacitor portion of the nonlinear inductor-capacitor LC resonator of the impedance Josephson parametric amplifier is a planar stub of a coplanar waveguide structure. [Effects of the Invention]

[0021] The beneficial effects of the technical solutions provided by the embodiments of the present application include at least the following:

[0022] In the process of manufacturing an impedance Josephson parametric amplifier, the Josephson junction and other underlying circuits are manufactured by laser direct writing, and at the same time, in order to ensure the manufacturing precision of the Josephson junction, a trial manufacturing process of a Josephson junction sample is introduced to obtain the oxidation conditions for formally manufacturing the Josephson junction, thereby ensuring the manufacturing precision of the impedance Josephson parametric amplifier, while at the same time reducing the manufacturing process of the impedance Josephson parametric amplifier and improving the manufacturing efficiency of the impedance Josephson parametric amplifier. [Brief explanation of the drawings]

[0023] [Figure 1] 1 is a structural schematic diagram of an impedance-matched Josephson parametric amplifier according to the present application; [Figure 2] 1 is a method flowchart of a chip manufacturing method according to one exemplary embodiment of the present application. [Figure 3] 1 is a method flowchart of a chip manufacturing method according to one exemplary embodiment of the present application. [Figure 4] FIG. 4 is a schematic diagram of a photoresist structure according to the embodiment shown in FIG. 3. [Figure 5]FIG. 4 is a schematic diagram illustrating the fabrication of a Josephson junction by a Dolan bridge according to the embodiment shown in FIG. 3. [Figure 6] FIG. 1 is a schematic diagram of a layout design according to the present application. [Figure 7] 1 is a flow diagram illustrating a manufacturing process for an impedance-transforming Josephson parametric amplifier according to the present application. [Figure 8] 1A and 1B are schematic diagrams illustrating changes in product form in a flow for manufacturing an impedance-converting Josephson parametric amplifier according to an embodiment of the present application. [Figure 9] 1 is a structural schematic diagram of a chip provided by one exemplary embodiment of the present application; [Figure 10] 1 is a schematic diagram of a chip manufacturing system according to one exemplary embodiment of the present application; [Figure 11] FIG. 1 is a schematic diagram of an application scenario of the solution provided by one embodiment of the present application. DETAILED DESCRIPTION OF THE INVENTION

[0024] Peeling: After applying a base photoresist, exposing it to light, and developing it, a photosensitive resist film with a certain pattern is used as a mask to apply resist, and the required material, such as metal, is deposited by evaporation or other methods. Next, the photosensitive resist is removed, and at the same time, any unnecessary material on the resist film is also peeled off cleanly, leaving only the original material structure with the pattern engraved on the base.

[0025] Undercut: A narrow top, wide bottom structure formed in a bilayer resist process by opening a window after exposing and developing the top-layer photoresist, allowing the bottom-layer resist to continue to erode in a developer solution, causing lateral expansion.

[0026] Resist remover: An organic solvent that can remove the remaining photoresist after the sample has been exposed and developed without reacting with light.

[0027] Pre-bake: This is one of the basic steps in the photolithography process, also known as soft bake. It involves slowly and thoroughly evaporating the solvent in the photoresist film at a certain temperature to dry the photoresist film.

[0028] Pier: An area left on the bottom circuit structure that is used to connect the air bridge to the bottom circuit.

[0029] Exposure & Development: A type of micro-nano processing technology, mainly involving ultraviolet photolithography. That is, a photoresist is coated on the surface of the substrate sample, and then ultraviolet light is passed through a mask and irradiated onto the surface of the substrate, using a photochemical reaction to change the properties of the exposed areas of the photoresist. The light-reactive areas are then dissolved in a specific solution, achieving the purpose of expressing and creating specific patterns on the substrate.

[0030] Etching: A type of microfabrication process that uses dry (other) and wet (liquid) processes to erode metal or other materials to create desired structures.

[0031] Josephson parametric amplifiers are an important component of superconducting quantum computing measurement circuits. Their main function is to enhance the readout signal strength during quantum bit measurement, while effectively suppressing readout noise, and achieve signal amplification of several photons at mK temperatures. Josephson parametric amplifiers can be divided into conventional narrow-band parametric amplifiers and impedance-matched Josephson parametric amplifiers. Compared to narrow-band parametric amplifiers, impedance-matched parametric amplifiers add an impedance converter to the input terminal, sacrificing the gain peak to exchange for a larger gain bandwidth, allowing them to meet multi-bit measurement tasks.

[0032] Referring to Figure 1, a structural schematic diagram of an impedance-matched Josephson parametric amplifier according to the present application is shown. As shown in Figure 1, the main structure of the impedance-matched Josephson parametric amplifier includes an impedance converter 110 and a parametric amplifier 120. Here, the parametric amplifier 120 includes a nonlinear LC resonator (including a planar capacitor and a nonlinear inductor Josephson junction) and a pump drive.

[0033] A Josephson junction is a type of superconductor-insulator-superconductor structure. Superconducting electrons can tunnel from one side to the other through a thin insulator film. Related technologies typically use an electron beam exposure machine to expose the shape of the junction area, and require the use of two-layer electron beam photoresists: methyl methacrylate (MMA) and polymethyl methacrylate (PMMA). MMA is the bottom-layer resist, approximately 400-800 nm thick, and PMMA is the top-layer resist, approximately 300-500 nm thick. The impedance converters in related technologies for superconducting impedance conversion parametric amplifiers all use a structure in which one quarter-wavelength and one half-wavelength waveguide are connected in series. This structure is sensitive to processing parameters and has certain requirements for the linewidth of the coplanar waveguide (CPW). Most of the capacitor structures in related art quantum parametric amplifiers use parallel plate dielectric capacitors, i.e., two superconducting plates sandwiched between an insulating layer, and the capacitor density of such structures is relatively high, allowing the required capacitor to be fabricated within a relatively small area.

[0034] In the related art, the fabrication of Josephson junctions has the following deficiencies:

[0035] First, when depositing a metal layer after forming a specific pattern layer by exposure, residues are likely to form on the sidewalls of the pattern layer, and they may form adhesion with the metal pattern on the substrate, making it difficult to peel off, resulting in defects in the shape of the final bonded area.

[0036] Second, most electron beam exposure methods require the fabrication of an additional metal layer as an electron beam overlay mark. According to the principle of electron beam exposure, the difference in atomic number between the metal layer material and the metal layer on the substrate must be relatively large so that the overlay mark can be identified and distinguished under a scanning electron microscope. This requirement necessitates the introduction of an additional exposure-coating-peeling process, which increases the process complexity.

[0037] In contrast, the following embodiments of the present application provide a chip manufacturing method for use in an impedance-matched Josephson parametric amplifier, which can ensure the manufacturing precision of Josephson junctions while reducing the complexity of the process and improving the manufacturing efficiency of the impedance-matched Josephson parametric amplifier.

[0038] 2, there is shown a method flowchart of a chip manufacturing method according to one exemplary embodiment of the present application. As shown in FIG. 2, the method includes the following steps 201 to 206:

[0039] Step 201: By using laser direct writing exposure, a first bottom layer circuit of an impedance Josephson parametric amplifier is fabricated on a substrate, and a second bottom layer circuit of a Josephson junction used for testing is fabricated on the substrate, thereby obtaining a first chip product.

[0040] In an embodiment of the present application, first, a first bottom layer circuit and a second bottom layer circuit of an impedance Josephson parametric amplifier can be simultaneously fabricated on the same substrate by laser direct writing. Here, the first bottom layer circuit is a bottom layer circuit that does not include a Josephson junction, and the second bottom layer circuit is a bottom layer circuit of a Josephson junction used for testing. Optionally, the second bottom layer circuit does not include a Josephson junction used for testing, for example, the second bottom layer circuit includes a port circuit of a Josephson junction used for testing.

[0041] Optionally, the second bottom layer circuit of the Josephson junction used for testing refers to determining the manufacturing conditions of the official circuit by testing the second bottom layer circuit. That is, the second bottom layer circuit is the circuit to be tested, and during the manufacturing process of the second bottom layer circuit, the testing is performed to determine the manufacturing conditions of the circuit, and the official circuit is manufactured using the conditions determined by the testing.

[0042] Step 202: Using a laser direct writing exposure method, a photoresist structure is formed on the first chip product to be used for fabricating Josephson junctions.

[0043] In an embodiment of the present application, after the first and second bottom layer circuits are fabricated, a photoresist structure used for fabricating Josephson junctions, such as a Dolan bridge structure used for fabricating Josephson junctions, is formed on the substrate corresponding to the position where the Josephson junctions need to be fabricated.

[0044] The solution disclosed in the embodiments of the present application can ensure that the manufacturing environment of the genuine Josephson junction product and the Josephson junction sample used for testing are consistent with each other by simultaneously manufacturing a test circuit for the genuine product on the same substrate, and that the manufacturing conditions, including but not limited to the photoresist thickness, exposure intensity, development time, junction area size design, and coating conditions, of the genuine Josephson junction product and the Josephson junction sample used for testing are consistent with each other, thereby enabling the oxidation conditions of the genuine Josephson junction product to be accurately determined through testing.

[0045] Step 203: Divide the first bottom layer circuit and the second bottom layer circuit of the first chip product, and obtain a second chip product including the second bottom layer circuit after division, and a third chip product including the first bottom layer circuit after division.

[0046] The first chip product is divided to separate the first and second bottom circuits, and the first and second bottom circuits are separated from each other after the division. The chip part with the second bottom circuit after the division is the second chip product, and the chip part with the first bottom circuit after the division is the third chip product.

[0047] Optionally, the first bottom layer circuit and the second bottom layer circuit of the first chip product are divided to obtain a second chip product including the second bottom layer circuit after division, and a third chip product including the first bottom layer circuit after division.

[0048] In an embodiment of the present application, after the photoresist structure used for fabricating Josephson junctions is formed, the second bottom layer circuit is cut from the substrate to obtain a third chip product corresponding to the final product and a second chip product for testing. Here, cutting the second bottom layer circuit from the substrate refers to cutting the first chip product and dividing the first and second bottom layer circuits into different cutting sections, thereby dividing the first chip product into a second chip product and a third chip product. Here, the first bottom layer circuit is in the third chip product, and the second bottom layer circuit is in the second chip product. That is, if the first bottom layer circuit of the first chip product is in area A and the second bottom layer circuit is in area B, it is necessary to divide area A and area B, and then the first chip product is divided to obtain a third chip product including the first bottom layer circuit and a second chip product including the second bottom layer circuit.

[0049] Step 204: Based on the photoresist structure covering the second bottom-layer circuit, a Josephson junction sample is fabricated on the second chip product to determine the oxidation conditions used to fabricate the oxide layer in the Josephson junction.

[0050] Since the second chip product and the third chip product are fabricated simultaneously on the same substrate, the two chips are identical in terms of conditions such as photoresist thickness, exposure intensity, development time, junction area size design, and coating conditions. When a Josephson junction sample is fabricated on the second chip product, if the fabricated Josephson junction sample meets the design requirements for the Josephson junction in the impedance Josephson parametric amplifier, the oxidation conditions used at this time can be used to fabricate the final product, resulting in an oxidation layer that meets the design requirements. In other words, the oxidation conditions corresponding to the fabricated Josephson junction sample that meets the design requirements can be used as the oxidation conditions for the Josephson junction in the final product to be subsequently fabricated, thereby ensuring the manufacturing accuracy of the Josephson junction in the final product.

[0051] Step 205: According to oxidation conditions, fabricate a Josephson junction on the third chip product based on the photoresist structure covering the first bottom layer circuit, and fabricate the third chip product as a fourth chip product.

[0052] Here, the method of fabricating Josephson junctions on the third chip product based on the photoresist structure corresponding to the first bottom layer circuit is similar to the method of fabricating a prototype Josephson junction sample. That is, oxidation conditions corresponding to the prototype Josephson junction sample that meets the design requirements are adopted to fabricate the oxide layer of the Josephson junction in the final product. After the oxidation conditions are determined, Josephson junctions are fabricated on the third chip product according to the oxidation conditions, and the third chip product, which originally did not include Josephson junctions, is transformed into a fourth chip product that includes Josephson junctions.

[0053] Step 206: Obtain a target chip product including an impedance Josephson parametric amplifier based on the fourth chip product.

[0054] As described above, the solution disclosed in the embodiments of the present application uses laser direct writing to fabricate Josephson junctions and other underlying circuits in the process of manufacturing an impedance Josephson parametric amplifier, and at the same time, in order to ensure the manufacturing precision of the Josephson junctions, a trial manufacturing process of Josephson junction samples is introduced to obtain the oxidation conditions for formally manufacturing the Josephson junctions, thereby ensuring the manufacturing precision of the impedance Josephson parametric amplifiers, while reducing the manufacturing process of the impedance Josephson parametric amplifiers and improving the manufacturing efficiency of the impedance Josephson parametric amplifiers.

[0055] Based on the embodiment shown in Fig. 2, a method flowchart of a chip manufacturing method shown in one exemplary embodiment of the present application is shown in Fig. 3. As shown in Fig. 3, the chip manufacturing method may include the following steps 301 to 306.

[0056] Step 301: A first bottom-layer circuit of an impedance Josephson parametric amplifier is fabricated on a substrate by laser direct writing exposure, and a second bottom-layer circuit of a Josephson junction used for testing is fabricated on the substrate to obtain a first chip product. The first bottom-layer circuit includes a capacitor part of a nonlinear inductor-capacitor LC resonator of the impedance Josephson parametric amplifier, and the capacitor part is a planar stub of a coplanar waveguide structure.

[0057] Optionally, the first and second bottom layer circuits do not include Josephson junctions.

[0058] The solution shown in the embodiments of the present application uses a planar stub of a coplanar waveguide structure as the capacitor part of a nonlinear inductor-capacitor LC resonator, eliminating the process step of manufacturing a dielectric layer, thereby reducing insertion loss and simplifying the process complexity and manufacturing difficulty.

[0059] A central conductor strip is fabricated on one side of a dielectric substrate, and conductive planes are fabricated on both sides adjacent to the central conductor strip. This creates a coplanar waveguide, also known as a coplanar microstrip transmission line. Because the center conductor is in the same plane as the conductive planes, it is very simple to mount components in parallel on the coplanar waveguide, allowing the fabrication of monolithic microwave integrated circuits with the transmission line and devices both on the same side.

[0060] In one possible implementation, the first bottom layer circuit further includes an impedance converter of an impedance Josephson parametric amplifier; A compensation deviation exists between the line width in the layout of the impedance converter and the design line width of the impedance converter, and the compensation deviation is determined based on an etching deviation when etching is performed on the third photoresist layer, the third photoresist layer being a photoresist layer applied on the bottom layer circuit material after the bottom layer circuit material is deposited on the substrate.

[0061] To address the strict requirements for the line width of the impedance converter, in the embodiments of the present application, when manufacturing the impedance converter part of the impedance Josephson parametric amplifier using the laser direct writing exposure method, an "etching compensation" method can be adopted, that is, by pre-reserving the etching deviation during actual processing in the layout, it can be ensured that the processed actual line width is closer to the design requirement, and the success rate can be increased.

[0062] For example, in the embodiment of the present application, the line width of the impedance transformer part can be left with actual deviation when designing the layout. For example, if the target value of the etching groove is 2 μm, the layout can be drawn to 1.7 μm (i.e., the etching compensation is 0.3 μm), and the etching time can be appropriately extended during actual etching to ensure that the etching groove is clean and complete, and also to achieve the required line width.

[0063] In one possible implementation, a first bottom layer circuit of an impedance Josephson parametric amplifier and a second bottom layer circuit of a Josephson junction used for testing are fabricated on a substrate by laser direct writing exposure. The above process of obtaining a first chip product may include the following steps S301a to S301e.

[0064] S301a: Deposit bottom layer circuit material on a substrate.

[0065] S301b: Apply a third photoresist layer onto the bottom layer circuit material.

[0066] S301c: Using a laser direct writing exposure method, the third photoresist layer is exposed and developed to form etching areas corresponding to the first bottom layer circuit and the second bottom layer circuit.

[0067] In the embodiment of the present application, the process of exposing and developing the third photoresist layer by laser direct writing exposure to form etching areas corresponding to the first bottom layer circuit and the second bottom layer circuit includes: defining circuit patterns of a first bottom layer circuit and a second bottom layer circuit in the third photoresist layer by laser direct writing; and developing the substrate in a developer to develop the etched areas corresponding to the first and second bottom layer circuits.

[0068] Here, the substrate and the material deposited on the substrate are placed in a developer and developed to obtain etched areas corresponding to the first and second bottom layer circuits.

[0069] S301d: Etch the third photoresist layer to remove the underlying circuit material in the etched areas.

[0070] S301e: The photoresist on the substrate is washed away to obtain the first chip product.

[0071] In the present embodiment, the process flow described above is used to deposit a bottom metal layer, typically an aluminum film, on a substrate, and then a single exposure-develop-etch process is used to fabricate the coplanar waveguide structures of impedance transformers and stub capacitors, pump-drive structures, and port circuits of test junction arrays.

[0072] Step 302: Using a laser direct writing exposure method, a photoresist structure is formed on the first chip product to be used for fabricating Josephson junctions.

[0073] In one possible implementation, the photoresist structure used to fabricate Josephson junctions can be exposed by a bilayer resist process.

[0074] Alternatively, the photoresist structure may be a Dolan bridge structure. For example, the bottom resist may be a lift-off resist (LOR) series photoresist, and the top resist may be a photoresist of a model number such as S1813 / S1805 / SPR955. A laser direct-writing tool is used to expose a Josephson junction sample array for testing and a proper Josephson junction junction area pattern. The exposed Josephson junction junction area pattern is then developed. Due to the different dissolution rates of the bottom and top photoresists in the developer, an undercut structure with a narrow top and a wide bottom is formed after development. Referring to FIG. 4, a schematic diagram of a photoresist structure according to an embodiment of the present application is shown. As shown in FIG. 4, in the Josephson junction design structure, the photoresist that connects the bottoms of two adjacent exposed regions to form a suspended structure is called a Dolan bridge 400.

[0075] Step 303: Divide the first bottom layer circuit and the second bottom layer circuit of the first chip product, and obtain a second chip product including the second bottom layer circuit after division, and a third chip product including the first bottom layer circuit after division.

[0076] Optionally, the first chip product is divided to separate the first bottom layer circuit and the second bottom layer circuit, and the first bottom layer circuit and the second bottom layer circuit are separated from each other after the division, where the chip part having the second bottom layer circuit after the division is the second chip product, and the chip part having the first bottom layer circuit after the division is the third chip product.

[0077] The first chip product is cut into a second chip product and a third chip product, where the second chip product is a chip product obtained by cutting the second bottom layer circuit from the first chip product, and the third chip product is a chip product obtained by cutting the first bottom layer circuit from the first chip product.

[0078] Step 304: Based on the second bottom-layer circuit and the corresponding photoresist structure, a Josephson junction sample is fabricated on the second chip product to determine the oxidation conditions used to fabricate the oxide layer in the Josephson junction.

[0079] In one possible implementation, a Josephson junction sample array is included on the second bottom layer circuit, the Josephson junction sample array including at least two Josephson junction sample port circuits, each corresponding to a set of photoresist structures; fabricating a Josephson junction sample on a second chip product based on the second bottom-layer circuit and the corresponding photoresist structure, and obtaining oxidation conditions used to fabricate an oxide layer in the Josephson junction; fabricating a Josephson junction sample corresponding to a first port circuit based on a photoresist structure covering the first port circuit under a first oxidation condition, the first port circuit being one port circuit of at least two Josephson junction samples in which no Josephson junction sample has been fabricated; and obtaining a first oxidation condition as an oxidation condition for manufacturing an oxide layer in the Josephson junction when the first resistance value meets a design requirement, the first resistance value being obtained by measuring a Josephson junction sample corresponding to the first port circuit based on the first port circuit.

[0080] Optionally, in a situation where the first resistance value does not satisfy the design requirement, the first oxidation condition and the first port circuit are updated and the test is continuously performed until an oxidation condition that enables the first resistance value to satisfy the design requirement is derived through the test.

[0081] In one possible implementation, the photoresist structure is a Dolan bridge structure, and the step of fabricating a Josephson junction sample corresponding to the first-port circuit based on the photoresist structure covering the first-port circuit under a first oxidation condition includes: obliquely evaporating a first superconducting layer of the Josephson junction sample corresponding to the first-port circuit based on a photoresist structure covering the first-port circuit; performing an oxidation treatment on the first superconducting layer according to a first oxidation condition to obtain an oxide insulating layer on the surface of the first superconducting layer; and vertically depositing a second superconducting layer of the Josephson junction sample corresponding to the first-port circuit based on the photoresist structure covering the first-port circuit to obtain the Josephson junction sample corresponding to the first-port circuit.

[0082] For example, FIG. 5 shows a schematic diagram of fabricating a Josephson junction using a Dolan bridge according to an embodiment of the present invention. As shown in part (a) of FIG. 5 , based on the Dolan bridge structure, a superconducting material is first deposited on a substrate below the Dolan bridge by oblique evaporation through an opening 501 on the Dolan bridge, thereby obtaining a first superconducting layer 502 of a Josephson junction sample. Next, an oxidation treatment is performed on the first superconducting layer 502 in an oxidation chamber, thereby obtaining an oxide insulating layer 503 on the surface of the first superconducting layer 502. Then, a superconducting material is deposited on the substrate oxide insulating layer below the Dolan bridge and on the substrate by vertical evaporation through an opening 504 on the Dolan bridge, thereby obtaining a second superconducting layer 505 of the Josephson junction sample. The first superconducting layer 502, the oxide insulating layer 503, and the second superconducting layer 505 constitute a Josephson junction / Josephson junction sample. Furthermore, due to the presence of the apertures 501, the superconducting material can be deposited on the oxide insulating layer and the substrate through the apertures 501 during vertical evaporation, thereby obtaining a superconducting layer 506. In Fig. 5, for the sake of convenience, the superconducting layer 506 is depicted as partially floating in the air, but in actual applications, the floating portion of the superconducting layer 506 may sink onto the substrate. A Josephson junction / Josephson junction sample manufactured by the above solution is shown in part (b) of Fig. 5.

[0083] In one possible implementation, the first oxidation conditions are: The information includes at least one of the gas flow rate of oxygen gas, the atmospheric pressure, and the oxidation time.

[0084] According to the solution described in the above embodiment of the present application, Josephson junction samples are fabricated under various oxidation conditions on a second chip product having a second bottom-layer circuit, and the resistance of the Josephson junction samples is measured to determine the oxidation conditions that meet the requirements. These conditions include the oxygen gas flow rate, pressure, and oxidation time, and may optionally include other oxidation conditions, such as the airflow angle and oxidation temperature. The above oxidation conditions are not limited to the embodiments of the present application.

[0085] Optionally, in addition to the oxidation conditions, when fabricating a Josephson junction sample with the second bottom layer circuit and the corresponding photoresist structure, other conditions for fabricating the Josephson junction can be further obtained, such as the deposition time of the superconducting material of the Josephson junction, the deposition flow rate of the superconducting material, the deposition angle, temperature, and pressure.

[0086] Step 305: According to oxidation conditions, fabricate a Josephson junction on the third chip product based on the photoresist structure covering the first bottom layer circuit, and fabricate the third chip product as a fourth chip product.

[0087] In the embodiment of the present application, when the photoresist architecture is a Doran bridge structure, the Josephson junction / Josephson junction sample can be fabricated by double tilt electron beam evaporation.

[0088] For example, first, the first layer of superconducting aluminum film for the Josephson junction sample is deposited at a relatively large tilt angle. The tilt angle is related to the thickness of the resist and must ensure that the first layer of aluminum film can pass through the Doran bridge. A constant flow of oxygen gas is supplied in a high-vacuum environment to oxidize the top surface of the first layer of aluminum film, forming an insulating layer for the Josephson junction sample. Next, the second layer of aluminum film for the Josephson junction sample is deposited from the front at a vertical angle. After deposition is complete, the sample is placed in a resist remover to remove the photoresist and strip off the excess metal, resulting in a complete Josephson junction sample.

[0089] The solution disclosed in the embodiment of the present application uses a laser direct writing method to expose the Josephson junctions, which, compared with conventional electron beam exposure, eliminates the need for an overlay mark layer and has the advantage that the Josephson junctions fabricated using laser direct writing are relatively large in size, making them less susceptible to damage when applied to superconducting parametric amplifier devices and more stable in performance. At the same time, due to the sensitivity of Josephson junctions to junction resistance parameters, the embodiment of the present application also adds a test junction array design in the layout, and simultaneously exposes and develops the test junctions and the formal sample to create respective junctions, ensuring that the junction resistance of the formal Josephson junctions meets the design value.

[0090] Step 306: An air bridge is fabricated at the base of the planar stub of the fourth chip product, and the fourth chip product is fabricated as the target chip product.

[0091] In one possible implementation, the step of fabricating an air bridge at the root of the planar stub of the fourth chip product to obtain the target chip product includes: applying a first photoresist layer on the fourth chip product; exposing and developing a first photoresist layer in a region corresponding to the base of the planar stub to define a pier region of the air bridge; performing a reflow process on the first photoresist layer so that the remaining photoresist in the first photoresist layer assumes an arched shape; depositing an air bridge body material on the first photoresist layer; applying a second photoresist layer over the bridge body material; exposing and developing the second photoresist layer to areas other than the bridge body of the air bridge; removing the bridge body material other than the bridge body of the air bridge by etching; and washing the photoresist off the fourth chip product to obtain a target chip product.

[0092] In one possible implementation, in an oxidizing condition, the resistance of the Josephson junction sample is less than the design resistance of the Josephson junction, and the resistance difference between the resistance of the Josephson junction sample and the design resistance of the Josephson junction matches the resistance increment for the air bridge Josephson junction.

[0093] In the solution shown in the embodiment of the present application, an air bridge can be added to the base of the stub to reduce the parasitic mode caused by the capacitor structure of the planar stub. Also, when selecting oxidation conditions, the relationship and difference between the resistance value of the Josephson junction sample and the design resistance value of the Josephson junction can be taken into consideration, thereby solving the problem that the air bridge process causes fluctuations in the resistance of the Josephson junction.

[0094] In the present embodiment, an air bridge can be fabricated using a thick resist. For example, in the first step, a photoresist SPR is uniformly coated on the bottom aluminum film, and the air bridge pier pattern is exposed and developed. A developer that does not corrode the aluminum film, such as AZdeveloper solution, can be used. In the second step, the sample is heated on a baking table for a reflow process, which causes the photoresist to arch and form the bridge body shape. In the third step, a layer of aluminum film with a thickness of 100 nanometers is deposited on the photoresist as the bridge body. In the third step, a photoresist SPR is again uniformly coated on the aluminum film, and the air bridge body pattern is exposed and developed. In the fourth step, the bridge body structure is etched using an acidic etching solution. Finally, the sample is placed in a resist remover to remove the photoresist and strip off excess metal.

[0095] The solution presented in the embodiment of this application provides a method for fabricating a Josephson impedance transforming junction parametric amplifier. The design is sensitive to parameters and has certain requirements for chip processing. The method has the following characteristics:

[0096] 1) Because of the sensitivity to impedance values, the line width of the etched grooves of the waveguide must be accurate. The solution presented in the embodiments of this application proposes an "etching compensation" method, that is, by pre-setting the etching deviation for the actual processing when drawing the layout and appropriately over-etching, it is ensured that the etching is complete and meets the line width requirements.

[0097] 2) The embodiment of this application uses a method of exposing Josephson junctions by laser direct writing. The basic idea is to use the laser direct writing exposure method, and utilize the difference in solubility in the developer of the upper and lower photoresist layers in the two-layer resist process to form a specific pattern layer, and then use a coating machine to deposit a metal layer using the pattern layer as a mask, and then peel it off to obtain a Josephson junction structure.

[0098] At the same time, because Josephson junctions are sensitive to junction resistance parameters, the present embodiment adds a test junction array design to the layout, explores oxidation parameters through the test junctions, and after obtaining ideal junction resistance, manufactures the junction area on a formal sample.

[0099] 3) An air bridge structure is introduced to suppress the parasitic mode caused by the capacitor. The air bridge process may cause a certain variation in the junction resistance of the completed Josephson junction, and the solution shown in the embodiment of this application can obtain the target junction resistance by selecting the oxidation conditions.

[0100] As described above, the solution disclosed in the embodiments of the present application uses laser direct writing to manufacture Josephson junctions and other underlying circuits in the process of manufacturing an impedance Josephson parametric amplifier, and at the same time, in order to ensure the manufacturing precision of the Josephson junctions, a trial manufacturing process of Josephson junction samples is introduced to obtain the oxidation conditions for formally manufacturing the Josephson junctions. This ensures the manufacturing precision of the impedance Josephson parametric amplifier, while reducing the manufacturing process of the impedance Josephson parametric amplifier and improving the manufacturing efficiency of the impedance Josephson parametric amplifier.

[0101] The method provided in this embodiment uses a planar stub of a coplanar waveguide structure as the capacitor part of a nonlinear inductor-capacitor LC resonator, eliminating the process step of manufacturing a dielectric layer, reducing insertion loss, and simplifying the process complexity and manufacturing difficulty.

[0102] The method provided by this embodiment can add an air bridge to the base of the stub to reduce the parasitic mode caused by the capacitor structure of the planar stub. Also, by considering the magnitude relationship and difference between the resistance value of the Josephson junction sample and the design resistance value of the Josephson junction when selecting oxidation conditions, the problem of the air bridge process causing fluctuations in the resistance of the Josephson junction can be solved.

[0103] The complete structure of the impedance-converting Josephson parametric amplifier according to the above embodiment of the present application includes input / output ports, an impedance converter, a nonlinear LC resonator (including a planar capacitor and a nonlinear inductor Josephson junction), a pump drive, a test junction array, and an air bridge structure. Here, the input / output ports, the impedance converter, the planar capacitor of the nonlinear LC resonator, the pump drive line, and the port of the test junction array can be patterned using a laser direct-write photolithography process with one exposure and one etching. The superconducting Josephson junction of the nonlinear LC resonator is fabricated using a laser direct-write bilayer resist process with exposure and a double-tilt electron beam evaporation process, and the air bridge structure is fabricated using a laser direct-write two-exposure and one-evaporation coating process as the final step.

[0104] The core processing criteria for the entire process are, first, accurate linewidth of the impedance transformer, and, second, accurate junction resistance of the Josephson junction. To meet the first criterion, the solution described in the above examples of this application employs a stable laboratory etching process to ensure that the deviation between the actual linewidth and the design value after each etching is a relatively stable value. To compensate for this deviation in the layout design and meet the second criterion, a test junction array is introduced and the test junction array and the final product are designed on the same substrate. See Figure 6, which shows a schematic diagram of the layout design described in this application. As shown in Figure 6, the test junction array and the final product are simultaneously exposed and developed to separate the test junction array. The test junction array is then used to explore the oxidation conditions for fabricating Josephson junctions by double-tilt electron beam evaporation. After obtaining appropriate oxidation data, Josephson junctions are fabricated on the final sample. It should be noted that the junction resistance corresponding to the optimal oxidation condition should be slightly smaller than the design resistance value, because the final step of the air bridge process may increase the junction resistance of the completed Josephson junction. In a stable experimental environment, this increase is usually relatively stable.

[0105] Referring to Figure 7, a flow diagram for fabricating an impedance-transforming Josephson parametric amplifier according to the present application is shown. As shown in Figure 7, the flow may include several steps:

[0106] S71: Deposit a bottom metal layer on a substrate.

[0107] Optionally, the metal layer is realized as an aluminum film, but in some embodiments, the metal layer may be realized as other metals, and this embodiment is not limited thereto.

[0108] S72: Spin-coat UV photoresist onto the bottom aluminum film and expose the bottom circuit structures of the impedance transformer and stub capacitor coplanar waveguide structures, pump drive structures, and test junction arrays.

[0109] Optionally, the UV photoresist is realized as S1805 photoresist.

[0110] S73: The photoresist that has deteriorated after exposure is developed and removed to expose the underlying metal of the defined pattern.

[0111] S74: The above pattern on the photoresist is transferred to the underlying metal using an acidic etchant, and then the sample is placed in a resist remover to remove the remaining photoresist.

[0112] S75: A bilayer photoresist is spin-coated on the bottom aluminum film, and the junction area patterns of the test junction array and the formal Josephson junction are exposed.

[0113] Here, the bottom layer resist is generally an LOR series, and the top layer resist is usually S1813 / S1805 / SPR955 or the like.

[0114] S76: The junction area pattern of the Josephson junction is exposed by development.

[0115] S77: Test junction arrays are split off from intact substrates and used to explore oxidation conditions for Josephson junctions.

[0116] S78: A small piece of the test junction array is placed in a coating machine, and the first layer of superconducting aluminum film of the Josephson junction is deposited at a relatively large tilt angle.

[0117] That is, a Josephson junction is deposited.

[0118] S79: In a high vacuum environment, a constant flow of oxygen gas is supplied to the test junction array to oxidize the top surface of the first layer of aluminum film, forming an insulating layer for the Josephson junctions.

[0119] S710: The second layer of the Josephson junction, an aluminum film, is deposited from the front at a perpendicular angle.

[0120] S711: The test junction array with deposited junction areas is removed from the coating equipment and placed in a resist remover to remove the photoresist and strip off excess metal, resulting in the complete Josephson junctions.

[0121] S712: The junction resistance of the Josephson junctions on the test junction array is measured using a tool such as a probe table, and after it matches the design resistance, deposition of the junction area is performed for the official product.

[0122] Optionally, when measuring the junction resistance of the Josephson junctions on the test junction array, the change in the resistance of the Josephson junctions due to the subsequent air bridge process must be taken into consideration. In a stable experimental environment, the rate of change in junction resistance due to the air bridge process is also relatively stable. If the junction resistance of the test junction array matches the design value after removing the influence of the air bridge, proceed to the next step of the air bridge manufacturing process. If not, select a next test junction array and repeat steps S78 to S712. After the design resistance is met, the deposition of the junction area in steps S78 to S712 is performed on the final product.

[0123] S713: Spin-coat UV photoresist SPR onto the bottom aluminum film and expose the pier structure of the air bridge.

[0124] S714: Reflow process: The substrate is placed on a resist baking table and baked at high temperature to make the resist surface arch.

[0125] S715: Deposit one relatively thick metal aluminum layer on the substrate as the bridge body, then uniformize one layer of photoresist SPR to expose the bridge body pattern.

[0126] S716: The bridge body pattern on the photoresist is transferred onto the metal aluminum layer using an acid etching solution to form a complete air bridge.Then, the sample is placed in a resist removal solution to remove the remaining photoresist and excess aluminum film.

[0127] Referring to FIG. 8, it shows a schematic diagram of the product transformation process in the manufacturing process of an impedance-conversion Josephson parametric amplifier according to an embodiment of the present invention. As shown in FIG. 8, first, a bottom metal layer, i.e., a metal aluminum film 820, is deposited on a substrate 810. Then, ultraviolet photoresist is spin-coated on the bottom aluminum film 820 and exposed to light to form a bottom circuit structure 830 including a coplanar waveguide structure of an impedance converter and a stub capacitor, a pump drive structure, and a test junction array. The above patterns on the photoresist are transferred to the bottom metal using an acidic etchant. The sample is then placed in a resist remover to remove the remaining photoresist. A two-layer photoresist is spin-coated on the bottom aluminum film and exposed to light to form the junction area patterns of the test junction array and the actual Josephson junctions. Development is performed to expose the junction area patterns of the Josephson junctions, thereby depositing Josephson junctions 840 and fabricating an air bridge 850.

[0128] The method for fabricating an impedance-converting Josephson parametric amplifier proposed in the present application uses "etching compensation" and a test junction array to explore oxidation conditions, thereby resolving the strict requirements for the line width and junction resistance of the impedance converter in the parametric amplifier and improving device performance. At the same time, the method for fabricating Josephson junctions by laser direct writing, compared with conventional electron beam lithography, has the advantages of eliminating the need for an overlay mark layer and being easy to peel, making the fabricated large-scale Josephson junctions less susceptible to damage when applied to superconducting parametric amplifier devices, and providing more stable performance.

[0129] Referring to Figure 9, a structural schematic diagram of a chip provided by one exemplary embodiment of the present application is shown. As shown in Figure 9, the chip includes: The device includes a substrate 91 and an impedance Josephson parametric amplifier 92 located on the substrate, where the impedance Josephson parametric amplifier 92 includes a signal input / output port 92a, an impedance transformer 92b, a nonlinear inductor-capacitor LC resonator 92c, a Josephson junction, and a pump structure 92d, where the capacitor portion 92c1 of the nonlinear LC resonator 92c is a planar stub of a coplanar waveguide structure.

[0130] In one possible implementation, the base of the planar stub includes an air bridge 92e, as shown in FIG.

[0131] Here, the chip is a chip product manufactured according to the method shown in FIG. 2, FIG. 3, or FIG.

[0132] 10 shows a schematic diagram of a chip manufacturing system according to one exemplary embodiment of the present application, which may be implemented as a production line device. As shown in FIG. 10, the chip manufacturing system includes a coating machine 1001, a photolithography machine 1002, an etching machine 1003, a deposition machine 1004, a cleaning machine 1005, an oxidation chamber 1006, and a cutting machine 1007. The coating machine 1001, the photolithography machine 1002, the deposition machine 1004, the etching machine 1003, and the cleaning machine 1005 are used to manufacture a first bottom layer circuit of an impedance Josephson parametric amplifier and a second bottom layer circuit of a Josephson junction used for testing on a substrate by laser direct writing exposure, thereby obtaining a first chip product; The coating machine 1001 and the photolithography machine 1002 are used to generate photoresist structures used to fabricate Josephson junctions on the first chip product by laser direct writing exposure; the cutting machine 1007 is used to divide the first chip product into the first bottom layer circuit and the second bottom layer circuit, and obtain a second chip product including the second bottom layer circuit after division, and a third chip product including the first bottom layer circuit after division; The deposition machine 1004 and the oxidation chamber 1006 are used to fabricate a Josephson junction sample on the second chip product based on the photoresist structure covering the second bottom layer circuit, thereby determining oxidation conditions used to fabricate an oxide layer in the Josephson junction; The deposition machine 1004 and the oxidation chamber 1006 are further used to fabricate a Josephson junction on the third chip product according to the oxidation conditions based on the photoresist structure covering the first bottom layer circuit, and fabricate the third chip product as a fourth chip product; The coating machine 1001, the photolithography machine 1002, the deposition machine 1004, the etching machine 1003, and the cleaning machine 1005 are further used to obtain a target chip product including the impedance Josephson parametric amplifier based on the fourth chip product.

[0133] In one possible implementation, the first bottom layer circuit includes a capacitor portion of the nonlinear inductor-capacitor LC resonator of the impedance Josephson parametric amplifier; The capacitor portion is a planar stub of a coplanar waveguide structure.

[0134] In one possible implementation, the coating machine 1001, the photolithography machine 1002, the deposition machine 1004, the etching machine 1003, and the cleaning machine 1005 are used to fabricate an air bridge at the base of the planar stub of the fourth chip product, and to fabricate the fourth chip product as the target chip product.

[0135] In one possible implementation, the step of fabricating an air bridge at the root of the planar stub of the fourth chip product to obtain the target chip product comprises: The coating machine 1001 is used to coat a first photoresist layer on the fourth chip product; the photolithography machine 1002 is used to expose and develop the first photoresist layer corresponding to the base position of the planar stub to form the pier region of the air bridge; performing a reflow process on the first photoresist layer to obtain an arched first photoresist layer; The deposition machine 1004 is used to deposit a bridge body material of the air bridge on the arch-shaped first photoresist layer; The coating machine 1001 is used to coat a second photoresist layer on the bridge body material; the photolithography machine 1002 is used to expose and develop the second photoresist layer in areas other than the air bridge body; the etching machine 1003 is used to remove the bridge body material other than the bridge body of the air bridge by etching; The cleaning machine 1005 is used to clean the photoresist of the fourth chip product to obtain the target chip product.

[0136] In one possible implementation, under the oxidizing condition, the resistance of the Josephson junction sample is less than the design resistance of the Josephson junction, and the difference in resistance between the resistance of the Josephson junction sample and the design resistance of the Josephson junction matches the resistance increment of the air bridge to the Josephson junction.

[0137] In one possible implementation, the deposition machine 1004 is used to deposit a bottom layer circuit material on the substrate; The coating machine 1001 is used to coat a third photoresist layer on the bottom layer circuit material; The photolithography machine 1002 is used to expose and develop the third photoresist layer by a laser direct writing exposure method, to form etching areas corresponding to the first bottom layer circuit and the second bottom layer circuit; the etching machine 1003 is used to perform an etching process on the third photoresist layer to remove the bottom circuit material in the etching area; The cleaning machine 1005 is used to clean the photoresist on the substrate to obtain the first chip product.

[0138] In one possible implementation, the photolithography machine 1002 is used to define the circuit patterns of the first bottom layer circuit and the second bottom layer circuit in the third photoresist layer by laser direct writing, and to develop the etching areas corresponding to the first bottom layer circuit and the second bottom layer circuit by placing the substrate in a developer and developing it.

[0139] In one possible implementation, the first bottom layer circuit includes an impedance converter of the impedance Josephson parametric amplifier; A compensation deviation exists between the line width in the layout of the impedance converter and the design line width of the impedance converter, and the compensation deviation is determined based on an etching deviation when etching the third photoresist layer.

[0140] In one possible implementation, the second bottom layer circuit includes a Josephson junction sample array, the Josephson junction sample array including at least two Josephson junction sample port circuits, each of the port circuits corresponding to a pair of the photoresist structures; The deposition machine 1004 and the oxidation chamber 1006 fabricate the Josephson junction sample corresponding to the first port circuit based on the photoresist structure covering the first port circuit under a first oxidation condition, and the first port circuit is one of the port circuits of at least two Josephson junction samples in which the Josephson junction sample is not fabricated; When a first resistance value satisfies a design requirement, the first oxidation condition is determined as an oxidation condition for manufacturing an oxide layer in a Josephson junction, and the first resistance value is obtained by measuring the Josephson junction sample corresponding to the first port circuit based on the first port circuit.

[0141] In one possible implementation, the oxidation chamber 1006 further comprises: In the situation where the first resistance value does not meet the design requirement, the first oxidation condition and the first port circuit are updated and tested.

[0142] In one possible implementation, the photoresist structure is a Dolan bridge structure; the deposition machine 1004 is used to obliquely deposit a first superconducting layer of the Josephson junction sample corresponding to the first port circuit according to the photoresist structure covering the first port circuit; the oxidation chamber 1006 is used to perform oxidation treatment on the first superconducting layer according to the first oxidation conditions to obtain an oxide insulating layer on the surface of the first superconducting layer; The deposition machine 1004 is used to vertically deposit a second superconducting layer of the Josephson junction sample corresponding to the first-port circuit based on the photoresist structure covering the first-port circuit, thereby obtaining the Josephson junction sample corresponding to the first-port circuit.

[0143] In one possible implementation, the first oxidation conditions are: The information includes at least one of the gas flow rate of oxygen gas, the atmospheric pressure, and the oxidation time.

[0144] 11, which shows a schematic diagram of an application scenario of a solution provided by one embodiment of the present application. As shown in FIG. 11, the application scenario may be a superconducting quantum computing platform, and the application scenario includes a quantum computing device 1101, a dilution refrigerator 1102, a control device 1103, and a computer 1104.

[0145] The quantum computing device 1101 is a circuit that operates on physical quantum bits, and may be realized as a quantum chip, for example, a superconducting quantum chip near absolute zero. The quantum chip can be manufactured and obtained by the solutions shown in the above embodiments of the present application. The dilution refrigerator 1102 is used to provide an absolute zero environment for the superconducting quantum chip.

[0146] Control device 1103 is used to control quantum computing device 1101, and computer 1104 is used to control control device 1103. For example, a programmed quantum program is compiled into instructions by software in computer 1104 and sent to control device 1103 (e.g., an electronic / microwave control system), and control device 1103 converts the instructions into electronic / microwave control signals and inputs them to dilution refrigerator 1102 to control superconducting qubits at a temperature below 10 mK. The readout process is the reverse, and a readout waveform is transmitted to quantum computing device 1101.

Claims

1. 1. A method of manufacturing a chip, the method comprising: By using laser direct writing exposure method, a first bottom layer circuit of an impedance Josephson parametric amplifier is fabricated on a substrate, and a second bottom layer circuit of a Josephson junction used for testing is fabricated on the substrate, thereby obtaining a first chip product; generating a photoresist structure used to fabricate the Josephson junction on the first chip product by laser direct writing exposure; dividing the first bottom layer circuit and the second bottom layer circuit of the first chip product to obtain a second chip product including the second bottom layer circuit after division, and a third chip product including the first bottom layer circuit after division; determining oxidation conditions used to fabricate an oxide layer in a Josephson junction by fabricating a Josephson junction sample on the second chip product based on the photoresist structure covering the second bottom layer circuit; According to the oxidation condition, fabricating the Josephson junction on the third chip product based on the photoresist structure covering the first bottom layer circuit, and fabricating the third chip product as a fourth chip product; and obtaining a target chip product including the impedance Josephson parametric amplifier based on the fourth chip product.

2. the first bottom layer circuit includes a capacitor portion of a nonlinear inductor-capacitor LC resonator of the impedance Josephson parametric amplifier; The method of claim 1 , wherein the capacitor portion is a planar stub of a coplanar waveguide structure.

3. The step of obtaining a target chip product including the impedance Josephson parametric amplifier based on the fourth chip product comprises:

3. The method of claim 2, further comprising the step of fabricating an air bridge at a root of the planar stub of the fourth chip product, and fabricating the fourth chip product as the target chip product.

4. The step of fabricating an air bridge at the root of the planar stub of the fourth chip product and fabricating the fourth chip product as the target chip product includes: applying a first photoresist layer on the fourth chip product; exposing and developing the first photoresist layer in a region corresponding to the base of the planar stub to define a pier region of the air bridge; performing a reflow process on the first photoresist layer to obtain an arched first photoresist layer; depositing a bridge body material of the air bridge on the arched first photoresist layer; applying a second photoresist layer on the bridge body material; exposing and developing the second photoresist layer to areas other than the bridge body of the air bridge; removing the bridge body material other than the bridge body of the air bridge by etching; and washing the photoresist of the fourth chip product to obtain the target chip product.

5. 4. The method of claim 3, wherein, in the oxidizing condition, the resistance of the Josephson junction sample is less than a design resistance of the Josephson junction, and a resistance difference between the resistance of the Josephson junction sample and the design resistance of the Josephson junction matches an increment in resistance of the air bridge for the Josephson junction.

6. The step of fabricating a first bottom layer circuit of an impedance Josephson parametric amplifier on a substrate by laser direct writing exposure, and fabricating a second bottom layer circuit of a Josephson junction used for testing on the substrate, to obtain a first chip product, includes: depositing a bottom layer circuit material on the substrate; applying a third photoresist layer over the bottom layer circuit material; Exposing and developing the third photoresist layer by a laser direct writing exposure method to form etching areas corresponding to the first bottom layer circuit and the second bottom layer circuit; performing an etching process on the third photoresist layer to remove the bottom layer circuit material in the etching areas; and cleaning the photoresist on the substrate to obtain the first chip product.

7. The step of exposing and developing the third photoresist layer by a laser direct writing exposure method to form etching areas corresponding to the first bottom layer circuit and the second bottom layer circuit, defining circuit patterns of the first bottom layer circuit and the second bottom layer circuit in a third photoresist layer by laser direct writing; 7. The method of claim 6, further comprising the steps of: placing the substrate in a developer solution to develop and developing into etched areas corresponding to the first underlying circuitry and the second underlying circuitry.

8. the first bottom layer circuit includes an impedance converter of the Josephson parametric amplifier; 8. The method of claim 7, wherein a compensation deviation exists between a line width in the layout of the impedance transformer and a design line width of the impedance transformer, and the compensation deviation is determined based on an etching deviation when performing an etching process on the third photoresist layer.

9. a Josephson junction sample array is included on the second bottom layer circuit, the Josephson junction sample array including at least two Josephson junction sample port circuits, each of the port circuits corresponding to a set of the photoresist structures; The step of determining oxidation conditions used to fabricate an oxide layer in a Josephson junction by fabricating a Josephson junction sample on the second chip product based on the photoresist structure covering the second bottom layer circuit includes: fabricating the Josephson junction sample corresponding to the first port circuit based on the photoresist structure covering the first port circuit under a first oxidation condition, the first port circuit being one port circuit of at least two Josephson junction samples in which the Josephson junction sample is not fabricated; 9. The method according to claim 1, further comprising: determining the first oxidation conditions as oxidation conditions for producing an oxide layer in the Josephson junction when a first resistance value satisfies a design requirement, the first resistance value being obtained by measuring the Josephson junction sample corresponding to the first port circuit based on the first port circuit.

10. The method comprises:

10. The method of claim 9, further comprising updating the first oxidation condition and the first port circuit and performing a test in a situation where the first resistance value does not meet the design requirement.

11. the photoresist structure is a Dolan bridge structure; The step of fabricating the Josephson junction sample corresponding to the first port circuit based on the photoresist structure covering the first port circuit under a first oxidation condition includes: obliquely evaporating a first superconducting layer of the Josephson junction sample corresponding to the first port circuit based on the photoresist structure covering the first port circuit; performing an oxidation treatment on the first superconducting layer according to the first oxidation conditions to obtain an oxide insulating layer on the surface of the first superconducting layer; and vertically evaporating a second superconducting layer of the Josephson junction sample corresponding to the first port circuit based on the photoresist structure covering the first port circuit, to obtain the Josephson junction sample corresponding to the first port circuit.

12. The first oxidation conditions are: The method of claim 11 , further comprising at least one of information on the oxygen gas flow rate, pressure, and oxidation time.

13. 1. A chip manufacturing system, the system including a coating machine, a photolithography machine, a deposition machine, an etching machine, an oxidation chamber, a cleaning machine, and a cutting machine; the coating machine, the photolithography machine, the deposition machine, the etching machine, and the cleaning machine are used to fabricate a first bottom layer circuit of an impedance Josephson parametric amplifier on a substrate, and fabricate a second bottom layer circuit of a Josephson junction used for testing on the substrate, thereby obtaining a first chip product; the coating machine and the photolithography machine are used to create photoresist structures used to fabricate the Josephson junctions on the first chip product; the cutting machine is used to separate the first bottom layer circuit and the second bottom layer circuit of the first chip product, and obtain a second chip product including the second bottom layer circuit after separation, and a third chip product including the first bottom layer circuit after separation; the deposition machine and the oxidation chamber are used to fabricate a Josephson junction sample on the second chip product based on the photoresist structure covering the second bottom layer circuit, thereby determining oxidation conditions used to fabricate an oxide layer in the Josephson junction; The deposition machine and the oxidation chamber are further used to fabricate the Josephson junction on the third chip product according to the oxidation conditions based on the photoresist structure covering the first bottom layer circuit, and fabricate the third chip product as a fourth chip product; The coating machine, the photolithography machine, the deposition machine, the etching machine, and the cleaning machine are further used to obtain a target chip product including the impedance Josephson parametric amplifier based on the fourth chip product.

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