Method for manufacturing a grid

Abstract

To provide a method for manufacturing a grid structure in a SiC semiconductor material.SOLUTION: A method for manufacturing a grid structure in a SiC semiconductor material includes steps of: a) providing a substrate including a doped semiconductor SiC material, the substrate including a first layer of a first conductivity type; b) by epitaxial growth, adding at least one doped semiconductor SiC material to form, on the first layer, separated second regions of a second conductivity type opposite to the first conductivity type; and c) by ion implantation, implanting ions in the first layer through the separated second regions to form first regions of the second conductivity type opposite to the first conductivity type, each of the separated second regions being in contact with one of the first regions.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a cost-effective method for fabricating improved grid structures by combining ion implantation and epitaxial growth. The grid may be a buried grid or a surface grid. [Background technology]

[0002] Buried doping structures or buried grids (BG) can be used to limit the electric field at the surface of the power semiconductor, thereby shielding sensitive areas such as Schottky contacts or MOS structures from the high electric fields in the drift layer. This is particularly important for devices based on wide-bandgap semiconductors such as SiC, where the electric field in the device drift layer can be up to 10 times greater than in silicon. Therefore, it is important to limit the electric field at the surface of the semiconductor or at the interface to other materials, such as gate oxides (SiO2), which can maintain a much lower critical electric field than the semiconductor.

[0003] According to the current state of the art, buried doping structures in SiC can be fabricated either by ion implantation or by epitaxial growth, for which etched grids or trench filled grids are known.

[0004] Ion-implanted backplane gates. The advantage is that selectively doped areas can be created by masking with oxide or photoresist masks. Doping can be controlled, as can uniformity across the wafer. This is a well-known doping technique. The disadvantage is that there is a limit to the doping level because implant damage increases as the implant dose increases. There is no diffusion of dopants in SiC, except for small atoms like boron, which results in the implanted pn-junction being located where the implant profile ends and implant damage is large. The implant energy limit imposes a thickness limit; a 1 μm thickness requires an implant energy of 400–1000 keV, depending on the ions implanted. High-energy implants are a costly process. Implanted p-grids have low emitter efficiency due to recombination at defect centers remaining from the implant damage, which limits the device's surge current capability by protecting the grid pn-diode against such high current levels.

[0005] Epitaxial BG-etched grid. A doped epilayer is grown and the grid is defined by etching and regrowth of the channel / drift layer. The advantage is that deeply doped structures are possible, and grid thickness is not an issue. Doping is damage-free even for high dopant concentrations. High doping concentrations close to the semiconductor-semimetal transition are possible. The disadvantage is that the sharp corners of the doped grid region result in field crowding, thus limiting the voltage blocking capability of the device.

[0006] Epitaxial BG - Trench-filled grid. A trench etch with rounded corners is performed, followed by trench filling with epitaxy, followed by subsequent planarization and epitaxial regrowth. Advantages include the possibility of deep doped structures. Grid thickness is not an issue. Damage-free doping is possible, even for high concentrations. High doping concentrations close to the semiconductor-semimetal transition are possible. Disadvantages include the complex process involving trench etch, two epitaxy regrowths, and planarization, which is a very costly process with submicron precision and uniformity. The regrowth in the trench requires a slow growth rate, making the process long and also costly.

[0007] U.S. Patent No. 5,705,406 discloses a method for fabricating semiconductor devices having a semiconductor layer of SiC by using ion implantation techniques. The patent teaches that ion implantation at elevated temperatures reduces implant damage and increases the ion implantation dose. It also discloses how to obtain a thicker BG using ion implantation. Repeated process cycles of thin layer epitaxial growth and ion implantation are disclosed.

[0008] U.S. Patent No. 6,897,133 discloses a method for fabricating Schottky diodes in silicon carbide. To avoid the sharp corners of the etched epitaxial backing, the epi-emitter is grown in a rounded trench-etched structure as opposed to the epitaxial backing-trench-filled grid described above. This is a difficult process requiring advanced etching and planarization to remove the doping outside the trench.

[0009] No. 8,633,560 discloses a semiconductor device. Problems with sharp corners are also known from trench grid manufacturing by combining trench etching with ion implantation, where rounded corners must be etched.

[0010] U.S. Patent Application No. 2014 / 169045 discloses a vertical bidirectional device in which current flows in a stacking direction of a semiconductor stack formed on a front surface of a substrate, the bidirectional device comprising: a first semiconductor element including a first channel formed on the semiconductor stack; and a second semiconductor element including a second channel provided in the semiconductor stack on a substrate side of the first semiconductor element. The first semiconductor element further comprises a first control electrode for controlling the first channel and formed on a surface of the semiconductor stack facing away from the substrate. The second semiconductor element includes a second control electrode formed on at least a portion of the surface of the semiconductor stack on which the first control electrode is formed and for controlling the second channel.

[0011] EP 2,075,847 discloses a SiC vertical MOSFET having a channel region and an n-type inverted electron guide formed via ion implantation in a lightly doped p-type deposited film, wherein second inversion layers are provided equidistant to the right and left of the inversion layer that becomes the electron guide in the device, and the inversion layers are formed via simultaneous ion implantation using the same mask, so that all of the channel regions in the device have a uniform length.

[0012] U.S. Patent Application Publication No. 2007 / 001194 discloses a semiconductor device having a pillar layer including first semiconductor pillars of a first conductivity type and second semiconductor pillars of a second conductivity type, which are laterally periodically alternated. The first and second semiconductor pillars are connected along the depth and include a plurality of diffusion layers formed in a third semiconductor layer. The diffusion layers have lateral widths that vary periodically along the depth. The average lateral width of the diffusion layers within a certain period is approximately equal to the average lateral width between different periods.

[0013] WO 98 / 32177 discloses a SiC Schottky diode having a substrate layer, a drift layer (2), and an emitter layer region (3) formed in the drift layer. A metal layer (4) makes an ohmic contact to the emitter layer region and a Schottky contact to the drift layer. Depletion of the drift layer region between two adjacent emitter layer regions allows the formation of a continuous depletion region (9) between the two adjacent p-type emitter layer regions in the blocking state of the diode. [Prior art documents] [Patent documents]

[0014] [Patent Document 1] U.S. Patent No. 5,705,406 [Patent Document 2] U.S. Patent No. 6,897,133 [Patent Document 3] U.S. Patent No. 8,633,560 [Patent Document 4] U.S. Patent Application No. 2014 / 169045 [Patent Document 5] EP2,075,847 [Patent Document 6] U.S. Patent Application No. 2007 / 001194 [Patent Document 7] WO98 / 32177 Summary of the Invention [Problem to be solved by the invention]

[0015] It is an object of the present invention to obviate at least some of the shortcomings in the prior art and to provide an improved grid and method for its manufacture. [Means for solving the problem]

[0016] After extensive research, it was discovered that advantages could be obtained in silicon carbide by combining ion implantation techniques with epitaxial growth.

[0017] In a first aspect, there is provided a method for the manufacture of a grid structure in a SiC semiconductor material, said method comprising: a) providing a substrate comprising a doped semiconducting SiC material, said substrate comprising a first layer n1; b) adding at least one doped semiconductor SiC material by epitaxial growth to form isolated second regions p2 on the first layer n1, with, if necessary, removing a portion of the added semiconductor material to form isolated second regions p2 on the first layer n1; c) implanting ions into the first layer n1 at least once in a stage selected from the group consisting of immediately after step a) and immediately after step b) by ion implantation to form first regions p1, wherein all of the second regions p2 are in contact with the first regions p1; Includes.

[0018] In a second aspect, there is provided a grid structure in a semiconductor material manufactured using a method as described above.

[0019] In a third aspect, there is provided a device manufactured using the method as described above, wherein the grid is then integrated into the device.

[0020] Further aspects and embodiments are defined in the appended claims, which are specifically incorporated herein by reference.

[0021] It is possible to fabricate a buried grid with an upper portion with rounded corners and a high doping level. The corners around the first implanted region p1 are rounded, which avoids field crowding and offers a number of advantages. Furthermore, the implanted portion of the device is lightly doped, which causes little damage. However, the highly doped portion is fabricated using epitaxial growth, which allows very high doping levels to be reached.

[0022] The second region p2 with high doping allows for an efficient low resistance ohmic contact.

[0023] The advantage is that it is possible to produce components with fast switching capabilities due to the low resistance of the doped grid.

[0024] One advantage is that very efficient blocking is obtained by avoiding field crowding at the corners of the grid, thus efficiently shielding the semiconductor surface from high electric fields, which can be used to lower the resistance or increase the operating temperature.

[0025] Another advantage is that during conduction, very efficient ejection of charge carriers from the doped grid into the first layer n1 is obtained, providing the ability to handle very high current levels and therefore improved and stable surge current capability.

[0026] Yet another advantage is that fabrication is simplified compared to the prior art, avoiding expensive processes such as high energy implants, separate high temperature annealing, and planarization with sub-micron precision.

[0027] Furthermore, with regard to the overall device process, edge termination can be formed simultaneously with the implanted p1 grid, avoiding additional costly fabrication steps.

[0028] The invention will now be described with reference to the following drawings. [Brief explanation of the drawings]

[0029] [Figure 1] 1 is a schematic cross-sectional view of a grid structure manufactured using a method according to the present invention; [Figure 2] 1 is another schematic cross-sectional view of an embedded grid structure fabricated using a method according to the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0030] Before the present invention is disclosed and described in detail, it is to be understood that this invention is not limited to the particular compounds, compositions, method steps, substrates, and materials disclosed herein, as such may vary somewhat. It is also to be understood that the terminology employed herein is used for the purpose of describing particular embodiments only, and is not intended to be limiting, as the scope of the present invention will be limited only by the appended claims and their equivalents.

[0031] It must be noted that as used in this specification and the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise.

[0032] Unless otherwise defined, all terms and scientific terms used herein have the meaning commonly understood by one of ordinary skill in the art to which this invention pertains.

[0033] As used throughout the specification and claims, "embedded grid" refers to a grid structure of material of one conductivity type in a material of the opposite conductivity type.

[0034] As used throughout the specification and claims, "conductivity type" refers to the type of conduction in a semiconductor material. n-type refers to electron conduction, meaning that excess electrons move through the semiconductor to provide electrical current flow, and p-type refers to hole conduction, meaning that excess holes move through the semiconductor to provide electrical current flow. n-type semiconductor materials are achieved by donor doping and p-type semiconductors by acceptor dopants. In SiC, nitrogen is commonly used as the donor dopant and aluminum as the acceptor dopant. When a material is a doped semiconductor such as SiC, the material has either conductivity type p or conductivity type n.

[0035] Those skilled in the art will recognize that for most semiconductor devices containing n-type and p-type doped materials, all doped materials can have their conductivity type swapped, with n becoming p and p becoming n. Thus, versions in which n is p-doped and p is n-doped are also encompassed.

[0036] "Doped" as used throughout the specification and claims means that an intrinsic semiconductor, such as SiC, has been doped with impurities to modify its electrical properties, making it an extrinsic semiconductor.

[0037] As used throughout the specification and claims, "epitaxial" indicates that the material is produced using epitaxial growth, in this case epitaxial growth of SiC.

[0038] "Substrate" as used throughout the specification and claims refers to a piece of material upon which a power device is constructed.

[0039] In a first aspect, there is provided a method for the manufacture of a grid structure in a SiC semiconductor material, said method comprising: a) providing a substrate comprising a doped semiconducting SiC material, said substrate comprising a first layer n1; b) adding at least one doped semiconductor SiC material by epitaxial growth to form isolated second regions p2 on the first layer n1, with, if necessary, removing a portion of the added semiconductor material to form isolated second regions p2 on the first layer n1; c) implanting ions into the first layer n1 at least once in a stage selected from the group consisting of immediately after step a) and immediately after step b) by ion implantation to form first regions p1, wherein all of the second regions p2 are in contact with the first regions p1; Includes.

[0040] The first layer n1, in one embodiment, is a lightly doped layer. There is a substrate that includes the first layer n1, and in one embodiment, the substrate includes one or more additional layers. Examples of additional layers include, but are not limited to, layers of opposite doping to the first layer n1.

[0041] The ion implantation to form the first region p1 may be performed before the second region p2 is formed on the first layer n1. However, the ions can also be implanted after the second region p2 is formed on the top surface of the first layer n1. In that case, the ions are implanted through the second region p2 to the first layer n1 below the second region p2 to form the first region p1.

[0042] In the above example, the result is a surface grid. The invention can also be used for the manufacture of a buried grid. In one example, the method further comprises, after step c), a step including epitaxial growth of a second layer n2 on the second region p2 and on the first layer n1. This will provide a buried grid.

[0043] There are several methods for manufacturing a grid according to the present invention. In one embodiment, the method further comprises, immediately after step a), a step comprising epitaxial growth of a second layer n2 on the first layer n1, followed by etching through the entire second layer n2 over certain areas, the latter step forming isolated second regions p2 on the bottom surface of the etched areas. This also gives the same type of structure with second regions p2 on top of first regions p1.

[0044] In one embodiment, the first layer n1 and the second layer n2 are n-doped, and the first region p1 and the second region p2 are p-doped.

[0045] The grid structure is fabricated from SiC.

[0046] When parts of the layer formed in step b) are removed, the layer is completely removed on selected areas so as to form islands constituting the second regions p2, thus isolating the second regions p2.

[0047] All of the second regions p2 are in contact with the first regions p1, i.e., all of the second regions p2 have a first region p1 below them, but not all of the first regions p1 necessarily have a second region p2 above them. In one embodiment, all of the second regions p2 are aligned with the first regions p1. This means that some or all of the first regions p1 have a second region p2 above them, and such second regions p2 are aligned above the first regions p1. Alignment means that the top surface of the first region p1, as viewed from above, coincides with the bottom surface of the second region p2, as viewed from below. Top is defined as the direction in which the second region p2 lies, and bottom is defined as the direction in which the first region p1 lies.

[0048] In one embodiment, a small portion of the first region p1 has the second region p2 thereon. In some applications, only a portion of the first region p1 has the second region p2 thereon. Thus, many first regions p1 do not have the second region p2 thereon, such that the second layer n2 is directly on top of the first region p1.

[0049] In an alternative embodiment, every first region p1 has a second region p2 above it.

[0050] In one embodiment, the contact area between the first region p1 and the second region p2 is such that the area of ​​the first region p1 and the area of ​​the second region p2 are matched and are of equal size and dimension. In an alternative embodiment, the surface of the second region p2 in contact with the first region p1 is slightly smaller than the area of ​​the first region p1 to ensure there are no corners in the heavily doped p2 that may create undesirably high electric fields.

[0051] In one embodiment, the epitaxial growth in step b) adds a layer having a thickness in the interval 0.1-3.0 μm, which layer thickness defines the thickness of the second region p2.

[0052] In one embodiment, the epitaxial growth in step b) utilizes Al as a dopant.

[0053] In one embodiment, the epitaxial growth of step b) is performed at intervals of 5e19 to 3e20 cm -3 At least one layer having a doping concentration of 0.1 to 0.5% is added.

[0054] In one embodiment, the at least one layer added in step b) has a doping gradient with a higher doping concentration furthest from the first region p1. The formed gradient of the second region p2 is advantageous when an ohmic contact is to be formed directly on the second region p2.

[0055] In one embodiment, removing the second region p2 in step b) is performed by dry etching.

[0056] In one embodiment, ion implantation is performed only before step b).

[0057] In one embodiment, the ion implantation in step c) is performed only before step b), and the epitaxial growth in step b) is performed simultaneously with the annealing of the implanted first regions p1, thereby performing the epitaxial growth and the annealing of the implanted first regions p1 in one step, which simplifies the fabrication process.

[0058] In one embodiment, ion implantation is performed at an energy of less than 350 keV. It should be remembered that high energy implantation is a costly process.

[0059] In one embodiment, the first region p1 has a thickness in the interval 0.2 to 2.0 μm. The thickness of the first region p1 is determined by the ion implantation process and also by a small extension followed by annealing.

[0060] In one embodiment, the first region p1 has an interval of 1e18 to 1e19 cm -3 The doping concentration is

[0061] In one embodiment, the first region p1 has a doping gradient with a higher doping concentration towards p2. Gradient doping, with the lowest doping level decreasing towards n1, has the advantage of avoiding high electric fields at the pn-junction p1-n1. A higher doping level towards p2 provides better emitter efficiency.

[0062] In one embodiment, B (boron) is used to dope the first region p1, where an ion implantation step is followed by a diffusion step. This will result in a device with a lower leakage current. In one embodiment, B is implanted at a higher energy than Al.

[0063] In one embodiment, at least one selected from the group consisting of Al and B is used for doping the first region p1.

[0064] In one embodiment, Al is used for doping the second region p2 and B is used for doping the first region p1.

[0065] In one embodiment, if step b) comprises epitaxial growth of the second layer n2, the epitaxial growth is carried out so that the thickness of the second layer n2 is in the interval 0.5-3 μm.

[0066] In one embodiment, a surface planarization step is performed after growing the second layer n2, in one embodiment, chemical-mechanical planarization (CMP) is used for planarization.

[0067] In one embodiment, an ohmic contact is made directly on at least one of the second regions p2, optionally with partial removal of the second layer n2 to expose p2 if necessary. A portion of the second layer n2 is removed above the region p2 where the ohmic contact is to be made. This will make p2 accessible for the creation of an ohmic contact directly on p2. In one embodiment, it is not necessary to remove a portion of the second layer n2 to expose p2; then, the ohmic contact can be made directly on p2 without removing a portion of the second layer n2.

[0068] In one embodiment, a Schottky contact is formed on at least a portion of the second layer (n2). For some embodiments, planarization may be required prior to deposition of the Schottky contact.

[0069] In one embodiment, the ratio of the thickness of p2 to the spacing between two second regions p2 is less than 1. The ratio of the thickness of p2 to the spacing between any two second regions p2 is less than 1 for all spaces between any two second regions p2. The thickness of p2 is defined as the thickness of the layer grown in step b) assuming that no material was removed from the top surface of the second region p2 during step c). The spacing is the distance between two second regions p2 measured at the n1-n2 interface. The spacing between two adjacent second regions p2 is the distance from one side of the second region p2 to the nearest side of the other second region p2. In many embodiments, the pattern of the second regions p2 is regular with equal spacing in all directions, making it easy to calculate the thickness-to-spacing ratio. For irregular patterns, the ratio can be calculated for each space, and then each ratio should be less than 1.

[0070] In one embodiment, edge termination of the device including the grid structure is integrated into fabrication step c) to simultaneously form the edge termination and the first region p1.

[0071] In a second aspect, a grid structure in a semiconductor material is provided, fabricated using the method described above. It is contemplated that there are a plurality of first regions p1 and second regions p2 with spaces between them that form the grid structure. In various embodiments, the first regions p1 and, optionally, the second regions p2 above form a pattern. One example is a hexagonal pattern when viewed from above. Other shapes are also encompassed.

[0072] In a third aspect, there is provided a device fabricated using the method as described above. The grid is then integrated into the device. One example of a device that can be made using the grid fabricated by this method is a MOSFET. Further examples of devices that can be made using the grid fabricated by this method include, but are not limited to, Schottky diodes, JFETs (Junction Field Effect Transistors), BJTs (bipolar junction transistors), and IGBTs (insulated-gate bipolar transistors).

[0073] A grid is a feature of a device that is fabricated with regularly spaced oppositely doped regions. The exact design is determined by the component or device in which the grid is used and its voltage, current, switching frequency, etc.

Claims

1. 1. A method for the manufacture of a grid structure in a SiC semiconductor material, said method comprising the steps of: (a) providing a substrate comprising a doped semiconducting SiC material, said substrate including a first layer of a first conductivity type; (b) applying by epitaxial growth at least one doped semiconducting SiC material to form an isolated second region on said first layer, said isolated second region having a doping concentration greater than 5×10 19 cm −3 and being of a second conductivity type opposite said first conductivity type; (c) implanting ions into the first layer through the isolated second regions to form first regions of a second conductivity type opposite to the first conductivity type by ion implantation, each of the isolated second regions being in contact with one of the first regions; A method comprising:

2. Forming the first region comprises: １８ cm －３ From 1 x 10 １９ cm －３ 2. The method of claim 1, further comprising the step of implanting the first region having a doping concentration in the interval.

3. 3. The method of claim 1, further comprising the step of: (d) growing a second layer of the first conductivity type over the isolated second region by epitaxial growth.

4. The method of claim 1 , further comprising forming an ohmic contact directly on at least one of the isolated second regions.

5. The method comprises: removing a portion of the second layer to expose at least one of the isolated second regions; 4. The method of claim 3, further comprising forming an ohmic contact directly on the exposed at least one isolated second region.

6. The method of claim 3 or 5, wherein the method further comprises forming a Schottky contact on at least a portion of the second layer.

7. 7. The method of claim 1, wherein step (c) comprises simultaneously forming the first region and an edge termination of a device having the grid structure.

8. 8. A grid structure in a semiconductor material produced by the method of any one of claims 1 to 7.

9. A device manufactured by the method of any one of claims 1 to 7.

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