Power semiconductor device and method of operation

Abstract

In at least one embodiment, the power semiconductor device (1) comprises: a source region (21); a channel region (22) in the semiconductor body (2); and a gate electrode (3) located in the channel region (22) and electrically insulated from the semiconductor body (2), wherein the channel region (22) is of a second conductivity type different from the first conductivity type; the channel region (22) comprises a first dopant having an activation energy of 0.15 eV or less; and the channel region (22) comprises a second dopant having an activation energy of 0.3 eV or more.

Description

[Technical Field]

[0001] A power semiconductor device is provided, as well as a method of operating such a power semiconductor device. [Background technology]

[0002] The paper H. Matsuura et al., ''Density and energy level of a deep-level Mg acceptor in 4H-SiC'', Japanese Journal of Applied Physics, January 2015, 54(1):011301, DOI:10.7567 / JJAP.54.011301, mentions doping of SiC with Mg.

[0003] The paper M. Noguchi et al., ''Channel engineering of 4H-SiC MOSFETs using sulfur as a deep level donor,'' 2018 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, 2018, pp. 8.3.1-8.3.4, DOI: 10.1109 / IEDM.2018.8614598, mentions doping SiC with sulfur to achieve higher threshold voltages in MOSFETs.

[0004] US Patent Application Publication No. 2016 / 0035836 mentions the use of various dopants. Summary of the Invention [Problem to be solved by the invention]

[0005] The problem to be solved is to provide a power semiconductor device with self-heating current protection. [Means for solving the problem]

[0006] This object is achieved, inter alia, by a power semiconductor device and an operating method as defined in the independent claims. Exemplary further developments form the subject matter of the dependent claims.

[0007] For example, a power semiconductor device, which may be a field effect transistor or an insulated gate bipolar transistor, uses a first dopant with a low activation energy and a second dopant with a high activation energy, such that the second dopant becomes relevant only well beyond the designed operating temperature range. If the second dopant becomes significantly activated at high temperatures, current choking occurs, achieving self-heating current protection.

[0008] In at least one embodiment, a power semiconductor device includes at least one source region and, optionally, a drain region of a first conductivity type or a collector layer of a second semiconductor type within a semiconductor body. Additionally, at least one channel region is present within the semiconductor body, e.g., electrically, but not necessarily geometrically, located between the at least one assigned source region and the drain region or collector layer. A gate electrode is located in the at least one channel region and is electrically insulated from the semiconductor body. The at least one channel region is of a second conductivity type different from the first conductivity type. The at least one channel region includes a first dopant having an activation energy of 0.15 eV or less and a second dopant having an activation energy of 0.3 eV or more.

[0009] According to at least one embodiment, the channel region being electrically located between the assigned source region and the drain region or collector layer can mean that in intended use of the power semiconductor device, current can flow from the respective source region to the drain region or collector layer only through the assigned channel region.

[0010] If the power semiconductor device is a field effect transistor, the channel region may be in direct contact with the respective source and / or drain regions, or the channel region may be separated from the source and / or drain regions by at least one other intermediate further region of the semiconductor body, such as a drift region, which may be of the first conductivity type.

[0011] If the power semiconductor device is an insulated gate bipolar transistor, the channel region may be in direct contact with the collector layer of the second conductivity type, or the channel region may be separated from the source region and / or the collector layer by at least one other intermediate further region of the semiconductor body, such as a drift region. The source region may also be called the emitter region, for example, if the power semiconductor device is an insulated gate bipolar transistor. However, due to their similar functions, the terms "source region" and "emitter region" are used synonymously herein.

[0012] There can be more than one source region, for example, at least one source region on each of the long sides of the gate electrode when viewed from the top view of the gate electrode, and there can be one drain region or one collector layer allocated for every source region.

[0013] A gate electrode may be applied over and / or within the semiconductor body. Between the gate electrode and the semiconductor is an electrically insulating material, such as a gate oxide. By electrically addressing the gate electrode, the flow of current through the channel region can be controlled in the intended use of the power semiconductor device.

[0014] There can be only one first dopant, or there can be multiple first dopants. Additionally, there can be only one second dopant, or there can be multiple second dopants. Optionally, additional dopants can be present, but only at least one first dopant and at least one second dopant can be present.

[0015] Thus, the power semiconductor devices described herein may relate to SiC short circuit protection based on at least one temperature activated second dopant.

[0016] Thus, the idea used in the power semiconductor device of the present invention is to introduce a current limiting layer into the channel region of, for example, a SiC MOSFET that automatically protects the device from short circuits or severe overcurrent or overload conditions, for example when driving a motor or an inductive load. This can be achieved by at least one of the following actions:

[0017] - Increasing the threshold voltage at very high temperatures well above the design operating range, and / or - Increasing the resistivity of, for example, a JFET region of a power semiconductor device at extremely high temperatures well above the normal operating temperature range.

[0018] The current limiting layer is realized by, for example, a p-type secondary dopant located at a deeper energy level in the bandgap compared to the primary dopants Al or B in SiC, which are mostly ionized at room temperature. Because these deep levels acting as p-type dopants do not ionize at low operating temperatures, under normal operating conditions, the contribution of such a current limiting layer is modest and does not reduce the mobility in the channel or accumulation regions of the device.

[0019] However, as the temperature increases, the additional second p-type dopant becomes activated, increasing the effective doping of the channel region and thus resulting in at least one of the following:

[0020] -When implanted below the channel region, they limit the current by increasing the threshold voltage.

[0021] - For example, creating a p-type dopant region that chokes current flow in a JFET region.

[0022] The power semiconductor devices described herein may be, or may be included in, MOS-based SiC trench or planar devices, such as MOSFETs and IGBTs. Thus, the power semiconductor devices may be, or may be present within, devices selected from the group including or consisting of metal-oxide-semiconductor field-effect transistors (MOSFETs), metal-insulator-semiconductor field-effect transistors (MISFETs), insulated-gate bipolar transistors (IGBTs), bipolar junction transistors (BJTs), and junction-gate field-effect transistors (JFETs). Furthermore, the power semiconductor devices described herein may be part of a thyristor, such as a gate-turn-off thyristor (GTO) or a gate-commutated thyristor (GCT).

[0023] Thus, it is proposed to implement the current limiting layer with a p+ type first dopant that ionizes at room temperature and a deeper p type second dopant within the bandgap of SiC that ionizes only at elevated temperatures. The deep p type second dopant can be located either near the doped well or in the JFET region in a planar MOSFET, but implementation as a trench device is also possible.

[0024] The following focuses on deep p-type second dopants, but generalization to deep n-type second dopants for n-channel region devices is also possible. The first and / or second dopants may be implanted or grown as part of the epitaxial layer.

[0025] According to at least one embodiment, the semiconductor body is made of a silicon-based semiconductor material such as SiC or Si, or the semiconductor body is made of a compound semiconductor material, for example a III-V compound semiconductor material such as GaN. The semiconductor body may be a substrate that is partially or completely doped, for example, by ion implantation or heat treatment. Furthermore, the semiconductor body may be partially or completely an epitaxially grown layer or sequence of layers that are doped during growth or doped afterward, for example, by ion implantation or heat treatment. The semiconductor body may be made of a single semiconductor material, although semiconductor bodies comprising multiple semiconductor materials are also possible.

[0026] According to at least one embodiment, the first dopant is at least one of B, Al, Ga. This may be the case for a semiconductor body made of SiC.

[0027] If the semiconductor body is made of Si, the first dopant may again be at least one of B, Al, and Ga. If the semiconductor body is made of GaN, the first dopant may be Si or Ge.

[0028] According to at least one embodiment, the second dopant is selected from the following group: Be, Cd, In, Mg, Zn. This may be the case for a semiconductor body made of SiC.

[0029] If the semiconductor body is made of Si, the second dopant may be at least one of Co, Mn, S, Tl, and Zn. If the semiconductor body is made of GaN, the first dopant may be Mg.

[0030] According to at least one embodiment, the first dopant is Al and the second dopant is Mg. This may be the case for a semiconductor body made of SiC.

[0031] According to at least one embodiment, the first conductivity type is n and the second conductivity type is p. However, it is also possible for the first conductivity type to be p and the second conductivity type to be n. The following will mainly discuss the first-mentioned case, i.e., the first conductivity type is n and the second conductivity type is p, but the information presented applies equally to the second-mentioned case, i.e., the first conductivity type is p and the second conductivity type is n.

[0032] According to at least one embodiment, the power semiconductor device is configured for an operating temperature of at least 200 K, or at least 250 K, and / or up to 550 K, or up to 450 K, or up to 380 K. Thus, the intended operating temperature range may be from 250 K to 450 K or from 250 K to 380 K.

[0033] According to at least one embodiment, the activation level of the second dopant is at most 10 -5 or up to 10 -4 or up to 10 -2 Thus, in the intended operating temperature range, the power semiconductor device is designed such that the second dopant is essentially inactive and therefore has no or only a small effect on the operating characteristics. For example, in the operating temperature range, the activation level of the first dopant exceeds the activation level of the second dopant by at least a factor of 10, or by at least a factor of 50, or by at least a factor of 100, or by at least a factor of 10. 3 The activation level may be the percentage of each dopant that is activated and / or ionized.

[0034] According to at least one embodiment, the maximum doping concentration of the second dopant in the channel region is at least 10 15 cm -3 or at least 10 16 cm -3 or at least 1×10 17 cm -3or at least 5×10 17 cm -3 Alternatively or additionally, the maximum doping concentration of the second dopant in the channel region is up to 5×10 19 cm -3 or up to 1×10 19 cm -3 or up to 10 18 cm -3 or up to 5×10 17 cm -3 For example, the maximum doping concentration of the second dopant in the channel region is 5×10 16 cm -3 5x10 or more 18 cm -3 or less or 1×10 17 cm -3 More than 1×10 18 cm -3 The following is the result.

[0035] According to at least one embodiment, the doping concentration of the first dopant in the channel region exceeds the doping concentration of the second dopant in the channel region by, for example, at least a factor of 1.2, or at least a factor of 1.5, or at least a factor of 1.8. Alternatively, or in addition, the doping concentration of the first dopant in the channel region exceeds the doping concentration of the second dopant by at most a factor of 5, or at most a factor of 3, or at most a factor of 2. This may be true for part or all of the channel region.

[0036] Alternatively, the maximum doping concentration of the first dopant in the channel region is less than the doping concentration of the second dopant in the channel region, for example, by at least a factor of 1.2, or at least a factor of 1.5, or at least a factor of 3. Alternatively, or in addition, the maximum doping concentration of the first dopant in the channel region is less than the doping concentration of the second dopant by at most a factor of 10, or at most a factor of 5, or at most a factor of 3.

[0037] In other words, the first dopant and the second dopant can have similar doping concentrations.

[0038] According to at least one embodiment, the first dopant and the second dopant have different doping profiles. This typically applies, for example, to the depth profile of the dopants along the growth direction of the semiconductor body and / or along a perpendicular to the gate electrode. For example, the average implantation depth of the first dopant, such as Al, is greater than the average implantation depth of the second dopant, such as Mg. Optionally, the average implantation depth of the first dopant exceeds the average implantation depth of the second dopant by at least a factor of 1.2 or at least a factor of 1.5, and / or by at most a factor of 5 or at most a factor of 2.

[0039] When viewed from a top view of the gate electrode, the first dopant and the second dopant can have the same or nearly the same distribution, e.g., the first dopant and the second dopant are applied using the same doping mask.

[0040] According to at least one embodiment, the entire channel region is doped with the second dopant. This may be true for the gate electrode and, therefore, the top view of the power semiconductor device. Thus, when viewed from the top view, there may be a continuous path of the second dopant extending from the source region to the drain region or collector layer or drift region.

[0041] In at least one embodiment, the channel region is only partially doped with the second dopant. This may be true of the gate electrode and thus the power semiconductor device from a top view. Therefore, when viewed from a top view, there is no continuous path of the second dopant from the source region to the drain region, collector layer, or drift region.

[0042] According to at least one embodiment, a central portion of the gate electrode and / or channel region as viewed in a top view of the gate electrode does not include the second dopant. Thus, for example, the second dopant is limited to one or more edge regions of the channel region as viewed in a top view of the gate electrode. At least one edge region may be directly adjacent to at least one source region.

[0043] In this context, dopant-free means that the concentration of each dopant is at most 1×10 14 cm -3 or up to 1×10 15 cm -3 It can mean that.

[0044] According to at least one embodiment, the second dopant is implanted into the channel region to a depth of at least 0.1 μm or at least 0.2 μm. Alternatively, or in addition, the second dopant is implanted into the channel region to a depth of up to 2 μm or up to 1 μm. Thus, the second dopant may be doped with a relatively shallow profile.

[0045] According to at least one embodiment, the power semiconductor device is planar. Thus, for example, the gate electrode is applied only on top of the semiconductor body without penetrating into the semiconductor body. In this case, the semiconductor body can have a flat top surface on which all electrodes can be applied.

[0046] According to at least one embodiment, the power semiconductor device is trench-type. Thus, for example, the gate electrode extends into the semiconductor body. For example, the semiconductor body can have a recess, which can be created by dry etching and is filled completely or partially with the gate electrode material and the gate insulating material. For example, the recess can terminate in the drift region. Alternatively, or in addition, the recess can extend away from the top surface and completely through the source region and / or well region. If the power semiconductor device is an insulated gate bipolar transistor, the recess can terminate away from the collector layer.

[0047] If the power semiconductor device is a field effect transistor, the drain and source regions may be on either side of the gate electrode on the top surface of the semiconductor body, for example, on two long sides of the gate electrode when viewed in top view of the gate electrode, in which case current flows essentially only from the source region to the drain region in a direction perpendicular to the growth direction of the semiconductor body, such that the field effect transistor has a lateral configuration.

[0048] Alternatively, at least one source and drain region may be located on opposite sides of the semiconductor body, in which case current essentially flows from the source region underneath the gate electrode in a direction perpendicular to the growth direction of the semiconductor body, and then flows parallel to the growth direction to the drain region.

[0049] According to at least one embodiment, the power semiconductor device is a power device. For example, the power semiconductor device is configured to have a maximum current through the channel region of at least 10 A or at least 50 A. Optionally, the maximum current is up to 500 A. Alternatively, or additionally, the power semiconductor device is configured to have a maximum voltage of at least 0.65 kV or at least 1.2 kV. Optionally, the maximum voltage may be up to 6.5 kV.

[0050] According to at least one embodiment, the shortest distance between the source region and the drain region or collector layer is at least 0.5 μm or at least 1.0 μm. Alternatively or additionally, the distance is at most 0.1 mm, at most 20 μm, or at most 10 μm. Thus, the distance between the source region and the drain region or collector layer is relatively large. Depending on the type of transistor design used, the distance may be measured along the growth direction of the semiconductor body or, in the case of a field-effect transistor, in a direction parallel to the top surface of the semiconductor body.

[0051] According to at least one embodiment, the length of the longer side of the gate electrode and / or channel region is at least 1 μm or at least 10 μm when viewed in a top view on the top surface and / or when viewed in a direction perpendicular to the main current flow direction near the source region, or alternatively or additionally, the length is at most 2 mm or at most 0.8 mm.

[0052] The power semiconductor device is for a vehicle power module that converts direct current from a battery into alternating current for an electric motor, for example in a hybrid or plug-in electric vehicle.

[0053] There is also provided a method for operating a power semiconductor device, whereby the power semiconductor device operates as described in relation to at least one of the above-described embodiments, and therefore features of the power semiconductor device are also disclosed for the method and vice versa.

[0054] In at least one embodiment, the method is for a power semiconductor device, wherein at room temperature, the first dopant is activated but the second dopant is not activated.

[0055] In accordance with at least one embodiment of the method, the second dopant acts as a component that provides self-heating current protection, i.e., self-limiting current. Otherwise, in the absence of the second dopant, an increase in current would also increase the temperature, making the semiconductor body more conductive and increasing the current, and so on.

[0056] By including the second dopant, the threshold voltage at the gate at which the power semiconductor device becomes conductive increases with increasing temperature, thereby avoiding or reducing the aforementioned effect. That is, above an operating temperature limit, the second dopant is activated, so that above the operating temperature limit, the effective doping concentration increases and therefore the threshold voltage of the power semiconductor device also increases, so that the current through the channel region decreases with increasing temperature. The operating temperature limit is, for example, the upper limit of the operating temperature range.

[0057] The power semiconductor devices and methods described herein will be described in further detail below by way of exemplary embodiments with reference to the drawings. Elements that are the same in the various figures are designated by the same reference numerals. However, the relationships between the elements are not shown to scale, and rather, individual elements may be exaggerated to aid understanding. [Brief explanation of the drawings]

[0058] [Figure 1] 1 is a schematic cross-sectional view of an exemplary embodiment of a power semiconductor device described herein. [Figure 2] 1 is a schematic cross-sectional view of an exemplary embodiment of a power semiconductor device described herein. [Figure 3] 1 is a schematic cross-sectional view of an exemplary embodiment of a power semiconductor device described herein. [Figure 4] 1 is a schematic cross-sectional view of an exemplary embodiment of a power semiconductor device described herein. [Figure 5] FIG. 2 is a schematic illustration of temperature distribution in an exemplary embodiment of a power semiconductor device described herein in cross section. [Figure 6] FIG. 2 is a schematic diagram of bandgaps for various dopants in exemplary embodiments of power semiconductor devices described herein. [Figure 7] FIG. 2 is a schematic diagram of the temperature behavior of an exemplary embodiment of a power semiconductor device described herein. [Figure 8] FIG. 2 is a schematic diagram of the temperature behavior of an exemplary embodiment of a power semiconductor device described herein. [Figure 9] 1 is a schematic top view of an exemplary embodiment of a power semiconductor device described herein; [Figure 10] 1 is a schematic cross-sectional view of an exemplary embodiment of a power semiconductor device described herein. [Figure 11] FIG. 1 is a schematic cross-sectional view showing effective dopant concentrations. [Figure 12] FIG. 1 is a schematic cross-sectional view showing effective dopant concentrations. [Figure 13] FIG. 1 is a schematic cross-sectional view showing effective dopant concentrations. [Figure 14] 1 is a schematic cross-sectional view of an exemplary embodiment of a power semiconductor device described herein. DETAILED DESCRIPTION OF THE INVENTION

[0059] 1 shows an exemplary embodiment of a power semiconductor device 1 configured as a field effect transistor. The power semiconductor device 1 comprises a semiconductor body 2 having a substrate 24 and an epitaxially grown portion 25. In contrast to the semiconductor body shown in this exemplary embodiment, the semiconductor body 2 may in each case consist of either the substrate 24 or the epitaxially grown portion 25, or the epitaxially grown portion 25 may be present on each major surface of the substrate 24.

[0060] Two source regions 21 are present in the semiconductor body 24, for example in the epitaxially grown portion 25. Furthermore, a drain region 23 is present in the semiconductor body 24, for example in the substrate 24.

[0061] Along the growth direction G of the semiconductor body 2, i.e., the growth direction of the epitaxially grown portion 25, there is a drift region 27 between the source region 21 and the drain region 23. Furthermore, each source region 21 is embedded in a well region 26.

[0062] Electrically, a channel region 22 exists between each source region 21 and drain region 23. A current I therefore flows from the source region 21 through the channel region 22 to the drain region 23. The main current flow direction is therefore firstly parallel to the top surface 20 of the semiconductor body 2 in the channel region 22, and secondly parallel to the growth direction G towards the drain region 23 through the drift region 27. The drift region 27 may reach the insulating material 31. This configuration may also be referred to as a vertical configuration.

[0063] On top surface 20 is a gate electrode 3 partially buried in an insulating material 31, such as a gate oxide. To simplify the drawing, external electrical connections to gate electrode 3, source region 21, and drain region 23 are not shown.

[0064] Optionally, the channel regions 22 for the source regions 21 are not connected to each other, so that there is no channel region in the central region below the gate electrode 3 .

[0065] Near the source region 21, which may protrude past the gate electrode 3, there is a first region A doped with a first dopant. Additionally, there is a second region B doped with a second dopant. Regions A and B may be substantially identical, at least when viewed in top view of the top surface 20. For example, regions A and B may be created by ion implantation, and the first and second dopants may be implanted using the same mask.

[0066] Regions A and B may be immediately adjacent to source region 21, but are separated from drain region 23 by drift region 27. In other words, channel region 22 is defined by source region 21 and drift region 27. Thus, channel region 22 and first region A may be congruent or identical.

[0067] The first dopant is activated at room temperature, i.e., at 300 K, while the second dopant has a higher activation energy such that it is activated only well above the set operating temperature range of the power semiconductor device 1. Thus, the second dopant can increase the gate voltage V at which the power semiconductor device 1 becomes conductive as the temperature rises, thus realizing self-heating current protection.

[0068] For example, the semiconductor body 2 consists of SiC or is based on SiC, the first dopant is Al and the second dopant is Mg.

[0069] Below are described exemplary geometric and doping features that may be applied to all exemplary embodiments individually, all together, or in any combination.

[0070] the maximum doping concentration of the second dopant in the channel region 22 and / or in the second region B is at least 1×10 16 cm -3 and / or up to 1 x 10 18 cm -3 is.

[0071] the maximum doping concentration of the first dopant in the channel region 22 and / or in the first region A is at least 1×10 16 cm -3 and / or up to 1 x 10 18 cm -3 is.

[0072] The first dopant may be Al, so that the channel region 22 is p-doped. The well region 26 is therefore also p-doped, and the source region 21, the drift region 27, and the drain region 23 are n-doped. Of course, the opposite doping scheme can alternatively be used.

[0073] The maximum doping concentration of the drift region 27 is at least 1×10 15 cm -3 and / or up to 1 x 10 17 cm -3 The maximum doping concentration of well region 26 may be at least 5×10 17 cm -3 and / or up to 5x10 19 cm -3 The maximum doping concentration of the drain region 23 may be at least 1×10 20 cm -3 and / or up to 1 x 10 22 cm -3 As n-type dopants, P, N, and / or As can be used.

[0074] The distance D between the source region 21 and the drain region 23 along the growth direction G may be at least 5 μm or at least 10 μm and / or at most 0.2 mm or at most 60 μm. Alternatively or additionally, the thickness of the well region 26 may be at least 0.2 μm and / or at most 1 μm.

[0075] The width W of the gate electrode 3 may be at least 1 μm and / or at most 10 μm or at most 3 μm. Alternatively or additionally, the thickness of the insulating material 31 between the gate electrode 3 and the semiconductor body 2 may be at least 40 nm and / or at most 0.2 μm.

[0076] In contrast to what is shown in FIG. 1, the drain region 23 does not necessarily have to be located at the bottom surface 29 of the semiconductor body 2, but may also be located within the semiconductor body 2, for example at the interface between the substrate 24 and the epitaxially grown portion 25.

[0077] In the exemplary embodiment of Fig. 14, the power semiconductor device 1 is an insulated gate bipolar transistor (IGBT for short). The semiconductor body 2 therefore comprises a collector layer 28, for example on the side of the substrate 24 remote from the gate electrode 3. The collector layer 28 is of the same conductivity type as the well region 26. The collector layer 28 is part of the substrate 24 and is doped, for example by ion implantation, or the collector layer 28 is a further region epitaxially grown on the substrate 24. In the embodiment of Fig. 14, the substrate 24 can also be considered as a drift region.

[0078] On the side of the collector layer 28 remote from the substrate 24 there is a collector electrode 51. The collector electrode 51 is a metallization applied to the semiconductor body 2, for example a metallization applied directly on the collector layer 28. For example, there is one common collector layer 28 and one common collector electrode 51 for all source regions 21. Optionally, there is a common metal source electrode 41 for the two source regions 21 shown in Figure 14, and such a source electrode 41 may also be present in all other exemplary embodiments.

[0079] For example, the collector layer 28 has a concentration of at least 1×10 17 cm -3 or at least 1×10 18 cm -3 , and / or up to 1×10 21 cm -3 At a maximum doping concentration of p + 14 includes an npnp semiconductor layer arrangement including, for example, a source region 21, a well region 26, a drift region 27 and a substrate 24, and a collector layer 28.

[0080] Otherwise, the same applies to Figure 14 as to Figure 1. 2 is in the form of a laterally configured field effect transistor, so that both the source region 21 and the drain region 23 can be located on the top surface 20, and so the bottom surface 29 can be free of electrodes.

[0081] Thus, channel region 22 extends directly from source region 21 to drain region 23, and no drift region needs to be included. Current I flows essentially parallel to top surface 20. Channel region 22 can be fully supplied with the second dopant such that first region A and second region B extend fully to the region below gate electrode 3.

[0082] 2, the second region B may be limited to only a part of the channel region 22, for example to an edge region located directly at the source region 21 similar to that of FIG. 1. The extent of the edge region may be, for example, at least 20% and / or at most 40% of the width of the gate electrode 3.

[0083] Otherwise, the same applies to Figure 2 as to Figure 1. 3, the gate electrode 3 is partially located in a trench in the semiconductor body 2. The channel region 22 may therefore extend parallel to the growth direction G from the source region 21 to the drain region 23. Note that no distinction is made between the terms "parallel" and "anti-parallel". For example, the trench, and therefore the gate electrode 3, may extend deeper into the semiconductor body 2 than the source region 21 and further into the semiconductor body 2 than the well region 26 and / or the second region B with the second dopant.

[0084] Thus, parallel to growth direction G, channel region 22 lies directly between source region 21 and drift region 27. Parallel to top surface 20, well region 26 and channel region 22, and thus first region A and second region B, may be directly adjacent to each other or may be spaced apart from each other. Regions A, B and well region 26 may have different depths or may have the same depth.

[0085] At least one source electrode 41 may be present on the top surface 20 . According to the diagram of Fig. 3, the power semiconductor device 1 is a vertically configured field effect transistor. However, in addition to what is shown in Fig. 3, the power semiconductor device 1 may also comprise a collector layer, and thus may be an IGBT as shown in Fig. 14.

[0086] Otherwise, the same applies to Figure 3 as to Figures 1, 14, and 2. 4, the first region A having the first dopant and the second region B having the second dopant are different from each other and may optionally not overlap at all. For example, the second region B is located below a central region of the gate electrode 3. A drift region 27 may extend between the first region A located directly at the source region 21 and the central second region B.

[0087] Thus, the channel region 22 may reach the second region B but may not pass completely through this second region B.

[0088] In the exemplary embodiment of FIG. 4, the vertical configuration of FIG. 1 is used, but the same applies to the configurations of FIGS.

[0089] Otherwise, the same contents as in FIGS. 1 to 3 and 14 also apply to FIG. 5 shows a typical temperature profile of an exemplary embodiment of the power semiconductor device 1. It can be seen that a relatively high lattice temperature TL can be reached below the gate electrode 3. Therefore, damage due to excessively high currents and therefore excessively high temperatures can occur, which can be prevented by using the second dopant.

[0090] In Figure 6, the band gaps E of several dopants are shown, with acceptors represented by circles and donors represented by diamonds. Thus, suitable "deep" second dopants for SiC with high activation energies may be, for example, In, Be, Mg, Zn, and / or Cd as p-type dopants. O, S, Se, and / or Te may be used as n-type dopants for the second dopant.

[0091] All dopants may be implanted or may be grown as part of the semiconductor body 2, for example as part of the epitaxially grown portion 25.

[0092] 7 and 8 show the transfer characteristics on a linear and logarithmic scale for the structure shown in Fig. 1. It can be seen that in the exemplary power semiconductor device 1 at 300K, the second dopant, in this case Mg, does not significantly affect the transfer characteristics since the second dopant is not substantially activated at this temperature.

[0093] However, at 600 K, which is well above the intended operating temperature range of the power semiconductor device 1, the activation of the second dopant causes the gate voltage V, at which a significant current density JD occurs, to be approximately 4 V higher than in the power semiconductor device 9 in which the second dopant is not present. Thus, at a nominal operating voltage of approximately 8 V, self-heating current protection can be achieved due to the second dopant.

[0094] In the top view of an exemplary embodiment of the power semiconductor device 1 as shown in FIG. 9, it can be seen that the gate electrode 3 may have a relatively small width W, for example 1.5 μm, while the length L of the long side may be significantly larger, for example 0.01 mm or more and 1 μm or less.

[0095] Otherwise, the same contents as those in FIGS. 1 to 8 and 14 also apply to FIG. In FIG. 10, the second dopant, and therefore second region B, is shown near the top surface 20, while the first dopant in first region A has a greater average doping depth such that first region A extends farther from the top surface 20 than second region B.

[0096] The same can be applied to all other exemplary embodiments. Otherwise, the same applies to Figure 10 as to Figures 1-9 and vice versa.

[0097] Figures 11-13 show the effective dopant concentrations. The darker the color of each region shown in Figures 11-13, the higher the effective doping concentration, i.e., the concentration of ions contributed by at least one dopant at each temperature. In this regard, Figure 11 relates to a temperature of 300 K, and Figures 12 and 13 relate to a temperature of 600 K. Figures 11-13 all relate to the basic configuration of Figure 1, with the presence of a second dopant in Figures 11 and 12 and the absence of a second dopant in Figure 13.

[0098] According to Figure 11, there is a relatively moderate effective doping concentration next to the source region 21 at 300 K due to Al as the first dopant, and Mg for the second dopant is not activated at this temperature. As can be seen from Figure 12, the effective doping concentration at 600 K is significantly higher compared to Figure 11 because both the first and second dopants are activated.

[0099] In contrast, referring to FIG. 13, when only the first dopant, i.e., only Al, is used to dope the channel region, the effective doping concentration at 600 K next to the source region 21 is much lower than in the case shown in FIG. 12.

[0100] The invention described herein is not limited by the description provided with respect to the exemplary embodiments, but rather the invention encompasses any novel feature and any combination of features, particularly any combination of features in the claims, even if that feature or combination itself is not explicitly set forth in the claims or exemplary embodiments. [Explanation of symbols]

[0101] List of Reference Numbers 1. Power semiconductor devices 2. Semiconductor body 20 Top side 21 Source Region 22 Channel Region 23 Drain region 24 PCB 25 Epitaxial growth area 26 well area 27 Drift Region 28 Collector layer 29 Bottom 3. Gate electrode 31 Electrical insulating materials 41 Source electrode 51 Collector electrode 9. Power semiconductor device without second dopant A: a first region having a first dopant B. A second region having a second dopant. D: Distance between source and drain regions EB band gap G growth direction I Current flow JD current density L gate length TL lattice temperature VG Gate voltage W gate width

Claims

1. A power semiconductor device (1), a source region (21) of a first conductivity type in the semiconductor body (2); a channel region (22) in said semiconductor body (2); a gate electrode (3) in said channel region (22) and electrically insulated from said semiconductor body (2); Equipped with - said channel region (22) is of a second conductivity type different from said first conductivity type; - said channel region (22) comprises a first dopant having an activation energy of at most 0.15 eV, said first dopant being of said second conductivity type; - said channel region (22) comprises a second dopant having an activation energy of at least 0.3 eV, said second dopant also being of said second conductivity type; The power semiconductor device (1) has an activation level of the second dopant of at most 10 for an operating temperature range of at least 200K to a maximum of 500K. －３ It is configured to be A power semiconductor device (1), wherein the maximum doping concentration of said second dopant in said channel region (22) is at least 10 16 cm −3 and at most 10 18 cm −3 .

2. A power semiconductor device (1), a source region (21) of a first conductivity type in the semiconductor body (2); a channel region (22) in said semiconductor body (2); a gate electrode (3) in said channel region (22) and electrically insulated from said semiconductor body (2); Equipped with - said channel region (22) is of a second conductivity type different from said first conductivity type; - said channel region (22) comprises a first dopant having an activation energy of at most 0.15 eV, said first dopant being of said second conductivity type; - said channel region (22) comprises a second dopant having an activation energy of at least 0.3 eV, said second dopant also being of said second conductivity type; The power semiconductor device (1) is configured for an operating temperature range of at least 200K up to 500K such that the activation level of the second dopant is at most 10 −3 in the operating temperature range; A power semiconductor device (1), wherein the doping concentration of the first dopant in the channel region (22) exceeds, at least locally, the doping concentration of the second dopant in the channel region (22) by at least a factor of 1.

5.

3. A power semiconductor device (1), a source region (21) of a first conductivity type in the semiconductor body (2); a channel region (22) in said semiconductor body (2); a gate electrode (3) in said channel region (22) and electrically insulated from said semiconductor body (2); Equipped with - said channel region (22) is of a second conductivity type different from said first conductivity type; - said channel region (22) comprises a first dopant having an activation energy of at most 0.15 eV, said first dopant being of said second conductivity type; - said channel region (22) comprises a second dopant having an activation energy of at least 0.3 eV, said second dopant also being of said second conductivity type; The power semiconductor device (1) is configured for an operating temperature range of at least 200K up to 500K such that the activation level of the second dopant is at most 10 −3 in the operating temperature range; The first dopant and the second dopant have different doping profiles.

4. A power semiconductor device (1), a source region (21) of a first conductivity type in the semiconductor body (2); a channel region (22) in said semiconductor body (2); a gate electrode (3) in said channel region (22) and electrically insulated from said semiconductor body (2); Equipped with - said channel region (22) is of a second conductivity type different from said first conductivity type; - said channel region (22) comprises a first dopant having an activation energy of at most 0.15 eV, said first dopant being of said second conductivity type; - said channel region (22) comprises a second dopant having an activation energy of at least 0.3 eV, said second dopant also being of said second conductivity type; The power semiconductor device (1) is configured for an operating temperature range of at least 200K up to 500K such that the activation level of the second dopant is at most 10 −3 in the operating temperature range; A power semiconductor device (1), wherein the entire channel region (22) is doped with the second dopant.

5. A power semiconductor device (1), a source region (21) of a first conductivity type in the semiconductor body (2); a channel region (22) in said semiconductor body (2); a gate electrode (3) in said channel region (22) and electrically insulated from said semiconductor body (2); Equipped with - said channel region (22) is of a second conductivity type different from said first conductivity type; - said channel region (22) comprises a first dopant having an activation energy of at most 0.15 eV, said first dopant being of said second conductivity type; - said channel region (22) comprises a second dopant having an activation energy of at least 0.3 eV, said second dopant also being of said second conductivity type; The power semiconductor device (1) is configured for an operating temperature range of at least 200K up to 500K such that the activation level of the second dopant is at most 10 −3 in the operating temperature range; 1. A power semiconductor device (1), wherein the channel region (22) is only partially doped with the second dopant such that a central portion of the semiconductor body (2) below the gate electrode (3) does not have the second dopant when viewed in a top view of the gate electrode (3).

6. A power semiconductor device (1), a source region (21) of a first conductivity type in the semiconductor body (2); a channel region (22) in said semiconductor body (2); a gate electrode (3) in said channel region (22) and electrically insulated from said semiconductor body (2); Equipped with - said channel region (22) is of a second conductivity type different from said first conductivity type; - said channel region (22) comprises a first dopant having an activation energy of at most 0.15 eV, said first dopant being of said second conductivity type; - said channel region (22) comprises a second dopant having an activation energy of at least 0.3 eV, said second dopant also being of said second conductivity type; The power semiconductor device (1) is configured for an operating temperature range of at least 200K up to 500K such that the activation level of the second dopant is at most 10 −3 in the operating temperature range; The power semiconductor device (1), wherein the second dopant is applied to the channel region (22) to a depth of at least 0.1 μm and at most 2 μm.

7. the semiconductor body (2) is SiC or Si, the first dopant is at least one of B, Al, and Ga; The power semiconductor device (1) according to any one of claims 1 to 6, wherein the second dopant is at least one of Be, Cd, Co, In, Mg, Mn, S, Tl, Zn.

8. 8. The power semiconductor device (1) according to claim 7, wherein the semiconductor body (2) is SiC, the first dopant is Al and the second dopant is Mg.

9. The power semiconductor device (1) according to any one of claims 1 to 8, wherein the first conductivity type is n and the second conductivity type is p.

10. The power semiconductor device (1) according to any one of claims 1 to 9, wherein the gate electrode (3) is planar, such that it is applied only on top of the semiconductor body (2) without penetrating into the semiconductor body (2).

11. 10. The power semiconductor device (1) according to any one of claims 1 to 9, wherein the gate electrode (3) is trench-type such that it extends into the semiconductor body (2) and is at least partially located in a trench formed in the semiconductor body (2).

12. The power semiconductor device (1) according to any one of claims 1 to 11, which is a power field effect transistor or a power insulated gate bipolar transistor configured such that a maximum current passing through the channel region (22) is at least 10 A.

13. 12. The power semiconductor device (1) according to claim 1, wherein a shortest distance (D) between the source region (21) and an associated collector layer (28) when the power semiconductor device (1) is a power insulated gate bipolar transistor or an associated drain region (23) when the power semiconductor device (1) is a field effect transistor is between 0.5 μm and 20 μm.

14. A method for operating a power semiconductor device (1) according to any one of claims 1 to 13, comprising: At room temperature, the first dopant is activated but the second dopant is not activated; As self-heating current protection, the second dopant is also activated when an operating temperature limit of the power semiconductor device (1) is exceeded, thereby increasing the threshold voltage of the power semiconductor device (1) when the operating temperature limit is exceeded and reducing the current through the channel region (22) as the temperature increases.

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