SiC wafer manufacturing method

Abstract

To provide an SiC wafer manufacturing method capable of sufficiently removing a work-affected layer at a small etching amount.SOLUTION: In a method for manufacturing an SiC wafer (40), a work-affected layer removing step of removing a work-affected layer on a surface of and inside the SiC wafer (40) is performed to manufacture the SiC wafer (40) with at least one part of the work-affected layer removed. In the work-affected layer removing step, while a reaction product is generated on the SiC wafer (40) using an oxidant, etching at an etching amount of 10 μm or less by heating under Si vapor pressure is performed to the SiC wafer (40) after a polishing step, from which the reaction product is removed, using abrasive so that the work-affected layer is removed. An internal stress is generated on the SiC wafer (40) after the polishing step, at an inner side of the work-affected layer due to the work-affected layer, so as to reduce an internal stress of the SiC wafer (40) by removing the work-affected layer in the work-affected layer removing step.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention mainly relates to a method for manufacturing a SiC wafer from which a process-affected layer has been removed. [Background technology]

[0002] Patent Document 1 describes that mechanical polishing of an SiC wafer, for example, causes polishing scratches on the surface of the SiC wafer and also causes latent scratches inside the SiC wafer. Patent Document 1 also describes a method for removing latent scratches by etching the surface of the SiC wafer by heating it under Si vapor pressure. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2015 / 151413 Summary of the Invention [Problem to be solved by the invention]

[0004] Here, when removing a work-affected layer such as latent scratches by etching as in Patent Document 1, it is preferable to remove the work-affected layer with a small amount of etching. This is because reducing the amount of etching reduces the time required to remove the work-affected layer, allows for efficient use of the single-crystal SiC as a raw material, and also reduces deterioration of the processing equipment used for etching.

[0005] The present invention has been made in view of the above circumstances, and a main object of the present invention is to provide a method for manufacturing a SiC wafer that can sufficiently remove the damaged layer with a small amount of etching.

[0006] The problem to be solved by the present invention is as described above. Next, the means for solving this problem and the effects thereof will be explained.

[0007] According to an aspect of the present invention, there is provided the following method for manufacturing a SiC wafer. Specifically, in this SiC wafer manufacturing method, a process-damaged layer removal step is performed to remove a process-damaged layer formed on the surface and inside of the SiC wafer, thereby manufacturing a SiC wafer from which at least a portion of the process-damaged layer has been removed. In the process-damaged layer removal step, a reaction product is generated on the SiC wafer using an oxidizing agent, and the reaction product is removed using abrasive grains to polish the surface of the polished wafer. The process-damaged layer is then removed by heating under Si vapor pressure to an etching depth of 10 μm or less. The polished wafer has internal stress due to the process-damaged layer, and removing the process-damaged layer in the process-damaged layer removal step reduces the internal stress of the SiC wafer.

[0008] Because the relatively soft reaction products generated by the oxidizing agent are removed using abrasive grains, the process-damaged layer is less likely to form than with other polishing methods. Therefore, even if the etching depth is 10 μm or less, the process-damaged layer can be sufficiently removed. Furthermore, because the etching depth is smaller than conventional methods, the processing time is reduced and the load on the processing equipment is also reduced. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a diagram illustrating an outline of a high-temperature vacuum furnace used in Si vapor pressure etching according to one embodiment of the present invention. [Figure 2] 2A to 2C are diagrams schematically showing the manufacturing process of the SiC wafer according to the present embodiment. [Figure 3] FIG. 2 is a perspective view showing the configuration of a polishing apparatus used in a polishing process. [Figure 4] 10A and 10B are diagrams illustrating that a process-affected layer and a stress layer generated on a SiC wafer after a polishing process are removed by a process-affected layer removal process. [Figure 5] 10A and 10B are diagrams showing scratch maps of a SiC wafer after a polishing process and a SiC wafer after a process-damaged layer removal process. [Figure 6]FIG. 10 is a diagram showing scratch maps for SiC wafers with different etching amounts in the process of removing a damaged layer. [Figure 7] FIG. 10 is a diagram comparing the surface roughness of a SiC wafer after a polishing process and the amount of scratches after a process-affected layer removal process. DETAILED DESCRIPTION OF THE INVENTION

[0010] Next, an embodiment of the present invention will be described with reference to the drawings. First, a high-temperature vacuum furnace 10 used in the SiC wafer manufacturing method of this embodiment will be described with reference to Fig. 1.

[0011] 1, the high-temperature vacuum furnace 10 includes a main heating chamber 21 and a preheating chamber 22. The main heating chamber 21 can heat SiC wafers 40 (single-crystal SiC substrates) having at least the surface made of single-crystal SiC (for example, 4H—SiC or 6H—SiC) to a temperature of 1000° C. or higher and 2300° C. The preheating chamber 22 is a space for preheating the SiC wafers 40 before heating them in the main heating chamber 21.

[0012] A vacuum forming valve 23, an inert gas injection valve 24, and a vacuum gauge 25 are connected to the main heating chamber 21. The vacuum forming valve 23 can adjust the degree of vacuum in the main heating chamber 21. The inert gas injection valve 24 can adjust the pressure of the inert gas in the main heating chamber 21. In this embodiment, the inert gas is, for example, a gas of a Group 18 element (a rare gas element) such as Ar, i.e., a gas that has little reactivity with solid SiC, excluding nitrogen gas. The vacuum gauge 25 can measure the degree of vacuum in the main heating chamber 21.

[0013] A heater 26 is provided inside the main heating chamber 21. In addition, heat-reflecting metal plates (not shown) are fixed to the side walls and ceiling of the main heating chamber 21, and these heat-reflecting metal plates are configured to reflect heat from the heater 26 toward the center of the main heating chamber 21. This allows the SiC wafers 40 to be heated powerfully and evenly, and the temperature can be raised to a temperature of 1000°C or higher and 2300°C or lower. The heater 26 can be, for example, a resistance heating heater or a high-frequency induction heating heater.

[0014] The high-temperature vacuum furnace 10 heats SiC wafers 40 contained in a crucible (container) 30. The container 30 is placed on a suitable support table or the like, and is configured to be movable from at least a preheating chamber to a main heating chamber by moving the support table. The container 30 includes an upper container 31 and a lower container 32 that can be fitted together. A support portion 33 provided on the lower container 32 of the container 30 can support the SiC wafer 40 so that both the main surface and the back surface of the SiC wafer 40 are exposed. The main surface of the SiC wafer 40 is the Si-plane, which is expressed as a (0001) crystal plane. The back surface of the SiC wafer 40 is the C-plane, which is expressed as a (000-1) crystal plane. The SiC wafer 40 may have an off-angle with respect to the Si-plane and C-plane, or the C-plane may be the main surface. Here, the main surface refers to one of the two largest surfaces (top and bottom surfaces in FIG. 1) of the SiC wafer 40, on which an epitaxial layer is formed in a subsequent process. The back surface refers to the surface opposite to the main surface.

[0015] The storage container 30 is composed of, in the portion constituting the wall surfaces (top surface, side surfaces, bottom surface) of the internal space in which the SiC wafers 40 are stored, a tantalum layer (Ta), a tantalum carbide layer (TaC and Ta2C), and a tantalum silicide layer (TaSi2 or Ta5Si3, etc.) in that order from the exterior side to the internal space side.

[0016] When heated, this tantalum silicide layer supplies Si to the internal space of the container 30. Furthermore, since the container 30 contains a tantalum layer and a tantalum carbide layer, it can take in ambient C vapor. This allows the internal space to be filled with a high-purity Si atmosphere during heating. Note that instead of providing a tantalum silicide layer, a Si source such as solid Si may be placed in the internal space. In this case, the solid Si sublimes during heating, creating a high-purity Si vapor pressure within the internal space.

[0017] When heating the SiC wafers 40, first, the storage container 30 is placed in the preheating chamber 22 of the high-temperature vacuum furnace 10 as shown by the chain line in FIG. 1 and preheated to an appropriate temperature (e.g., about 800°C). Next, the storage container 30 is moved to the main heating chamber 21, which has been heated to a preset temperature (e.g., about 1800°C). Thereafter, the SiC wafers 40 are heated while adjusting the pressure, etc. Note that preheating may be omitted.

[0018] Next, a manufacturing process for the SiC wafer 40 of this embodiment (particularly the SiC wafer 40 on which an epitaxial layer is formed) will be described with reference to Fig. 2. Fig. 2 is a diagram schematically showing the manufacturing process for the SiC wafer 40 of this embodiment.

[0019] The SiC wafer 40 is fabricated from an ingot 4. The ingot 4 is a mass of single-crystal SiC fabricated by a known sublimation method, solution growth method, or the like. As shown in FIG. 2 , the SiC ingot 4 is cut at predetermined intervals using a cutting means such as a diamond wire to fabricate multiple SiC wafers 40 from the ingot 4 (wafer fabrication process). The SiC wafer 40 may also be fabricated by other methods. For example, a damaged layer may be formed in the ingot 4 by laser irradiation or the like, and then the ingot 4 may be cut into wafers and extracted. Alternatively, a SiC wafer having at least a surface of single-crystal SiC may be fabricated by bonding a single-crystal SiC substrate and a polycrystalline SiC substrate obtained from an ingot or the like, followed by a process such as peeling, as needed. The SiC wafer 40 fabricated from the ingot 4 but before the following machining process may also be referred to as an as-sliced ​​wafer or an unprocessed wafer.

[0020] Next, the SiC wafer 40 is subjected to a machining process. In the machining process, for example, at least the main surface of the SiC wafer 40 is mechanically ground using a diamond wheel or the like. The machining process is a process performed to make the SiC wafer 40 have a target thickness. The machining process may be performed in multiple stages using tools with different abrasive grain sizes. The SiC wafer 40 after machining and before the following polishing process can also be referred to as a ground SiC wafer.

[0021] Next, the SiC wafer 40 is subjected to a polishing process. Conventionally, chemical mechanical polishing (CME) is performed on the SiC wafer 40 after the machining process using a predetermined slurry. Slurry is a mixture of abrasive grains and a chemical solution. In this embodiment, polishing is also performed using a slurry, but the chemical solution of the slurry used in this embodiment has an oxidizing effect (details will be described later). This type of polishing is called chemo-mechanical polishing.

[0022] The polishing step of this embodiment will be described in detail below with reference to Fig. 3. This is a perspective view showing the configuration of a polishing device 50 used in the polishing step.

[0023] 3, the polishing apparatus 50 includes a rotary support table 51, a polishing pad 52, a slurry supply pipe 53, a wafer carrier 55, and a pad conditioner 56. The polishing apparatus 50 is not limited to the configuration shown in FIG. 3 and described below, and the shape and configuration of each part may differ from those of this embodiment.

[0024] The rotary support base 51 is a disk-shaped member that is rotatable around its axial direction as shown in Fig. 3. A disk-shaped polishing pad 52 made of urethane foam or other material is attached to the upper surface of the rotary support base 51. Slurry is supplied onto the polishing pad 52 from a slurry supply pipe 53. Details of the slurry used in this embodiment and the effects of the slurry will be described later.

[0025] The wafer carrier 55 is configured to be able to fix the SiC wafer 40 to its underside. The wafer carrier 55 presses the main surface (surface to be polished) of the SiC wafer 40 fixed to its underside against the polishing pad 52. The wafer carrier 55 is also configured to be able to rotate around its axial direction as shown in FIG. 3 while pressing the SiC wafer 40 against the polishing pad 52. The rotational centers of the rotary support 51 and the wafer carrier 55 are different. This configuration allows slurry to act on the SiC wafer 40. As polishing progresses, the minute pores in the polishing pad 52 become clogged with processing debris, reaction products, and the like. The pad conditioner 56 removes this clogging by scraping the surface of the polishing pad 52.

[0026] Here, the slurry of this embodiment contains an oxidizing agent that oxidizes the SiC wafer 40. As described above, the slurry is composed of a chemical solution and abrasive grains. The slurry is, for example, an alumina slurry, a cerium oxide slurry, a manganese oxide slurry, or an iron oxide slurry, and the chemical solution is, for example, potassium permanganate, hydrogen peroxide, or ammonium peroxide, and the abrasive grains are, for example, alumina, cerium oxide, manganese oxide, or iron oxide. In the slurry of this embodiment, the above-mentioned chemical solution acts as an oxidizing agent.

[0027] The SiC wafer 40 is oxidized by the slurry, generating reaction products (oxides such as oxide films). The reaction products are, for example, silicon oxides (silicon dioxide, etc.). The reaction products are removed by the abrasive grains, thereby removing the surface of the SiC wafer 40 and polishing it. This reduces the surface roughness of the SiC wafer 40. The reaction products generated by the oxidation of SiC have a lower hardness than SiC. The abrasive grains, such as alumina, contained in the slurry used in this embodiment have a lower hardness than SiC but a higher hardness than the reaction products (e.g., silicon dioxide). The method for measuring hardness is not particularly limited, and examples that can be used include Vickers hardness, Mohs hardness, and Knoop hardness. In this way, by performing the polishing process using abrasive grains with a hardness between that of the reaction products and SiC, the reaction products generated on the SiC wafer 40 can be removed, the SiC portion of the SiC wafer 40 can be prevented from being scratched, and a large force can be prevented from being applied to the SiC wafer 40. The SiC wafer 40 after the polishing step and before the process-affected layer removal step described below can also be referred to as a polished SiC wafer.

[0028] Next, the damaged layer removal step will be described. First, the damaged layer and the like generated on the SiC wafer 40 (polished SiC wafer) will be described with reference to Fig. 4. Fig. 4 is a diagram illustrating that the damaged layer and stress layer generated on the SiC wafer 40 (polished SiC wafer) are removed by the damaged layer removal step.

[0029] As shown in Fig. 4, a process-affected layer and a stress layer are formed on the SiC wafer 40 after the polishing process. The process-affected layer is a region where distortion occurs due to internal stress and where crystal collapse or dislocation occurs. The process-affected layer is formed when force is applied to the surface or interior of the SiC wafer 40 or the surface of the SiC wafer 40 is scraped during at least one of the wafer fabrication process, the machining process, and the polishing process. The process-affected layer is a portion where the SiC of the SiC wafer 40 has irreversibly changed (plastically deformed).

[0030] Furthermore, portions of the process-affected layer that have a large degree of crystal collapse or dislocation are referred to as latent scratches. Unlike process-affected layers such as polishing scratches that occur only near the surface of the SiC wafer 40, latent scratches are characterized by the fact that they occur even inside the SiC wafer 40. Furthermore, latent scratches are characterized by becoming apparent during heat treatment. Specifically, even if the surface of the SiC wafer 40 appears sufficiently flat when observed under a microscope, if latent scratches remain inside, the latent scratches become apparent when the SiC wafer 40 is subjected to heat treatment (e.g., Si vapor pressure etching or epitaxial layer formation, which will be described later), causing significant surface roughness in the SiC wafer 40. Because of these characteristics, latent scratches are more difficult to remove than other process-affected layers because removing them requires a large amount of the SiC wafer 40 to be removed and it is difficult to confirm whether the latent scratches have been removed.

[0031] The stress layer is generated on the inner side of the processing-affected layer (opposite the main surface, below the processing-affected layer). Like the processing-affected layer, the stress layer is a portion where distortion occurs due to the generation of internal stress. However, unlike the processing-affected layer, the stress layer has no or almost no crystal collapse or dislocation. The cause of the generation of the stress layer is the same as the cause of the processing-affected layer. Furthermore, the stress layer has residual internal stress due to the presence of the processing-affected layer caused by the above-mentioned reasons. The stress layer is a portion where the SiC of the SiC wafer 40 is reversibly changed (elastically deformed). Therefore, by removing the processing-affected layer, the internal stress generated in the stress layer is released, and the stress layer returns to a state where no distortion occurs.

[0032] Furthermore, in this embodiment, since reaction products are generated and then removed in the polishing process, as described above, it is possible to suppress the application of large forces to the SiC wafer 40 in the polishing process. Therefore, the formation of a process-affected layer and a stress layer is reduced, or the stress layer is formed preferentially over the process-affected layer. As a result, the process-affected layer and the stress layer can be removed with a smaller etching amount than in the past. Note that, in this embodiment, the etching amount refers to the amount by which the main surface of the SiC wafer 40 is etched in the thickness direction (the amount of thickness reduction, i.e., the etching depth).

[0033] In this embodiment, the process-affected layer removal step is performed by Si vapor pressure etching, in which the SiC wafer 40 is heated under Si vapor pressure. Specifically, for example, the SiC wafer 40 having an off-angle is placed in the container 30 and heated under Si vapor pressure in a high-temperature vacuum furnace 10 at a temperature ranging from 1500°C to 2200°C, preferably from 1600°C to 2000°C. During this heating, an inert gas may be supplied in addition to the Si vapor. Supplying the inert gas can reduce the etching rate of the SiC wafer 40. Other than the Si vapor and the inert gas, no other vapor source is used. By heating the SiC wafer 40 under these conditions, the surface is etched while being planarized. Specifically, the following reactions occur: To put it simply, when the SiC wafer 40 is heated under Si vapor pressure, the SiC in the SiC wafer 40 is thermally decomposed and reacts chemically with Si to become SiC, SiC, etc., and is sublimated. At the same time, the Si in the Si atmosphere bonds with C on the surface of the SiC wafer 40, causing self-organization and flattening. (1) SiC(s) → Si(v) + C(s) (2) 2SiC(s) → Si(v) + SiC2(v) (3) SiC(s) + Si(v) → Si2C(v)

[0034] Since Si vapor pressure etching is a thermochemical etching process rather than a mechanical process such as grinding or polishing, it does not cause the formation of damaged or stressed layers. Therefore, unlike mechanical processes, it can remove existing damaged or stressed layers without forming new ones.

[0035] The top of Figure 4 shows a SiC wafer 40 (polished wafer) after the polishing process. This SiC wafer 40 has a process-affected layer including latent scratches and a stress layer. In the process-affected layer removal process, Si vapor pressure etching is performed with an etching depth of 10 µm or less. Since it is predicted that the polishing process of this embodiment will reduce the process-affected layer to 10 µm or less, all or most of the process-affected layer (including latent scratches) will be removed by performing the process-affected layer removal process of this embodiment.

[0036] The center and bottom of Figure 4 show the SiC wafer 40 after the damage-caused layer removal step has been performed. As described above, the stress layer is caused by the damage-caused layer, and the stress layer disappears when the damage-caused layer is removed. Therefore, by performing the damage-caused layer removal step, it is possible to manufacture a SiC wafer 40 that is completely or almost completely free of the damage-caused layer and the stress layer.

[0037] 5 shows the results of an experiment that confirmed that high-quality SiC wafers 40 can be obtained by performing processing according to the method of this embodiment. In this experiment, the state of scratch formation on the main surface of an SiC wafer 40 after a polishing process using an alumina slurry as the slurry and an SiC wafer 40 after a process-damaged layer removal process in which the etching depth was 3.4 μm were observed. A scratch is a linear flaw and is a type of process-damaged layer.

[0038] As shown in Figure 5, a large number of scratches exist on the SiC wafer 40 after the polishing process. However, most of these scratches were removed by etching only 3.4 µm. This confirmed that SiC wafers 40 with almost no damaged layer or stress layer can be manufactured with a significantly smaller etching amount than conventional methods.

[0039] The thickness of the damaged layer varies depending on the conditions of the polishing process, so the minimum required etching amount varies. However, compared to the minimum etching amount (10 μm) required for a conventional polishing process, the etching amount required in this embodiment is smaller. Figure 6 shows scratch maps after the damaged layer removal process for SiC wafers 40 with different etching amounts in the damaged layer removal process. The upper ED in each scratch map indicates the etching amount, and the lower Ra indicates the surface roughness (specifically, the arithmetic mean roughness Ra; the same applies below) after the damaged layer removal process. As shown in Figure 6, there are few or no scratches in any of the scratch maps for any etching amount. In other words, by using the method of this embodiment, SiC wafers 40 with few or no scratches can be manufactured by simply etching 20 nm, which is the minimum etching amount. Considering these experimental results, the lower limit of the etching depth in the process-damaged layer removal step is preferably, for example, 20 nm, 50 nm, 75 nm, 0.1 μm, 0.15 μm, 0.5 μm, 1 μm, 3 μm, or 5 μm, and the upper limit of the etching depth in the process-damaged layer removal step is preferably, for example, 1 μm, 3 μm, 5 μm, or 10 μm. By using the method of this embodiment, SiC wafers 40 that are almost free of process-damaged layers and stress layers can be manufactured with a smaller etching depth than conventional methods. This reduces the time required for processing the SiC wafers 40 and also reduces the load on the high-temperature vacuum furnace 10.

[0040] Furthermore, when compared with the removal amount in the machining step, the etching amount in the process-affected layer removal step is preferably smaller than the removal amount in the machining step.

[0041] Next, an epitaxial layer formation process is performed to form an epitaxial layer 41 on the main surface of the SiC wafer 40. In the epitaxial layer formation process, the SiC wafer 40 is placed on a susceptor, which is then placed in a heating chamber and subjected to chemical vapor deposition (CVD). Then, by introducing source gases and the like in a high-temperature environment, the epitaxial layer 41 made of single-crystal SiC is formed on the SiC substrate. The epitaxial layer 41 can also be formed by other methods. For example, the epitaxial layer 41 can be formed using a solution growth method such as the MSE method or a close-spaced sublimation method. The MSE method, also known as metastable solvent epitaxy, is a growth method using a SiC wafer, a feed substrate with higher free energy than the SiC wafer, and a Si melt. The SiC wafer and the feed substrate are arranged facing each other, and heated under vacuum with the Si melt interposed between them. This allows single-crystal SiC to be grown on the surface of the SiC wafer.

[0042] Next, with reference to FIG. 7, an experiment to confirm the relationship between the surface roughness of the SiC wafer 40 after the polishing step and the amount of scratches after the subsequent process-affected layer removal step will be described.

[0043] In this experiment, three types of SiC wafers 40 with different surface roughness after the polishing process were prepared. The surface roughness after the polishing process differed depending on the polishing conditions (size of abrasive grains, rotation speed of polishing pad 52, pressing force of wafer carrier 55, etc.). The slurry used in the polishing process was alumina slurry. The three types of SiC wafers 40 were also subjected to the process-damaged layer removal process under the same conditions. The etching depth in the process-damaged layer removal process was 3.4 μm.

[0044] The two sets of photographs at the top and center of Figure 7 were obtained by microscopic observation of SiC wafers 40 with surface roughnesses of 0.46 nm and 0.64 nm after the polishing process, respectively, and SiC wafers 40 after the process-damaged layer removal process. Furthermore, scratches on the surface of the SiC wafer 40 appear as thin lines. When the surface roughnesses after the polishing process are 0.46 nm and 0.64 nm, scratches are hardly visible after the process-damaged layer removal process. It can also be seen that the SiC wafer 40 with a surface roughness of 0.46 nm after the polishing process has slightly fewer scratches after the process-damaged layer removal process.

[0045] On the other hand, the bottom pair of photographs in Figure 7 were obtained by microscopic observation of a SiC wafer 40 with a surface roughness of 0.91 nm after the polishing process and a SiC wafer 40 after the process-damaged layer removal process. The conditions for the process-damaged layer removal process were the same. When the surface roughness after the polishing process was 0.91 nm, a large number of scratches were observed after the process-damaged layer removal process. Furthermore, a large scratch was observed slightly to the left of the center in the horizontal direction on this SiC wafer 40.

[0046] From the above, it can be seen that when the surface roughness after the polishing process is small, scratches are less likely to occur after the process-affected layer removal process. Furthermore, by setting the surface roughness of the SiC wafer 40 after the polishing process to 0.7 nm or less, it is possible to manufacture a SiC wafer 40 with sufficiently few scratches. Furthermore, by setting the surface roughness of the SiC wafer 40 after the polishing process to 0.5 nm or less, it is possible to manufacture a SiC wafer 40 with even fewer scratches.

[0047] As described above, in the method for manufacturing the SiC wafer 40 of this embodiment, a process-damaged layer removal step is performed to remove a process-damaged layer formed on the surface and inside of the SiC wafer 40, thereby manufacturing a SiC wafer 40 from which at least a portion of the process-damaged layer has been removed. In the process-damaged layer removal step, a reaction product is generated on the SiC wafer 40 using an oxidizing agent, and the SiC wafer 40 after the polishing step, from which the reaction product has been removed using abrasive grains, is then etched by an etching amount of 10 μm or less by heating under Si vapor pressure, thereby removing the process-damaged layer. In the SiC wafer 40 after the polishing step, stress is generated inside the process-damaged layer due to the process-damaged layer, and removing the process-damaged layer in the process-damaged layer removal step reduces the internal stress of the SiC wafer 40.

[0048] Because the relatively soft reaction products generated by the oxidizing agent are removed using abrasive grains, the process-damaged layer is less likely to form than with other polishing methods. Therefore, even if the etching depth is 10 μm or less, the process-damaged layer can be sufficiently removed. Furthermore, because the etching depth is smaller than conventional methods, the processing time is reduced and the load on the processing equipment is also reduced.

[0049] Furthermore, in the method for manufacturing the SiC wafer 40 of this embodiment, the arithmetic surface roughness (Ra) of the surface of the SiC wafer 40 after the polishing step is 0.7 nm or less.

[0050] The smaller the surface roughness of the SiC wafer 40 after the polishing step, the less likely it is that a damaged layer such as scratches will remain after the subsequent damaged layer removal step, allowing for the production of high-quality SiC wafers 40.

[0051] In the method for manufacturing the SiC wafer 40 of this embodiment, the process-damaged layer removing step involves etching with an etching amount of 5 nm or more or 20 nm or more.

[0052] This allows the damaged layer contained in the SiC wafer 40 after the polishing process to be sufficiently removed.

[0053] The method for manufacturing the SiC wafer 40 of this embodiment also includes a polishing step performed before the process-affected layer removal step. In the polishing step, a reaction product is generated on the SiC wafer 40 using an oxidizing agent, and the reaction product is removed using abrasive grains, thereby polishing the surface.

[0054] As a result, the relatively soft reaction products generated by the use of the oxidizing agent are removed using abrasive grains, which makes it less likely that a process-affected layer will be generated on the SiC wafer 40 compared to polishing using other methods, and therefore the process-affected layer can be easily removed.

[0055] In the method for manufacturing the SiC wafer 40 of this embodiment, the polishing step is performed using abrasive grains that are lower in hardness than SiC.

[0056] As a result, the reaction products produced using the oxidizing agent are less hard than SiC, so by using the above abrasive grains, it is possible to remove the reaction products while preventing scratches from occurring in the SiC portion.

[0057] The preferred embodiment of the present invention has been described above, but the above configuration can be modified, for example, as follows.

[0058] The manufacturing process described in the above embodiment is merely an example, and the order of the processes may be changed, some processes may be omitted, or other processes may be added. For example, a surface cleaning process using hydrogen etching may be performed before the epitaxial layer formation process.

[0059] The temperature conditions and pressure conditions described above are merely examples and can be changed as appropriate. It is also possible to use a heating device other than the high-temperature vacuum furnace 10 described above, to use polycrystalline SiC wafers 40, or to use a container with a different shape or material than the storage container 30. For example, the outer shape of the storage container is not limited to a cylindrical shape, and may be a cube or rectangular parallelepiped. [Explanation of symbols]

[0060] 10 High temperature vacuum furnace 40 SiC wafers

Claims

1. A method for manufacturing a SiC wafer from which at least a portion of a process-affected layer has been removed, by performing a process-affected layer removal step of removing a process-affected layer generated on a surface of a SiC wafer and inside the SiC wafer, a polishing step of generating a reaction product on the SiC wafer using an oxidizing agent and removing the reaction product using abrasive grains to obtain a polished wafer having a polished surface; a process-affected layer removal step of removing the process-affected layer by etching the polished wafer by an etching amount of 10 μm or less by heating under Si vapor pressure; Including, A method for manufacturing a SiC wafer from which a processing-damaged layer has been removed, characterized in that stress is generated in the polished wafer deeper than the processing-damaged layer due to the processing-damaged layer, and the internal stress of the SiC wafer is reduced by removing the processing-damaged layer in the processing-damaged layer removal step.

2. A method for manufacturing a SiC wafer from which the processing-affected layer according to claim 1 has been removed, comprising: The method for producing a SiC wafer from which a work-affected layer has been removed, wherein the arithmetic surface roughness (Ra) of the surface of the wafer after polishing is 0.7 nm or less.

3. A method for manufacturing a SiC wafer from which the processing-affected layer according to claim 1 or 2 has been removed, comprising: The method for manufacturing a SiC wafer from which a process-affected layer has been removed, wherein the polishing step is performed using the abrasive grains having a hardness lower than that of SiC.

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