Display device manufacturing equipment

Abstract

To provide a display device that is not faulty and improves visibility.SOLUTION: A display device includes: a board that includes a first display area including a first pixel region, a second pixel region, and a transparent region, and a second display area; a first pixel that is disposed on the first pixel region, and includes a first pixel electrode, a first counter electrode, and a first intermediate layer disposed between the first pixel electrode and the first counter electrode, and a second pixel that is disposed on the second pixel region, and includes the second pixel region, a second counter electrode, and a second intermediate layer disposed between the second pixel electrode and the second counter electrode, the first counter electrode is disposed in the first mutually separated pixel regions, the second counter electrode is disposed in the second mutually separated pixel regions, and the first counter electrode and the second counter electrode have a first contact region in which the first pixel region and the second pixel region that are adjacent mutually are connected electrically and mutually.SELECTED DRAWING: Figure 14

Description

[Technical Field]

[0001] The present invention relates to an apparatus and a method, and more particularly to a display device, a display device manufacturing apparatus, and a display device manufacturing method. [Background technology]

[0002] Recently, the applications of display devices have become more diverse, and the range of their use has expanded as display devices have become thinner and lighter.

[0003] As display devices are utilized in a variety of ways, there are various methods for designing the shape of the display device, and the number of functions that can be applied to or associated with the display device is increasing. Summary of the Invention [Problem to be solved by the invention]

[0004] The present invention provides a display device having a sensor area where a sensor or the like is arranged inside the display area, as a method for increasing the functions applicable to or linkable with the display device, and a manufacturing apparatus and method for the same.

[0005] However, such challenges are exemplary and are not intended to limit the scope of the invention. [Means for solving the problem]

[0006] One embodiment of the present invention discloses a display device including a substrate including a first display region and a second display region, each including a first pixel region, a second pixel region, and a transmissive region; a first pixel arranged on the first pixel region, the first pixel electrode, a first counter electrode, and a first intermediate layer arranged between the first pixel electrode and the first counter electrode; and a second pixel arranged on the second pixel region, the second pixel electrode, a second counter electrode, and a second intermediate layer arranged between the second pixel electrode and the second counter electrode, the first counter electrode and the second counter electrode being arranged in the first pixel region and spaced apart from each other, and the second counter electrode and the first counter electrode being arranged in the second pixel region and spaced apart from each other, and the first counter electrode and the second counter electrode having a first contact region where the adjacent first pixel region and the second pixel region are electrically connected to each other.

[0007] In this embodiment, the pixel regions and the transmissive regions are alternately arranged in a grid pattern.

[0008] In this embodiment, the transmissive region is defined by the first pixel region and the second pixel region connected to each other.

[0009] In this embodiment, the first contact region is also a region where the first opposing electrode and the second opposing electrode make surface contact with each other.

[0010] In the present embodiment, in the first contact region, the second opposing electrode is disposed on the first opposing electrode.

[0011] In this embodiment, the pixel defining layer may further include a pixel defining layer disposed on the first pixel electrode and the second pixel electrode, the pixel defining layer having a first opening and a second opening exposing central portions of the first pixel electrode and the second pixel electrode, respectively, and the first contact region may be disposed on the pixel defining layer. In this embodiment, the first display area and the second display area may have different light transmittances.

[0012] In this embodiment, the resolution of the image provided in the first display area is lower than the resolution of the image provided in the second display area.

[0013] In this embodiment, the second display region includes a third pixel region and a fourth pixel region arranged adjacent to each other, and further includes a third pixel arranged on the third pixel region and including a third pixel electrode, a third opposing electrode, and a third intermediate layer arranged between the third pixel electrode and the third opposing electrode, and a fourth pixel arranged on the fourth pixel region and including a fourth pixel electrode, a fourth opposing electrode, and a fourth intermediate layer arranged between the fourth pixel electrode and the fourth opposing electrode, and the third opposing electrode and the fourth opposing electrode have a second contact region that electrically connects the adjacent third pixel region and the fourth pixel region to each other.

[0014] In this embodiment, one of the third opposing electrode or the fourth opposing electrode may have a third contact region that protrudes into the first display region and electrically connects the third opposing electrode to the first opposing electrode, or electrically connects the fourth opposing electrode to the second opposing electrode.

[0015] In the present embodiment, the fourth opposing electrode is disposed on the first opposing electrode in the third contact region.

[0016] In this embodiment, the display device further includes a pixel defining layer disposed on the third pixel electrode and the fourth pixel electrode, and at least one of the second contact region and the third contact region is disposed on the pixel defining layer.

[0017] In the present embodiment, the fourth opposing electrode is disposed on the third opposing electrode in the second contact region.

[0018] In the present embodiment, the third opposing electrode, the fourth opposing electrode, and the second contact region are arranged to cover the entire surface of the second display region.

[0019] In this embodiment, the third opposing electrode and the fourth opposing electrode are also in the form of a line. In this embodiment, the first opposing electrode and the third opposing electrode are arranged in parallel, and the second opposing electrode and the fourth opposing electrode are arranged in parallel.

[0020] In this embodiment, the substrate includes a non-display area surrounding at least a portion of the second display area, and at least one of the third opposing electrode and the fourth opposing electrode protrudes from the second display area into the non-display area.

[0021] Another embodiment of the present invention provides a display device including a substrate including a first display region and a second display region, each including a first pixel region, a second pixel region, and a transmissive region; a first pixel disposed on the first pixel region, the first pixel electrode, a first counter electrode, and a first intermediate layer disposed between the first pixel electrode and the first counter electrode; a second pixel disposed on the second pixel region, the second pixel electrode, a second counter electrode, and a second intermediate layer disposed between the second pixel electrode and the second counter electrode; and a component disposed on one side of the substrate corresponding to the first display region, the component including an electronic element for emitting and receiving light, the component being disposed on the first pixel region spaced apart from the first counter electrode, the second counter electrode being disposed in the second pixel region spaced apart from the first counter electrode, the first counter electrode and the second counter electrode being disposed in the first pixel region and the second pixel region adjacent to each other. In one embodiment, the component emits or receives light through the transmissive region, and the light transmittance of the second display region is lower than the light transmittance of the first display region.

[0022] Yet another embodiment of the present invention discloses an apparatus for manufacturing a display device, comprising: a chamber, a portion of which is selectively opened and closed; a first support portion disposed in the chamber and supporting a substrate; a mask assembly disposed in the chamber facing the substrate; a second support portion disposed in the chamber and supporting the mask assembly; and a deposition source disposed in the chamber and supplying a deposition material to the substrate, wherein the mask assembly comprises a mask frame and a mask sheet placed on the mask frame, the mask sheet including a first opening and a second opening disposed in a portion of the mask sheet different from the first opening, the first opening and the second opening being arranged in a line, a width of the mask sheet between the first opening and the second opening adjacent to each other being smaller than a width of the mask sheet between the second opening adjacent to each other, or shapes of the first opening and the second opening are different from each other.

[0023] In this embodiment, the deposition source is located at the edge of the chamber.

[0024] In this embodiment, the first opening is square and the second opening is also rectangular.

[0025] In this embodiment, at least one of the first support part and the second support part can adjust the relative position of the substrate and the mask assembly.

[0026] Yet another embodiment of the present invention discloses a method for manufacturing a display device, including the steps of: placing a substrate and a mask assembly in a chamber; forming a first opposing electrode and a third opposing electrode in a first display area and a second display area of ​​the substrate, respectively, by causing a deposition material supplied from a deposition source to pass through the mask assembly; changing the position of at least one of the substrate and the mask assembly; and forming a second opposing electrode at least partially overlapping with the first opposing electrode and a fourth opposing electrode at least partially overlapping with the third opposing electrode in the first display area and the second display area, respectively, by causing the deposition material supplied from the deposition source to pass through the mask assembly.

[0027] In the present embodiment, a first contact region where the first opposing electrode and the second opposing electrode overlap and a second contact region where the third opposing electrode and the fourth opposing electrode overlap are disposed on a pixel defining layer.

[0028] In this embodiment, the substrate includes a non-display area arranged to surround at least a portion of the second display area, and a portion of at least one of the third opposing electrode and the fourth opposing electrode protrudes into the non-display area in the second display area.

[0029] In this embodiment, a transmissive region is disposed between the first opposing electrode and the second opposing electrode.

[0030] In the present embodiment, the third opposing electrode, the fourth opposing electrode, and a second contact region where the third opposing electrode and the fourth opposing electrode overlap are arranged to cover the entire surface of the second display region.

[0031] In this embodiment, a first contact region where the first opposing electrode and the second opposing electrode overlap is also a region where the first opposing electrode and the second opposing electrode make surface contact with each other.

[0032] In this embodiment, the second contact region where the third opposing electrode and the fourth opposing electrode overlap is also a region where the third opposing electrode and the fourth opposing electrode make surface contact with each other.

[0033] In this embodiment, the first display area and the second display area have different light transmittances. In this embodiment, at least one of the third opposing electrode and the fourth opposing electrode has a third contact area that protrudes into the first display area, and the third contact area can be electrically connected to at least one of the first opposing electrode and the second opposing electrode.

[0034] In this embodiment, the first opposing electrodes and the third opposing electrodes are arranged in a first direction, and the first opposing electrodes are arranged in a second direction different from the first direction.

[0035] In this embodiment, the first opposing electrodes and the second opposing electrodes are connected in a third direction different from the first direction and the second direction.

[0036] Further aspects, features, and advantages will become apparent from the following drawings, claims, and detailed description of the invention.

[0037] Such general and specific aspects may be implemented using a system, a method, a computer program, or any combination of systems, methods, and computer programs. [Effects of the Invention]

[0038] According to an embodiment of the present invention, it is possible to realize a display panel having an expanded display area so that an image can be displayed even in an area where components are arranged, and a display device including the same, although the scope of the present invention is not limited by such an effect. [Brief explanation of the drawings]

[0039] [Figure 1]1 is a perspective view illustrating a display device according to an embodiment of the present invention; [Figure 2] 1 is a cross-sectional view simply illustrating a display device according to an embodiment of the present invention. [Figure 3] 1 is a plan view schematically illustrating a display panel according to an embodiment of the present invention; [Figure 4] 4 is an enlarged plan view showing an embodiment of the first display region of FIG. 3. FIG. [Figure 5] 2 is an equivalent circuit diagram of a pixel of a display panel according to an embodiment of the present invention; [Figure 6] 2 is an equivalent circuit diagram of a pixel of a display panel according to an embodiment of the present invention; [Figure 7] FIG. 2 is a schematic layout diagram of a pixel circuit of a pixel according to an embodiment of the present invention. [Figure 8] 8 is a cross-sectional view taken along lines II' and II-II' in FIG. 7. [Figure 9] 2 is a plan view showing a part of a first display region according to an embodiment of the present invention. FIG. [Figure 10] 2 is a plan view showing a part of a first display area according to an embodiment of the present invention. FIG. [Figure 11] 3A to 3C are cross-sectional views schematically illustrating a part of a manufacturing process of a display panel according to an embodiment of the present invention. [Figure 12] 3A to 3C are cross-sectional views schematically illustrating a part of a manufacturing process of a display panel according to an embodiment of the present invention. [Figure 13] FIG. 10 is a cross-sectional view schematically showing a cross section taken along line BB' in FIG. 9. [Figure 14] 2 is a plan view showing the arrangement of counter electrodes of a display panel according to an embodiment of the present invention; FIG. [Figure 15] FIG. 15 is a cross-sectional view schematically showing a cross section taken along line CC' in FIG. [Figure 16] FIG. 15 is a cross-sectional view schematically showing a cross section taken along line DD' in FIG. [Figure 17] FIG. 15 is a cross-sectional view schematically showing a cross section taken along line EE' in FIG. [Figure 18]FIG. 10 is a perspective view illustrating a display device according to another embodiment of the present invention. [Figure 19] 10 is a plan view schematically illustrating a display area and a non-display area of ​​a display panel according to another embodiment of the present invention. [Figure 20] 1 is a cross-sectional view schematically illustrating a display device manufacturing apparatus according to an embodiment of the present invention. [Figure 21] FIG. 21 is a plan view showing a portion of one embodiment of the mask sheet shown in FIG. 20. [Figure 22] 10 is a plan view schematically illustrating a display area and a non-display area of ​​a display panel according to still another embodiment of the present invention. [Figure 23] 21 is a plan view showing a part of another embodiment of the mask sheet shown in FIG. 20. FIG. [Figure 24] 10 is a plan view schematically illustrating a display area and a non-display area of ​​a display panel according to still another embodiment of the present invention. [Figure 25] FIG. 21 is a plan view showing a part of still another embodiment of the mask sheet shown in FIG. 20. [Figure 26] 10 is a plan view schematically illustrating a display area and a non-display area of ​​a display panel according to still another embodiment of the present invention. [Figure 27] 10 is a plan view schematically illustrating a display area and a non-display area of ​​a display panel according to still another embodiment of the present invention. [Figure 28] 10 is a plan view schematically illustrating a display area and a non-display area of ​​a display panel according to still another embodiment of the present invention. [Figure 29] 10 is a plan view schematically illustrating a display area and a non-display area of ​​a display panel according to still another embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0040] The present invention can be modified in various ways and has various embodiments, and specific embodiments will be illustrated in the drawings and described in detail. The advantages and features of the present invention, as well as methods for achieving them, will become clearer with reference to the following detailed description of the embodiments together with the drawings. However, the present invention is not limited to the following embodiments, and may be embodied in various forms.

[0041] Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings. When describing with reference to the drawings, identical or corresponding components will be denoted by the same reference numerals, and duplicate descriptions thereof will be omitted.

[0042] In the following embodiments, terms such as first and second are used not in a limiting sense but to distinguish one component from another.

[0043] In the following embodiments, singular expressions include plural expressions unless the context clearly indicates otherwise.

[0044] In the following embodiments, terms such as "comprise" or "have" mean that the features or components described in the specification are present, and do not preclude the possibility that one or more other features or components may be added.

[0045] In the following embodiments, when a part such as a film, region, or component is said to be on or above another part, this does not only include the case where it is directly on top of the other part, but also the case where another film, region, component, etc. is interposed between them.

[0046] In the drawings, the size of components may be exaggerated or reduced for the sake of convenience. For example, the size and thickness of each component shown in the drawings are arbitrarily shown for the sake of convenience, and the present invention is not necessarily limited to what is shown in the drawings.

[0047] In the following embodiments, the x-axis, y-axis, and z-axis are not limited to the three axes on a Cartesian coordinate system, but are interpreted in a broad sense to include such axes. For example, the x-axis, y-axis, and z-axis may be orthogonal to each other, or may indicate different directions that are not orthogonal to each other.

[0048] If an embodiment can be implemented differently, the order of certain steps may be different from that described. For example, two steps described in succession may be performed substantially simultaneously or may be performed in the reverse order from that described.

[0049] FIG. 1 is a perspective view showing a display device according to an embodiment of the present invention.

[0050] 1, the display device 1 includes a display area DA that displays an image and a non-display area NDA that does not display an image. The display area DA includes a second display area DA2 and a first display area DA1 located within the second display area DA2. The display device 1 can provide a main image using light emitted from a plurality of main pixels PXm arranged in the second display area DA2.

[0051] The display device 1 includes a first display area DA1 within a second display area DA2. As will be described later with reference to FIG. 2, the first display area DA1 is also an area where components such as sensors using infrared rays, visible light, or sound are disposed below. The first display area DA1 includes a transmissive area TA through which light and / or sound can pass, either output from the components or traveling toward the components. In an embodiment of the present invention, when infrared rays are transmitted through the first display area DA1, the light transmittance is approximately 10% or more, more preferably 20% or more, 25% or more, 50% or more, 85% or more, or even 90% or more. The light transmittance of the first display area DA1 is different from that of the second display area DA2. For example, the light transmittance of the first display area DA1 is higher than that of the second display area DA2.

[0052] In this embodiment, a plurality of auxiliary pixels PXa are arranged in the first display area DA1, and a predetermined image is provided using light emitted from the plurality of auxiliary pixels PXa. The image provided from the first display area DA1 is an auxiliary image and has lower resolution than the image provided from the second display area DA2. That is, the first display area DA1 includes a transmissive area TA through which light and / or sound passes, and the number of auxiliary pixels PXa arranged per unit area is smaller than the number of main pixels PXm arranged per unit area in the second display area DA2.

[0053] The first display area DA1 is at least partially surrounded by the second display area DA2, and in one embodiment, FIG. 1 shows the first display area DA1 totally surrounded by the second display area DA2.

[0054] In the following, an organic light emitting display device is described as an example of a display device 1 according to an embodiment of the present invention, but the display device of the present invention is not limited thereto. In other embodiments, an inorganic EL display (Inorganic Electro Luminescent Display), a quantum dot light emitting display, etc. Various display devices such as quantum dot light emitting displays are used.

[0055] Although FIG. 1 illustrates that the first display area DA1 is disposed on one side (upper right side) of the second display area DA2, which is rectangular, the present invention is not limited to this. The shape of the first display area DA1 may be a circle, an ellipse, or a polygon such as a triangle or a pentagon, and the position and number of the first display area DA1 may be changed in various ways.

[0056] 2 is a cross-sectional view showing a simplified display device according to an embodiment of the present invention, taken along line AA' in FIG.

[0057] Referring to FIG. 2, the display device 1 includes a display panel 10 including display elements and a component 20 located below the display panel 10 and corresponding to a first display area DA1.

[0058] The display panel 10 includes a substrate 100, a display element layer 200 disposed on the substrate 100, and a thin film encapsulation layer 300 as a sealing member for sealing the display element layer 200. The display panel 10 further includes a lower protective film 175 disposed under the substrate 100.

[0059] The substrate 100 includes glass or a polymer resin. The polymer resin may be polyethersulfone (PES), polyarylate (PAR), or polyetherimide (PEI). , polyetherimide), polyethylene naphthalate (PEN, polyethyelenennapthalate), polyethylene terephthalate (PET, polyethyeleneterepthalate), polyphenylene sulfide (PPS, polyphenylenesulfide), polyimide (PI, polyimide), polycarbonate (PC, polycarbonate), or cellulose acetate propionate (CAP, cellulose acetate propionate), etc. The substrate 100 comprising a polymer resin may be flexible, rollable, or The substrate 100 may have a multi-layer structure including a layer containing the polymer resin described above and an inorganic layer (not shown).

[0060] The display element layer 200 includes a circuit layer including thin film transistors (TFTs), organic light emitting diodes OLED as display elements, and an insulating layer IL therebetween.

[0061] The second display area DA2 is provided with a main pixel PXm including a thin film transistor (TFT) and an organic light-emitting diode (OLED) connected thereto, and the first display area DA1 is provided with an auxiliary pixel PXa including a thin film transistor (TFT) and an organic light-emitting diode (OLED) connected thereto, and wiring (not shown) electrically connected to the main pixel PXm and the auxiliary pixel PXa is provided.

[0062] In addition, a transmissive area TA, in which no thin film transistors (TFTs) or pixels are arranged, is arranged in the first display area DA1. The transmissive area TA is understood to be an area through which light / signals emitted from the component 20 or light / signals incident on the component 20 are transmitted. It is possible.

[0063] The component 20 is located in the first display area DA1. The component 20 may be an electronic element that uses light or sound. For example, the component 20 may be a sensor that receives and uses light, such as an infrared sensor, a sensor that outputs and senses light or sound to measure distance, a sensor that recognizes fingerprints, a small lamp that outputs light, or a speaker that outputs sound. It goes without saying that electronic elements that use light can use light in various wavelength bands, such as visible light, infrared light, and ultraviolet light. The number of components 20 arranged in the first display area DA1 may be plural. For example, a light-emitting element and a light-receiving element may be provided together as the component 20 in one first display area DA1. Alternatively, a light-emitting unit and a light-receiving unit may be provided in one component 20.

[0064] The thin film encapsulation layer 300 includes at least one inorganic encapsulation layer and at least one organic encapsulation layer. In this regard, Figure 2 shows first and second inorganic encapsulation layers 310, 330 with an organic encapsulation layer 320 therebetween.

[0065] The first and second inorganic encapsulation layers 310 and 330 include one or more inorganic insulating materials selected from the group consisting of aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride. The organic encapsulation layer 320 includes a polymer-based material. Polymer-based materials include polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyethylene sulfonate, polyoxymethylene, polyarylate, hexamethyldisiloxane, acrylic resins (e.g., polymethyl methacrylate, polyacrylic acid, etc.), or any combination thereof.

[0066] The lower protective film 175 is attached to the lower part of the substrate 100 and serves to support and protect the substrate 100. The lower protective film 175 has an opening 175OP corresponding to the first display area DA1. The opening 175OP in the lower protective film 175 can improve the light transmittance of the first display area DA1. The lower protective film 175 is made of a material including polyethylene terephthalate (PET) or polyimide (PI). can be.

[0067] The area of ​​the first display area DA1 is larger than the area in which the component 20 is disposed. Although the area of ​​the first display area DA1 and the area of ​​the opening 175OP are illustrated as being the same in FIG. 2, the area of ​​the opening 175OP provided in the lower protective film 175 may not be the same as the area of ​​the first display area DA1. For example, the area of ​​the opening 175OP may be smaller than the area of ​​the first display area DA1.

[0068] Although not shown, the display panel 10 may include an input sensing member for sensing a touch input, a polarizer and a retarder, or a color filter and a black matrix. Further components such as anti-reflection members and transparent windows may be provided.

[0069] Meanwhile, in this embodiment, the thin film encapsulation layer 300 is used as a sealing member for sealing the display element layer 200, but the present invention is not limited thereto. For example, a sealing substrate that is bonded to the substrate 100 by a sealant or frit may also be used as a member for sealing the display element layer 200.

[0070] Fig. 3 is a plan view schematically illustrating a display panel according to an embodiment of the present invention, and Fig. 4 is an enlarged plan view illustrating an embodiment of the first display area DA1 of Fig. 3.

[0071] 3 and 4, various components constituting the display panel 10 are disposed on a substrate 100. The substrate 100 includes a display area DA and a non-display area NDA surrounding the display area DA. The display area DA includes a second display area DA2 where a main image is displayed and a first display area DA1 with a transmissive area TA therein where an auxiliary image is displayed.

[0072] A plurality of main pixels PXm are arranged in the second display area DA2. Each main pixel PXm includes a display element such as an organic light emitting element (OLED). Each main pixel PXm can emit light of, for example, red, green, blue, or white through the organic light emitting element (OLED). In this specification, a main pixel PXm is understood to be a pixel that emits light of any one of the colors red, green, blue, and white, as described above. The second display area DA2 is covered with the sealing member described with reference to FIG. 2 to protect it from external air, moisture, etc.

[0073] The first display area DA1 is disposed inside the second display area DA2, and a plurality of auxiliary pixels PXa are disposed in the first display area DA1. Each of the auxiliary pixels PXa includes a display element such as an organic light-emitting diode (OLED). Each of the auxiliary pixels PXa emits light through the OLED, for example, The sub-pixels PXa can emit red, green, blue, or white light. In this specification, the sub-pixels PXa are understood to be pixels that emit light of any one of red, green, blue, and white, as described above. Meanwhile, the first display area DA1 includes transmissive areas TA disposed between the sub-pixels PXa.

[0074] The first display area DA1 includes a transmissive area TA, and the resolution of the first display area DA1 is lower than that of the second display area DA2. For example, the resolution of the first display area DA1 is approximately half that of the second display area DA2. In some embodiments, the resolution of the second display area DA2 is 400 ppi or more, and the resolution of the first display area DA1 is approximately 200 ppi.

[0075] The first display area DA1 will be described with reference to FIG.

[0076] The first display area DA1 includes auxiliary pixel areas PA1 each including at least one auxiliary pixel PXa, and transmissive areas TA, which are alternately arranged along the first direction DR1 and the second direction DR2, for example, in a grid pattern.

[0077] The auxiliary pixel area PA1 includes auxiliary pixels Pr that emit red light, auxiliary pixels Pg that emit green light, and auxiliary pixels Pb that emit blue light. While pentile-type auxiliary pixels PXa are shown in FIG. 4, the auxiliary pixels PXa may be formed in a stripe pattern or various other shapes. Although eight auxiliary pixels PXa are shown in FIG. 4, the number of auxiliary pixels PXa can be varied depending on the resolution of the first display area DA1.

[0078] In one embodiment, one main pixel PXm and one auxiliary pixel PXa include the same pixel circuit, but the present invention is not limited to this. It goes without saying that the pixel circuit included in the main pixel PXm and the pixel circuit included in the auxiliary pixel PXa may be different from each other.

[0079] The transmissive region TA does not include auxiliary pixels PXa. The absence of auxiliary pixels PXa means that the auxiliary pixels PXa do not include display elements such as organic light-emitting elements (OLEDs). In other words, the transmissive region TA does not include the pixel electrodes, intermediate layers, and counter electrodes constituting the organic light-emitting elements (OLEDs), as well as the pixel circuits electrically connected thereto. Of course, some of the signal lines PL, DL, SL, and EL connected to supply signals to the auxiliary pixels PXa located in the subpixel region PA1 may be positioned across the transmissive region TA. However, even in this case, the signal lines PL, DL, SL, and EL may be positioned to bypass the center of the transmissive region TA in order to increase the transmittance of the transmissive region TA.

[0080] Although not shown, a conductive layer (not shown) is disposed on the substrate 100 corresponding to the subpixel area PA1 of the first display area DA1. The conductive layer is disposed below the subpixel PXa, for example, between the thin film transistor of the subpixel PXa and the substrate 100. The conductive layer prevents external light emitted from the component 20 from being incident on and affecting the pixel circuit PC (FIG. 5) of the subpixel PXa. A constant voltage or signal is applied to such a conductive layer to prevent damage to the pixel circuit PC due to electrostatic discharge. A plurality of conductive layers may be provided in the first display area DA1, and, in some cases, different voltages may be applied to each conductive layer.

[0081] 3, each pixel PXm, PXa is electrically connected to an outer circuit arranged in the non-display area NDA, in which a first scan driving circuit 110, a second scan driving circuit 120, terminals 140, a data driving circuit 150, a first power supply line 160, and a second power supply line 170 are arranged.

[0082] The first scan drive circuit 110 provides scan signals to each pixel PXm, PXa through scan lines SL. The first scan drive circuit 110 provides light-emitting control signals to each pixel through light-emitting control lines EL. The second scan drive circuit 120 is arranged alongside the first scan drive circuit 110 across the display area DA. Some of the pixels PXm, PXa arranged in the display area DA are electrically connected to the first scan drive circuit 110, and the rest are connected to the second scan drive circuit 120. In other embodiments, the second scan drive circuit 120 is omitted.

[0083] The terminal 140 is disposed on one side of the substrate 100. The terminal 140 is not covered by an insulating layer and is exposed to be electrically connected to the printed circuit board PCB. A terminal PCB-P of the printed circuit board PCB is electrically connected to the terminal 140 of the display panel 10. The printed circuit board PCB transmits signals or power from a controller (not shown) to the display panel 10. Control signals generated by the controller are transmitted to the first and second scan driving circuits 110 and 120, respectively, via the printed circuit board PCB. The controller provides first and second power supplies ELVDD and ELVSS (see FIGS. 5 and 6, described below) to the first and second power supply wirings 160 and 170, respectively, via first and second connection wirings 161 and 171. The first power supply voltage ELVDD is provided to each pixel PXm, PXa through the driving voltage line PL connected to the first power supply wiring 160, and the second power supply voltage ELVSS is provided to the counter electrode of each pixel PXm, PXa connected to the second power supply wiring 170.

[0084] The data driving circuit 150 is electrically connected to the data lines DL. Data signals from the data driving circuit 150 are provided to the pixels PXm, PXa through connection wiring 151 connected to the terminals 140 and the data lines DL connected to the connection wiring 151. Although FIG. 3 illustrates the data driving circuit 150 being disposed on the printed circuit board PCB, in other embodiments, the data driving circuit 150 is disposed on the substrate 100. For example, the data driving circuit 150 is disposed between the terminals 140 and the first power supply wiring 160.

[0085] The first power supply line 160 connects the second display area DA2 and the terminal 14 0 and includes a first sub-line 162 and a second sub-line 163 extending side by side in the x-direction. A second power supply line 170 is loop-shaped with one side open and partially surrounds the display area DA.

[0086] 5 and 6 are equivalent circuit diagrams of pixels of a display panel according to an embodiment of the present invention.

[0087] 5 and 6, each of the pixels PXm and PXa includes a pixel circuit PC connected to a scan line SL and a data line DL, and an organic light emitting element OLED connected to the pixel circuit PC.

[0088] The pixel circuit PC includes a driving thin film transistor T1, a switching thin film transistor T2, and a storage capacitor Cst. The switching thin film transistor T2 is connected to a scan line SL and a data line DL, and transmits a data signal DM input through the data line DL to the driving thin film transistor T1 in response to a scan signal Sn input through the scan line SL.

[0089] The storage capacitor Cst is connected to the switching thin film transistor T2 and the driving voltage line PL, and stores a voltage corresponding to the difference between the voltage transmitted from the switching thin film transistor T2 and the first power supply voltage ELVDD (or driving voltage) supplied to the driving voltage line PL. The driving thin film transistor T1 is connected to the driving voltage line PL and the storage capacitor Cst, and outputs an organic light emitting diode (OLED) from the driving voltage line PL in response to the voltage value stored in the storage capacitor Cst. The driving current flowing through the light element OLED is controlled, and the organic light emitting element OLED can emit light having a predetermined brightness depending on the driving current.

[0090] Although the pixel circuit PC includes two thin film transistors and one storage capacitor in FIG. 5, the present invention is not limited thereto. As shown in FIG. 6, the pixel circuit PC includes seven thin film transistors and one storage capacitor. Although FIG. 6 shows one storage capacitor, the pixel circuit PC may include two or more storage capacitors.

[0091] 6, each pixel PXm, PXa includes a pixel circuit PC and an organic light emitting diode OLED connected to the pixel circuit PC. The pixel circuit PC includes a plurality of thin film transistors and a storage capacitor. The capacitors are connected to the signal lines SL, SL-1, EL, DL, the initialization voltage line VL, and the drive voltage line PL.

[0092] 6 illustrates that pixels PXm and PXa are connected to signal lines SL, SL-1, EL, and DL, an initialization voltage line VL, and a driving voltage line PL, but the present invention is not limited to this. In another embodiment, at least one of the signal lines SL, SL-1, EL, and DL, the initialization voltage line VL, or the driving voltage line PL is shared by adjacent pixels.

[0093] The signal lines include a scan line SL for transmitting a scan signal Sn, a previous scan line SL-1 for transmitting a previous scan signal Sn-1 to the first initialization thin film transistor T4 and the second initialization thin film transistor T7, an emission control line EL for transmitting an emission control signal En to the operation control thin film transistor T5 and the emission control thin film transistor T6, and a data line DL crossing the scan line SL for transmitting a data signal DM. The driving voltage line PL transmits a driving voltage ELVDD to the driving thin film transistor T1, and the initialization voltage line VL transmits an initialization voltage Vint for initializing the driving thin film transistor T1 and the pixel electrode.

[0094] The driving gate electrode G1 of the driving thin film transistor T1 is connected to the lower electrode CE1 of the storage capacitor Cst, the driving source electrode S1 of the driving thin film transistor T1 is connected to the lower driving voltage line PL via the operation control thin film transistor T5, and the driving drain electrode D1 of the driving thin film transistor T1 is electrically connected to the pixel electrode of the main organic light emitting element OLED via the emission control thin film transistor T6. The driving thin film transistor T1 receives the data signal DM through the switching operation of the switching thin film transistor T2, and supplies the driving current I to the main organic light emitting element OLED. OLED supply.

[0095] The switching gate electrode G2 of the switching thin film transistor T2 is connected to the scan line SL, the switching source electrode S2 of the switching thin film transistor T2 is connected to the data line DL, and the switching drain electrode D2 of the switching thin film transistor T2 is connected to the driving source electrode S1 of the driving thin film transistor T1 and also connected to the lower driving voltage line PL via the operation control thin film transistor T5. The switching thin film transistor T2 is turned on by the scan signal Sn transmitted through the scan line SL to perform a switching operation of transmitting the data signal DM transmitted to the data line DL to the driving source electrode S1 of the driving thin film transistor T1.

[0096] The compensation gate electrode G3 of the compensation thin film transistor T3 is connected to the scan line SL, the compensation source electrode S3 of the compensation thin film transistor T3 is connected to the driving drain electrode D1 of the driving thin film transistor T1, and is also connected to the pixel electrode of the organic light emitting element OLED through the light emitting control thin film transistor T6. The compensation drain electrode D3 of the compensation thin film transistor T3 is connected to the lower electrode CE1 of the storage capacitor Cst, the first electrode CE2 of the first initialization thin film transistor T4, The compensation thin film transistor T3 is connected to the initialization drain electrode D4 and the driving gate electrode G1 of the driving thin film transistor T1. The compensation thin film transistor T3 is turned on by a scan signal Sn transmitted through the scan line SL to electrically connect the driving gate electrode G1 and the driving drain electrode D1 of the driving thin film transistor T1, thereby diode-connecting the driving thin film transistor T1.

[0097] The first initialization gate electrode G4 of the first initialization thin film transistor T4 is connected to the previous scan line SL-1, the first initialization source electrode S4 of the first initialization thin film transistor T4 is connected to the second initialization drain electrode D7 of the second initialization thin film transistor T7 and the initialization voltage line VL, and the first initialization drain electrode D4 of the first initialization thin film transistor T4 is connected to the lower electrode CE1 of the storage capacitor Cst, the compensation drain electrode D3 of the compensation thin film transistor T3, and the driving gate electrode G1 of the driving thin film transistor T1. The first initialization thin film transistor T4 is turned on by the previous scan signal Sn-1 transmitted through the previous scan line SL-1 to transmit the initialization voltage Vint to the driving gate electrode G1 of the driving thin film transistor T1, thereby performing an initialization operation to initialize the voltage of the driving gate electrode G1 of the driving thin film transistor T1.

[0098] The operation control gate electrode G5 of the operation control thin film transistor T5 is connected to the light emitting control line EL, the operation control source electrode S5 of the operation control thin film transistor T5 is connected to the lower driving voltage line PL, and the operation control drain electrode D5 of the operation control thin film transistor T5 is connected to the driving source electrode S1 of the driving thin film transistor T1 and the switching drain electrode D2 of the switching thin film transistor T2.

[0099] The emission control gate electrode G6 of the emission control thin film transistor T6 is connected to the emission control line EL, the emission control source electrode S6 of the emission control thin film transistor T6 is connected to the driving drain electrode D1 of the driving thin film transistor T1 and the compensation source electrode S3 of the compensation thin film transistor T3, and the emission control drain electrode D6 of the emission control thin film transistor T6 is electrically connected to the second initialization source electrode S7 of the second initialization thin film transistor T7 and the pixel electrode of the organic light emitting element OLED.

[0100] The operation control thin film transistor T5 and the emission control thin film transistor T6 are simultaneously turned on by an emission control signal En transmitted through the emission control line EL, and a driving voltage ELVDD is transmitted to the main organic light emitting element OLED, causing a driving current I OLED Make it flow.

[0101] A second initialization gate electrode G7 of the second initialization thin film transistor T7 is connected to the previous scan line SL-1, a second initialization source electrode S7 of the second initialization thin film transistor T7 is connected to the emission control drain electrode D6 of the emission control thin film transistor T6 and the pixel electrode of the main organic light emitting element OLED, and a second initialization drain electrode D7 of the second initialization thin film transistor T7 is connected to the first initialization source electrode S4 of the first initialization thin film transistor T4 and the initialization voltage line VL. The second initialization thin film transistor T7 is turned on by a previous scan signal Sn-1 transmitted through the previous scan line SL-1 to initialize the pixel electrode of the main organic light emitting element OLED.

[0102] 6 shows a case where the first initialization thin film transistor T4 and the second initialization thin film transistor T7 are connected to the previous scan line SL-1, but the present invention is not limited thereto. In another embodiment, the first initialization thin film transistor T4 is connected to the previous scan line SL-1 and driven by a previous scan signal Sn-1, and the second initialization thin film transistor T7 is connected to a separate signal line (e.g., a next scan line) and driven by a signal transmitted to the signal line.

[0103] The upper electrode CE2 of the storage capacitor Cst is connected to the driving voltage line PL, and the counter electrode of the organic light emitting element OLED is connected to a common voltage ELVSS. As a result, the organic light emitting element OLED receives a driving current I from the driving thin film transistor T1. OLED The light is transmitted to the light source, and the light is emitted to display an image.

[0104] Although FIG. 6 illustrates that the compensation thin film transistor T3 and the first initialization thin film transistor T4 have dual gate electrodes, the compensation thin film transistor T3 and the first initialization thin film transistor T4 may have one gate electrode.

[0105] Figure 7 is a schematic layout diagram of a pixel circuit of a pixel according to an embodiment of the present invention, and Figure 8 is a cross-sectional view taken along lines II' and II-II' in Figure 7.

[0106] Referring to Figures 7 and 8, the driving thin film transistor T1, the switching thin film transistor T2, the compensation thin film transistor T3, the first initialization thin film transistor T4, the operation control thin film transistor T5, the light-emitting control thin film transistor T6, and the second initialization thin film transistor T7 are arranged along the semiconductor layer 1130.

[0107] The semiconductor layer 1130 is disposed on a substrate on which a buffer layer made of an inorganic insulating material is formed. In this embodiment, the semiconductor layer 1130 includes low temperature polysilicon (LTPS). Polysilicon materials have high electron mobility (100 cm / Vs or more). ), which has low energy consumption and excellent reliability, is used in the semiconductor layer of thin film transistors in display devices. However, the present invention is not limited thereto, and in other embodiments, the semiconductor layer 1130 may be formed of amorphous silicon (a-Si) and / or an oxide semiconductor, and some semiconductor layers of a plurality of thin film transistors may be formed of low temperature polysilicon (LTPS) and other semiconductor layers may be formed of amorphous silicon (a-Si) and / or an oxide semiconductor.

[0108] Some regions of the semiconductor layer 1130 correspond to the semiconductor layers of the driving thin film transistor T1, the switching thin film transistor T2, the compensation thin film transistor T3, the first initialization thin film transistor T4, the operation control thin film transistor T5, the emission control thin film transistor T6, and the second initialization thin film transistor T7. That is, it can be understood that the semiconductor layers of the driving thin film transistor T1, the switching thin film transistor T2, the compensation thin film transistor T3, the first initialization thin film transistor T4, the operation control thin film transistor T5, the emission control thin film transistor T6, and the second initialization thin film transistor T7 are connected to each other and bent into various shapes.

[0109] The semiconductor layer 1130 includes a channel region and source and drain regions on either side of the channel region, which are understood to be the source and drain electrodes of the corresponding thin film transistor. Hereinafter, for convenience, the source and drain regions will be referred to as the source and drain electrodes, respectively.

[0110] The driving thin film transistor T1 includes a driving gate electrode G1 overlapping the driving channel region, and a driving source electrode S1 and a driving drain electrode D1 on both sides of the driving channel region. The driving channel region overlapping with the driving gate electrode G1 has an omega-shaped bent shape, forming a long channel length in a narrow space. When the driving channel region is long, the driving range of the gate voltage becomes wide, and the light emitted from the organic light emitting diode OLED becomes large. This allows for more precise control of the gradation of light emitted, improving display quality.

[0111] The switching thin film transistor T2 has a switching gate electrode G2 overlapping the switching channel region, and switching source electrodes S2 and S3 on both sides of the switching channel region. The switching drain electrode D2 is connected to the driving source electrode S1.

[0112] The compensation thin film transistor T3 is a dual thin film transistor, and includes a compensation gate electrode G3 overlapping two compensation channel regions, and a compensation source electrode S3 and a compensation drain electrode D3 disposed on both sides. The compensation thin film transistor T3 is connected to the driving gate electrode G1 of the driving thin film transistor T1 through a node connection line 1174 described below.

[0113] The first initialization thin film transistor T4 is a dual thin film transistor, and includes a first initialization gate electrode G4 overlapping two first initialization channel regions, and a first initialization source electrode S4 and a first initialization drain electrode D4 disposed on both sides.

[0114] The operation control thin film transistor T5 includes an operation control gate electrode G5 overlapping the operation control channel region, and an operation control source electrode S4 and an operation control drain electrode D5 located on both sides thereof. The operation control drain electrode D5 is connected to the driving source electrode S1.

[0115] The light-emitting control thin film transistor T6 includes a light-emitting control gate electrode G6 overlapping the light-emitting control channel region, and a light-emitting control source electrode S6 and a light-emitting control drain electrode D6 located on both sides. The light-emitting control source electrode S6 is connected to the driving drain electrode D1.

[0116] The second initialization thin film transistor T7 includes a second initialization gate electrode G7 overlapping the second initialization channel region, and a second initialization source electrode S7 and a second initialization drain electrode D7 located on both sides thereof.

[0117] The above-mentioned thin film transistors are connected to the signal lines SL, SL-1, EL, DL, the initialization voltage line VL, and the drive voltage line PL.

[0118] On the semiconductor layer 1130, the scan line SL, the previous scan line SL-1, the light emitting control line EL, and the driving gate electrode G1 are arranged with an insulating layer sandwiched therebetween.

[0119] The scan lines SL extend along a first direction DR1. A region of the scan line SL corresponds to the switching and compensation gate electrodes G2 and G3. For example, the regions of the scan line SL overlapping with the channel regions of the switching and compensation thin film transistors T2 and T3 correspond to the switching and compensation gate electrodes G2 and G3, respectively.

[0120] The previous scan line SL-1 extends along the first direction DR1, and some regions of the previous scan line SL-1 correspond to the first and second initialization gate electrodes G4 and G7, respectively. For example, the regions of the previous scan line SL-1 that overlap with the channel regions of the first and second initialization driving thin film transistors T4 and T7 correspond to the first and second initialization gate electrodes G4 and G7, respectively.

[0121] The emission control line EL extends along the first direction DR1. Regions of the emission control line EL correspond to the operation control and emission control gate electrodes G5 and G6, respectively. For example, regions of the emission control line EL that overlap with the channel regions of the operation control and emission control driving thin film transistors T6 and T7 correspond to the operation control and emission control gate electrodes G5 and G6, respectively.

[0122] The driving gate electrode G1 is a floating electrode, and is connected to the compensation thin film transistor T3 through the node connection line 1174 described above.

[0123] An electrode voltage line HL is arranged above the scan line SL, previous scan line SL-1, light emission control line EL, and drive gate electrode G1 with an insulating layer sandwiched therebetween.

[0124] The electrode voltage line HL extends in a first direction DR1 to cross the data line DL and the driving voltage line PL. A portion of the electrode voltage line HL covers at least a portion of the driving gate electrode G1 and forms a storage capacitor Cst together with the driving gate electrode G1. For example, the driving gate electrode G1 becomes the lower electrode CE1 of the storage capacitor Cst, and a portion of the electrode voltage line HL becomes the upper electrode CE2 of the storage capacitor Cst. The upper electrode CE2 of the storage capacitor Cst is electrically connected to the driving voltage line PL. In this regard, the electrode voltage line HL is connected to the driving voltage line PL disposed on the electrode voltage line HL through a contact hole CNT. Therefore, the electrode voltage line HL has the same voltage level (constant voltage) as the driving voltage line PL. For example, the electrode voltage line HL has a constant voltage of +5V. The electrode voltage line HL can be understood as a lateral driving voltage line.

[0125] The driving voltage lines PL extend along the second direction DR2, and the electrode voltage lines HL electrically connected to the driving voltage lines PL extend along the first direction DR1 that intersects with the second direction DR2, so that the multiple driving voltage lines PL and electrode voltage lines HL form a mesh structure in the display area.

[0126] On the electrode voltage line HL, a data line DL, a driving voltage line PL, an initialization connection line 1173, and a node connection line 1174 are arranged with an insulating layer sandwiched therebetween.

[0127] The data line DL extends in the second direction DR2 and is connected to the switching source electrode S2 of the switching thin film transistor T2 through the contact hole 1154. A part of the data line DL is understood to be the switching source electrode.

[0128] The driving voltage line PL extends in the second direction DR2 and is connected to the electrode voltage line HL through the contact hole CNT as described above. It is also connected to the operation control thin film transistor T5 through the contact hole 1155. The driving voltage line PL is connected to the operation control drain electrode D5 through the contact hole 1155.

[0129] One end of the initialization connection line 1173 is connected to the first and second initialization thin film transistors T4 and T7 through a contact hole 1152, and the other end is connected to an initialization voltage line VL (to be described later) through a contact hole 1151.

[0130] One end of the node connection line 1174 is connected to the compensation drain electrode D3 through a contact hole 1156, and the other end is connected to the drive gate electrode G1 through a contact hole 1157.

[0131] An initialization voltage line VL is disposed on the data line DL, the drive voltage line PL, the initialization connection line 1173, and the node connection line 1174 with an insulating layer sandwiched therebetween.

[0132] The initialization voltage line VL extends in the first direction DR1 and is connected to the first and second initialization driving thin film transistors T4 and T7 through an initialization connection line 1173. The initialization voltage line VL has a constant voltage (for example, −2V).

[0133] The initialization voltage line VL is disposed on the same layer as the pixel electrode 210 of the organic light emitting diode OLED (FIG. 8), and contains the same material as the pixel electrode 210. The pixel electrode 210 is connected to the light emitting control thin film transistor T6. The pixel electrode 210 is connected to the connection metal 1175 through the contact hole 1163, and the connection metal 1175 is connected to the connection metal 1175 through the contact hole 1153. and connected to the light emission control drain electrode D6.

[0134] Although FIG. 7 illustrates that the initialization voltage line VL is disposed on the same layer as the pixel electrode 210, in other embodiments, the initialization voltage line VL is disposed on the same layer as the electrode voltage line HL.

[0135] Hereinafter, a stacked structure included in a display panel according to an embodiment of the present invention will be described with reference to FIG.

[0136] The substrate 100 includes glass or a polymer resin. The polymer resin may be polyethersulfone (PES), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), poly Examples of suitable polymer resins include ethylene terephthalate (PET), polyphenylene sulfide (PPS), polyimide (PI), polycarbonate (PC), and cellulose acetate propionate (CAP). The substrate 100 containing the polymer resin has flexible, rollable, or bendable properties. The substrate 100 may also have a multilayer structure including a layer containing the aforementioned polymer resin and an inorganic layer (not shown).

[0137] The buffer layer 111 is located on the substrate 100 and reduces or blocks penetration of foreign matter, moisture, or external air from underneath the substrate 100, and provides a flat surface on the substrate 100. The buffer layer 111 may include an inorganic material such as an oxide or a nitride, an organic material, or an organic-inorganic composite, and may have a single-layer or multi-layer structure of an inorganic material and an organic material. A barrier layer (not shown) that blocks penetration of external air may be further included between the substrate 100 and the buffer layer 111.

[0138] Gate electrodes G1 and G6 are disposed on the semiconductor layers A1 and A6, sandwiching a first gate insulating layer 112 therebetween. The gate electrodes G1 and G6 are formed of a single layer or multiple layers containing molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc. As an example, the gate electrodes G1 and G6 are also formed of a single layer of Mo. The scan line SL (see FIG. 7), the previous scan line SL-1, and the light-emitting control line EL are formed in the same layer as the gate electrodes G1 and G6. That is, the gate electrodes G1 and G6, the scan line SL (see FIG. 7), the previous scan line SL-1, and the light-emitting control line EL are disposed on the first gate insulating layer 112.

[0139] The first gate insulating layer 112 includes silicon oxide (SiO2), silicon nitride (SiNx), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2), etc.

[0140] A second gate insulating layer 113 is provided to cover the gate electrodes G1 and G6. The second gate insulating layer 113 includes silicon oxide (SiO2), silicon nitride (SiNx), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), zinc oxide (ZnO2), or the like.

[0141] The lower electrode CE1 of the storage capacitor Cst is integrally formed with the driving gate electrode G1 of the driving thin film transistor T1, for example, the driving gate electrode G1 of the driving thin film transistor T1 can function as the lower electrode CE1 of the storage capacitor Cst.

[0142] The upper electrode CE2 of the storage capacitor Cst overlaps with the lower electrode CE1 with the second gate insulating layer 113 sandwiched therebetween. In this case, the second gate insulating layer 113 is The upper electrode CE2 functions as a dielectric layer for the upper electrode CE2. The upper electrode CE2 includes a conductive material such as molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and is formed of a single layer or multiple layers including the above materials. For example, the upper electrode CE2 can be a single layer of Mo or a multilayer of Mo / Al / Mo.

[0143] Although the storage capacitor Cst is illustrated as overlapping with the driving thin film transistor T1 in the drawings, the present invention is not limited thereto, and various modifications are possible, such as arranging the storage capacitor Cst so as not to overlap with the driving thin film transistor T1.

[0144] The upper electrode CE2 functions as an electrode voltage line HL. For example, a part of the electrode voltage line HL also serves as the upper electrode CE2 of the storage capacitor Cst.

[0145] An interlayer insulating layer 115 is provided to cover the upper electrode CE2. The interlayer insulating layer 115 may include silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), aluminum oxide (AlO), titanium oxide (TiO), tantalum oxide (TaO), hafnium oxide (HfO), zinc oxide (ZnO), or the like. Although the interlayer insulating layer 115 is illustrated as a single layer in FIG. 8, in one embodiment, the interlayer insulating layer 115 may have a multi-layer structure.

[0146] The data lines DL, the driving voltage lines PL, and the connection metal 1175 are disposed on the interlayer insulating layer 115. The data lines DL, the driving voltage lines PL, and the connection metal 1175 may include conductive materials such as molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may be formed as a single layer or multilayer including the above materials. For example, the data lines DL, the driving voltage lines PL, and the connection metal 1175 may have a Ti / Al / Ti multilayer structure.

[0147] The upper electrode CE2 of the storage capacitor Cst is connected to the driving voltage line PL through a contact hole CNT defined in the interlayer insulating layer 115. This means that the electrode voltage line HL is connected to the driving voltage line PL through the contact hole CNT. Therefore, the electrode voltage line HL has the same voltage level (constant voltage) as the driving voltage line PL.

[0148] The connection metal 1175 is connected to the semiconductor layer A6 of the emission control thin film transistor T6 through a contact hole 1153 that penetrates the interlayer insulating layer 115, the second gate insulating layer 113, and the first gate insulating layer 112. The emission control thin film transistor T6 is electrically connected to the pixel electrode 210 of the organic light emitting diode OLED through the connection metal 1175.

[0149] A planarization layer 117 is disposed on the data lines DL, the driving voltage lines PL, and the connection metal 1175, and an organic light emitting diode OLED is disposed on the planarization layer 117.

[0150] The planarization layer 117 has a flat upper surface so that the pixel electrode 210 is formed flat. The planarization layer 117 is formed of a single layer or multiple layers of an organic material film. Such a planarization layer 117 can be made of a common material such as BCB (Benzocyclobutene), polyimide, HMDSO (Hexamethyldisiloxane), PXMMA (Polymethylmethacrylate), or polystyrene (PS). Examples of suitable planarization layers include general-purpose polymers, polymer derivatives having phenolic groups, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorine-based polymers, p-xylene polymers, vinyl alcohol polymers, and blends thereof. The planarization layer 117 may include an inorganic material. Examples of suitable planarization layers include silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), aluminum oxide (AlO), titanium oxide (TiO), tantalum oxide (TaO), hafnium oxide (HfO), and the like. The planarization layer 117 may include, for example, inorganic materials such as silicon dioxide (SiO2), zinc oxide (ZnO2), etc. If the planarization layer 117 includes an inorganic material, it may improve chemical planarization polishing depending on the case. On the other hand, the planarization layer 117 may include both organic and inorganic materials.

[0151] The pixel electrode 210 may also be a (semi-)transparent electrode or a reflective electrode. In some embodiments, the pixel electrode 210 includes a reflective film made of Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, or a compound thereof, and a transparent or semi-transparent electrode layer formed on the reflective film. The transparent or semi-transparent electrode layer may be made of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium tin oxide (IZO). In some embodiments, the pixel electrode 210 may have a stacked structure of ITO / Ag / ITO.

[0152] A pixel defining film 119 is disposed on the planarization layer 117. The pixel defining film 119 has an opening 119OP that exposes the center of the pixel electrode 210, thereby defining the light-emitting area of ​​the pixel. The pixel defining film 119 also increases the distance between the edge of the pixel electrode 210 and the counter electrode 230 above the pixel electrode 210, thereby preventing arcs from occurring at the edge of the pixel electrode 210. The pixel defining film 119 is made of a material such as polyimide, polyamide, and aluminum. Acrylic resin, benzocyclobutene, HMDSO (hexamethyldisiloxane) and phenolic resin The insulating layer is formed by a method such as spin coating using an organic insulating material.

[0153] The intermediate layer 220 of the organic light-emitting diode OLED includes an organic light-emitting layer. The organic light-emitting layer includes an organic material containing a fluorescent or phosphorescent material that emits red, green, blue, or white light. The organic light-emitting layer is a low-molecular-weight organic material or a high-molecular-weight organic material. Functional layers such as a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL), and an electron injection layer (EIL) are optionally disposed below and above the organic light-emitting layer. The intermediate layer 220 is disposed corresponding to each of the plurality of pixel electrodes 210. However, the configuration is not limited thereto. The intermediate layer 220 can be variously modified, such as including a layer that is integral across the plurality of pixel electrodes 210.

[0154] The counter electrode 230 may be a light-transmitting electrode or a reflective electrode. In some embodiments, the counter electrode 230 may be a transparent or semi-transparent electrode formed of a thin metal film with a low work function, such as Li, Ca, LiF / Ca, LiF / Al, Al, Ag, Mg, or a compound thereof. A transparent conductive oxide (TCO) film, such as ITO, IZO, ZnO, or In2O3, may be disposed on the thin metal film.

[0155] When the pixel electrode 210 is provided as a reflective electrode and the counter electrode 230 is provided as a translucent electrode, light emitted from the intermediate layer 220 is emitted toward the counter electrode 230, and the display device can also be a front-emitting type. When the pixel electrode 210 is configured as a transparent or semi-transparent electrode and the counter electrode 230 is configured as a reflective electrode, light emitted from the intermediate layer 220 is emitted toward the substrate 100, and the display device can also be a back-emitting type. However, this embodiment is not limited to this. The display device of this embodiment may also be a double-sided emission type that emits light in both the front and back directions.

[0156] In this embodiment, the counter electrode 230 is disposed over the entire second display area DA2, with a portion of its edge located in the non-display area NDA. The counter electrode 230 is integrally formed with the main pixels PXm located in the second display area DA2, i.e., the plurality of organic light emitting diodes OLED, and corresponds to the plurality of pixel electrodes 210.

[0157] On the other hand, the counter electrode 230 is also provided in the auxiliary pixel PXa located in the first display area DA1. However, the first display area DA1 includes the auxiliary pixel area PA1 where the auxiliary pixel PXa is located and the transmissive area TA, and a portion of the counter electrode 230 is not provided in the area corresponding to the transmissive area TA. Of course, in the case of a top-emission type display device, light is emitted toward the counter electrode 230, but the transmittance is partially reduced by the counter electrode 230. Therefore, by not providing the counter electrode 230 in the area corresponding to the transmissive area TA, the transmittance of the transmissive area TA can be improved.

[0158] To this end, the counter electrode 230 disposed in the first display area DA1 may have a patterned shape for each auxiliary pixel area PA1. The counter electrode 230 disposed in the first display area DA1 may be formed by removing a portion of the area corresponding to the transmissive area TA using laser lift-off, or may be formed using FMM mask patterning. Hereinafter, in this embodiment, it is assumed that the counter electrode 230 is formed in the first display area DA1 using FMM mask patterning.

[0159] 9 and 10 are plan views showing a portion of a first display area according to an embodiment of the present invention.

[0160] 9 and 10, as described above, the first display area DA1 includes an auxiliary pixel area PA1 and a transmissive area TA, and auxiliary pixels PXa are arranged in the auxiliary pixel area PA1. The auxiliary pixel area PA1 includes a first pixel area PA1-1 and a second pixel area PA1-2, as shown in FIG. 9, and a plurality of first pixels PXa1 are arranged in the first pixel area PA1-1, and a plurality of second pixels PXa2 are arranged in the second pixel area PA1-2.

[0161] In this embodiment, a first opposing electrode 230a is provided on the first pixel region PA1-1, and a second opposing electrode 230b is provided on the second pixel region PA1-2. The first opposing electrode 230a is disposed corresponding to the first pixel region PA1-1, and the second opposing electrode 230b is disposed corresponding to the second pixel region PA1-2. The first opposing electrode 230a and the second opposing electrode 230b are in contact with each other in a partial region. In this case, the shapes of the first opposing electrode 230a and the second opposing electrode 230b are the same.

[0162] 10, a plurality of first pixels PXa1 are disposed on the first pixel region PA1-1. Each of the first pixels PXa1 includes a scan line to which a scan signal is supplied and a data line to which a data signal is supplied. The scan lines extend along a first direction DR1, and the data lines extend along a second direction DR2 that intersects with, for example, is perpendicular to, the first direction DR1. It goes without saying that other signal lines PL, EL, SL-1, and VL (FIG. 7) may also be disposed on the first pixel region PA1-1.

[0163] The data lines and some of the scan lines are located on the transparent area TA. In this case, for example, the scan lines have a detour area arranged around the edge of the transparent area TA to improve the transmittance of the transparent area TA. Such a detour area is also applied to the other signal lines PL, EL, SL-1, and VL (FIG. 7).

[0164] The plurality of first pixels PXa1 arranged on the first pixel region PA1-1 include a first counter electrode 230a formed integrally on one first pixel region PA1-1.

[0165] The plurality of second pixels PXa2 arranged on the second pixel region PA1-2 include a second counter electrode 230b formed integrally on one second pixel region PA1-2.

[0166] The first pixel region PA1-1 and the second pixel region PA1-2 are arranged on different lines. In this case, the first pixel region PA1-1 and the second pixel region PA1-2 are arranged to surround the transmission region TA. That is, the first pixel region PA1-1 and the second pixel region PA1 -2 are arranged in a zigzag pattern.

[0167] The first opposing electrode 230a and the second opposing electrode 230b are disposed corresponding to the first pixel region PA1-1 and the second pixel region PA1-2, respectively, and are in contact with each other in some regions. The first opposing electrode 230a and the second opposing electrode 230b have a first contact region CTA1 where they are in contact with each other in the region where the first pixel region PA1-1 and the second pixel region PA1-2 are adjacent, and are electrically connected to each other through the first contact region CTA1.

[0168] In the above case, the first opposing electrode 230a and the second opposing electrode 230b are connected to each other through the first contact area CTA1, thereby improving the resistance of the opposing electrodes 230a and 230b arranged on the first display area DA1.

[0169] 11 and 12 are cross-sectional views schematically showing a part of a manufacturing process of a display panel according to an embodiment of the present invention, and Fig. 13 is a cross-sectional view schematically showing a cross section taken along line BB' in Fig. 9.

[0170] 11 to 13, an insulating layer IL in which a pixel circuit PC is located is formed on a substrate 100, and a first pixel electrode 210a and a second pixel electrode 210b electrically connected to the pixel circuit PC are formed on the insulating layer IL. The first pixel electrode 210a is disposed in a first pixel area PA1-1, and the second pixel electrode 210b is disposed in a second pixel area PA1-2.

[0171] A pixel defining layer 119 having openings exposing the central portions of the first and second pixel electrodes 210a and 210b is formed on the first and second pixel electrodes 210a and 210b, respectively. A first intermediate layer 220a and a second intermediate layer 220b are formed on the first and second pixel electrodes 210a and 210b, respectively, exposed through the openings in the pixel defining layer 119. The first and second intermediate layers 220a and 220b are understood to be made of the same material as the intermediate layer 220 described above in FIG. 8.

[0172] Then, a first opposing electrode 230a and a second opposing electrode 230b are formed on the first intermediate layer 220a and the second intermediate layer 220b. In this embodiment, the first opposing electrode 230a and the second opposing electrode 230b are formed through different processes. In this case, the same mask sheet 422 of a mask assembly (not shown) described below is used to form the first opposing electrode 230a and the second opposing electrode 230b. That is, the second opposing electrode 230b is formed on the substrate 100 after the first opposing electrode 230a is formed and at least one of the mask assembly and the substrate 100 is moved to a position different from its initial position. In another embodiment, the first opposing electrode 230a may be formed on the substrate 100 after the second opposing electrode 230b is formed and at least one of the mask assembly and the substrate 100 is moved to a position different from its initial position. For the sake of convenience, the following detailed description will be focused on the case where the position of the substrate 100 is moved after the first opposing electrode 230a is formed, and the second opposing electrode 230b is formed.

[0173] Specifically, as shown in Fig. 11, a first opposing electrode 230a is formed on a first intermediate layer 220a. The first opposing electrode 230a is formed by depositing a deposition material that has passed through a first opening 422a of a mask sheet 422 onto a substrate 100. Thereafter, as shown in Fig. 12, the substrate 100 is moved to the left in Fig. 11, and a second opposing electrode 230b is formed on a second intermediate layer 220b. The second opposing electrode 230b is formed through the first opening 422a of the mask sheet 422.

[0174] 13, the first opposing electrode 230a and the second opposing electrode 230b formed as described above are in surface contact with each other at the first contact region CTA1. The surface contact between the first opposing electrode 230a and the second opposing electrode 230b means that no layer is interposed between the first opposing electrode 230a and the second opposing electrode 230b, and the second opposing electrode 230b is stacked on the first opposing electrode 230a, resulting in contact with each other.

[0175] In the first contact region CTA1, the second opposing electrode 230b is disposed on the first opposing electrode 230a. This means that the second opposing electrode 230b is formed in a process subsequent to the first opposing electrode 230a. In another embodiment, when the second opposing electrode 230b is formed in a process subsequent to the first opposing electrode 230a, the first opposing electrode 230a is disposed on the second opposing electrode 230b in the first contact region CTA1. The first contact region CTA1 is formed to a thickness approximately twice or less than that of a region in which only the first opposing electrode 230a or the second opposing electrode 230b is disposed, due to the surface contact between the first opposing electrode 230a and the second opposing electrode 230b. In addition, it is preferable that the first contact region CTA1 is not disposed on the light-emitting regions of the first pixel PXa1 and the second pixel PXa2. In this case, the "light emitting region" is defined as first and second openings OP1 and OP2 formed in the pixel defining layer 119 and exposing the central portions of the first and second pixel electrodes 210a and 210b, respectively. That is, the first contact region CTA1 is provided so as not to overlap with the first and second openings OP1 and OP2 formed in the pixel defining layer 119.

[0176] A larger area of ​​the first contact region CTA1 is more advantageous in reducing the resistance of the counter electrodes 230a and 230b. However, as described above, if the area of ​​the first contact region CTA1 is increased beyond a certain level, it will overlap with the light-emitting regions of the pixels PXa1 and PXa2, which will cause a decrease in the light-emitting quality of the pixels PXa1 and PXa2.

[0177] Therefore, the area of ​​the first contact region CTA1 is formed to such an extent that it does not block the first opening OP1 and the second opening OP2.

[0178] 11 and 13, the transmissive region TA does not include a display element such as an organic light emitting element (OLED) and a pixel circuit PC electrically connected thereto, unlike the first pixel region PA1-1, and is defined as a region where a portion of a layer disposed on the substrate 100 is removed.

[0179] Fig. 14 is a plan view showing the arrangement of counter electrodes of a display panel according to an embodiment of the present invention. Fig. 15 is a cross-sectional view schematically showing a cross section taken along line CC' in Fig. 14. Fig. 16 is a cross-sectional view schematically showing a cross section taken along line DD' in Fig. 14. Fig. 17 is a cross-sectional view schematically showing a cross section taken along line EE' in Fig. 14.

[0180] 14 to 17, as described above, the first display area DA1 includes a first pixel area PA1-1, a second pixel area PA1-2, and a transmissive area TA. In this case, a first opposing electrode 230a is disposed in the first pixel area PA1-1, and a second opposing electrode 230b is disposed in the second pixel area PA1-2. In this case, the first display area DA1 is formed as described in FIG.

[0181] The second display area DA2 includes a main pixel area PA2, which includes a third pixel area PA2-1 and a fourth pixel area PA2-2 adjacent to each other, in which a third opposing electrode 230c and a fourth opposing electrode 230d are disposed, respectively.

[0182] In this case, the third opposing electrode 230c is formed simultaneously with the first opposing electrode 230a, and the fourth opposing electrode 230d is formed simultaneously with the second opposing electrode 230b. In this case, the third opposing electrode 230c and the fourth opposing electrode 230d have the same shape because they are formed using the same mask assembly.

[0183] The third opposing electrode 230c and the fourth opposing electrode 230d are formed in a line shape and are integrated. A plurality of the third opposing electrodes 230c and the fourth opposing electrodes 230d are provided. In this case, when the third opposing electrode 230c and the fourth opposing electrode 230d are formed in a line, the third opposing electrode 230c is arranged in a line with the first opposing electrode 230a, and the fourth opposing electrode 230d is arranged in a line with the second opposing electrode 230b. The third opposing electrodes 230c and the fourth opposing electrodes 230d are arranged alternately in a direction different from the direction in which the first opposing electrode 230a and the third opposing electrode 230c are arranged in a line. In this case, the adjacent third opposing electrodes 230c and the fourth opposing electrodes 230d include overlapping regions, and the third opposing electrodes 230c and the fourth opposing electrodes 230d are in surface contact with each other in such overlapping regions. In this case, the third opposing electrodes 230c and the fourth opposing electrodes 230d are connected to each other to cover the entire second display region DA2.

[0184] In another embodiment, a plurality of third opposing electrodes 230c and a plurality of fourth opposing electrodes 230d are provided. When a plurality of third opposing electrodes 230c and a plurality of fourth opposing electrodes 230d are provided, the plurality of third opposing electrodes 230c are arranged in a line with the first opposing electrodes 230a, and the plurality of fourth opposing electrodes 230d are arranged in a line with the second opposing electrodes 230b. Furthermore, the third opposing electrodes 230c and the fourth opposing electrodes 230d are alternately arranged and at least partially overlap each other. In this case, adjacent third opposing electrodes 230c and fourth opposing electrodes 230d are connected to each other. In this case, the plurality of third opposing electrodes 230c arranged in a line are connected to each other in the direction of arrangement. In another embodiment, the plurality of third opposing electrodes 230c may be arranged spaced apart in the arrangement direction, and adjacent third opposing electrodes 230c arranged in a row may be connected by a fourth opposing electrode 230d. In this case, the fourth opposing electrodes 230d may also be connected to each other in a row similar to the third opposing electrodes 230c, but adjacent fourth opposing electrodes 230d may be connected through the third opposing electrode 230c, and adjacent fourth opposing electrodes 230d may not be connected to each other in a row, but may be connected through the third opposing electrode 230c. For ease of explanation, the following description will focus on the case where a plurality of third opposing electrodes 230c and a plurality of fourth opposing electrodes 230d are provided, and adjacent third opposing electrodes 230c are arranged in a row, adjacent third opposing electrodes 230c and fourth opposing electrodes 230d are arranged in a row, and adjacent fourth opposing electrodes 230d are connected to each other.

[0185] In this case, the third opposing electrode 230c and the fourth opposing electrode 230d, which are connected to each other, include a second contact region CTA2 that overlaps each other. In this case, the thickness of the second contact region CTA2 is greater than either the thickness of the third opposing electrode 230c or the thickness of the fourth opposing electrode 230d, as described above. In this case, in the second contact region CTA2, either the third opposing electrode 230c or the fourth opposing electrode 230d directly contacts the top surface of the other of the third opposing electrode 230c or the fourth opposing electrode 230d, depending on the order in which the third opposing electrode 230c and the fourth opposing electrode 230d are formed. In this case, the third opposing electrode 230c and the fourth opposing electrode 230d are in surface contact with each other. For convenience of explanation, the following detailed description will focus on the case in which the fourth opposing electrode 230d is disposed on the third opposing electrode 230c, as shown in FIG. 15.

[0186] Meanwhile, a sixth contact region CTA6 may be formed in the second contact region CTA2 as needed. In such a case, two adjacent third opposing electrodes 230c are arranged in a line in the sixth contact region CTA6, and one or two fourth opposing electrodes 230d are arranged on the third opposing electrodes 230c. In another embodiment, two overlapping fourth opposing electrodes 230d are arranged in a line in the sixth contact region CTA6, and one or two third opposing electrodes 230c are arranged on the fourth opposing electrodes 230d. In this case, all opposing electrodes arranged in the sixth contact region CTA6 are arranged to be in surface contact with each other. In addition, the total thickness of the opposing electrodes arranged in the sixth contact region CTA6 is less than the thickness of the third opposing electrodes 230c or the fourth opposing electrodes 230d. Of these, one is thicker than the other.

[0187] One of the third opposing electrodes 230c or the fourth opposing electrodes 230d protrudes into the first display region DA1. For example, among the plurality of third opposing electrodes 230c, a portion of the third opposing electrode 230c closest to the first display region DA1 protrudes into the first display region DA1 and is disposed in the first display region DA1. In another embodiment, among the plurality of fourth opposing electrodes 230d, a portion of the fourth opposing electrode 230d closest to the first display region DA1 protrudes into the first display region DA1 and is disposed in the first display region DA1. For convenience of explanation, the following detailed description will focus on the case where a portion of the fourth opposing electrode 230d closest to the first display region DA1 is disposed in the first display region DA1.

[0188] A portion of the fourth opposing electrode 230d disposed in the first display area DA1 includes a third contact area CTA3 overlapping with the first opposing electrode 230a. In this case, in the third contact area CTA3, one of the first opposing electrode 230a or the fourth opposing electrode 230d is disposed in surface contact with the other of the first opposing electrode 230a or the fourth opposing electrode 230d, depending on the manufacturing order, as shown in FIG. 16. In this case, even when the second opposing electrode 230b and the third opposing electrode 230c overlap in the third contact area CTA3, although not shown in FIG. 14, the arrangement is similar to the arrangement of the first opposing electrode 230a and the fourth opposing electrode 230d described above.

[0189] Adjacent third opposing electrodes 230c arranged in a row overlap each other to form a fourth contact area CTA4. Adjacent fourth opposing electrodes 230d arranged in a row overlap each other to form a fifth contact area CTA5. The thickness of the fourth contact area CTA4 and the fifth contact area CTA5 is approximately the same as the thickness of one of the third opposing electrodes 230c and the fourth opposing electrode 230d. Specifically, when forming adjacent third opposing electrodes 230c, a portion of the deposition material passing through the openings in a mask sheet (not shown) is deposited on the substrate 100 located behind the mask sheet portions located between the openings. In this case, when the third opposing electrode 230c is formed by deposition on the substrate 100 disposed on the rear surface between the openings of the mask sheet, the thickness of the third opposing electrode 230c is thinner than the thickness of the other parts of the third opposing electrode 230c. Similarly to the third opposing electrode 230c, when the fourth opposing electrode 230d is formed, the thickness of a part of the fourth opposing electrode 230d is different from the thickness of the other parts of the fourth opposing electrode 230d.

[0190] Therefore, the thickness of each third opposing electrode 230c overlapping each other in the fourth contact region CTA4 is thinner than the thickness of other parts of the third opposing electrodes 230c, and when the third opposing electrodes 230c overlap each other, the thickness becomes approximately similar to the thickness of other parts of the third opposing electrodes 230c. Furthermore, the fifth contact region CTA5 where the fourth opposing electrodes 230d overlap each other also has a structure similar to that of the fourth contact region CTA4.

[0191] At least one pixel is arranged in each of the first pixel region PA1-1, second pixel region PA1-2, third pixel region PA2-1, and fourth pixel region PA2-2. For example, a first pixel PXa1 is arranged in the first pixel region PA1-1, and a second pixel PXa2 is arranged in the second pixel region PA1-2. A third pixel PXm1 is arranged in the third pixel region PA2-1, and a fourth pixel PXm2 is arranged in the fourth pixel region PA2-2. In this case, the third pixel PXm1 and the fourth pixel PXm2 include a third intermediate layer 220c and a fourth intermediate layer 220d, respectively. Such pixels may be the same as or similar to those described above.

[0192] Fig. 18 is a perspective view showing a display device according to another embodiment of the present invention, and Fig. 19 is a plan view schematically showing a display area and a non-display area of ​​a display panel according to another embodiment of the present invention.

[0193] 18 and 19, the display device 1 is similar to that shown in Fig. 1. In this case, the display device 1 includes a first display area DA1, a second display area DA2, and a non-display area NDA.

[0194] Unlike in FIG. 1, the first display region DA1 is also a fixed region of the display device 1. The first display region DA1 has a similar shape to the second display region DA2. For example, the first display region DA1 is formed long in the X-axis direction. The first display region DA1 has a higher light transmittance than the second display region DA2, and the resolution of the first display region DA1 is lower than the resolution of the second display region DA2. As described above, the auxiliary pixels PXa are arranged in the first display region DA1, and the main pixels PXm are arranged in the second display region DA2. The first display region DA1 also includes a transmissive region TA where the auxiliary pixels PXa are not arranged.

[0195] Components are arranged at various positions in the first display area DA1, and at least one component is arranged in the first display area DA1.

[0196] The first display area DA1 includes a first pixel area PA1-1, a second pixel area PA1-2, and a transmissive area TA. The first pixel area PA1-1 and the second pixel area PA1-2 are alternately arranged, and the transmissive area TA is defined by the adjacent first pixel area PA1-1 and second pixel area PA1-2. In particular, the transmissive area TA is shielded by the first pixel area PA1-1 and the second pixel area PA1-2, which are connected to each other. A first counter electrode 230a and a second counter electrode 230b are arranged in the first pixel area PA1-1 and the second pixel area PA1-2, respectively. They are connected by overlapping each other via a first contact area CTA1. A first pixel PXa1 and a second pixel PXa2 are arranged in the first pixel area PA1-1 and the second pixel area PA1-2, respectively. In addition, one of the third opposing electrode 230c or the fourth opposing electrode 230d is arranged to protrude into the first display area DA1. In this case, one of the third opposing electrode 230c or the fourth opposing electrode 230d overlaps the first opposing electrode 230a or the second opposing electrode 230b in the first display area DA1. For convenience of explanation, the following description will focus on the case where the first opposing electrode 230a and the fourth opposing electrode 230d overlap each other. In such a case, the first opposing electrode 230a and the fourth opposing electrode 230d include a third contact area CTA3 arranged to overlap each other.

[0197] The second display area DA2 includes a third pixel area PA2-1 and a fourth pixel area PA2-2. The third pixel area PA2-1 and the fourth pixel area PA2-2 have the same shape and are arranged alternately. A third opposing electrode 230c and a fourth opposing electrode 230d are arranged in the third pixel area PA2-1 and the fourth pixel area PA2-2, respectively. A third pixel PXm1 and a fourth pixel PXm2 are arranged in the third pixel area PA2-1 and the fourth pixel area PA2-2, respectively.

[0198] The first opposing electrode 230a arranged in the first display area DA1 and the third opposing electrode 230c arranged in the second display area DA2 are arranged in a line, and the second opposing electrode 230b and the fourth opposing electrode 230d are also arranged in a line. That is, the first opposing electrode 230a and the third opposing electrode 230c form one line, and the second opposing electrode 230b and the fourth opposing electrode 230d are also arranged to form one line.

[0199] A plurality of the third opposing electrodes 230c are provided, and the third opposing electrodes 230c arranged in a line are at least partially overlapped with each other. The fourth opposing electrodes 230d are arranged in a row and at least partially overlap each other. Furthermore, the adjacent third opposing electrodes 230c and fourth opposing electrodes 230d also at least partially overlap each other. The overlapping third opposing electrodes 230c and fourth opposing electrodes 230d include a second contact region CTA2, the overlapping third opposing electrodes 230c include a fourth contact region CTA4, and the overlapping fourth opposing electrodes 230d include a fifth contact region CTA5. The fourth opposing electrode 230d is disposed in the fourth contact region CTA4, and the fourth opposing electrode 230d overlaps the third opposing electrode 230c or the fifth contact region CTA5. A sixth contact region CTA6, where the third opposing electrode 230c overlaps the fourth opposing electrode 230d, is disposed in at least one of the fourth contact region CTA4 and the fifth contact region CTA5.

[0200] The first to sixth contact regions CTA1 to CTA6 are the same as or similar to those described with reference to FIGS. 9 to 17, and therefore detailed description thereof will be omitted.

[0201] When the first to fourth opposing electrodes 230a to 230d are arranged as described above, the first opposing electrode 230a and the fourth opposing electrode 230d are connected to each other. In this case, as described above, the transmissive area TA is arranged between the first opposing electrode 230a and the second opposing electrode 230b, so that light generated from components arranged on the first display area DA1 and light incident on the components are not blocked.

[0202] Furthermore, the counter electrodes that overlap each other in the contact region where they overlap each other are in surface contact with each other, which reduces the resistance on the counter electrodes, and therefore the display device 1 operates stably.

[0203] 20 is a cross-sectional view schematically illustrating an apparatus for manufacturing a display device according to an embodiment of the present invention, and FIG. 21 is a plan view illustrating a portion of an embodiment of the mask sheet illustrated in FIG.

[0204] 20 and 21, the display panel (not shown) of the display device 1 is manufactured by a manufacturing apparatus 400 for the display device.

[0205] The display device manufacturing apparatus 400 includes a chamber 410, a mask assembly 420, a first support unit 430, a second support unit 440, a deposition source 450, a magnetic force generating unit 460, a vision unit 470, and a pressure adjusting unit 480.

[0206] The chamber 410 has a space formed therein, and a part of the chamber 410 is formed to be open. In this case, a gate valve 411 is disposed in the open part of the chamber 410 so as to be able to open and close.

[0207] The mask assembly 420 is selectively disposed inside the chamber 410. In this case, the mask assembly 420 includes a mask frame 421 and a mask sheet 422. The mask frame 421 is formed by connecting a plurality of frames together and includes an opening therein. In this case, the mask frame 421 includes one opening or a plurality of openings separated from each other. In this case, the mask frame 421 is formed in a lattice shape like a window frame. The mask sheet 422 is fixed in a tensioned state to the mask frame 421. In this case, the mask sheet 422 has openings arranged therein so that the deposition material can pass through.

[0208] The mask sheet 422 includes first openings 422a through which the deposition material passes to form the first opposing electrode (not shown) or the second opposing electrode (not shown). The mask sheet 422 also includes first openings 422a through which the deposition material passes to form the third opposing electrode (not shown) or the fourth opposing electrode (not shown). The first opening 422a and the second opening 422b include two openings 422b. In this case, the first opening 422a and the second opening 422b may have various shapes. For example, the shape of the first opening 422a and the shape of the second opening 422b may be the same. In another embodiment, the shape of the first opening 422a and the shape of the second opening 422b may be different. For convenience of explanation, the following detailed description will focus on the case where the shape of the first opening 422a and the shape of the second opening 422b are different from each other.

[0209] The shape of the first opening 422a corresponds to the first pixel region PA1-1 or the second pixel region PA1-2. For example, the shape of the first opening 422a includes a rectangle, a square, or a diamond. In this case, the deposition material passing through the first opening 422a is deposited on the substrate 100 to form a first opposing electrode or a second opposing electrode. When a plurality of first openings 422a are provided, the plurality of first openings 422a are spaced apart sufficiently so that the deposition material passing through each first opening 422a is not connected to each other after being deposited on the substrate 100.

[0210] The second openings 422b are formed to have a different shape from the first openings 422a. The size of the second openings 422b is larger than the size of the first openings 422a. The second distance WI2 between adjacent first openings 422a and second openings 422b is the same as the first distance WI1 between adjacent first openings 422a. Meanwhile, the third distance WI3 between adjacent second openings 422b is different from the first distance WI1 and the second distance WI2. For example, the third distance WI3 is smaller than the first distance WI1 and the second distance WI2. The third distance WI3 is narrow enough so that the deposition material passing through adjacent second openings 422b overlaps each other and is deposited on the substrate 100. In this case, the deposition material passing through the plurality of second openings 422b forms third opposing electrodes 230c or fourth opposing electrodes 230d arranged in a line and connected to each other on the substrate 100.

[0211] The substrate 100 is placed on the first support part 430. At this time, the first support part 430 adjusts the position of the substrate 100. For example, the first support part 430 includes a UVW stage.

[0212] The mask assembly 420 is placed on the second support part 440. In this case, the second support part 440 can adjust the position of the mask assembly 420 in a manner similar to the first support part 430.

[0213] The deposition source 450 stores a deposition material, vaporizes the deposition material, or sublimes the deposition material, and supplies the vaporized deposition material to the chamber 410. The deposition source 450 includes a heater therein, and the heater is operated to heat the deposition material inside the deposition source 450, thereby melting or sublimating the deposition material. In this case, the deposition source 450 is disposed at the center or edge of the chamber 410. For convenience of explanation, the following description will be focused on the case where the deposition source 450 is disposed at the edge of the chamber 410.

[0214] The magnetic force generator 460 is disposed in the chamber 410 to bring the substrate 100 into close contact with the mask assembly 420. The magnetic force generator 460 includes an electromagnet or a permanent magnet that generates a magnetic force.

[0215] The vision unit 470 is disposed in the chamber 410 and photographs the positions of the mask assembly 420 and the substrate 100. At this time, the vision unit 470 photographs at least one alignment mark of the mask assembly 420 and the substrate 100.

[0216] The pressure adjusting unit 480 is connected to the chamber 410 and adjusts the pressure inside the chamber 410. In this case, the pressure adjusting unit 480 includes a connection pipe 481 connected to the chamber 410 and a pump 482 disposed in the connection pipe 481.

[0217] The display device 1 is manufactured by the display device manufacturing apparatus 400. In this case, the display device manufacturing apparatus 400 may manufacture the display device 1 according to not only the above-described embodiment but also the following embodiment. However, for the sake of convenience, the following detailed description will focus on the case where the display device manufacturing apparatus 400 manufactures the pixel region of the display panel (not shown) shown in FIG. 19. Hereinafter, the same reference numerals as those in FIG. 19 indicate the same components.

[0218] Specifically, the substrate 100 on which an insulating layer (not shown) is formed and the mask assembly 420 are placed inside the chamber 410. At this stage, the pixel electrodes (not shown) and organic light-emitting layers (not shown) of the thin film transistors (not shown) and organic light-emitting elements (not shown) are formed.

[0219] After the substrate 100 and the mask assembly 420 are placed on the first support part 430 and the second support part 440, respectively, the substrate 100 and the mask assembly 420 are photographed through the vision part 470. Thereafter, the substrate 100 and the mask assembly 420 are aligned.

[0220] When the deposition source 450 is activated to supply a deposition material, the deposition material passes through the first opening 422a and the second opening 422b of the mask sheet 422 and is deposited on the organic light-emitting layer and the pixel defining layer of the substrate 100. At this time, the deposition material passing through the first opening 422a forms the first opposing electrode 230a as described above, and the deposition material passing through the second opening 422b forms the third opposing electrode 230c and the fourth contact area CTA4.

[0221] When deposited as described above, the first and third opposing electrodes 230a and 230c are arranged in a line, and a plurality of such lines are provided and arranged spaced apart from each other. After the above process is completed, the position of at least one of the substrate 100 and the mask assembly 420 is changed. For example, the position of the mask assembly 420 is fixed, and then the position of the substrate 100 is changed. In another embodiment, the position of the substrate 100 may be fixed, and then the position of the mask assembly 420 may be changed. In still another embodiment, the positions of both the substrate 100 and the mask assembly 420 may be changed. For convenience of explanation, the following description will focus on the case where the position of the mask assembly 420 is fixed, and then the position of the substrate 100 is changed.

[0222] When the position of the substrate 100 is changed, the first opening 422a and the second opening 422b are arranged to correspond to portions of the substrate 100 where the first opposing electrodes 230a and the third opposing electrodes 230c are not formed. That is, the first opening 422a is arranged between adjacent first opposing electrodes 230a, and the second opening 422b is arranged between adjacent third opposing electrodes 230c.

[0223] After the position of the substrate 100 is changed, a deposition material is supplied from the deposition source 450. The deposition material passes through the first opening 422a and the second opening 422b and is deposited on the substrate 100. At this time, the deposition material passing through the first opening 422a is deposited on the substrate 100 to form the second opposing electrode 230b, and the deposition material passing through the second opening 422b is deposited on the substrate 100 to form the fourth opposing electrode 230d. When the fourth opposing electrode 230d is formed, the second contact region CTA2, the fifth contact region CTA5, and the sixth contact region CTA6 are also formed. In particular, in this case, the second opposing electrode 230b is disposed between the first opposing electrodes 230a and is connected through the first contact region CTA1. The fourth opposing electrode 230d is disposed between the second opposing electrodes 230b, and the fourth opposing electrode 230d is connected to the first opposing electrode 230a through the third contact region CTA3, and is connected to the third opposing electrode 230c through the second contact region CTA2 and the sixth contact region CTA6.

[0224] At least one of the third opposing electrode 230c and the fourth opposing electrode 230d protrudes from the frame of the second display area DA2 into the non-display area NDA. In this case, the third opposing electrode 230c and the fourth opposing electrode 230d are connected to each other in the second display area DA2, and are arranged to cover the second display area DA2.

[0225] Therefore, the opposing electrodes disposed on the substrate 100 are connected to each other through the respective contact regions.

[0226] 22 is a plan view schematically illustrating a display area and a non-display area of ​​a display panel according to still another embodiment of the present invention, and FIG. 23 is a plan view illustrating a portion of another embodiment of the mask sheet illustrated in FIG.

[0227] 22 and 23, the display device manufacturing apparatus (not shown) is similar to that shown in Fig. 20. Hereinafter, differences from the display device manufacturing apparatus shown in Fig. 20 will be described in detail.

[0228] The mask sheet 422 includes a first opening 422a and a second opening 422b. The first opening 422a is square, and the second opening 422b is rectangular. The second opening 422b is formed long along the longitudinal direction of the mask sheet 422. In particular, the second opening 422b is formed so that the third opposing electrode 230c covers the second display region DA2 of the substrate 100.

[0229] The method of forming the counter electrodes using the display device manufacturing apparatus is similar to that described above with reference to Figures 20 and 21. Specifically, the first counter electrode 230a is formed in the first display area DA1, and the third counter electrode 230c is formed in the second display area DA2 simultaneously with the formation of the first counter electrode 230a. At this time, at least a portion of the third counter electrode 230c protrudes from the second display area DA2 into the non-display area NDA. Also, at least a portion of the third counter electrode 230c protrudes from the second display area DA2 into the first display area DA1.

[0230] Thereafter, the position of the substrate (not shown) is changed to form the second opposing electrode 230b and the fourth opposing electrode 230d. In this case, a portion of the second opposing electrode 230b overlaps with the first opposing electrode 230a, and another portion of the second opposing electrode 230b overlaps with the third opposing electrode 230c. In this case, the overlapping portions form the first contact region CTA1 and the third contact region CTA3, respectively. In addition, a portion of the fourth opposing electrode 230d overlaps with the third opposing electrode 230c, and the overlapping of the fourth opposing electrode 230d and the third opposing electrode 230c forms the second contact region CTA2. In this case, a portion of the fourth opposing electrode 230d protrudes from the second display region DA2 into the non-display region NDA.

[0231] Therefore, in the above case, the counter electrodes arranged in each display area are connected to each other. In particular, all of the counter electrodes arranged on the substrate 100 are connected to each other. Furthermore, the counter electrodes connected to each other are in surface contact, which can minimize the surface resistance of the counter electrodes.

[0232] By ensuring the transmissive area TA, the display device 1 does not degrade the functionality of the components arranged in the first display area DA1.

[0233] Fig. 24 is a plan view schematically showing a display area and a non-display area of ​​a display panel according to still another embodiment of the present invention, and Fig. 25 is a plan view showing a part of still another embodiment of the mask sheet shown in Fig. 20.

[0234] 24 and 25, the manufacturing apparatus (not shown) for the display device is the same as that shown in FIG. Hereinafter, differences from the display device manufacturing apparatus shown in FIG.

[0235] The mask sheet 422 includes a first opening 422a and a second opening 422b. The first opening 422a is also square, and the second opening 422b has the same shape as the first opening 422a. In this case, the first distance WI1 between adjacent first openings 422a and second openings 422b, which are arranged in a line, is different from the third distance WI3 between adjacent second openings 422b. For example, the third distance WI3 is shorter than the first distance WI1. Furthermore, the third distance WI3 is shorter than the second distance WI2 between adjacent first openings 422a and second openings 422b. The second distance WI2 is the same as the first distance WI1.

[0236] The method of forming the counter electrodes using the display device manufacturing apparatus is similar to that described with reference to Figures 20 and 21. Specifically, the first counter electrode 230a is formed in the first display area DA1, and the third counter electrode 230c is formed in the second display area DA2 together with the first counter electrode 230a. At this time, at least a portion of the third counter electrode 230c protrudes from the second display area DA2 to the non-display area NDA. Also, at least a portion of the third counter electrode 230c protrudes from the second display area DA2 to the first display area DA1. The third counter electrodes 230c disposed in the second display area DA2 are spaced apart from each other.

[0237] Thereafter, the position of the substrate (not shown) is changed to form the second opposing electrode 230b and the fourth opposing electrode 230d. In this case, a portion of the second opposing electrode 230b overlaps with the first opposing electrode 230a, and another portion of the second opposing electrode 230b overlaps with the third opposing electrode 230c. In this case, the overlapping portions form the first contact region CTA1 and the third contact region CTA3, respectively. In addition, a portion of the fourth opposing electrode 230d overlaps with the third opposing electrode 230c, and the overlapping of the fourth opposing electrode 230d and the third opposing electrode 230c forms the second contact region CTA2. In this case, a portion of the fourth opposing electrode 230d protrudes from the second display region DA2 into the non-display region NDA.

[0238] In this case, the first opposing electrodes 230a and the second opposing electrodes 230b are arranged in a zigzag pattern and connected to each other, and the third opposing electrodes 230c and the fourth opposing electrodes 230d are arranged in a zigzag pattern and connected to each other. Also, at least one of the plurality of third opposing electrodes 230c is connected to at least one of the plurality of second opposing electrodes 230b, and at least one of the plurality of fourth opposing electrodes 230d is connected to at least one of the plurality of first opposing electrodes 230a.

[0239] Therefore, in the above case, the counter electrodes arranged in each display area are connected to each other. In particular, all the counter electrodes arranged on the substrate 100 are connected to each other. Furthermore, the counter electrodes connected to each other are in surface contact with each other, thereby minimizing the surface resistance of the counter electrodes.

[0240] By ensuring the transmissive area TA, the display device (not shown) does not reduce the functionality of the components arranged in the first display area DA1.

[0241] FIG. 26 is a plan view schematically showing a display area and a non-display area of ​​a display panel according to still another embodiment of the present invention.

[0242] Referring to FIG. 26, the display panel (not shown) includes a first display area DA1, a transmissive area TA, a second display area DA2, and a non-display area NDA. The first display area DA1 includes a first pixel area PA1-1 and a second pixel area PA1-2. The second display area DA2 includes a third pixel area PA2-1 and a fourth pixel area PA2-2. Pixels are arranged in each of the regions PA1-1 to PA2-2. For example, four first pixels PXa1 are arranged in the first pixel region PA1-1, and four second pixels PXa2 are arranged in the second pixel region PA1-2. Furthermore, the third pixel region PA2-1 and the fourth pixel region PA2-2 each include four third pixels PXm1 and four fourth pixels PXm2. In this case, each pixel is rectangular, and two of the four pixels arranged in one pixel region can embody the same color.

[0243] A first opposing electrode 230a is disposed in the first pixel region PA1-1, a second opposing electrode 230b is disposed in the second pixel region PA1-2, a third opposing electrode 230c is disposed in the third pixel region PA2-1, and a fourth opposing electrode 230d is disposed in the fourth pixel region PA2-2. The first to fourth opposing electrodes 230a to 230d are disposed so as to partially overlap each other, thereby forming contact regions. The first contact region CTA1 is formed by the first opposing electrode 230a and the second opposing electrode 230b overlapping each other, and the second contact region CTA2 is formed by the third opposing electrode 230c and the fourth opposing electrode 230d overlapping each other. The third contact region CTA3 is formed by the first opposing electrode 230a and the fourth opposing electrode 230d overlapping each other. The fourth contact region CTA4 is formed by overlapping adjacent third opposing electrodes 230c, the fifth contact region CTA5 is formed by overlapping adjacent fourth opposing electrodes 230d, and the sixth contact region CTA6 is formed by overlapping adjacent third opposing electrodes 230c, second contact region CTA2, and fourth opposing electrode 230d.

[0244] Therefore, in the above case, the counter electrodes arranged in each display area are connected to each other. In particular, all the counter electrodes arranged on the substrate 100 are connected to each other. Furthermore, the counter electrodes connected to each other are in surface contact with each other, thereby minimizing the surface resistance of the counter electrodes.

[0245] By ensuring the transmissive area TA, the display device 1 does not degrade the functionality of the components arranged in the first display area DA1.

[0246] FIG. 27 is a plan view schematically showing a display area and a non-display area of ​​a display panel according to still another embodiment of the present invention.

[0247] Referring to FIG. 27, the display panel (not shown) is similar to that shown in FIG. 26. In this case, three pixels are arranged in each pixel region. In such a case, one of the three pixels in one pixel region is larger than the remaining two of the three pixels. For example, one of the three pixels is rectangular, and the remaining two of the three pixels are square.

[0248] FIG. 28 is a plan view schematically showing a display area and a non-display area of ​​a display panel according to still another embodiment of the present invention.

[0249] Referring to Figure 28, the display panel (not shown) is similar to that shown in Figure 26. In this case, four pixels are arranged in each pixel region. In such a case, the four pixels arranged in one pixel region are the same size.

[0250] FIG. 29 is a plan view schematically showing a display area and a non-display area of ​​a display panel according to still another embodiment of the present invention.

[0251] Referring to FIG. 29, the display panel (not shown) is similar to that shown in FIG. 15, FIG. 19, or FIG. 24. In this case, the pixels are arranged in a diamond shape. In this case, the first opposing electrode 230a and the second opposing electrode 230b arranged in the first display area DA1 are each arranged to cover four pixels, and the third opposing electrode 230c and the fourth opposing electrode 230d arranged in the second display area DA2 are each arranged to cover nine pixels.

[0252] Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely an example, and those skilled in the art will understand that various modifications and variations of the embodiment are possible. Therefore, the true technical scope of protection of the present invention should be determined by the technical spirit of the claims. [Explanation of symbols]

[0253] 10 Display panel 20 Components 100 boards 110 First scan drive circuit 111 Buffer layer 112 First gate insulating layer 113 Second gate insulating layer 115 Interlayer insulation layer 117 Planarization layer 119 Pixel-defined membrane 120 Second scan drive circuit 130 Second scan drive circuit 140 terminals 150 Data drive circuit 151 Connection wiring 160 1st power supply wiring 162 First sub-wiring 163 Second sub-wiring 170 2nd power supply wiring 175 Bottom protective film 200 display element layer 210 pixel electrode 220 Middle Class 230 Counter electrode 230a First opposing electrode 230b Second opposing electrode 230c Third opposing electrode 230d Fourth opposing electrode 300 Thin film sealing layer 310 pixel electrode 320 Organic sealing layer 400 Display device manufacturing equipment 410 Chamber 420 Mask assembly 421 Mask Frame 422 Mask Sheet 430 1st support part 440 Second support part 470 Vision Department 480 Pressure adjustment unit 1130 Semiconductor layer 1151, 1152, 1153, 1154, 1155, 1156, 1157, 1163 Contact Hole 1173 Initialization Connection Line 1174 Node Connection Lines 1175 Connection Metal

Claims

1. a chamber having a portion that is opened and closed; a first support disposed in the chamber and configured to support a substrate; a mask assembly disposed in the chamber facing the substrate; a second support portion disposed within the chamber and supporting the mask assembly; a deposition source disposed in the chamber to supply a deposition material to the substrate; The mask assembly includes: Mask frame and a mask sheet to be placed on the mask frame, the mask sheet includes a plurality of first openings and a plurality of second openings disposed in portions of the mask sheet different from the first openings, the first openings and the second openings being arranged in a line, the first openings being spaced apart at a distance such that the deposition material passing through the first openings is not connected to each other after being deposited on the substrate, and the second openings being spaced apart at a distance such that the deposition material passing through the second openings is overlapped with each other after being deposited on the substrate; 10. The apparatus for manufacturing a display device, wherein at least one of the first support portion and the second support portion is capable of adjusting a relative position between the substrate and the mask assembly.

2. 2. The display device manufacturing apparatus according to claim 1, wherein the deposition source is disposed at an edge portion of the chamber.

3. 2. The display device manufacturing apparatus according to claim 1, wherein the first opening is square and the second opening is rectangular.

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