Self-test circuit for an integrated circuit and method of operating a self-test circuit for an integrated circuit - Patents.com

Abstract

To provide a self-test circuit for an integrated circuit that enables it to provide a test that can be performed within a predetermined maximum time.SOLUTION: A self-test circuit 200 for an integrated circuit with multiple scan chains 224 is provided. Each scan chain has a plurality of first storage elements 110, a data input unit 226 that supplies test data to the scan chain and is connected to one of the plurality of first storage elements, a plurality of second storage elements 112, and a switching device 220 with a first switching position and a second switching position. The switching device is connected between the first storage element and the second storage element. The switching device connects the last first storage element of each of the plurality of first storage elements with the data output unit 228 in the first switching position, and connects the last first storage element of each of the plurality of first storage elements with the first second storage element of the plurality of second storage elements in the second switching position.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a method of operating a self-test circuit for an integrated circuit and a cell test circuit for an integrated circuit. [Background technology]

[0002] Electronic systems, especially safety-related electronic systems, must be periodically tested for errors if they are to meet standards for functional safety, such as ISO 26262 for the automotive sector. Built-in or integrated self-test circuits for identifying logic errors, also known as LBIST (Logic Built-In Self-Test), are currently common devices for performing such tests.

[0003] During this test, a distinction is made between so-called "key-on" and "key-off" tests.

[0004] As used herein, "key-on" tests refer to tests that are run at startup for normal operation, e.g., when the system is switched on / booted, e.g., when the vehicle is started, or during normal operation. Tests that are run at startup are also referred to as "Power-On Self-Test (POST)," and tests that are run during normal operation are also referred to as "Mission-Mode LBIST."

[0005] In contrast, a "key-off" test is typically performed away from normal operation, for example for post-manufacturing quality assurance of an electronic system of which the integrated circuit is a part, or after it has been taken out of service, for example due to an error.

[0006] Safety-related elements are typically tested by a "key-on" test, while systems tested by a "key-off" test typically contain additional elements that are not safety-related.

[0007] LBIST is a structural approach: unlike functional approaches such as software-based self-test, LBIST is not performed at the system boundary of the system under test or within the component under test, but rather using a specially adapted architecture, the so-called scan architecture.

[0008] FIG. 1 shows a prior art self-test circuit 100 for an integrated circuit.

[0009] The self-test circuit 100 typically includes multiple scan chains 108, 114. Each scan chain may include multiple storage elements 110 or 112, such as flip-flops, that may be serially connected for each scan chain 108, 114. Additional compression logic (decompressor 102, compressor 104) is often implemented as a so-called "Design-for-Test" (DFT) measure.

[0010] To enable "key-on" LBIST testing within existing "key-off" LBIST test equipment, the scan system or compression system may have to be modified.

[0011] This is because the period allowed to perform the test is much shorter for a "key on" test than for a "key off" test, for example only 5 ms for a "key on" test.

[0012] Generally, the execution time for "key-on" testing is reduced and kept below a predetermined limit by forming a short scan chain 108 dedicated for "key-on" testing, while the scan chain 114 utilized for "key-off" testing is longer and distinct from the short scan chain 108.

[0013] The self-test circuit 100 can be configured to not fill or utilize the distinct "key-off" scan chain 114 at all when performing a "key-on" test.

[0014] However, this can have two disadvantages: the adjustment may require a corresponding extension of the "key-off" scan chain 114, for example, because the total number of scan chains 108, 114 is limited (e.g., based on the configuration of blocks 102 and 104 for data compression), thereby extending the test time for the "key-off" test, and / or the test time may remain the same or approximately the same. However, this may require a significant number of tests to be omitted. Alternatively, a combination of these two, i.e., the omission of a significant number of tests and a (less significant) extension of the "key-off" scan chain 114 and thus the test time, can be used. Summary of the Invention [Means for solving the problem]

[0015] In various embodiments, a self-test circuit for an integrated circuit is provided that reduces the time required to perform a "key-off" test (despite the number of tests being the same as or greater than the prior art), yet still provides a "key-on" test that can be performed within a predetermined maximum time, e.g., 5 ms.

[0016] In various embodiments, the self-test circuitry may include multiple scan chains, each of which has storage elements for "key-on" testing and storage elements for "key-off" testing, and all of which have approximately the same length.

[0017] In various embodiments, each scan chain of the plurality of scan chains can be configured such that a plurality of first storage elements (for "key-on" testing) are located at the beginning (i.e., input side) of the respective scan chain, followed by a plurality of second storage elements (used only for "key-off" testing). Between the first and second storage elements can be located a switch switchable between a first switching position in which the last first storage element of the plurality of first storage elements is connected to the data output and a second switching position in which the last first storage element of the plurality of first storage elements is connected to the first second storage element of the plurality of second storage elements.

[0018] In simple terms, this switch allows for a shortcut to be created that allows data evaluation after passing through the first storage element, which can be used to allow evaluation of multiple (e.g. safety-related) tests (e.g. "key-on" tests or more general overall tests where short test times are important) within a short time that can be performed by the first storage element.

[0019] When the switch is in the second switching position, the entire scan chain can be filled with test data and evaluated, for example, within the framework of a "key-off" test. Since the storage elements are now uniformly distributed throughout the scan chain, minimal test time can be achieved, which can reduce the time required for post-manufacturing testing, for example.

[0020] In various embodiments, the self-test circuit may further include a logic circuit configured to pairwise combine the output data output by the last first storage element of the plurality of first storage elements, which may include, for example, an XOR or XNOR gate.

[0021] In various embodiments, the output data (i.e., the processed test data) can be provided to a memory device, such as a linear feedback shift register (LFSR, e.g., Multiple Input Signature Register (MISR) 106 of FIG. 1), that is configured or available for examining the output response. Both the output data output after the first memory element and the output data output after the second memory element can be provided to the memory device.

[0022] An embodiment of the invention is shown in the drawings and is explained in more detail below. [Brief explanation of the drawings]

[0023] [Figure 1] 1 is a schematic illustration of a self-test circuit for an integrated circuit according to the prior art; [Figure 2] 1 is a schematic illustration of a self-test circuit for an integrated circuit, according to various embodiments. [Figure 3] FIG. 2 is another schematic illustration of a self-test circuit for an integrated circuit, according to various embodiments. [Figure 4] FIG. 2 is yet another schematic illustration of a self-test circuit for an integrated circuit, according to various embodiments. [Figure 5] FIG. 2 is yet another schematic illustration of a self-test circuit for an integrated circuit, according to various embodiments. [Figure 6] 1 is a flowchart of a method of operating a self-test circuit for an integrated circuit, according to various embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0024] In the following detailed description, reference is made to the accompanying drawings, which form a part of this application and in which are shown, by way of illustration, specific embodiments in which the present invention may be practiced. In this regard, directional terms such as "upward," "downward," "forward," "rearward," "frontward," "rearward," etc. are used with reference to the orientation of the illustrated figures. Because components of the embodiments can be positioned in several different orientations, the directional terms are used for purposes of illustration and are in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. It is to be understood that features of various exemplary embodiments described herein may be combined with one another unless otherwise specified. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.

[0025] Within the framework of this specification, the terms "connected," "coupled," and "coupled" are used to denote both direct and indirect connections, and are used to denote direct or indirect connections and direct or indirect couplings. In the drawings, wherever convenient, the same or similar elements are labeled with the same reference numerals.

[0026] 2-5 each show a simplified schematic diagram of a self-test circuit 200 for an integrated circuit, according to various embodiments.

[0027] During normal operation, also referred to as operational or functional mode, of the integrated circuit (only those elements of the integrated circuit that are also part of self-test circuit 200 are shown), storage elements 110, 112 can store data values, and logic circuitry (not shown) can use these data values ​​to perform combinatorial logic, for example by applying Boolean operations.

[0028] For self-test purposes, storage elements 110, 112 can be preloaded with test data to allow for better control during testing. For preloading purposes, storage elements 110, 112 are or can be coupled in series to form a scan chain.

[0029] A test cycle (here an LBIST cycle) may have three stages: First, test data, e.g., pseudo-random numbers, are loaded into storage element 110 or into storage elements 110 and 112 (these two options are explained in more detail below), e.g., pushed along scan chain 224.

[0030] In the second stage, the test data is processed by the logic circuit under test (e.g., simulating or implementing combinational logic), which leads to the detection of possible errors propagating through the logic circuit 106.

[0031] In the third stage, the processed test data is pushed from one storage element 110 or 112 of the scan chain 224 to another storage element 110 or 112 .

[0032] Typically, the scan chain 224 and corresponding LBIST method are designed such that the third stage of a test cycle is simultaneously the first stage of a subsequent test cycle. In other words, the test data processed and output by one of the plurality of logic circuits can form the input data in the subsequent test cycle for the subsequent logic circuit along the scan chain 224.

[0033] The self-test circuit 200 may include a plurality of scan chains 224 , each of which may include a plurality of first storage elements 110 and a plurality of second storage elements 112 .

[0034] Each first storage element 110 and each second storage element 112 may, in various embodiments, comprise at least one flip-flop, typically a plurality of flip-flops, or another storage element, such as a latch.

[0035] In various embodiments, each scan chain 224 can be configured such that a plurality of first storage elements 110 is provided at the beginning of each scan chain 224, followed by a plurality of second storage elements 112.

[0036] In other words, each scan chain 224 may have a first storage element 110 arranged on the input side and a second storage element 112 arranged on the output side.

[0037] In other words, in various embodiments, a test scheme for self-testing is provided in which the scan chains 224 are configured such that the first storage elements 110 (e.g., flip-flops for testing safety-related systems) used for "key-on" LBIST are distributed across all of the scan chains 224 and are located at the beginning of each of the scan chains 224.

[0038] In each scan chain 224, the first first storage element 110 of the plurality of first storage elements 110 may be coupled, e.g., connected, to a data input 226. The last second storage element 112 of the plurality of second storage elements 112 may be coupled, e.g., connected, to a (second) data output, also referred to as a (second) data output 228.

[0039] The last first memory element 110 of the plurality of first memory elements 110 can be selectively connected by the switch 220 in each scan chain 224 to a (first) data output section 222 (also referred to as a (first) data output section 222) (in a first switching position) or to the first second memory element 112 of the plurality of second memory elements 112 (in a second switching position).

[0040] A plurality of switches 220 together can form a switching device, and all of the switches 220 of the switching device 220 can be configured such that they are all in a position corresponding to a first switching position, or all of the switches are in a position corresponding to a second switching position.

[0041] The self-test circuit 200 may further include a decompressor 102 for decompressing the test data at the data input 226. The decompressor 102 may be formed in substantially any known manner.

[0042] The self-test circuit 200 may further include a compressor 104 at the data output 228 for compressing the processed test data (also referred to as output data). The compressor 104 may be configured in a manner substantially known per se.

[0043] The decompressor 102 and compressor 104 together may form compression logic 102,104.

[0044] In various embodiments, the output data can be provided to a memory device 106, for example a linear feedback shift register (LFSR, possibly a MISR with multiple inputs). The memory device 106 can be formed, for example, as part of the compressor 104 (as shown exemplarily in FIG. 2). Alternatively or additionally, the memory device 106 (in this case, for example, a two-part or multi-part memory device) can be formed separately from the compressor 104 and coupled between the data output 222 or 228 and the compressor 104. In FIGS. 3, 4, and 5, the memory device 106 is exemplarily shown coupled between the first data output 222 and the compressor 104. The compressor 104 can, in various embodiments, include the (additional) memory device 106.

[0045] For example, the output data output by the first data output unit 222 followed by a plurality of first memory elements 110, and for example, the output data output by the second data output unit 228 followed by a plurality of second memory elements 112 can both be supplied to the memory device 106.

[0046] Self-test circuitry 200 may be configured such that self-test circuitry 200 is operable in a normal operation test mode to test elements of the integrated circuit that are related to normal operation.

[0047] In a normal operation test mode, the switching device may be in a first switching position.

[0048] In the normal operation test mode, the first storage element 110 may be configured to provide test data as operation test data for the normal operation test.

[0049] The number of first storage elements 110 may be significantly smaller than the number of second storage elements 112 in various embodiments, or may generally be smaller than or at most equal to the number of second storage elements 112.

[0050] The number of scan chains may be in the thousands. Of these, a few percent, e.g., several dozens long each, are flip-flops, and the rest are non-safety-related flip-flop scan chains 112, varying in length from several dozen to, e.g., 100. This means that some flip-flops are available for "key-on" testing and about 10 times as many flip-flops for "key-off" testing. Correspondingly, the number of first storage elements 110 may be up to 80% of the number of second storage elements 112, e.g., up to 60%, e.g., up to 40%, e.g., up to 20%, e.g., up to 10%, e.g., up to 5%, in various embodiments.

[0051] In various embodiments, the number of first storage elements 110 can be selected so that the maximum execution time of a self-test using only the first storage elements 110 (which may be used for a "key-on" self-test) is or does not exceed 10 ms, e.g., 5 ms, e.g., 4 ms, e.g., 3 ms.

[0052] Furthermore, the number of first storage elements 110 may vary slightly from one scan chain 224 to another. In other words, the number of first storage elements 110 in each scan chain 224 may deviate from the arithmetic mean value of the number of first storage elements 110 per scan chain 224 by at most 10%, e.g., at most 5%, and optionally be the same. By uniformly distributing the first storage elements 110 among the scan chains 224, the shortest execution time for the self-test using the first storage elements 110 can be achieved, since in this case the self-test is only fully completed once all scan chains 224 have been processed. Therefore, an individually excessively long scan chain 224 may increase the overall execution time, which can be avoided by ensuring that all scan chains 224 have approximately the same number of first storage elements 110. This is exemplarily illustrated in FIGS. 2, 3, and 4.

[0053] In various embodiments, the total number of second storage elements 112 in all scan chains 224 may exceed the total number of first storage elements 110 in all scan chains 224, as long as there are a maximum number of scan chains 224 with first storage elements 110, e.g., storage elements 110 having a predetermined minimum length. In the illustrative case shown in FIG. 5 , an additional scan chain 114 may be provided that includes only second storage elements 112. In this case, self-test circuit 200 may be configured to fill the second storage elements 112 of a scan chain 114 with test data only if the second storage elements 112 of the scan chain 224 are also filled with test data.

[0054] For clarity, the switch 220 provides a shortcut that allows data evaluation after passing through the first storage element 110. In this case, each scan chain 224 provides processed test data to a respective data output 222.

[0055] This can be performed by the first memory element 110 and can be used to enable the evaluation of multiple (e.g., safety-related) tests within a short period of time (e.g., "key-on" tests or more general overall tests where short test times are important).

[0056] Self-test circuit 200 may also be operable, according to various embodiments, in a manufacturing test mode, for example, following fabrication of the integrated circuit, in which switching device 220 is in the second switching position.

[0057] This means that test data can be loaded into the first storage element 110 as well as into the second storage element 112. This makes it possible to provide test data as production test data for production testing, i.e. for all tests that are to be performed as part of production.

[0058] In various embodiments, the overall lengths of the scan chains 224 (and possibly additional scan chains 114) may be approximately the same. In other words, the sum of the number of first storage elements 110 and the number of second storage elements 112 in each scan chain 224 may deviate from the arithmetic mean value of the sum of first storage elements and second storage elements per scan chain 224 by at most 10%, e.g., at most 5%, and may optionally be the same.

[0059] Furthermore, in various embodiments (see FIG. 5), the number of second memory elements 112 in each scan chain 114 may deviate from the arithmetic mean value of the sum of the first memory elements and second memory elements per scan chain 224 by up to 10 percent, e.g., up to 5%, or may optionally be the same.

[0060] According to various embodiments, the self-test circuit 200 may further include a logic circuit 330, such as an XOR circuit or an XNOR circuit, which may be coupled to the data output section 222 and configured to logically combine the output data of the last first storage element 110 of each of the plurality of first storage elements 110 in pairs. This is exemplarily shown in FIG. 3 .

[0061] The data output of logic circuit 330 may be provided to storage device 106 for evaluation. Alternatively, the data output of the logic circuit may be provided to additional logic circuit 440, which may be coupled to logic circuit 330 and configured to logically combine, in pairs, the output data of logic circuits 330 that are logically combined in pairs.

[0062] The additional logic circuit 440 may similarly comprise or consist of an XOR or XNOR circuit, corresponding embodiments of which are shown in FIGS.

[0063] When the switches are in the second switching position, the entire scan chain can be filled with test data and evaluated, for example, within the framework of a "key-off" test. Because the storage elements are uniformly distributed among all scan chains, minimal test times can be achieved, thus reducing the time required for post-manufacturing testing, for example.

[0064] As already indicated above, the last first storage element 110 of each of the plurality of first storage elements 110 can be connected to the storage device 106 (e.g., a 32-bit MISR module). 32 data input channels may be provided to the MISR. Typically, more than 32 scan chains are available.

[0065] In such a case, logic circuitry 330 and possibly further logic circuitry 440 may be provided to compress the data output of the first memory element 110 to a number of memory input channels, which may be, for example, 32 (see Figures 3, 4 and 5).

[0066] A single stage of logic, e.g., a single stage XOR tree, can compress 64 storage elements into the 32 filter inputs provided, while another logic circuit 440 can compress 256 outputs into the 32 filter inputs.

[0067] In various embodiments, logic circuit 330 or logic circuit 440 may be substantially only one additional circuit component compared to self-test circuit 100 of FIG.

[0068] In various embodiments, a balanced and calibrated self-test circuit 200 is provided.

[0069] Various embodiment configurations may allow for the omission of rules for short LBIST scan chains 224. In other words, the number and length of scan chains 224 for a scan / compression system (i.e., self-test circuit 200) can be defined independently of "key-on" LBIST requirements.

[0070] FIG. 6 shows a flow chart 600 of a method for operating a self-test circuit for an integrated circuit.

[0071] The method includes (at 610) providing a self-test circuit for an integrated circuit having a plurality of scan chains, each scan chain having a plurality of first storage elements, a data input for providing test data to the scan chain and connected to one of the plurality of first storage elements, a plurality of second storage elements, and a switching device, the method further including (at 620) switching the switching device to either a first position for a normal operation test mode for testing elements of the integrated circuit associated with normal operation, or to a second position for a production test mode for testing the integrated circuit following manufacture.

[0072] The following summarizes some examples.

[0073] Example 1 is a self-test circuit for an integrated circuit having a plurality of scan chains, each scan chain including a plurality of first storage elements, a data input section that supplies test data to the scan chain and is connected to one of the plurality of first storage elements, a plurality of second storage elements, and a switching device having a first switching position and a second switching position, coupled between the first storage elements and the second storage elements, and configured to connect a last first storage element of each of the plurality of first storage elements to a data output section in the first switching position and to connect a last first storage element of each of the plurality of first storage elements to a first second storage element of the plurality of second storage elements in the second switching position.

[0074] Example 2 is the self-test circuit described in Example 1, wherein the self-test circuit is operable to test elements of the integrated circuit related to normal operation in a normal operation test mode, and in the normal operation test mode, the switching device is in a first switching position.

[0075] A third embodiment is the self-test circuit described in the second embodiment, and the first storage element is configured to supply test data as operation test data for a normal operation test.

[0076] Example 4 is the self-test circuit of any one of Examples 1 to 3, wherein the self-test circuit is operable following manufacture of the integrated circuit in a manufacturing test mode, and in the manufacturing test mode, the switching device is in a second switching position.

[0077] A fifth embodiment is the self-test circuit according to the fourth embodiment, wherein the first storage element and the second storage element are configured to provide test data as manufacturing test data for a manufacturing test.

[0078] A sixth embodiment is a self-test circuit according to any one of the first to fifth embodiments, wherein the number of first memory elements in each scan chain deviates by a maximum of 10% from the arithmetic mean value of the number of first memory elements per scan chain, and is optionally the same.

[0079] A seventh embodiment is a self-test circuit according to any one of the first to sixth embodiments, wherein the sum of the number of first memory elements and the number of second memory elements in each scan chain deviates by a maximum of 10% from the arithmetic mean value per scan chain of the sum of the first memory elements and the second memory elements, and is optionally the same.

[0080] Example 8 is the self-test circuit described in Example 2 or 3, wherein the number of first memory elements in each memory chain is less than or equal to a predetermined limit value corresponding to a predetermined maximum execution time for the normal operation test.

[0081] Example 9 is the self-test circuit described in Example 8, with a maximum execution time of 10 ms.

[0082] A tenth embodiment is the self-test circuit according to any one of the first to ninth embodiments, wherein in each scan chain, the number of first storage elements is equal to or less than the number of second storage elements.

[0083] Example 11 is the self-test circuit of any one of Examples 1 to 10, wherein the at least one first storage element and / or the at least one second storage element includes a flip-flop.

[0084] Example 12 is the self-test circuit according to any one of Examples 1 to 11, wherein the self-test circuit further includes a logic circuit coupled to the data output section and configured to logically combine output data of the last first memory element of each of the plurality of first memory elements in pairs.

[0085] Example 13 is the self-test circuit described in Example 12, wherein the self-test circuit further includes an additional logic circuit, the additional logic circuit being coupled to the logic circuit and configured to logically couple output data of the logic circuits logically coupled in pairs.

[0086] A fourteenth embodiment is the self-test circuit according to the twelfth or thirteenth embodiment, in which the logic circuit has or is configured from an XOR circuit or an XNOR circuit.

[0087] Example 15 is the self-test circuit according to any one of Examples 1 to 14, wherein the switching device includes a plurality of switches, each of which for each scan chain is coupled between a first storage element and a second storage element of the scan chain, and the switches are configured such that all of the switches are in a position corresponding to the first switching position or all of the switches are in a position corresponding to the second switching position.

[0088] Example 16 is a method of operating the self-test circuit of any one of Examples 1 to 15. The method includes switching the switching device to either a first switching position for a normal operation test mode for testing elements of the integrated circuit associated with normal operation or a second switching position for a production test mode for testing the integrated circuit following production.

[0089] Example 17 is the method described in Example 16, further comprising loading operational test data into the first storage element when the switching device is in the first switching position, or loading production test data into the first storage element and the second storage element when the switching device is in the second switching position.

[0090] Example 18 is the method described in Example 17, further comprising the step of evaluating output data provided to the data output by a last first storage element of each of the plurality of first storage elements when the switching device is in a first switching position, or evaluating output data provided to another data output by a last second storage element of each of the plurality of second storage elements when the switching device is in a second switching position.

[0091] Example 19 is the method described in Example 18, further comprising the step of logically combining, in pairs, output data of the last first storage elements of each of the plurality of first storage elements before the evaluation when the switching device is in the first switching position.

[0092] Example 20 is the method according to example 19, wherein the pairwise logical combination comprises an XOR combination or an XNOR combination.

[0093] Further advantageous embodiments of the above described device will become apparent from the description of the method, and vice versa.

Claims

1. 1. A self-test circuit for an integrated circuit, the self-test circuit comprising: - a plurality of scan chains, each of which: a plurality of first storage elements; a data input section for supplying test data to the scan chain and connected to one of the first plurality of storage elements; a plurality of second storage elements; a switching device having a first switching position and a second switching position; and the switching device is coupled between the first storage element and the second storage element, and is configured to connect a last first storage element of each of the plurality of first storage elements to a data output in the first switching position, and to connect a last first storage element of each of the plurality of first storage elements to a first second storage element of the plurality of second storage elements in the second switching position; the self-test circuitry is operable following manufacture of the integrated circuit in a manufacturing test mode with the switching device in the second switching position. Self-test circuit.

2. The first memory element and the second memory element are configured to provide the test data as manufacturing test data for the manufacturing test mode.

2. The self-test circuit of claim 1.

3. A self-test circuit for an integrated circuit, the self-test circuit comprising: - a plurality of scan chains, each of which: a plurality of first storage elements; a data input section for supplying test data to the scan chain and connected to one of the first plurality of storage elements; a plurality of second storage elements; a switching device having a first switching position and a second switching position; and the switching device is coupled between the first storage element and the second storage element, and is configured to connect a last first storage element of each of the plurality of first storage elements to a data output in the first switching position, and to connect a last first storage element of each of the plurality of first storage elements to a first second storage element of the plurality of second storage elements in the second switching position; the self-test circuit further includes a logic circuit coupled to the data output section and configured to logically combine output data of a last first storage element of each of the plurality of first storage elements in pairs; the self-test circuit further includes an additional logic circuit, the additional logic circuit being coupled to the logic circuit and configured to logically couple, in pairs, the output data of the logic circuits that are logically coupled in pairs. Self-test circuit.

4. The logic circuit has an XOR circuit or an XNOR circuit.

4. The self-test circuit of claim 3.

5. the self-test circuitry is operable to test elements of the integrated circuit related to normal operation in a normal operation test mode, and in the normal operation test mode, the switching device is in the first switching position; 5. A self-test circuit according to claim 1.

6. the first storage element is configured to supply the test data as operation test data for the normal operation test mode; 6. The self-test circuit of claim 5.

7. the number of the first storage elements in each of the scan chains deviates by a maximum of 10% from the arithmetic mean value of the number of the first storage elements per scan chain, and is optionally the same; 7. A self-test circuit according to any one of claims 1 to 6.

8. the sum of the number of the first storage elements and the number of the second storage elements in each of the scan chains deviates by a maximum of 10% from the arithmetic mean value per scan chain of the sum of the first storage elements and the second storage elements, and is optionally the same; 8. A self-test circuit according to any one of claims 1 to 7.

9. the number of the first storage elements in each storage device chain is less than or equal to a predetermined limit value corresponding to a predetermined maximum execution time for the normal operation test mode; 7. The self-test circuit according to claim 5 or 6.

10. The maximum execution time is 10 ms.

10. The self-test circuit of claim 9.

11. In each of the scan chains, the number of the first storage elements is equal to or less than the number of the second storage elements.

11. A self-test circuit according to any one of claims 1 to 10.

12. At least one of the first storage elements and / or at least one of the second storage elements comprises a flip-flop.

12. A self-test circuit according to any one of claims 1 to 11.

13. the switching device includes a plurality of switches, each of which per scan chain is coupled between the first storage element and the second storage element of the scan chain, and the switches are configured such that all of the switches are in a position corresponding to the first switching position or all of the switches are in a position corresponding to the second switching position.

13. A self-test circuit according to any one of claims 1 to 12.

14. A method of operating a self-test circuit according to any one of claims 1 to 13, said method comprising: switching the switching device to either the first switching position for a normal operation test mode for testing elements of the integrated circuit associated with normal operation or to the second switching position for a production test mode for testing the integrated circuit following manufacture. method.

15. The method further comprises: loading operational test data into the first storage element when the switching device is in the first switching position; or loading manufacturing test data into the first storage element and the second storage element when the switching device is in the second switching position; 15. The method of claim 14.

16. The method further comprises: - evaluating the output data provided to the data output by the last of each of the first storage elements when the switching device is in the first switching position, or - evaluating the output data provided by the last second storage element of each of the plurality of second storage elements to a further data output when the switching device is in the second switching position, 16. The method of claim 15.

17. The method further comprises the step of, when the switching device is in the first switching position, logically combining the output data of each last one of the first storage elements in pairs before the evaluation.

17. The method of claim 16.

18. The logical combination in the pair comprises an XOR combination or an XNOR combination.

18. The method of claim 17.

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