field-effect transistor

Abstract

To provide a field effect transistor using a trench structure and having higher withstanding voltage.SOLUTION: A field effect transistor 1 includes a first n-type semiconductor layer 10 formed of gallium oxide semiconductor, a second n-type semiconductor layer 11 formed of Si, p-type semiconductor parts 14a and 14b embedded in trenches 12a and 12b, n-type regions 15a and 15b provided on a part of a surface layer on an upper surface of an inter-trench region 13 of the second n-type semiconductor layer 11, p-type regions 16a and 16b provided in the inter-trench region 13 so as to surround the n-type regions 15a and 15b, a gate electrode 17 provided on the inter-trench region 13 through a gate insulating film 18, a source electrode 20 connected to the n-type regions 15a and 15b and the p-type semiconductor parts 14a and 14b, and a drain electrode 21 connected to the first n-type semiconductor layer 10.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a field effect transistor. [Background technology]

[0002] Conventionally, a field effect transistor with a trench gate structure has been known, which uses a bonded Ga2O3 substrate and a Si substrate as a semiconductor layer (see Patent Document 1). In a field effect transistor with such a trench gate structure, the breakdown voltage of the element can be increased by providing the bottom of the trench, where the electric field is concentrated, in a layer made of a material with high dielectric breakdown field strength, such as Ga2O3. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 6873516 Summary of the Invention [Problem to be solved by the invention]

[0004] However, in a field effect transistor having a trench gate structure, even if the semiconductor layer can withstand the electric field concentrated at the bottom of the trench, there is a risk that dielectric breakdown will occur in the gate insulating film at the bottom of the trench.

[0005] An object of the present invention is to provide a field effect transistor that utilizes a trench structure and has a higher breakdown voltage. [Means for solving the problem]

[0006] In order to achieve the above object, one aspect of the present invention provides the following field-effect transistors [1] to [5].

[0007] [1] A field effect transistor comprising: a first n-type semiconductor layer made of a gallium oxide-based semiconductor; a second n-type semiconductor layer made of Si provided on the first n-type semiconductor layer; a p-type semiconductor portion embedded in a trench extending from an upper surface of the second n-type semiconductor layer to the first n-type semiconductor layer; an n-type region provided in a part of a surface layer of an upper surface of an inter-trench region sandwiched on both sides by the trenches of the second n-type semiconductor layer; a p-type region provided in the inter-trench region so as to surround the n-type region; a gate electrode provided on the inter-trench region via a gate insulating film; a source electrode connected to the n-type region and the p-type semiconductor portion; and a drain electrode connected to the first n-type semiconductor layer. [2] The field effect transistor according to [1] above, wherein the p-type semiconductor portion is made of a p-type oxide semiconductor. [3] The field-effect transistor according to [2] above, wherein the p-type oxide semiconductor is p-type NiO. [4] The field effect transistor according to any one of the above [1] to [3], wherein the width of the inter-trench region is 0.5 μm or more and 2.0 μm or less. [5] The field effect transistor according to any one of the above [1] to [4], wherein the trench is 0.5 μm or more deeper than the upper surface of the first n-type semiconductor layer. [Effects of the Invention]

[0008] According to the present invention, it is possible to provide a field effect transistor that utilizes a trench structure and has a higher breakdown voltage. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a vertical cross-sectional view of a field effect transistor according to a first embodiment of the present invention. [Figure 2] FIG. 2 is a horizontal cross-sectional view of the field-effect transistor according to the first embodiment of the present invention taken along the line AA shown in FIG. [Figure 3]FIG. 3 is a vertical cross-sectional view of a field effect transistor according to a first embodiment of the present invention in which the second n-type semiconductor layer is thinned. [Figure 4] FIG. 4 is a vertical cross-sectional view of a field effect transistor according to a first embodiment of the present invention, in which a downwardly facing convex portion is provided on the gate electrode. [Figure 5] FIG. 5 is a vertical cross-sectional view of a modified example of the field-effect transistor according to the first embodiment of the present invention. [Figure 6] FIG. 6 is a horizontal cross-sectional view of a modified field effect transistor taken along the line BB shown in FIG. [Figure 7] FIG. 7 is a vertical cross-sectional view of another modified example of the field effect transistor according to the first embodiment of the present invention. [Figure 8] FIG. 8 is a horizontal cross-sectional view of a field effect transistor as another modified example, taken along the line CC shown in FIG. [Figure 9] FIG. 9 is a vertical cross-sectional view of a field effect transistor according to the second embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0010] [First embodiment] (Field-effect transistor structure) 1 is a vertical cross-sectional view of a field effect transistor 1 according to a first embodiment of the present invention. The field effect transistor 1 is a vertical field effect transistor having a planar structure.

[0011] The field-effect transistor 1 includes a first n-type semiconductor layer 10 made of a gallium oxide-based semiconductor, a second n-type semiconductor layer 11 made of Si provided on the first n-type semiconductor layer 10, p-type semiconductor portions 14a and 14b embedded in trenches 12a and 12b reaching from the upper surface of the second n-type semiconductor layer 11 to the first n-type semiconductor layer 10, n-type regions 15a and 15b provided on a part of the surface layer of the upper surface of the trench region 13 sandwiched between the trenches 12a and 12b of the second n-type semiconductor layer 11, p-type regions 16a and 16b provided so as to surround the n-type regions 15a and 15b in the trench region 13, a gate electrode 17 provided on the trench region 13 via a gate insulating film 18, a source electrode 20 connected to the n-type regions 15a and 15b and the p-type semiconductor portions 14a and 14b, and a drain electrode 21 connected to the first n-type semiconductor layer 10.

[0012] The first n-type semiconductor layer 10 is made of a single crystal of a gallium oxide-based semiconductor having a β-type crystal structure. Here, the gallium oxide-based semiconductor refers to Ga2O3 or Ga2O3 to which elements such as Al and In are added. For example, the gallium oxide-based semiconductor has a composition represented by (Ga x Al y In (1-x-y) )2O3 (0 < x ≤ 1, 0 ≤ y ≤ 1, 0 < x + y ≤ 1). When Al is added to Ga2O3, the bandgap widens, and when In is added, the bandgap narrows.

[0013] Further, the first n-type semiconductor layer 10 contains donor impurities such as Si and Sn. Further, the first n-type semiconductor layer 10 typically includes, as shown in FIG. 1, a layer 101 having a high donor concentration for ohmic connection of the drain electrode 21 and a layer 102 thereon. For example, the layer 101 has a donor concentration of 1 × 10 18 cm -3 or more and 1 × 10 21 cm -3 or less, and the layer 102 has a donor concentration of 1 × 10 15 cm -3 or more and 1 × 10 17 cm -3The donor concentration is as follows: For example, the thickness of the layer 101 is 30 μm or more and 600 μm or less, and the thickness of the layer 102 is 5 μm or more and 50 μm or less.

[0014] Layer 101 of first n-type semiconductor layer 10 is typically made of a gallium oxide-based semiconductor substrate. In this case, the substrate is formed by slicing a bulk crystal of a gallium oxide-based single crystal grown by a melt growth method such as the FZ (Floating Zone) method or the EFG (Edge Defined Film Fed Growth) method, and polishing the surface. Layer 102 of first n-type semiconductor layer 10 is typically an epitaxial film formed using the upper surface of layer 101 as a base surface.

[0015] The second n-type semiconductor layer 11 is a layer made of single crystal Si. The second n-type semiconductor layer 11 contains donor impurities such as phosphorus, and has a concentration of, for example, 1×10 12 cm -3 That's it, 1 x 10 18 cm -3 With the following donor concentrations:

[0016] If the second n-type semiconductor layer 11 is too thin, it becomes difficult to form the n-type regions 15a, 15b and the p-type regions 16a, 16b, whereas if it is too thick, it becomes necessary to form the trenches 12a, 12b deeply. For this reason, the thickness of the second n-type semiconductor layer 11 is preferably, for example, 0.3 μm or more and 1.0 μm or less.

[0017] The method for forming the second n-type semiconductor layer 11 is not particularly limited, and for example, a Si single crystal may be epitaxially grown using the upper surface of the first n-type semiconductor layer 10 as a base surface, or a substrate bonding technique such as the Smart Cut method may be used to bond a Si substrate to the first n-type semiconductor layer 10. Note that using a substrate bonding technique such as the Smart Cut method is preferable to epitaxial growth because it can improve the crystal quality of the second n-type semiconductor layer 11.

[0018] In a field-effect transistor having a trench gate structure, it is necessary for the n-type semiconductor layer and the p-type semiconductor layer to form a p-n junction for its operation. However, when the semiconductor layer is composed of a layer made of a gallium oxide-based semiconductor and a layer made of Si, as in the field-effect transistor 1, it is difficult to form a p-n junction between them. For example, a layer of SiGa or Ga metal may be formed at the interface between the n-type semiconductor layer and the p-type semiconductor layer, or a layer with a very high donor concentration may be formed near the interface of the n-type semiconductor layer due to Si diffusion from the p-type semiconductor layer because Si acts as a donor in the gallium oxide-based semiconductor. On the other hand, in the field-effect transistor 1 having a planar structure, it is only necessary to form a p-n junction between the second n-type semiconductor layer 11 and the p-type regions 16 a, 16 b formed therein for its operation. Therefore, forming a p-n junction is easier than in a field-effect transistor having a trench gate structure.

[0019] The trenches 12a and 12b extend from the upper surface of the second n-type semiconductor layer 11 (the surface opposite to the first n-type semiconductor layer 10) to the first n-type semiconductor layer 10. That is, the bottoms of the trenches 12a and 12b and the bottoms of the p-type semiconductor portions 14a and 14b embedded in the trenches 12a and 12b are located below the upper surface of the first n-type semiconductor layer 10 (the surface on the second n-type semiconductor layer 11 side). The trenches 12a and 12b are formed by, for example, photolithography and dry etching.

[0020] The p-type semiconductor portions 14a, 14b are made of a p-type semiconductor, and p-type Si is preferred from the viewpoint of ease of manufacturing, for which trench filling technology has been established. On the other hand, a p-type oxide semiconductor is preferred from the viewpoint of being less reactive with the gallium oxide-based semiconductor that constitutes the first n-type semiconductor layer 10. Furthermore, among p-type oxide semiconductors, p-type NiO is preferably used as the material for the p-type semiconductor portions 14a, 14b, as it has been confirmed that it particularly increases the breakdown voltage of the field-effect transistor 1. The p-type semiconductor portions 14a, 14b are formed by depositing a p-type semiconductor in the trenches 12a, 12b, for example, by a CVD method, a sputtering method, or the like.

[0021] By providing the p-type semiconductor portions 14a and 14b, an electric field is concentrated at the bottoms of the p-type semiconductor portions 14a and 14b when a reverse bias is applied to the field-effect transistor 1 (when it is off). The bottoms of the p-type semiconductor portions 14a and 14b are located within the first n-type semiconductor layer 10 made of a gallium oxide-based semiconductor with high dielectric breakdown field strength, which suppresses dielectric breakdown in the semiconductor layer due to electric field concentration and increases the withstand voltage of the field-effect transistor 1. Furthermore, by providing the p-type semiconductor portions 14a and 14b and concentrating the electric field within the first n-type semiconductor layer 10, the channel resistance can be reduced by using Si, which has a higher electron mobility than a gallium oxide-based semiconductor, as the material for the second n-type semiconductor layer 11 in which the channel is formed, and this reduces the on-resistance of the device.

[0022] Furthermore, unlike a field-effect transistor with a trench gate structure in which a gate electrode and a gate insulating film are embedded in the trench, the field-effect transistor 1 in which the p-type semiconductor portions 14a and 14b are embedded in the trenches 12a and 12b does not have an insulator at the bottom of the trench. Therefore, there is no risk of dielectric breakdown of the insulator due to an electric field concentrated at the bottom of the trench. Furthermore, since the gate insulating film 18 of the field-effect transistor 1 having a planar structure is located on the second n-type semiconductor layer 11 to which no electric field is applied, there is no risk of dielectric breakdown.

[0023] Furthermore, if an insulator is present at the bottom of the trench, there is a risk that the characteristics of the element may fluctuate due to charging up of the insulator. However, in the field-effect transistor 1, the charge generated in the p-type semiconductor portions 14a, 14b can be released to the outside via the source electrode 20, so there is no risk of the element characteristics fluctuating due to charging up.

[0024] If the distance between the p-type semiconductor portions 14a and 14b, i.e., the width of the inter-trench region 13, is too large, a depletion layer extending from the p-type semiconductor portions 14a and 14b makes it difficult to close the current path between the p-type semiconductor portions 14a and 14b when a reverse bias is applied to the field-effect transistor 1, which may prevent the field-effect transistor 1 from turning off. On the other hand, if the width of the inter-trench region 13 is too small, it becomes difficult to form the n-type regions 15a, 15b and the p-type regions 16a, 16b. For this reason, the width of the inter-trench region 13 is preferably, for example, 0.5 μm or more and 2.0 μm or less.

[0025] Furthermore, in order to effectively close the current path by the depletion layers spreading from the p-type semiconductor portions 14a and 14b when a reverse bias is applied to the field-effect transistor 1, it is preferable that the bottoms of the p-type semiconductor portions 14a and 14b are 0.5 μm or more below the upper surface of the first n-type semiconductor layer 10, that is, that the trenches 12a and 12b are 0.5 μm or more deeper than the upper surface of the first n-type semiconductor layer 10.

[0026] The n-type regions 15a and 15b are the sources of the field-effect transistor 1 and have a high donor concentration to form an ohmic connection with the source electrode 20. For example, they are formed by ion-implanting donor impurities such as arsenic into the surface of the second n-type semiconductor layer 11.

[0027] The p-type regions 16a and 16b are p-type regions in the inter-trench region 13 provided to surround the n-type regions 15a and 15b in order to isolate the n-type regions 15a and 15b from the region of the inter-trench region 13 where the n-type regions 15a and 15b are not provided, and are formed, for example, by ion implantation of an acceptor impurity such as boron into the surface of the second n-type semiconductor layer 11. When a voltage is applied to the gate electrode 17, a horizontal channel is formed in the portion of the p-type regions 16a and 16b located on the surface layer of the inter-trench region 13, and a current flows between the source electrode 20 and the drain electrode 21.

[0028] Figure 2 is a horizontal cross-sectional view of the field-effect transistor 1 taken along the line AA shown in Figure 1. Figure 2 shows an example of the horizontal pattern of the p-type semiconductor portions 14a and 14b (trenches 12a and 12b), the n-type regions 15a and 15b, and the p-type regions 16a and 16b. In Figure 2, the horizontal position of the gate electrode 17 is indicated by a dotted line.

[0029] The horizontal patterns of the p-type semiconductor portions 14a, 14b (trenches 12a, 12b), n-type regions 15a, 15b, and p-type regions 16a, 16b are not limited to those shown in Figure 2. For example, trenches 12a, 12b may both be part of a single trench that is connected at a portion not shown in the vertical cross section of Figure 1. That is, p-type semiconductor portions 14a, 14b may both be part of a single p-type semiconductor portion. Furthermore, n-type regions 15a, 15b may both be part of a single n-type region.

[0030] The gate electrode 17 is made of a metal such as polycrystalline Si doped with a high concentration of donors, tungsten, or tungsten silicide, which is a compound of tungsten and Si. The gate insulating film 18 provided between the gate electrode 17 and the inter-trench region 13 and the interlayer insulating film 19 provided to cover the sides and the top of the gate electrode 17 are made of an insulator such as a silicon oxide film.

[0031] The source electrode 20 is made of a metal such as aluminum, and the drain electrode 21 is made of a metal such as titanium or aluminum.

[0032] 3, in the field-effect transistor 1, the second n-type semiconductor layer 11 may be thinned to such an extent that the bottom surface of the second n-type semiconductor layer 11 coincides with the bottom surfaces of the p-type regions 16a and 16b in the n-type semiconductor layer 11. By thinning the second n-type semiconductor layer 11, avalanche breakdown in the second n-type semiconductor layer 11 can be suppressed, and the breakdown voltage of the field-effect transistor 1 can be improved.

[0033] 4, in the field-effect transistor 1, a downward protrusion 171 that penetrates into a part of the inter-trench region 13 (a part where the n-type regions 15a, 15b are not provided) may be provided on the gate electrode 17. Since the part of the second n-type semiconductor layer 11 below the protrusion 171 becomes thinner, avalanche breakdown in the second n-type semiconductor layer 11 can be more effectively suppressed and the breakdown voltage of the field-effect transistor 1 can be further improved.

[0034] (Variation 1) FIG. 5 is a vertical cross-sectional view of a field effect transistor 2 which is a modified example of the field effect transistor 1 according to the first embodiment of the present invention.

[0035] Fig. 6 is a horizontal cross-sectional view of the field-effect transistor 2 taken along the cutting line BB shown in Fig. 5. Fig. 6 shows an example of the horizontal pattern of the p-type semiconductor portions 14a, 14b (trenches 12a, 12b), the n-type region 15a, and the p-type region 16a in the field-effect transistor 2. In Fig. 6, the horizontal position of the gate electrode 17 is indicated by a dotted line.

[0036] Field-effect transistor 2 differs from field-effect transistor 1 in that, of n-type regions 15a and 15b, only n-type region 15a is provided. If forming both n-type region 15a and n-type region 15b would shorten the gate length (the horizontal distance electrons travel) to the point that it would be difficult to manufacture the device, providing only n-type region 15a makes it possible to lengthen the gate length (increase the horizontal width of p-type region 16a) without changing the device size. This reduces the difficulty of manufacturing the device and allows for stable manufacturing.

[0037] Furthermore, in the field effect transistor 2, similarly to the field effect transistor 1, the second n-type semiconductor layer 11 may be thinned to such an extent that the bottom surface of the second n-type semiconductor layer 11 coincides with the bottom surface of the p-type region 16a in the n-type semiconductor layer 11. By thinning the second n-type semiconductor layer 11, avalanche breakdown in the second n-type semiconductor layer 11 can be suppressed, and the breakdown voltage of the field effect transistor 2 can be improved.

[0038] Furthermore, in the field-effect transistor 2, similarly to the field-effect transistor 1, a downward protrusion 171 that penetrates into a part of the inter-trench region 13 (a part where the n-type region 15a is not provided) may be provided on the gate electrode 17. Since the part of the second n-type semiconductor layer 11 below the protrusion 171 becomes thinner, avalanche breakdown in the second n-type semiconductor layer 11 can be more effectively suppressed and the breakdown voltage of the field-effect transistor 2 can be further improved.

[0039] (Variation 2) FIG. 7 is a vertical cross-sectional view of a field effect transistor 3 which is another modified example of the field effect transistor 1 according to the first embodiment of the present invention.

[0040] 8 is a horizontal cross-sectional view of the field-effect transistor 3 taken along the cutting line CC shown in FIG. 7. FIG. 8 shows an example of the horizontal pattern of the p-type semiconductor portions 14a and 14b (trenches 12a and 12b), the n-type regions 15a and 15b, and the p-type regions 16a and 16b in the field-effect transistor 3. In addition, the horizontal position of the gate electrode 17 is indicated by a dotted line in FIG. 7. The vertical cross-section shown in FIG. 7 corresponds to the vertical cross-section of the field-effect transistor 3 taken along the cutting line DD shown in FIG. 8.

[0041] The field effect transistor 3 differs from the field effect transistor 1 in that the longitudinal direction of the horizontal pattern of the p-type semiconductor portions 14a and 14b (trenches 12a and 12b) is perpendicular to the longitudinal direction of the horizontal pattern of the gate electrode 17, the n-type regions 15a and 15b, and the p-type regions 16a and 16b. By arranging the p-type semiconductor portions 14a and 14b and the gate electrode 17 in three dimensions, the degree of freedom in design is improved, and it is expected that the difficulty of manufacturing the element will be reduced.

[0042] Furthermore, in the field effect transistor 3, similarly to the field effect transistor 1, the second n-type semiconductor layer 11 may be thinned to such an extent that the bottom surface of the second n-type semiconductor layer 11 coincides with the bottom surfaces of the p-type regions 16a, 16b in the n-type semiconductor layer 11. By thinning the second n-type semiconductor layer 11, avalanche breakdown in the second n-type semiconductor layer 11 can be suppressed, and the breakdown voltage of the field effect transistor 3 can be improved.

[0043] Furthermore, in the field effect transistor 3, similarly to the field effect transistor 1, a downward protrusion 171 that penetrates into a part of the inter-trench region 13 (a part where the n-type regions 15a, 15b are not provided) may be provided on the gate electrode 17. Since the part of the second n-type semiconductor layer 11 below the protrusion 171 becomes thinner, avalanche breakdown in the second n-type semiconductor layer 11 can be more effectively suppressed and the breakdown voltage of the field effect transistor 3 can be further improved.

[0044] (Effects of the first embodiment) According to the field effect transistors 1 to 3 of the first embodiment of the present invention, the trench structure in which the p-type semiconductor portions 14a, 14b (or the p-type semiconductor portion 14a) are buried in the trenches 12a, 12b (or the trench 12a) and the planar structure in which the gate insulating film 18 is provided on the inter-trench region 13 overcomes the drawback of the trench gate structure, namely, dielectric breakdown of the insulator due to the electric field concentrated at the bottom of the trench, and a higher breakdown voltage can be obtained.

[0045] Second Embodiment (Field-effect transistor structure) 9 is a vertical cross-sectional view of a field effect transistor 4 according to the second embodiment of the present invention. The field effect transistor 4 is a vertical field effect transistor having a trench gate structure.

[0046] The field-effect transistor 4 includes a first n-type semiconductor layer 10 made of a gallium oxide-based semiconductor, a p-type semiconductor layer 41 made of Si provided on the first n-type semiconductor layer 10, a second n-type semiconductor layer 42 made of Si provided on the p-type semiconductor layer 41, p-type semiconductor portions 46a, 46b embedded in bottoms of trenches 43a, 43b extending from an upper surface of the second n-type semiconductor layer 42 to the first n-type semiconductor layer 10, gate electrodes 44a, 44b embedded and covered by gate insulating films 45a, 45b on the p-type semiconductor portions 46a, 46b in the trenches 43a, 43b, a source electrode 47 connected to an upper surface of the second n-type semiconductor layer 42 and the p-type semiconductor portions 46a, 46b, and a drain electrode 48 connected to the first n-type semiconductor layer 10.

[0047] The p-type semiconductor layer 41 and the second n-type semiconductor layer 42 are layers made of single crystal Si. The p-type semiconductor layer 41 contains an acceptor impurity such as boron, and has a dopant concentration of, for example, 1×10 15 cm -3 That's it, 1 x 10 18 cm -3 The second n-type semiconductor layer 42 contains donor impurities such as phosphorus and arsenic, and has an acceptor concentration of, for example, 1×10 18 cm -3 That's it, 1 x 1021 cm -3 The p-type semiconductor layer 41 has a thickness of, for example, 0.3 μm or more and 1.2 μm or less, and the second n-type semiconductor layer 42 has a thickness of, for example, 0.1 μm or more and 0.3 μm or less.

[0048] The trenches 43a and 43b are formed by, for example, photolithography and dry etching.

[0049] The p-type semiconductor portions 46a, 46b are made of a p-type semiconductor, and p-type Si is preferred from the viewpoint of ease of manufacturing, for which trench filling technology has been established. On the other hand, a p-type oxide semiconductor is preferred from the viewpoint of being less likely to react with the gallium oxide-based semiconductor that constitutes the first n-type semiconductor layer 10. Furthermore, among p-type oxide semiconductors, p-type NiO is preferably used as the material for the p-type semiconductor portions 46a, 46b, as it has been confirmed that it particularly increases the breakdown voltage of the field-effect transistor 4. The p-type semiconductor portions 46a, 46b are formed by depositing a p-type semiconductor in the trenches 43a, 43b by, for example, a CVD method or a sputtering method.

[0050] The bottoms of the gate electrodes 44a, 44b are located below the upper surface (surface on the p-type semiconductor layer 41 side) of the first n-type semiconductor layer 10. This allows the electric field to be concentrated in the first n-type semiconductor layer 10 made of a gallium oxide-based semiconductor with high dielectric breakdown field strength, thereby increasing the withstand voltage of the field-effect transistor 4. Furthermore, by concentrating the electric field in the first n-type semiconductor layer 10, the channel resistance can be reduced by using Si, which has a higher electron mobility than a gallium oxide-based semiconductor, as the material for the p-type semiconductor layer 41 in which a channel is formed, thereby reducing the on-resistance of the element.

[0051] Furthermore, by providing the p-type semiconductor portions 46a and 46b, it is possible to alleviate the concentration of an electric field on the gate insulating films 45a and 45b below the gate electrodes 44a and 44b when a reverse bias is applied (when the field effect transistor 4 is off) to the field effect transistor 4. Furthermore, in the field effect transistor 4, the p-type semiconductor portions 46a and 46b are connected to the source electrode 47 at a portion not shown in the cross section of Fig. 9, and charges generated in the p-type semiconductor portions 46a and 46b can be released to the outside via the source electrode 47, so there is no risk of fluctuations in the device characteristics due to charge-up.

[0052] If the distance between trenches 43a and 43b is too large, a depletion layer extending from gate insulating films 45a and 45b will weaken the effect of reducing the electric field strength at the junction between n-type semiconductor layer 10 and p-type semiconductor layer 41 when a reverse bias is applied to field-effect transistor 4, potentially resulting in dielectric breakdown in p-type semiconductor layer 41. On the other hand, if the distance between trenches 43a and 43b is too small, it will be difficult to form trenches 43a and 43b by patterning using a stepper. For this reason, the distance between trenches 43a and 43b is preferably, for example, 0.6 μm or more and 1.8 μm or less.

[0053] Furthermore, in order to effectively reduce the electric field strength at the junction between the n-type semiconductor layer 10 and the p-type semiconductor layer 41 by the depletion layers extending from the gate insulating films 45a and 45b when a reverse bias is applied to the field-effect transistor 4, it is preferable that the bottoms of the gate electrodes 44a and 44b are 0.6 μm or more below the top surface of the first n-type semiconductor layer 10.

[0054] The gate electrodes 44a and 44b are made of a metal such as polycrystalline Si doped with a high concentration of donors, tungsten, or tungsten silicide, which is a compound of tungsten and Si. The gate insulating films 45a and 45b are made of an insulator such as a silicon oxide film.

[0055] The source electrode 47 is made of a metal such as aluminum, and the drain electrode 48 is made of a metal such as titanium or aluminum.

[0056] (Effects of the second embodiment) According to the field-effect transistor 4 of the second embodiment of the present invention, by providing p-type semiconductor portions 46a, 46b under the gate electrodes 44a, 44b covered with the gate insulating films 45a, 45b in the trenches 43a, 43b, the concentration of the electric field on the gate insulating films 45a, 45b under the gate electrodes 44a, 44b is alleviated, and by dissipating the charges generated in the p-type semiconductor portions 46a, 46b to the outside via the source electrode 47, charging up of the p-type semiconductor portions 46a, 46b can be prevented.

[0057] Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments and various modifications can be made without departing from the spirit and scope of the invention. Furthermore, the components of the above-described embodiments can be combined in any manner without departing from the spirit and scope of the invention.

[0058] Furthermore, the above-described embodiments do not limit the scope of the invention as claimed, and it should be noted that not all of the combinations of features described in the embodiments are necessarily essential to the means for solving the problems of the invention. [Explanation of symbols]

[0059] 1, 2, 3...field effect transistor, 10...first n-type semiconductor layer, 11...second n-type semiconductor layer, 12a, 12b...trench, 13...inter-trench region, 14a, 14b...p-type semiconductor portion, 15a, 15b...n-type region, 16a, 16b...p-type region, 17...gate electrode, 18...gate insulating film, 20...source electrode, 21...drain electrode, 4...field effect transistor, 41...p-type semiconductor layer, 42...second n-type semiconductor layer, 43a, 43b...trench, 44a, 44b...gate electrode, 45a, 45b...gate insulating film, 46a, 46b...p-type semiconductor portion, 47...source electrode, 48...drain electrode

Claims

1. a first n-type semiconductor layer made of a gallium oxide-based semiconductor; a second n-type semiconductor layer made of Si provided on the first n-type semiconductor layer; a p-type semiconductor portion embedded in a trench extending from an upper surface of the second n-type semiconductor layer to the first n-type semiconductor layer; an n-type region provided in a part of a surface layer of an upper surface of an inter-trench region sandwiched by the trenches on both sides of the second n-type semiconductor layer; a p-type region provided in the inter-trench region so as to surround the n-type region; a gate electrode provided on the inter-trench region via a gate insulating film; a source electrode connected to the n-type region and the p-type semiconductor portion; a drain electrode connected to the first n-type semiconductor layer; A field effect transistor comprising:

2. the p-type semiconductor portion is made of a p-type oxide semiconductor; 2. The field effect transistor of claim 1.

3. the p-type oxide semiconductor is p-type NiO; 3. The field effect transistor of claim 2.

4. The width of the inter-trench region is 0.5 μm or more and 2.0 μm or less. The field effect transistor according to any one of claims 1 to 3.

5. the trench is 0.5 μm or more deeper than the top surface of the first n-type semiconductor layer; The field effect transistor according to any one of claims 1 to 4.

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