Semiconductor device and method for manufacturing the same

Abstract

To suppress an increase of a saturation current.SOLUTION: A semiconductor device comprises: a first trench which is provided while extending from a top face of a first impurity layer into a first semiconductor layer; a second trench which is provided while extending from a top face of a second impurity layer to lower than a bottom face of the first semiconductor layer; a second semiconductor layer of a first conductivity type which is provided in a surface layer of the first impurity layer and disposed while being held between the first trench and a third impurity layer in a planar view; and a third semiconductor layer of the first conductivity type which is provided in a surface layer of the second impurity layer and disposed while being held between the second trench and the third impurity layer in the planar view.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The technology disclosed in this specification relates to semiconductor technology. [Background technology]

[0002] For example, a semiconductor device such as that shown in Patent Document 1, specifically an insulated gate bipolar transistor (IGBT), has a trench structure (specifically, shallow gate trenches) periodically formed on the upper surface of an N-type semiconductor substrate. An oxide film layer is formed on the side and bottom surfaces of the gate trench, and a buried layer made of, for example, polysilicon is further provided surrounded by the oxide film layer. The buried layer in the gate trench is connected to a gate electrode.

[0003] The IGBT also has another trench structure (specifically, a deep gate trench) adjacent to the gate trench and periodically formed on the upper surface of the substrate. An oxide film layer is formed on the side and bottom surfaces of the gate trench, and a buried layer is further provided surrounded by the oxide film layer. The buried layer in the gate trench is connected to another gate electrode.

[0004] The IGBT also has one or more trench structures (specifically, deep dummy trenches) formed on the upper surface of the substrate, adjacent to another gate trench on the opposite side of the gate trench. An oxide film layer is formed on the side and bottom of the dummy trench, and a buried layer is further provided surrounded by the oxide film layer. The buried layer in the dummy trench is connected to the emitter electrode.

[0005] Meanwhile, an N-type layer is formed on the surface of the substrate between the gate trenches. A P-type layer is formed on the surface of the N-type layer. Furthermore, an N+ type emitter layer and a P+ type emitter layer are selectively formed on the surface of the P-type layer.

[0006] The N-type layer contacts the substrate, the oxide layer of the gate trench, and the oxide layer of the other gate trench.

[0007] The P-type layer contacts the P+ type emitter layer, the N-type layer, the oxide layer of the gate trench, and the oxide layer of the other gate trench.

[0008] The N+ type emitter layer contacts the P type layer, the oxide layer of the gate trench, and the oxide layer of the other gate trench. [Prior art documents] [Patent documents]

[0009] [Patent Document 1] Japanese Patent Application Publication No. 2019-186318 Summary of the Invention [Problem to be solved by the invention]

[0010] When the IGBT is turned on, the gate electrode and the other gate electrode are simultaneously turned on, and electrons are injected into the substrate from the gate trench and the other gate trench, which increases the saturation current of the IGBT and shortens the maximum short-circuit pulse width that can be short-circuited.

[0011] To ensure short-circuit capability, the electron injection efficiency per unit area can be reduced by increasing the spacing between adjacent N+ emitter layers, thereby suppressing the saturation current. However, increasing this spacing increases the parasitic resistance in the region where the P+ emitter layer is formed, degrading the Vce(sat)-Eoff tradeoff characteristics.

[0012] In addition, by driving the other gate electrodes at a lower voltage than the gate electrodes (for example, the gate electrodes are ±15 V and the other gate electrodes are ±9 V), electron injection from the gate trench can be suppressed and the saturation current can be reduced. However, driving them at different gate voltages complicates the operation of the gate driver.

[0013] The technology disclosed in this specification has been made in consideration of the problems described above, and is a technology for suppressing an increase in saturation current while preventing a deterioration in the Vce(sat)-Eoff trade-off characteristics or an increase in the complexity of gate driver operation. [Means for solving the problem]

[0014] A semiconductor device according to a first aspect of the technology disclosed in the present specification includes a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type provided on a surface layer of the semiconductor substrate, a first impurity layer of a second conductivity type and a second impurity layer of the second conductivity type selectively provided on a surface layer of the first semiconductor layer, a first trench provided from an upper surface of the first impurity layer to reach inside the first semiconductor layer, at least one second trench provided from an upper surface of the second impurity layer to reach below a lower surface of the first semiconductor layer, a first electrode layer surrounded by an oxide film and embedded in the first trench, a second electrode layer surrounded by an oxide film and embedded in the second trench, a first gate electrode connected to the first electrode layer, and the The semiconductor device comprises a second gate electrode connected to a second electrode layer, a third impurity layer of a second conductivity type provided across a surface layer of the first impurity layer and a surface layer of the second impurity layer, a second semiconductor layer of a first conductivity type provided on the surface layer of the first impurity layer and sandwiched between the first trench and the third impurity layer in a planar view, and a third semiconductor layer of a first conductivity type provided on the surface layer of the second impurity layer and sandwiched between the second trench and the third impurity layer in a planar view, wherein the impurity concentration of the first semiconductor layer is higher than the impurity concentration of the semiconductor substrate, the impurity concentration of the second impurity layer is higher than the impurity concentration of the first impurity layer, and the impurity concentration of the third impurity layer is higher than the impurity concentration of the second impurity layer. [Effects of the Invention]

[0015] According to at least the first aspect of the technique disclosed in the present specification, it is possible to suppress an increase in saturation current while preventing a deterioration in the Vce(sat)-Eoff trade-off characteristics or an increase in the complexity of the gate driver operation.

[0016] Furthermore, objects, features, aspects, and advantages associated with the technology disclosed herein will become more apparent from the detailed description and accompanying drawings set forth below. [Brief explanation of the drawings]

[0017] [Figure 1] 1 is a diagram illustrating an example of a configuration of a semiconductor device according to an embodiment; [Figure 2] 10A and 10B are diagrams illustrating a modified example of the configuration of the semiconductor device according to the embodiment. [Figure 3] 1 is a diagram illustrating an example of a configuration of a semiconductor device according to an embodiment; [Figure 4] 10A and 10B are diagrams illustrating a modified example of the configuration of the semiconductor device according to the embodiment. [Figure 5] 53 is a diagram showing examples of output characteristics in the configuration shown in FIG. 52, the configuration shown in FIG. 2, and the configuration shown in FIG. 4. FIG. [Figure 6] 53 is a diagram showing examples of output characteristics in the configuration shown in FIG. 52, the configuration shown in FIG. 2, and the configuration shown in FIG. 4. FIG. [Figure 7] FIG. 53 is a diagram showing an example of a comparison of normalized saturation current values ​​in the configuration shown in FIG. 52, the configuration shown in FIG. 2, and the configuration shown in FIG. [Figure 8] FIG. 10 is a diagram showing the relationship between a saturation current value and the maximum value of a pulse width capable of short-circuit interruption. [Figure 9] FIG. 5 is a diagram showing an example of the normalized concentration dependency of a P-type layer on a saturation voltage Vce(sat) in the configuration shown in FIG. [Figure 10] FIG. 5 is a diagram showing an example of the dependency of the normalized concentration of the P-type layer on the saturation current Ic(sat) in the configuration shown in FIG. 4. [Figure 11]FIG. 5 is a diagram showing an example of the normalized concentration dependency of the N-type layer on the saturation voltage Vce(sat) in the configuration shown in FIG. [Figure 12] FIG. 5 is a diagram showing an example of the normalized concentration dependency of the N-type layer on the saturation current Ic(sat) in the configuration shown in FIG. [Figure 13] FIG. 1 is a diagram showing an example of a circuit diagram of a double-gate controlled IGBT. [Figure 14] 14 is an example of a sequence of gate voltages input to the IGBT shown in FIG. 13. [Figure 15] FIG. 14 is a diagram showing an example of a turn-off waveform of the IGBT shown in FIG. [Figure 16] FIG. 5 is a diagram showing an example of the dependency of dt on Eoff when the impurity concentration of the N-type layer in the configuration shown in FIG. 4 is different. [Figure 17] FIG. 10 is a diagram showing an example of a saturation voltage Vce(sat)-Eoff trade-off characteristic. [Figure 18] 1 is a diagram illustrating an example of a configuration of a semiconductor device according to an embodiment; [Figure 19] 19 is a cross-sectional view taken along the cross section D1 shown in FIG. 18. [Figure 20] 19 is a cross-sectional view taken along the cross section D2 shown in FIG. 18. [Figure 21] 19A to 19C are diagrams illustrating an example of a method for manufacturing the structure shown in FIG. 18. [Figure 22] 19A to 19C are diagrams illustrating an example of a method for manufacturing the structure shown in FIG. 18. [Figure 23] 19A to 19C are diagrams illustrating an example of a method for manufacturing the structure shown in FIG. 18. [Figure 24] 19A to 19C are diagrams illustrating an example of a method for manufacturing the structure shown in FIG. 18. [Figure 25] 19A to 19C are diagrams illustrating an example of a method for manufacturing the structure shown in FIG. 18. [Figure 26] 19A to 19C are diagrams illustrating an example of a method for manufacturing the structure shown in FIG. 18. [Figure 27] 19A to 19C are diagrams illustrating another example of a method for manufacturing the structure shown in FIG. 18. [Figure 28]19A to 19C are diagrams illustrating another example of a method for manufacturing the structure shown in FIG. 18. [Figure 29] 19A to 19C are diagrams illustrating another example of a method for manufacturing the structure shown in FIG. 18. [Figure 30] 19A to 19C are diagrams illustrating another example of a method for manufacturing the structure shown in FIG. 18. [Figure 31] 19A to 19C are diagrams illustrating an example of a method for manufacturing the structure shown in FIG. 18. [Figure 32] 19A to 19C are diagrams illustrating an example of a method for manufacturing the structure shown in FIG. 18. [Figure 33] 19A to 19C are diagrams illustrating an example of a method for manufacturing the structure shown in FIG. 18. [Figure 34] 19A to 19C are diagrams illustrating an example of a method for manufacturing the structure shown in FIG. 18. [Figure 35] 19A to 19C are diagrams illustrating an example of a method for manufacturing the structure shown in FIG. 18. [Figure 36] 19A to 19C are diagrams illustrating an example of a method for manufacturing the structure shown in FIG. 18. [Figure 37] 19A to 19C are diagrams illustrating an example of a method for manufacturing the structure shown in FIG. 18. [Figure 38] 19A to 19C are diagrams illustrating an example of a method for manufacturing the structure shown in FIG. 18. [Figure 39] 19A to 19C are diagrams illustrating an example of a method for manufacturing the structure shown in FIG. 18. [Figure 40] 19A to 19C are diagrams illustrating an example of a method for manufacturing the structure shown in FIG. 18. [Figure 41] 19A to 19C are diagrams illustrating an example of a method for manufacturing the structure shown in FIG. 18. [Figure 42] 19A to 19C are diagrams illustrating an example of a method for manufacturing the structure shown in FIG. 18. [Figure 43] 19A to 19C are diagrams illustrating another example of a method for manufacturing the structure shown in FIG. 18. [Figure 44] 19A to 19C are diagrams illustrating another example of a method for manufacturing the structure shown in FIG. 18. [Figure 45] 19A to 19C are diagrams illustrating another example of a method for manufacturing the structure shown in FIG. 18. [Figure 46] 19A to 19C are diagrams illustrating another example of a method for manufacturing the structure shown in FIG. 18. [Figure 47]19A to 19C are diagrams illustrating another example of a method for manufacturing the structure shown in FIG. 18. [Figure 48] 19A to 19C are diagrams illustrating another example of a method for manufacturing the structure shown in FIG. 18. [Figure 49] 19A to 19C are diagrams illustrating another example of a method for manufacturing the structure shown in FIG. 18. [Figure 50] 10 is a diagram showing the correlation between the trench opening width and the trench bottom depth. FIG. [Figure 51] FIG. 5 is a diagram showing the relationship between the breakdown voltage and the trench spacing of the structures shown in FIGS. [Figure 52] 1A and 1B are diagrams illustrating an example of the configuration of a semiconductor device having a dummy trench; [Figure 53] 1A and 1B are diagrams illustrating an example of the configuration of a semiconductor device having a dummy trench; DETAILED DESCRIPTION OF THE INVENTION

[0018] Hereinafter, embodiments will be described with reference to the accompanying drawings. In the following embodiments, detailed features are shown for the purpose of explaining the technology, but these are merely examples and are not necessarily essential features for enabling the embodiments to be implemented.

[0019] The drawings are schematic, and for the sake of convenience, components may be omitted or simplified as appropriate. The relative sizes and positions of components shown in different drawings are not necessarily accurately depicted and may be changed as appropriate. Hatching may also be used in drawings such as plan views that are not cross-sectional views to facilitate understanding of the embodiments.

[0020] In the following description, the same components are denoted by the same reference numerals, and their names and functions are also the same. Therefore, detailed descriptions of them may be omitted to avoid duplication.

[0021] Furthermore, in the description given in this specification, when a certain component is described as "comprising," "including," or "having," unless otherwise specified, this is not an exclusive expression that excludes the presence of other components.

[0022] Furthermore, although ordinal numbers such as "first" or "second" may be used in the descriptions in this specification, these terms are used for convenience to facilitate understanding of the contents of the embodiments, and the contents of the embodiments are not limited to the order that may result from these ordinal numbers.

[0023] Furthermore, in the description provided in this specification, terms that indicate specific positions or directions, such as "top," "bottom," "left," "right," "side," "bottom," "front," or "back," may be used, but these terms are used for convenience to facilitate understanding of the contents of the embodiments and have no relation to the positions or directions when the embodiments are actually implemented.

[0024] Furthermore, in the description of the present specification, when "the upper surface of ..." or "the lower surface of ..." is used, it is intended to include not only the upper surface or lower surface of the target component itself, but also a state in which another component is formed on the upper surface or lower surface of the target component. For example, when it is described as "B provided on the upper surface of A," it does not preclude another component "C" from being interposed between A and B.

[0025] First Embodiment The semiconductor device according to the present embodiment will be described below. For convenience of explanation, first, the techniques related to the configuration of the semiconductor device known to the inventors will be described.

[0026] 52 and 53 are diagrams showing an example of the configuration of a semiconductor device having a dummy trench. The semiconductor device shown in FIGS. 52 and 53, specifically an insulated gate bipolar transistor (IGBT), has a trench structure (specifically, shallow gate trenches 81) periodically formed on the upper surface of an N-type semiconductor substrate 1. A gate oxide film 6 is formed on the side and bottom surfaces of the gate trench 81, and a buried layer 7 made of, for example, polysilicon is further provided surrounded by the gate oxide film 6. The buried layer 7 in the gate trench 81 is connected to a gate electrode G1.

[0027] The IGBT also has a trench structure (specifically, deep gate trenches 82) adjacent to the gate trenches 81 and periodically formed on the upper surface of the substrate 1. A gate oxide film 6 is formed on the side and bottom surfaces of the gate trenches 82, and a buried layer 7 is further provided surrounded by the gate oxide film 6. The buried layer 7 in the gate trench 82 is connected to the gate electrode G2.

[0028] The IGBT also has one or more trench structures (specifically, deep dummy trenches 9) formed on the upper surface of the substrate 1 adjacent to the gate trench 82 on the side opposite the gate trench 81. A gate oxide film 6 is formed on the side and bottom of the dummy trench 9, and a buried layer 7 is further provided surrounded by the gate oxide film 6. The buried layer 7 in the dummy trench 9 is connected to the emitter electrode E.

[0029] Meanwhile, an N-type layer 3 is formed in the surface layer of the substrate 1 between the gate trenches 81 and 82 by, for example, ion implantation or thermal diffusion. The impurity concentration of the N-type layer 3 is higher than the impurity concentration of the substrate 1. A P-type layer 2 is formed in the surface layer of the N-type layer 3. Furthermore, an N+ type emitter layer 4 and a P+ type emitter layer 5 are selectively formed in the surface layer of the P-type layer 2.

[0030] The N-type layer 3 is in contact with the substrate 1, the gate oxide film 6 of the gate trench 81, and the gate oxide film 6 of the gate trench .

[0031] The P-type layer 2 is in contact with the P+ type emitter layer 5, the N-type layer 3, the gate oxide film 6 of the gate trench 81, and the gate oxide film 6 of the gate trench .

[0032] The N+ type emitter layer 4 is in contact with the P type layer 2, the gate oxide film 6 of the gate trench 81, and the gate oxide film 6 of the gate trench .

[0033] <Configuration of semiconductor device> FIG. 1 is a diagram showing an example of the configuration of a semiconductor device according to the present embodiment. The semiconductor device shown in the present embodiment is particularly a semiconductor device including a bipolar transistor having an insulated gate. The semiconductor device also includes a reverse conducting IGBT (RC-IGBT). The target semiconductor devices also include other semiconductor devices such as metal-oxide-semiconductor field-effect transistors (MOSFETs). In the following embodiments, a semiconductor device of a high breakdown voltage class with a breakdown voltage of about 3300 V is shown as an example, but the breakdown voltage class is not limited to such a high breakdown voltage.

[0034] 1, specifically, the IGBT, has a trench structure (specifically, shallow gate trenches 81) periodically formed on the upper surface of an N-type semiconductor substrate 1. A gate oxide film 6 is formed on the side and bottom surfaces of the gate trench 81, and further, a buried layer 7 made of, for example, polysilicon is provided and surrounded by the gate oxide film 6. The buried layer 7 in the gate trench 81 is connected to a gate electrode G1.

[0035] The IGBT also has a trench structure (specifically, deep gate trenches 82) adjacent to the gate trenches 81 and periodically formed on the upper surface of the substrate 1. A gate oxide film 6 is formed on the side and bottom surfaces of the gate trenches 82, and a buried layer 7 is further provided surrounded by the gate oxide film 6. The buried layer 7 in the gate trench 82 is connected to the gate electrode G2.

[0036] On the other hand, an N-type layer 3 is formed in the surface layer of the substrate 1 between the gate trenches 81 and 82. A P-type layer 21 and a P-type layer 22 (channel layer) are selectively formed in the surface layer of the N-type layer 3. An N+-type emitter layer 41 and a P+-type emitter layer 5 are selectively formed in the surface layer of the P-type layer 21. An N+-type emitter layer 42 and a P+-type emitter layer 5 are selectively formed in the surface layer of the P-type layer 22. The P+-type emitter layer 5 is provided across the surface layers of the P-type layer 21 and the P-type layer 22.

[0037] The gate trench 81 is provided from the upper surface of the P-type layer 21 to reach into the N-type layer 3. The gate trench 82 is provided from the upper surface of the P-type layer 22 to reach below the lower surface of the N-type layer 3.

[0038] The N-type layer 3 is in contact with the substrate 1, the gate oxide film 6 of the gate trench 81, and the gate oxide film 6 of the gate trench .

[0039] The P-type layer 21 is in contact with the P+ type emitter layer 5, the N-type layer 3, the gate oxide film 6 of the gate trench 81, and the gate oxide film 6 of the gate trench .

[0040] The N+ type emitter layer 41 is in contact with the P type layer 21 and the gate oxide film 6 of the gate trench 81. The N+ type emitter layer 41 is disposed between the gate trench 81 and the P+ type emitter layer 5 in plan view.

[0041] The P-type layer 22 is in contact with the P+ type emitter layer 5, the N-type layer 3, and the gate oxide film 6 of the gate trench .

[0042] The N+ type emitter layer 42 contacts the P type layer 22 and the gate oxide film 6 of the gate trench 82. The N+ type emitter layer 42 is arranged to be sandwiched between the gate trench 82 and the P+ type emitter layer 5 in a plan view.

[0043] Here, the depth (d1) of the bottom surface of the gate trench 81 (from the upper surface of the P+ type emitter layer 5), the depth (d2) of the lower surface of the N type layer 3 (from the upper surface of the P+ type emitter layer 5), and the depth (d3) of the bottom surface of the gate trench 82 (from the upper surface of the P+ type emitter layer 5) satisfy the relationship of "d1 < d2 < d3".

[0044] Also, the peak impurity concentration (P1) of the P type layer 21 and the peak impurity concentration (P2) of the P type layer 22 satisfy the relationship of "P1 < P2".

[0045] And the semiconductor device shown in FIG. 1 is connected to the gate electrode G2 and the gate electrode G1, and includes a control unit 500 that controls the gate electrode G2 and the gate electrode G1 so that the turn-off timing of the voltage signal of the gate electrode G1 is later than the turn-off timing of the voltage signal of the gate electrode G2.

[0046] FIG. 2 is a diagram showing a modification of the configuration of the semiconductor device according to the present embodiment.

[0047] The semiconductor device shown in FIG. 2 has one or more trench structures (specifically, deep dummy trenches 9) formed on the upper surface of the substrate 1, adjacent to the gate trench 82 on the side opposite to the gate trench 81, in addition to the semiconductor device shown in FIG. 1. The gate oxide film 6 is formed on the side surface and the bottom surface of the dummy trench 9, and furthermore, an embedded layer 7 is provided surrounded by the gate oxide film 6. The embedded layer 7 in the dummy trench 9 is connected to the emitter electrode E. The dummy trench 9 is provided to reach below the lower surface of the N type layer 3 from the upper surface of the substrate 1.

[0048] In FIG. 2, the P-type layer 22 and the N-type layer 3 are formed between the gate trench 82 and the dummy trench 9, but the P-type layer 22 and the N-type layer 3 do not have to be formed in that location, or other diffusion layers may be formed instead of the P-type layer 22 and the N-type layer 3.

[0049] 2 can be made equal to the depth of the bottom surface of the gate trench 82. By forming them in this manner, the dummy trench 9 and the gate trench 82 can be formed simultaneously, thereby reducing manufacturing costs.

[0050] <Second embodiment> A semiconductor device according to the present embodiment will be described. In the following description, components similar to those described in the above embodiments will be denoted by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0051] <Configuration of semiconductor device> FIG. 3 is a diagram showing an example of the configuration of a semiconductor device according to this embodiment.

[0052] 3, specifically, the IGBT, has a trench structure (specifically, shallow gate trenches 81) periodically formed on the upper surface of an N-type semiconductor substrate 1. A gate oxide film 6 is formed on the side and bottom surfaces of the gate trench 81, and further, a buried layer 7 made of, for example, polysilicon is provided and surrounded by the gate oxide film 6. The buried layer 7 in the gate trench 81 is connected to a gate electrode G1.

[0053] The IGBT also has a trench structure (specifically, deep gate trenches 82) adjacent to the gate trenches 81 and periodically formed on the upper surface of the substrate 1. A gate oxide film 6 is formed on the side and bottom surfaces of the gate trenches 82, and a buried layer 7 is further provided surrounded by the gate oxide film 6. The buried layer 7 in the gate trench 82 is connected to the gate electrode G2.

[0054] On one hand, an N-type layer 31 and an N-type layer 32 are selectively formed on the surface layer of the substrate 1 between the gate trench 81 and the gate trench 82. Further, a P-type layer 21 is formed on the surface layer of the N-type layer 31. Also, a P-type layer 22 is formed on the surface layer of the N-type layer 32.

[0055] Furthermore, an N+-type emitter layer 41 and a P+-type emitter layer 5 are selectively formed on the surface layer of the P-type layer 21. Also, an N+-type emitter layer 42 and a P+-type emitter layer 5 are selectively formed on the surface layer of the P-type layer 22.

[0056] The N-type layer 31 contacts the substrate 1 and the gate oxide film 6 of the gate trench 81.

[0057] The N-type layer 32 contacts the substrate 1 and the gate oxide film 6 of the gate trench 82.

[0058] The P-type layer 21 contacts the P+-type emitter layer 5, the N-type layer 31, and the gate oxide film 6 of the gate trench 81.

[0059] The N+-type emitter layer 41 contacts the P-type layer 21 and the gate oxide film 6 of the gate trench 81.

[0060] The P-type layer 22 contacts the P+-type emitter layer 5, the N-type layer 32, and the gate oxide film 6 of the gate trench 82.

[0061] The N+-type emitter layer 42 contacts the P-type layer 22 and the gate oxide film 6 of the gate trench 82.

[0062] Here, the depth (d1) of the bottom surface of the gate trench 81 (from the upper surface of the P+-type emitter layer 5), the depth (d2a) of the lower surface of the N-type layer 31 (from the upper surface of the P+-type emitter layer 5), the depth (d2b) of the lower surface of the N-type layer 32 (from the upper surface of the P+-type emitter layer 5), and the depth (d3) of the bottom surface of the gate trench 82 (from the upper surface of the P+-type emitter layer 5) satisfy the relationships of "d1 < d2a < d3" and "d1 < d2b < d3".

[0063] Also, the peak impurity concentration (P1) of the P-type layer 21 and the peak impurity concentration (P2) of the P-type layer 22 satisfy the relationship of "P1 < P2".

[0064] Also, the peak impurity concentration (N1) of the N-type layer 31 and the peak impurity concentration (N2) of the N-type layer 32 satisfy the relationship of "N1 < N2".

[0065] And, the semiconductor device shown in FIG. 3 is connected to the gate electrode G2 and the gate electrode G1, and includes a control unit 500 that controls the gate electrode G2 and the gate electrode G1 so that the turn-off timing of the voltage signal of the gate electrode G1 is later than the turn-off timing of the voltage signal of the gate electrode G2 .

[0066] FIG. 4 is a diagram showing a modified example of the configuration of the semiconductor device according to the present embodiment.

[0067] The semiconductor device shown in FIG. 4 has one or more trench structures (specifically, deep dummy trenches 9) formed on the upper surface of the substrate 1 adjacent to the gate trench 82 on the side opposite to the gate trench 81 in addition to the semiconductor device shown in FIG. 3. A gate oxide film 6 is formed on the side surface and the bottom surface of the dummy trench 9, and a buried layer 7 is provided surrounded by the gate oxide film 6. The buried layer 7 in the dummy trench 9 is connected to the emitter electrode E.

[0068] In FIG. 4, although the P-type layer 22 and the N-type layer 32 are formed between the gate trench 82 and the dummy trench 9, the P-type layer 22 and the N-type layer 32 may not be formed at this location, or other diffusion layers may be formed instead of the P-type layer 22 and the N-type layer 32.

[0069] Here, the N-type layer 31 (and the P-type layer 21) is formed along the direction in which the gate trenches 81 and 82 extend in a plan view of the substrate 1. And the N-type layer 31 (and the P-type layer 21) is formed adjacent to the gate trench 81 in a plan view.

[0070] Similarly, the N-type layer 32 (and the P-type layer 22) are formed along the direction in which the gate trenches 81 and 82 extend in a plan view of the substrate 1. The N-type layer 32 (and the P-type layer 22) are formed adjacent to the gate trench 82 in a plan view.

[0071] The allowable range of the peak impurity concentration of the substrate 1 in FIGS. 1 to 4 is, for example, 1×10 12 cm -3 Above and 1×10 14 cm -3 The following is the result.

[0072] The peak impurity concentration of the P-type layer 21 in FIGS. 1 to 4 is, for example, 2.0×10 17 cm -3 The tolerance is, for example, 1×10 16 cm -3 Above and 1×10 17 cm -3 The concentration gradient of the P-type layer 21 in FIGS. 1 to 4 is, for example, 8.0×10 17 cm -3 1 to 4, the peak impurity concentration of the P-type layer 22 is, for example, 4.0×10 17 cm -3 The tolerance is, for example, 1×10 16 cm -3 Above and 1×10 17 cm -3 The concentration gradient of the P-type layer 22 in FIGS. 1 to 4 is, for example, 8.0×10 17 cm -3 / μm.

[0073] The peak impurity concentration of the N-type layer 31 in FIGS. 3 and 4 is, for example, 1.5×10 16 cm -3 The tolerance is, for example, 1×10 15 cm -3 Above and 1×10 16 cm -3The concentration gradient of the N-type layer 31 in FIGS. 17 cm -3 The peak impurity concentration of the N-type layer 32 in FIGS. 3 and 4 is, for example, 5.0×10 16 cm -3 The tolerance is, for example, 1×10 15 cm -3 Above and 1×10 16 cm -3 The concentration gradient of the N-type layer 32 in FIGS. 17 cm -3 / μm.

[0074] The allowable range of the peak impurity concentration of the N+ type emitter layer 41 in FIGS. 1 to 4 is, for example, 1×10 18 cm -3 Above and 1×10 19 cm -3 The allowable range of the peak impurity concentration of the N+ type emitter layer 42 in FIGS. 1 to 4 is, for example, 1×10 18 cm -3 Above and 1×10 19 cm -3 The following is the result.

[0075] The allowable range of the peak impurity concentration of the P+ type emitter layer 5 in FIGS. 1 to 4 is, for example, 1×10 18 cm -3 Above and 1×10 20 cm -3 The following is the result.

[0076] <About the action> Figures 5 and 6 are diagrams showing examples of output characteristics in the configuration shown in Figure 52, the configuration shown in Figure 2, and the configuration shown in Figure 4. Figure 6 is an enlarged view of the region up to a voltage value of 5V in Figure 5. In Figures 5 and 6, the vertical axis represents the current value, and the horizontal axis represents the voltage value [V].

[0077] 5 and 6, the output characteristics of the configuration shown in FIG. 52 are shown by a thin solid line, the output characteristics of the configuration shown in FIG. 52 with the spacing S (see FIG. 53) adjusted are shown by a thin two-dot chain line, the output characteristics of the configuration shown in FIG. 52 with the voltage of the gate electrode G2 adjusted are shown by a thin one-dot chain line, the output characteristics of the configuration shown in FIG. 2 are shown by a thick one-dot chain line, the output characteristics of the configuration shown in FIG. 4 are shown by a thick solid line, and the rated current is shown by a thick two-dot chain line.

[0078] 5 and 6, in the configuration shown in Fig. 52, gate electrode G1 and gate electrode G2 are turned on simultaneously, and electrons are injected into substrate 1 from gate trench 81 and gate trench 82. This increases the saturation current.

[0079] 52 in which the interval S (see FIG. 53) is adjusted, the saturation current can be suppressed by adjusting the interval S between adjacent N+ type emitter layers 4. However, Vce(sat) becomes high.

[0080] 52, in which the voltage applied to the gate electrode G2 is adjusted, the saturation current can be suppressed by adjusting the voltage applied to the gate electrode G2. However, the gate electrodes G1 and G2 are driven with different voltage values, which complicates the operation of the gate driver.

[0081] On the other hand, in the case of the configuration shown in FIG. 2, it is possible to reduce the saturation current while suppressing the deterioration of Vce(sat) without changing the gate voltage.

[0082] Furthermore, in the case of the configuration shown in FIG. 4, it is also possible to reduce the saturation current while suppressing the deterioration of Vce(sat) without changing the gate voltage.

[0083] Fig. 7 is a diagram showing an example of a comparison of normalized saturation current values ​​in the configuration shown in Fig. 52, the configuration shown in Fig. 2, and the configuration shown in Fig. 4. In Fig. 7, the vertical axis represents the normalized current value.

[0084] According to Figure 7, it can be seen that the saturation current value is large in A, which corresponds to the configuration shown in Figure 52, while the saturation current value is reduced to about 50% compared to A in B, which corresponds to the configuration shown in Figure 2, and C, which corresponds to the configuration shown in Figure 4.

[0085] Fig. 8 is a diagram showing the relationship between the saturation current value and the maximum pulse width at which short-circuit interruption is possible. In Fig. 8, the vertical axis represents the maximum pulse width [μs], and the horizontal axis represents the saturation current value. Fig. 8 shows the relationship at 150°C, for example.

[0086] Referring to FIG. 8, it can be seen that when the saturation current value is reduced, the current value during short-circuit operation is also reduced, and therefore the maximum value of the pulse width capable of breaking a short circuit increases.

[0087] From the above relationship, it can be seen that by applying the configurations shown in the above embodiments (FIGS. 1 to 4), it is possible to guarantee short-circuit resistance without changing the gate voltage.

[0088] Next, the mechanism of the reduction in the saturation current value resulting from the configuration shown in the above embodiment (FIGS. 1 to 4) will be described.

[0089] When the output of the IGBT is saturated, the trench structure portion operates as a MOSFET, injecting an electron current into the substrate 1. This electron current then becomes the base current of the bipolar transistor, controlling the output current between the collector and emitter.

[0090] When the electron current injected into the substrate 1 decreases, the saturation current of the IGBT also decreases. When the structure is constant (identical), the electron current of the MOSFET is determined by the applied voltage and the threshold voltage of the MOSFET. The threshold voltage of the MOSFET is determined by the impurity concentration of the P-type layer in the part that operates as a MOSFET.

[0091] 1 to 4, by setting the peak impurity concentration (P2) of the P-type layer (i.e., P-type layer 22) in the portion of gate trench 82 that operates as a MOSFET higher than the peak impurity concentration (P1) of P-type layer 21, the threshold voltage of the portion that operates as a MOSFET increases. As a result, the electron current can be reduced without changing the gate voltage. This reduces the saturation current value of the IGBT.

[0092] Next, a mechanism for improving the Vce(sat)-Eoff tradeoff of an IGBT resulting from the configurations shown in the above embodiments (FIGS. 1 to 4) will be described.

[0093] The inclusion of the P-type layer 22 in the configuration shown in FIG. 2 reduces electron injection from the deep gate trench 82, resulting in a slight increase in the on-state Vce(sat) of the IGBT.

[0094] Fig. 9 is a diagram showing an example of the concentration dependency of the normalized P-type layer 22 on the saturation voltage Vce(sat) in the configuration shown in Fig. 4. In Fig. 9, the vertical axis represents the saturation voltage [V] and the rate of change, and the horizontal axis represents the normalized impurity concentration of the P-type layer 22. In Fig. 9, circles represent voltage values, and squares represent the rate of change.

[0095] 10 is a diagram showing an example of the concentration dependency of the normalized P-type layer 22 on the saturation current Ic(sat) in the configuration shown in FIG. 4. In FIG. 10, the vertical axis represents the saturation current [A] and the rate of change, and the horizontal axis represents the normalized impurity concentration of the P-type layer 22. In FIG. 10, circles represent current values, and squares represent the rate of change.

[0096] 11 is a diagram showing an example of the normalized concentration dependency of the N-type layer 32 on the saturation voltage Vce(sat) in the configuration shown in FIG. 4. In FIG. 11, the vertical axis represents the saturation voltage [V] and the rate of change, and the horizontal axis represents the normalized impurity concentration of the N-type layer 32. In FIG. 11, circles represent voltage values, and squares represent the rate of change.

[0097] 12 is a graph showing an example of the normalized concentration dependency of the N-type layer 32 on the saturation current Ic(sat) in the configuration shown in FIG. 4. In FIG. 12, the vertical axis represents the saturation current [A] and the rate of change, and the horizontal axis represents the normalized impurity concentration of the N-type layer 32. In FIG. 12, circles represent current values, and squares represent the rate of change.

[0098] As shown in Figures 9 and 10, when the impurity concentration of the P-type layer 22 increases, the saturation current Ic(sat) decreases significantly (change range = 10%), but the saturation voltage Vce(sat) increases slightly (change range = 3%).

[0099] Also, as shown in Figures 11 and 12, when the impurity concentration of the N-type layer 32 increases, the saturation voltage Vce(sat) decreases (variation range = 7%), but the saturation current Ic(sat) remains almost constant (variation range = 0.4%).

[0100] As described above, in the configuration shown in FIG. 4, for example, by setting appropriate impurity concentrations in the P-type layer 22 and the N-type layer 32, it is possible to reduce the saturation voltage Vce(sat) while suppressing the saturation current Ic(sat).

[0101] FIG. 13 is a diagram showing an example of a circuit diagram of a double-gate-controlled IGBT. As shown in FIG. 13, the gate voltage of an IGBT 100 is controlled by gate electrodes G1 and G2. Gate electrodes G1 and G2 are connected to a signal source 102 via resistors, and gate electrode G1 is further connected to the signal source 102 via a delay circuit 101. Here, the signal source 102, delay circuit 101, and circuit resistor correspond to a control unit. However, the circuit resistor may be built into the signal source 102 and delay circuit 101.

[0102] 14 is an example of a sequence of gate voltages input to the IGBT 100 shown in FIG. 13. As shown in FIG. 14, the gate voltage applied from the gate electrode G1 is V g1and the gate voltage applied from the gate electrode G1 is V g2 Since the gate electrode G1 is connected to the signal source 102 via the delay circuit 101, the gate voltage applied from the gate electrode G1 is delayed by dt. That is, the signal source 102 is connected to the gate electrodes G1 and G2 (when the circuit resistance is omitted), and the turn-off timing of the voltage signal of the gate electrode G1 can be controlled to be later than the turn-off timing of the voltage signal of the gate electrode G2.

[0103] Fig. 15 is a diagram showing an example of a turn-off waveform of the IGBT 100 shown in Fig. 13. In Fig. 15, the vertical axis represents current value [A] and voltage value [V], and the horizontal axis represents time [s]. Waveform 200 represents the waveform of the current value, and waveform 201 represents the waveform of the voltage value.

[0104] Here, the time difference between the turn-off of the gate electrode G1 and the gate electrode G2 is defined as delay time dt, and the loss from the turn-off of the gate electrode G2 to the current cut-off is defined as Eoff.

[0105] Fig. 16 is a diagram showing an example of the dependence of dt on Eoff when the impurity concentration of the N-type layer 32 is different in the configuration shown in Fig. 4. In Fig. 16, circles indicate cases where the impurity concentration of the N-type layer 32 is low, and squares indicate cases where the impurity concentration of the N-type layer 32 is high.

[0106] As shown in FIG. 16, when the impurity concentration of the N-type layer 32 is high, Eoff is large when dt is equal to or less than a certain value, but when dt exceeds a certain value, Eoff becomes small regardless of whether the impurity concentration of the N-type layer 32 is high or low.

[0107] 17 is a diagram showing an example of the saturation voltage Vce(sat)-Eoff trade-off characteristic, in which the vertical axis represents normalized Eoff and the horizontal axis represents normalized saturation voltage Vce(sat).

[0108] The circles in FIG. 17 correspond to the configuration shown in FIG. 52 with the spacing S (see FIG. 53) adjusted, the squares in FIG. 17 correspond to the configuration shown in FIG. 2, and the triangles in FIG. 17 correspond to the configuration shown in FIG. 4.

[0109] In any of the above configurations, dt is adjusted so that Eoff is minimized. Also, the spacing S in the configuration shown in Fig. 52 is adjusted so that the saturation current Ic is constant.

[0110] 2 and 4, it can be seen that the saturation voltage Vce(sat) is reduced in the configuration shown in FIG. 2 compared to the configuration shown in FIG. 52 in which the spacing S is adjusted. It can also be seen that the saturation voltage Vce(sat) and Eoff are further reduced in the configuration shown in FIG. 4 compared to the configuration shown in FIG. 52 in which the spacing S is adjusted and the configuration shown in FIG. 2.

[0111] Therefore, in the configuration shown in FIG. 4, by adjusting the impurity concentration of the P-type layer 22, the impurity concentration of the N-type layer 32, and the delay time dt, it is possible to improve the saturation voltage Vce(sat)-Eoff trade-off characteristics while suppressing the saturation current.

[0112] <Third embodiment> A semiconductor device and a method for manufacturing the semiconductor device according to the present embodiment will be described. In the following description, components similar to those described in the above embodiments will be denoted by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0113] <Configuration of semiconductor device> FIG. 18 is a diagram showing an example of the configuration of a semiconductor device according to this embodiment.

[0114] 18, specifically, the IGBT has a trench structure (specifically, shallow gate trenches 81) periodically formed on the upper surface of an N-type semiconductor substrate 1. A gate oxide film 6 is formed on the side and bottom surfaces of the gate trench 81, and further, a buried layer 7 made of, for example, polysilicon is provided and surrounded by the gate oxide film 6. The buried layer 7 in the gate trench 81 is connected to a gate electrode G1 (not shown here).

[0115] The IGBT also has a trench structure (specifically, deep gate trenches 82) adjacent to the gate trenches 81 and periodically formed on the upper surface of the substrate 1. A gate oxide film 6 is formed on the side and bottom surfaces of the gate trenches 82, and a buried layer 7 is further provided surrounded by the gate oxide film 6. The buried layer 7 in the gate trench 82 is connected to a gate electrode G2 (not shown here).

[0116] Meanwhile, an N-type layer 331 and an N-type layer 332 are selectively formed on the surface layer of the substrate 1 between the gate trenches 81 and 82. A P-type layer 321 is formed on the surface layer of the N-type layer 331. A P-type layer 322 is formed on the surface layer of the N-type layer 332.

[0117] Here, the N-type layer 331 (and the P-type layer 321) is formed to extend in a direction intersecting the direction in which the gate trenches 81 and 82 extend in a plan view of the substrate 1. In other words, the N-type layer 331 (and the P-type layer 321) is formed across the adjacent gate trenches 81 and 82 in a plan view.

[0118] Similarly, the N-type layer 332 (and the P-type layer 322) is formed to extend in a direction intersecting the direction in which the gate trenches 81 and 82 extend in a plan view of the substrate 1. That is, the N-type layer 332 (and the P-type layer 322) is formed across the adjacent gate trenches 81 and 82 in a plan view.

[0119] Furthermore, an N+ type emitter layer 41 and a P+ type emitter layer 5 are selectively formed on the surface layer of the P type layer 321. Also, an N+ type emitter layer 42 and a P+ type emitter layer 5 are selectively formed on the surface layer of the P type layer 322.

[0120] The N type layer ۳۳۱ contacts the substrate ۱, the gate oxide film ۶ of the gate trench ۸۱, and the gate oxide film ۶ of the gate trench ۸۲.

[0121] The N type layer ۳۳۲ contacts the substrate ۱, the gate oxide film ۶ of the gate trench ۸۱, and the gate oxide film ۶ of the gate trench ۸۲.

[0122] The P type layer ۳۲۱ contacts the P+ type emitter layer ۵, the N type layer ۳۳۱, the gate oxide film ۶ of the gate trench ۸۱, and the gate oxide film ۶ of the gate trench ۸۲.

[0123] The N+ type emitter layer ۴۱ contacts the P type layer ۳۲۱ and the gate oxide film ۶ of the gate trench ۸۱.

[0124] The P type layer ۳۲۲ contacts the P+ type emitter layer ۵, the N type layer ۳۳۲, the gate oxide film ۶ of the gate trench ۸۱, and the gate oxide film ۶ of the gate trench ۸۲.

[0125] The N+ type emitter layer ۴۲ contacts the P type layer ۳۲۲ and the gate oxide film ۶ of the gate trench ۸۲.

[0126] Here, the depth (d۱) of the bottom surface of the gate trench ۸۱ (from the upper surface of the P+ type emitter layer ۵), the depth (d۲a) of the lower surface of the N type layer ۳۳۱ (from the upper surface of the P+ type emitter layer ۵), the depth (d۲b) of the lower surface of the N type layer ۳۳۲ (from the upper surface of the P+ type emitter layer ۵), and the depth (d۳) of the bottom surface of the gate trench ۸۲ (from the upper surface of the P+ type emitter layer ۵) satisfy the relationships of "d۱ < d۲a < d۳" and "d۱ < d۲b < d۳".

[0127] Also, the peak impurity concentration (P۱) of the P type layer ۳۲۱ and the peak impurity concentration (P۲) of the P type layer ۳۲۲ satisfy the relationship of "P۱ < P۲".

[0128] Also, the peak impurity concentration (N1) of the N-type layer 331 and the peak impurity concentration (N2) of the N-type layer 332 satisfy the relationship of "N1 < N2".

[0129] And the semiconductor device shown in FIG. 18 is connected to the gate electrode G2 and the gate electrode G1, and includes a control unit 500 that controls the gate electrode G2 and the gate electrode G1 such that the turn-off timing of the voltage signal of the gate electrode G1 is later than the turn-off timing of the voltage signal of the gate electrode G2.

[0130] Note that in FIG. 18, an N-type layer 3 may be provided instead of the N-type layer 331 and the N-type layer 332.

[0131] FIG. 19 is a cross-sectional view of the cross-section D1 shown in FIG. 18. As shown in the example of FIG. 19, the P-type layer 321 is formed across adjacent gate trenches 81 and 82 in a plan view. Similarly, the P-type layer 322 is formed across adjacent gate trenches 81 and 82 in a plan view.

[0132] FIG. 20 is a cross-sectional view of the cross-section D2 shown in FIG. 18. As shown in the example of FIG. 20, the N-type layer 331 is formed across adjacent gate trenches 81 and 82 in a plan view. Similarly, the N-type layer 332 is formed across adjacent gate trenches 81 and 82 in a plan view.

[0133] <Regarding the manufacturing method of the semiconductor device> Next, a manufacturing method of the structure shown in FIG. 18 will be described. FIGS. 21 to 26 are diagrams showing an example of the manufacturing method of the structure shown in FIG. 18. In FIGS. 21 to 26, an example of a process of forming a P-type layer and an N-type layer by four implantations is shown. In FIGS. 21 to 26, a cross-sectional view of the cross-section D3 in FIG. 18 is shown on the left side, and a cross-sectional view of the cross-section D4 in FIG. 18 is shown on the right side.

[0134] First, as shown in FIG. 21, a silicon oxide film 400 is formed on the upper surface of the substrate 1.

[0135] Next, as shown in FIG. 22, P+ ions are implanted into the upper surface of the substrate 1 while the areas where the P-type layer 321 and the N-type layer 331 are to be formed are masked (i.e., the structure of cross section D3 in the left figure is masked).

[0136] Next, as shown in Figure 23, with the areas where the P-type layer 321 and the N-type layer 331 will be formed masked (i.e., with the structure of cross section D3 in the left figure masked), B+ ions are implanted into the upper surface of the substrate 1.

[0137] 24, in a state where the areas where the P-type layer 322 and the N-type layer 332 are to be formed are masked (i.e., in a state where the structure of cross section D4 in the right diagram is masked), P+ ions are implanted into the upper surface of the substrate 1. Note that the concentration of the P+ ion implantation in this step is lower than the concentration of the P+ ion implantation shown in FIG.

[0138] 25, in a state where the areas where the P-type layer 322 and the N-type layer 332 are to be formed are masked (i.e., in a state where the structure of cross section D4 in the right diagram is masked), B ions are implanted into the upper surface of the substrate 1. Note that the concentration of the B ions implanted in this step is lower than the concentration of the B ions implanted shown in FIG.

[0139] In this way, a structure can be manufactured in which the P-type layer 321 is formed on the surface of the N-type layer 331, and the P-type layer 322 is formed on the surface of the N-type layer 332, as shown in FIG.

[0140] 21 to 26, cross section D3 is masked first, but cross section D4 may be masked first. Also, in FIGS. 21 to 26, P ions are implanted first, but B ions may be implanted first.

[0141] 27 to 30 are diagrams showing another example of a method for manufacturing the structure shown in Fig. 18. Fig. 27 to 30 show an example of a process for forming a P-type layer and an N-type layer by two implantations. In Fig. 27 to 30, a cross-sectional view of cross-section D3 in Fig. 18 is shown on the left, and a cross-sectional view of cross-section D4 in Fig. 18 is shown on the right.

[0142] First, as shown in FIG. 27, a silicon oxide film 400 is formed on the upper surface of the substrate 1.

[0143] 28, in a state where the areas where the P-type layer 321 and the N-type layer 331 are to be formed are partially masked with an implantation mask 405 (i.e., in a state where only the structure of cross-section D3 in the left figure is covered with a photoresist mask having a stripe pattern or a dot pattern), P+ ions are implanted into the upper surface of the substrate 1. As a result of this implantation, P+ ions are implanted at a lower concentration into the structure of cross-section D3 that is covered with the implantation mask 405 than into the structure of cross-section D4 that is not covered with the implantation mask 405. In this way, an N-type layer 331 is simultaneously formed in the surface layer of the substrate 1 having the structure of cross-section D3, and an N-type layer 332 is simultaneously formed in the surface layer of the substrate 1 having the structure of cross-section D4.

[0144] 29, in a state where the areas where the P-type layer 321 and the N-type layer 331 will be formed are partially masked with an implantation mask 405 (i.e., in a state where only the structure of cross-section D3 in the left figure is covered with a photoresist mask having a stripe pattern or a dot pattern), B ions are implanted into the upper surface of the substrate 1. As a result of this implantation, B ions are implanted at a lower concentration into the structure of cross-section D3 covered with the implantation mask 405 than into the structure of cross-section D4 which is not covered with the implantation mask 405. In this way, the P-type layer 321 is simultaneously formed on the surface of the N-type layer 331 in the structure of cross-section D3, and the P-type layer 322 is simultaneously formed on the surface of the N-type layer 332 in the structure of cross-section D4.

[0145] As a result, a structure in which P-type layer 321 is formed on the surface of N-type layer 331 and P-type layer 322 is formed on the surface of N-type layer 332 as shown in FIG. 30 can be manufactured with fewer processes.

[0146] Although P+ ions are implanted first in FIGS. 27 to 30, B+ ions may be implanted first.

[0147] 31 to 42 are diagrams showing an example of a method for manufacturing the structure shown in Fig. 18. Fig. 31 to 42 show an example of a process for forming a trench structure by two etching steps. In Fig. 31 to 42, a cross-sectional view of cross-section D3 in Fig. 18 is shown on the left, and a cross-sectional view of cross-section D4 in Fig. 18 is shown on the right.

[0148] 31, a silicon oxide film 400 is formed on the upper surface of a substrate 1. Then, a resist 401 having an opening is formed on the upper surface of the silicon oxide film 400, and then As + ions are implanted.

[0149] Next, as shown in FIG. 32, the implanted ions are diffused (drive-in) by a high temperature treatment.

[0150] Next, as shown in FIG. 33, a resist 402 having openings at cross sections D3 and D4 is formed on the upper surface of the silicon oxide film 400, and the silicon oxide film 400 is etched.

[0151] 34, a gate trench 81 is formed using a resist 402. Also, an N+ type emitter layer 41 is formed.

[0152] Next, as shown in FIG. 35, a gate oxide film 6 is formed inside (on the side and bottom surfaces of) the gate trench 81.

[0153] Next, as shown in FIG. 36, polysilicon is deposited on the upper surface of the substrate 1 including the inside (side surface and bottom surface) of the gate trench 81.

[0154] Next, as shown in FIG. 37, etching back is performed so as to leave the polysilicon buried inside the gate trench 81, thereby forming the buried layer 7, and the upper surface of the buried layer 7 is oxidized.

[0155] 38, a resist 403 having openings at cross sections D3 and D4 is formed on the upper surface of the silicon oxide film 400, and the silicon oxide film 400 is etched. Note that the positions of the openings in the resist 403 are different from the positions of the openings in the resist 402.

[0156] 39, a gate trench 82 is formed using a resist 403. An N+ type emitter layer 42 is also formed.

[0157] Next, as shown in FIG. 40, a gate oxide film 6 is formed inside (on the side and bottom surfaces of) the gate trench 82.

[0158] Next, as shown in FIG. 41, polysilicon is deposited on the upper surface of the substrate 1 including the inside (side surface and bottom surface) of the gate trench 82.

[0159] Next, as shown in FIG. 42, etching back is performed so as to leave the polysilicon buried inside the gate trench 82, thereby forming the buried layer 7, and the upper surface of the buried layer 7 is oxidized.

[0160] 31 to 42, the gate trench 81 is formed first, but the gate trench 82 may be formed first. Also, the N+ type emitter layer 41 and the N+ type emitter layer 42 may be formed after the corresponding trenches are formed.

[0161] 43 to 49 are diagrams showing another example of a method for manufacturing the structure shown in Fig. 18. Fig. 43 to 49 show an example of a process for forming a trench structure by a single etching. In Fig. 43 to 49, a cross-sectional view of cross-section D3 in Fig. 18 is shown on the left, and a cross-sectional view of cross-section D4 in Fig. 18 is shown on the right.

[0162] 43, a silicon oxide film 400 is formed on the upper surface of a substrate 1. Then, a resist 401 having an opening is formed on the upper surface of the silicon oxide film 400, and then As + ions are implanted.

[0163] Next, as shown in FIG. 44, the implanted ions are diffused (drive-in) by a high temperature treatment.

[0164] Next, as shown in FIG. 45, a resist 404 having a plurality of openings with different opening widths at each of cross sections D3 and D4 is formed on the upper surface of the silicon oxide film 400, and the silicon oxide film 400 is etched at the openings with each opening width.

[0165] 46, a gate trench 581 and a gate trench 582 are simultaneously formed using a resist 404. Also, an N+ type emitter layer 41 and an N+ type emitter layer 42 are formed.

[0166] Here, the width of the opening in the resist 404 for forming the gate trench 581 is narrower than the width of the opening for forming the gate trench 582. As a result, the width of the gate trench 581 is narrower than the width of the gate trench 582. Furthermore, due to the correlation between the opening width and the etching rate, the depth of the bottom surface of the gate trench 581 is shallower than the depth of the bottom surface of the gate trench 582.

[0167] Next, as shown in FIG. 47, a gate oxide film 6 is formed inside the gate trench 81 (side surface and bottom surface) and inside the gate trench 82 (side surface and bottom surface).

[0168] Next, as shown in FIG. 48, polysilicon is deposited on the upper surface of the substrate 1 including the insides (side surfaces and bottom surfaces) of the gate trenches 81 and the insides (side surfaces and bottom surfaces) of the gate trenches 82.

[0169] Next, as shown in FIG. 49, etching is performed so as to leave the polysilicon buried inside the gate trenches 81 and 82, thereby forming buried layers 7 inside the gate trenches 81 and 82, and oxidizing the upper surfaces of the buried layers 7.

[0170] Fig. 50 is a diagram showing the correlation between the trench opening width and the trench bottom depth, in which the vertical axis represents the trench depth [µm] and the horizontal axis represents the trench opening width [nm].

[0171] As shown in FIG. 50, it can be seen that the greater the opening width of the trench, the deeper the trench becomes.

[0172] 51 is a diagram showing the relationship between the breakdown voltage and trench spacing in the structures shown in FIGS. 1 to 4. In FIG. 51, the vertical axis represents the breakdown voltage [V] at 25° C., and the horizontal axis represents the spacing between trenches [μm]. Here, the spacing between trenches corresponds to the spacing between adjacent gate trenches 82, the spacing between adjacent dummy trenches 9, or the spacing between adjacent gate trenches 82 and dummy trenches 9.

[0173] 51, it can be seen that the withstand voltage decreases as the distance between the gate trenches 82 increases. For example, when the implantation dose of the N-type layer 31 and the N-type layer 32 is 0 and the trench distance is 15 μm, the withstand voltage is approximately 90% of the target withstand voltage.

[0174] If the interval between the gate trenches 82 is too wide, the field plate effect between the gate trenches 82 weakens, and the electric field concentrates near the bottom of the gate trench 82. This reduces the withstand voltage.

[0175] The dependency of the withstand voltage on the trench spacing becomes more sensitive as the implantation amount (dose) of the N-type layer 31 and the N-type layer 32 increases. In other words, when a semiconductor device has the N-type layer 31 and the N-type layer 32, the trench spacing needs to be narrower than 15 μm to maintain 90% or more of the target withstand voltage.

[0176] <Effects Produced by the Multiple Embodiments Described Above> Next, examples of effects obtained by the above-described embodiments will be described. Note that in the following description, the effects will be described based on the specific configurations exemplified in the above-described embodiments, but these may be replaced with other specific configurations exemplified in the present specification as long as the same effects are obtained. In other words, for convenience, only one of the associated specific configurations may be described as a representative below, but the representatively described specific configuration may be replaced with another associated specific configuration.

[0177] Furthermore, the replacement may be made across multiple embodiments, i.e., configurations illustrated in different embodiments may be combined to produce the same effect.

[0178] According to the above-described embodiment, the semiconductor device includes a semiconductor substrate of a first conductivity type (N-type), an N-type first semiconductor layer, a first impurity layer of a second conductivity type (P-type), a P-type second impurity layer, a first trench, at least one second trench, a first electrode layer, a second electrode layer, a first gate electrode, a second gate electrode, a P-type third impurity layer, an N-type second semiconductor layer, and an N-type third semiconductor layer. Here, the semiconductor substrate corresponds to, for example, substrate 1. The first semiconductor layer corresponds to, for example, at least one of N-type layer 3, N-type layer 31, N-type layer 32, N-type layer 331, N-type layer 332, etc. The first impurity layer corresponds to, for example, P-type layer 21, P-type layer 321, etc. The second impurity layer corresponds to, for example, P-type layer 22, P-type layer 322, etc. The first trench corresponds to, for example, a gate trench 81, a gate trench 581, etc. The second trench corresponds to, for example, a gate trench 82, a gate trench 582, etc. The first electrode layer corresponds to, for example, a buried layer 7, etc. The second electrode layer corresponds to, for example, a buried layer 7, etc. The first gate electrode corresponds to, for example, a gate electrode G1, etc. The second gate electrode corresponds to, for example, a gate electrode G2, etc. The third impurity layer corresponds to, for example, a P+ type emitter layer 5, etc. The second semiconductor layer corresponds to, for example, an N+ type emitter layer 41, etc. The third semiconductor layer corresponds to, for example, an N+ type emitter layer 42, etc. The N-type layer 3 is provided in a surface layer of the substrate 1. The P-type layer 21 and the P-type layer 22 are selectively provided in a surface layer of the N-type layer 3. The gate trench 81 is provided from the upper surface of the P-type layer 21 to reach into the N-type layer 3. The gate trench 82 is provided from the upper surface of the P-type layer 22 to reach below the lower surface of the N-type layer 3. The buried layer 7 is surrounded by a gate oxide film 6 and buried in the gate trench 81 and the gate trench 82. The gate electrode G1 is connected to the buried layer 7 in the gate trench 81. The gate electrode G2 is connected to the buried layer 7 in the gate trench 82.The P+ type emitter layer 5 is provided across the surface layer of the P type layer 21 and the surface layer of the P type layer 22. The N+ type emitter layer 41 is provided in the surface layer of the P type layer 21. The N+ type emitter layer 41 is disposed between the gate trench 81 and the P+ type emitter layer 5 in a planar view. The N+ type emitter layer 42 is provided in the surface layer of the P type layer 22. The N+ type emitter layer 42 is disposed between the gate trench 82 and the P+ type emitter layer 5 in a planar view. Here, the impurity concentration of the N type layer 3 is higher than the impurity concentration of the substrate 1. The impurity concentration (P2) of the P type layer 22 is higher than the impurity concentration (P1) of the P type layer 21. The impurity concentration of the P+ type emitter layer 5 is higher than the impurity concentration (P2) of the P type layer 22.

[0179] This configuration suppresses an increase in saturation current while preventing a deterioration in the Vce(sat)-Eoff trade-off characteristics and complicating the gate driver operation.

[0180] Furthermore, even if other configurations shown as examples in this specification are appropriately added to the above configuration, that is, even if other configurations in this specification that were not mentioned as the above configuration are appropriately added, the same effect can be achieved.

[0181] Furthermore, according to the embodiment described above, the first semiconductor layer includes a fourth semiconductor layer provided at a position overlapping with the P-type layer 21 in a planar view, and a fifth semiconductor layer provided at a position overlapping with the P-type layer 22 in a planar view. Here, the fourth semiconductor layer corresponds to, for example, the N-type layer 31. Furthermore, the fifth semiconductor layer corresponds to, for example, the N-type layer 32. The impurity concentration (N2) of the N-type layer 32 is higher than the impurity concentration (N1) of the N-type layer 31. With this configuration, it is possible to suppress an increase in saturation current while preventing a deterioration in the Vce(sat)-Eoff trade-off characteristic and complicated gate driver operation.

[0182] Furthermore, according to the embodiment described above, the semiconductor device includes a control unit 500 connected to the gate electrodes G1 and G2, and controlling the turn-off timing of the voltage signal of the gate electrode G1 to be later than the turn-off timing of the voltage signal of the gate electrode G2. With this configuration, it is possible to suppress the loss from the turn-off of the gate electrode G2 until the current is turned off, thereby suppressing the saturation current and improving the saturation voltage Vce(sat)-Eoff trade-off characteristics.

[0183] Furthermore, according to the embodiment described above, P-type layer 21 is provided along the direction in which gate trench 81 extends in a plan view. Furthermore, P-type layer 22 is provided along the direction in which gate trench 82 extends in a plan view. This configuration increases the degree of freedom in the shape of the P-type layer provided between the trenches.

[0184] Furthermore, according to the embodiment described above, P-type layer 321 and P-type layer 322 are each provided across gate trench 81 and gate trench 82 in plan view. Such a configuration can increase the degree of freedom in the shape of the P-type layer provided between the trenches.

[0185] Furthermore, according to the above-described embodiment, the semiconductor device includes at least one third trench, a third electrode layer, and an emitter electrode E. Here, the third trench corresponds to, for example, a dummy trench 9. The third electrode layer corresponds to, for example, a buried layer 7. The dummy trench 9 is provided from the upper surface of the substrate 1 to a position below the lower surface of the N-type layer 3. The buried layer 7 is buried in the dummy trench 9 and surrounded by a gate oxide film 6. The emitter electrode E is connected to the buried layer 7 in the dummy trench 9. The dummy trench 9 is adjacent to the gate trench 82 on the side opposite to the gate trench 81. This configuration enhances the field plate effect, thereby improving the withstand voltage of the semiconductor device.

[0186] Furthermore, according to the embodiment described above, the width W2 of the gate trench 82 is wider than the width W1 of the gate trench 81. Furthermore, the width W3 of the dummy trench 9 is wider than the width W1 of the gate trench 81. With this configuration, the gate trenches 581 and 582 can be formed simultaneously using the resist 404, thereby reducing manufacturing costs.

[0187] Moreover, according to the embodiment described above, the depth of the bottom surface of the dummy trench 9 is equal to the depth of the bottom surface of the gate trench 82. With such a configuration, the dummy trench 9 and the gate trench 82 can be formed simultaneously, thereby reducing manufacturing costs.

[0188] Moreover, according to the embodiment described above, the semiconductor device includes a plurality of gate trenches 82. The semiconductor device also includes a plurality of dummy trenches 9. The spacing between adjacent gate trenches 82, the spacing between adjacent dummy trenches 9, or the spacing between adjacent gate trenches 82 and dummy trenches 9 is narrower than 15 μm. With this configuration, 90% or more of the withstand voltage can be maintained.

[0189] According to the embodiment described above, in the method for manufacturing a semiconductor device, an N-type N-type layer 3 is provided on the surface of an N-type substrate 1. Then, a P-type P-type layer 21 and a P-type P-type layer 22 are selectively provided on the surface of the N-type layer 3. Then, an N-type N+-type emitter layer 41 is provided on a portion of the surface of the P-type layer 21. Then, an N-type N+-type emitter layer 42 is provided on a portion of the surface of the P-type layer 22. Then, a gate trench 81 is provided extending from the upper surface of the P-type layer 21 to the inside of the N-type layer 3. Then, at least one gate trench 82 is provided extending from the upper surface of the P-type layer 22 to below the lower surface of the N-type layer 3. Then, a P+-type emitter layer 5 is provided across the surface of the P-type layer 21 and the surface of the P-type layer 22. Here, the N+-type emitter layer 41 is sandwiched between the gate trench 81 and the P+-type emitter layer 5 in a planar view. Furthermore, the N+ type emitter layer 42 is sandwiched between the gate trench 82 and the P+ type emitter layer 5 in a plan view. Then, a buried layer 7 is provided in the gate trench 81 and surrounded by a gate oxide film 6. Then, a buried layer 7 is provided in the gate trench 82 and surrounded by the gate oxide film 6. Then, a gate electrode G1 is provided connected to the buried layer 7. Then, a gate electrode G2 is provided connected to the buried layer 7. Here, the impurity concentration of the N type layer 3 is higher than the impurity concentration of the substrate 1. Also, the impurity concentration (P2) of the P type layer 22 is higher than the impurity concentration (P1) of the P type layer 21. Also, the impurity concentration of the P+ type emitter layer 5 is higher than the impurity concentration (P2) of the P type layer 22.

[0190] This configuration suppresses an increase in saturation current while preventing a deterioration in the Vce(sat)-Eoff trade-off characteristics and complicating the gate driver operation.

[0191] Unless otherwise specified, the order in which the processes are performed can be changed.

[0192] Furthermore, even if other configurations shown as examples in this specification are appropriately added to the above configuration, that is, even if other configurations in this specification that were not mentioned as the above configuration are appropriately added, the same effect can be achieved.

[0193] Furthermore, according to the embodiment described above, with a portion of the surface of the N-type layer 3 covered with the implantation mask 405 having a stripe pattern or a dot pattern, the P-type layer 321 is simultaneously formed by ion implantation in the region covered with the implantation mask 405, and the P-type layer 322 is simultaneously formed in the region not covered with the implantation mask 405. With this configuration, a structure in which the P-type layer 321 is formed on the surface of the N-type layer 331 and the P-type layer 322 is formed on the surface of the N-type layer 332 can be manufactured with a small number of processes.

[0194] Furthermore, according to the embodiment described above, with the upper surface of substrate 1 covered with an etching mask having a first opening and a second opening wider than the first opening, gate trench 581 is simultaneously formed in the region corresponding to the first opening and gate trench 582 is simultaneously formed in the region corresponding to the second opening by etching. This configuration can shorten the etching process.

[0195] Furthermore, according to the embodiment described above, the method for manufacturing a semiconductor device includes a control unit 500 connected to gate electrode G1 and gate electrode G2. The control unit 500 controls the turn-off timing of the voltage signal of gate electrode G1 to be later than the turn-off timing of the voltage signal of gate electrode G2. This configuration suppresses the loss from the turn-off of gate electrode G2 until the current is turned off, thereby suppressing the saturation current and improving the saturation voltage Vce(sat)-Eoff trade-off characteristics.

[0196] <Modifications of the above-described embodiments> In the multiple embodiments described above, the material, composition, dimensions, shape, relative positional relationship, or implementation conditions of each component may also be described, but these are merely examples in all aspects and are not limiting.

[0197] Therefore, countless modifications and equivalents not shown as examples are contemplated within the scope of the technology disclosed in the present specification, including, for example, modifying, adding, or omitting at least one component, and further, extracting at least one component in at least one embodiment and combining it with a component in another embodiment.

[0198] Furthermore, in at least one of the embodiments described above, when a material name or the like is stated without being specifically specified, unless a contradiction arises, it is assumed that the material in question includes other additives, such as alloys.

[0199] Furthermore, unless a contradiction arises, when it is stated in the above-described embodiments that "one" component is provided, "one or more" of that component may also be provided.

[0200] Furthermore, each component in the embodiments described above is a conceptual unit, and the scope of the technology disclosed in this specification includes cases where one component is made up of multiple structures, cases where one component corresponds to part of a structure, and even cases where multiple components are provided in one structure.

[0201] Furthermore, each of the components in the embodiments described above includes structures having other structures or shapes as long as they perform the same function.

[0202] Furthermore, the descriptions in this specification are incorporated by reference for all purposes related to the present technology, and none of them are admitted to be prior art.

[0203] Various aspects of the present disclosure are summarized below as appendices.

[0204] (Appendix 1) a semiconductor substrate of a first conductivity type; a first semiconductor layer of a first conductivity type provided on a surface layer of the semiconductor substrate; a first impurity layer of a second conductivity type and a second impurity layer of a second conductivity type selectively provided on a surface layer of the first semiconductor layer; a first trench provided from an upper surface of the first impurity layer to reach the inside of the first semiconductor layer; at least one second trench provided from an upper surface of the second impurity layer to a position below a lower surface of the first semiconductor layer; a first electrode layer embedded in the first trench and surrounded by an oxide film; a second electrode layer embedded in the second trench and surrounded by an oxide film; a first gate electrode connected to the first electrode layer; a second gate electrode connected to the second electrode layer; a third impurity layer of a second conductivity type provided across a surface layer of the first impurity layer and a surface layer of the second impurity layer; a second semiconductor layer of a first conductivity type provided on a surface layer of the first impurity layer and sandwiched between the first trench and the third impurity layer in a plan view; a third semiconductor layer of a first conductivity type that is provided on a surface layer of the second impurity layer and is disposed between the second trench and the third impurity layer in a plan view; the impurity concentration of the first semiconductor layer is higher than the impurity concentration of the semiconductor substrate; the impurity concentration of the second impurity layer is higher than the impurity concentration of the first impurity layer; the impurity concentration of the third impurity layer is higher than the impurity concentration of the second impurity layer; Semiconductor device.

[0205] (Appendix 2) a semiconductor substrate of a first conductivity type; a first semiconductor layer of a first conductivity type and a second semiconductor layer of a first conductivity type selectively provided on a surface layer of the semiconductor substrate; a first impurity layer of a second conductivity type provided on a surface layer of the first semiconductor layer; a second impurity layer of a second conductivity type provided on a surface layer of the second semiconductor layer; a first trench provided from an upper surface of the first impurity layer to reach the inside of the first semiconductor layer; at least one second trench provided from an upper surface of the second impurity layer to a position below a lower surface of the second semiconductor layer; a first electrode layer embedded in the first trench and surrounded by an oxide film; a second electrode layer embedded in the second trench and surrounded by an oxide film; a first gate electrode connected to the first electrode layer; a second gate electrode connected to the second electrode layer; a third impurity layer of a second conductivity type provided across a surface layer of the first impurity layer and a surface layer of the second impurity layer; a third semiconductor layer of a first conductivity type provided on a surface layer of the first impurity layer and sandwiched between the first trench and the third impurity layer in a plan view; a fourth semiconductor layer of a first conductivity type that is provided on a surface layer of the second impurity layer and is disposed between the second trench and the third impurity layer in a plan view; the impurity concentration of the first semiconductor layer is higher than the impurity concentration of the semiconductor substrate; the impurity concentration of the second semiconductor layer is higher than the impurity concentration of the first semiconductor layer; the impurity concentration of the second impurity layer is higher than the impurity concentration of the first impurity layer; the impurity concentration of the third impurity layer is higher than the impurity concentration of the second impurity layer; Semiconductor device.

[0206] (Appendix 3) 3. The semiconductor device according to claim 1, further comprising a control unit connected to the first gate electrode and the second gate electrode, and controlling the turn-off timing of the voltage signal of the first gate electrode to be later than the turn-off timing of the voltage signal of the second gate electrode; Semiconductor device.

[0207] (Appendix 4) The semiconductor device according to any one of Supplementary Notes 1 to 3, the first impurity layer is provided along a direction in which the first trench extends in a plan view, the second impurity layer is provided along a direction in which the second trench extends in a plan view; Semiconductor device.

[0208] (Appendix 5) The semiconductor device according to any one of Supplementary Notes 1 to 3, the first impurity layer and the second impurity layer are each provided across the first trench and the second trench in a plan view; Semiconductor device.

[0209] (Appendix 6) A semiconductor device according to any one of appendices 1, 3 to 5, at least one third trench provided from the upper surface of the semiconductor substrate to a depth below the lower surface of the first semiconductor layer; a third electrode layer embedded in the third trench and surrounded by an oxide film; an emitter electrode connected to the third electrode layer, the third trench is adjacent to the second trench on the opposite side to the first trench; Semiconductor device.

[0210] (Appendix 7) 6. The semiconductor device according to any one of Supplementary Notes 2 to 5, at least one third trench provided from the upper surface of the semiconductor substrate to a depth below the lower surface of the second semiconductor layer; a third electrode layer embedded in the third trench and surrounded by an oxide film; an emitter electrode connected to the third electrode layer, the third trench is adjacent to the second trench on the opposite side to the first trench; Semiconductor device.

[0211] (Appendix 8) 8. The semiconductor device according to claim 6 or 7, The width of the second trench is wider than the width of the first trench, The width of the third trench is wider than the width of the first trench. Semiconductor device.

[0212] (Appendix 9) 9. The semiconductor device according to any one of Supplementary Notes 6 to 8, The depth of the bottom surface of the third trench is equal to the depth of the bottom surface of the second trench. Semiconductor device.

[0213] (Appendix 10) The semiconductor device according to any one of Supplementary Notes 6 to 9, a plurality of the second trenches; a plurality of the third trenches; a distance between adjacent second trenches, a distance between adjacent third trenches, or a distance between adjacent second trenches and third trenches is narrower than 15 μm; Semiconductor device.

[0214] (Appendix 11) a first conductive type first semiconductor layer is provided on a surface layer of a first conductive type semiconductor substrate; a first impurity layer of a second conductivity type and a second impurity layer of a second conductivity type are selectively provided on a surface layer of the first semiconductor layer; a second semiconductor layer of a first conductivity type is provided on a part of a surface layer of the first impurity layer; a third semiconductor layer of a first conductivity type is provided on a part of a surface layer of the second impurity layer; providing a first trench extending from an upper surface of the first impurity layer to the inside of the first semiconductor layer; providing at least one second trench extending from an upper surface of the second impurity layer to a position below a lower surface of the first semiconductor layer; a third impurity layer of a second conductivity type is provided across a surface layer of the first impurity layer and a surface layer of the second impurity layer; the second semiconductor layer is sandwiched between the first trench and the third impurity layer in a plan view, the third semiconductor layer is sandwiched between the second trench and the third impurity layer in a plan view, providing a first electrode layer surrounded by an oxide film and embedded in the first trench; providing a second electrode layer surrounded by an oxide film and embedded in the second trench; providing a first gate electrode connected to the first electrode layer; providing a second gate electrode connected to the second electrode layer; the impurity concentration of the first semiconductor layer is higher than the impurity concentration of the semiconductor substrate; the impurity concentration of the second impurity layer is higher than the impurity concentration of the first impurity layer; the impurity concentration of the third impurity layer is higher than the impurity concentration of the second impurity layer; A method for manufacturing a semiconductor device.

[0215] (Appendix 12) 12. A method for manufacturing a semiconductor device according to claim 11, a first impurity layer formed in a region covered with the implantation mask and a second impurity layer formed in a region not covered with the implantation mask by ion implantation, while a portion of a surface layer of the first semiconductor layer is covered with an implantation mask having a stripe pattern or a dot pattern; A method for manufacturing a semiconductor device.

[0216] (Appendix 13) a first semiconductor layer of the first conductivity type and a second semiconductor layer of the first conductivity type are selectively provided on a surface layer of a semiconductor substrate of the first conductivity type; a first impurity layer of a second conductivity type is provided on a surface layer of the first semiconductor layer; a second impurity layer of a second conductivity type is provided on a surface layer of the second semiconductor layer; a third semiconductor layer of a first conductivity type is provided on a part of a surface layer of the first impurity layer; a fourth semiconductor layer of a first conductivity type is provided on a part of a surface layer of the second impurity layer; providing a first trench extending from an upper surface of the first impurity layer to the inside of the first semiconductor layer; providing at least one second trench extending from an upper surface of the second impurity layer to a position below a lower surface of the second semiconductor layer; a third impurity layer of a second conductivity type is provided across a surface layer of the first impurity layer and a surface layer of the second impurity layer; the third semiconductor layer is sandwiched between the first trench and the third impurity layer in a plan view, the fourth semiconductor layer is sandwiched between the second trench and the third impurity layer in a plan view, providing a first electrode layer surrounded by an oxide film and embedded in the first trench; providing a second electrode layer surrounded by an oxide film and embedded in the second trench; providing a first gate electrode connected to the first electrode layer; providing a second gate electrode connected to the second electrode layer; the impurity concentration of the first semiconductor layer is higher than the impurity concentration of the semiconductor substrate; the impurity concentration of the second semiconductor layer is higher than the impurity concentration of the first semiconductor layer; the impurity concentration of the second impurity layer is higher than the impurity concentration of the first impurity layer; the impurity concentration of the third impurity layer is higher than the impurity concentration of the second impurity layer; A method for manufacturing a semiconductor device.

[0217] (Appendix 14) 14. A method for manufacturing a semiconductor device according to claim 13, With a surface layer of the first semiconductor layer covered with an implantation mask having a stripe pattern or a dot pattern, the first impurity layer is simultaneously provided in a region covered with the implantation mask and the second impurity layer is simultaneously provided in a region not covered with the implantation mask by ion implantation. A method for manufacturing a semiconductor device.

[0218] (Appendix 15) A method for manufacturing a semiconductor device according to any one of appendices 11 to 14, a first trench formed in a region corresponding to the first opening and a second trench formed in a region corresponding to the second opening by etching, while covering an upper surface of the semiconductor substrate with an etching mask having a first opening and a second opening whose opening width is wider than that of the first opening; A method for manufacturing a semiconductor device.

[0219] (Appendix 16) 16. A method for manufacturing a semiconductor device according to any one of appendices 11 to 15, a control unit connected to the first gate electrode and the second gate electrode is further provided; the control unit controls the turn-off timing of the voltage signal of the first gate electrode to be later than the turn-off timing of the voltage signal of the second gate electrode. A method for manufacturing a semiconductor device. [Explanation of symbols]

[0220] 1 substrate, 500 control section, E emitter electrode, G1 gate electrode, G2 gate electrode.

Claims

1. a semiconductor substrate of a first conductivity type; a first semiconductor layer of a first conductivity type provided on a surface layer of the semiconductor substrate; a first impurity layer of a second conductivity type and a second impurity layer of a second conductivity type selectively provided on a surface layer of the first semiconductor layer; a first trench provided from an upper surface of the first impurity layer to reach the inside of the first semiconductor layer; at least one second trench provided from an upper surface of the second impurity layer to a position below a lower surface of the first semiconductor layer; a first electrode layer embedded in the first trench and surrounded by an oxide film; a second electrode layer embedded in the second trench and surrounded by an oxide film; a first gate electrode connected to the first electrode layer; a second gate electrode connected to the second electrode layer; a third impurity layer of a second conductivity type provided across a surface layer of the first impurity layer and a surface layer of the second impurity layer; a second semiconductor layer of a first conductivity type provided on a surface layer of the first impurity layer and sandwiched between the first trench and the third impurity layer in a plan view; a third semiconductor layer of a first conductivity type that is provided on a surface layer of the second impurity layer and is disposed between the second trench and the third impurity layer in a plan view; an impurity concentration of the first semiconductor layer is higher than an impurity concentration of the semiconductor substrate; an impurity concentration of the second impurity layer is higher than an impurity concentration of the first impurity layer; the impurity concentration of the third impurity layer is higher than the impurity concentration of the second impurity layer; Semiconductor device.

2. a semiconductor substrate of a first conductivity type; a first semiconductor layer of a first conductivity type and a second semiconductor layer of a first conductivity type selectively provided on a surface layer of the semiconductor substrate; a first impurity layer of a second conductivity type provided on a surface layer of the first semiconductor layer; a second impurity layer of a second conductivity type provided on a surface layer of the second semiconductor layer; a first trench provided from an upper surface of the first impurity layer to reach the inside of the first semiconductor layer; at least one second trench provided from an upper surface of the second impurity layer to a position below a lower surface of the second semiconductor layer; a first electrode layer embedded in the first trench and surrounded by an oxide film; a second electrode layer embedded in the second trench and surrounded by an oxide film; a first gate electrode connected to the first electrode layer; a second gate electrode connected to the second electrode layer; a third impurity layer of a second conductivity type provided across a surface layer of the first impurity layer and a surface layer of the second impurity layer; a third semiconductor layer of a first conductivity type provided on a surface layer of the first impurity layer and sandwiched between the first trench and the third impurity layer in a plan view; a fourth semiconductor layer of a first conductivity type that is provided on a surface layer of the second impurity layer and is disposed between the second trench and the third impurity layer in a plan view; an impurity concentration of the first semiconductor layer is higher than an impurity concentration of the semiconductor substrate; the impurity concentration of the second semiconductor layer is higher than the impurity concentration of the first semiconductor layer; an impurity concentration of the second impurity layer is higher than an impurity concentration of the first impurity layer; the impurity concentration of the third impurity layer is higher than the impurity concentration of the second impurity layer; Semiconductor device.

3. 3. The semiconductor device according to claim 1, a control unit connected to the first gate electrode and the second gate electrode, and controlling the turn-off timing of the voltage signal of the first gate electrode to be later than the turn-off timing of the voltage signal of the second gate electrode; Semiconductor device.

4. 3. The semiconductor device according to claim 1, the first impurity layer is provided along a direction in which the first trench extends in a plan view, the second impurity layer is provided along a direction in which the second trench extends in a plan view; Semiconductor device.

5. 3. The semiconductor device according to claim 1, the first impurity layer and the second impurity layer are each provided across the first trench and the second trench in a plan view; Semiconductor device.

6. 2. The semiconductor device according to claim 1, at least one third trench provided from the upper surface of the semiconductor substrate to a position below the lower surface of the first semiconductor layer; a third electrode layer embedded in the third trench and surrounded by an oxide film; an emitter electrode connected to the third electrode layer, the third trench is adjacent to the second trench on the opposite side to the first trench; Semiconductor device.

7. 3. The semiconductor device according to claim 2, at least one third trench provided from the upper surface of the semiconductor substrate to a position below the lower surface of the second semiconductor layer; a third electrode layer embedded in the third trench and surrounded by an oxide film; an emitter electrode connected to the third electrode layer, the third trench is adjacent to the second trench on the opposite side to the first trench; Semiconductor device.

8. 8. The semiconductor device according to claim 6, The width of the second trench is wider than the width of the first trench, The width of the third trench is wider than the width of the first trench. Semiconductor device.

9. 8. The semiconductor device according to claim 6, The depth of the bottom surface of the third trench is equal to the depth of the bottom surface of the second trench. Semiconductor device.

10. 8. The semiconductor device according to claim 6, a plurality of the second trenches; a plurality of the third trenches; a distance between adjacent second trenches, a distance between adjacent third trenches, or a distance between adjacent second trenches and third trenches is narrower than 15 μm; Semiconductor device.

11. a first semiconductor layer of a first conductivity type is provided on a surface layer of a semiconductor substrate of a first conductivity type; a first impurity layer of a second conductivity type and a second impurity layer of a second conductivity type are selectively provided on a surface layer of the first semiconductor layer; a second semiconductor layer of a first conductivity type is provided on a part of a surface layer of the first impurity layer; a third semiconductor layer of a first conductivity type is provided on a part of a surface layer of the second impurity layer; providing a first trench extending from an upper surface of the first impurity layer to the inside of the first semiconductor layer; providing at least one second trench extending from an upper surface of the second impurity layer to a position below a lower surface of the first semiconductor layer; a third impurity layer of a second conductivity type is provided across a surface layer of the first impurity layer and a surface layer of the second impurity layer; the second semiconductor layer is sandwiched between the first trench and the third impurity layer in a plan view, the third semiconductor layer is sandwiched between the second trench and the third impurity layer in a plan view, providing a first electrode layer surrounded by an oxide film and embedded in the first trench; providing a second electrode layer surrounded by an oxide film and embedded in the second trench; providing a first gate electrode connected to the first electrode layer; providing a second gate electrode connected to the second electrode layer; an impurity concentration of the first semiconductor layer is higher than an impurity concentration of the semiconductor substrate; an impurity concentration of the second impurity layer is higher than an impurity concentration of the first impurity layer; the impurity concentration of the third impurity layer is higher than the impurity concentration of the second impurity layer; A method for manufacturing a semiconductor device.

12. 12. The method for manufacturing a semiconductor device according to claim 11, a first impurity layer formed in a region covered with the implantation mask and a second impurity layer formed in a region not covered with the implantation mask by ion implantation, the first impurity layer being formed in a region covered with the implantation mask and the second impurity layer being formed in a region not covered with the implantation mask, respectively, in a state where a part of a surface layer of the first semiconductor layer is covered with an implantation mask having a stripe pattern or a dot pattern; A method for manufacturing a semiconductor device.

13. a first semiconductor layer of the first conductivity type and a second semiconductor layer of the first conductivity type are selectively provided on a surface layer of a semiconductor substrate of the first conductivity type; a first impurity layer of a second conductivity type is provided on a surface layer of the first semiconductor layer; a second impurity layer of a second conductivity type is provided on a surface layer of the second semiconductor layer; a third semiconductor layer of a first conductivity type is provided on a part of a surface layer of the first impurity layer; a fourth semiconductor layer of a first conductivity type is provided on a part of a surface layer of the second impurity layer; providing a first trench extending from an upper surface of the first impurity layer to the inside of the first semiconductor layer; providing at least one second trench extending from an upper surface of the second impurity layer to a position below a lower surface of the second semiconductor layer; a third impurity layer of a second conductivity type is provided across a surface layer of the first impurity layer and a surface layer of the second impurity layer; the third semiconductor layer is sandwiched between the first trench and the third impurity layer in a plan view, the fourth semiconductor layer is sandwiched between the second trench and the third impurity layer in a plan view, providing a first electrode layer surrounded by an oxide film and embedded in the first trench; providing a second electrode layer surrounded by an oxide film and embedded in the second trench; providing a first gate electrode connected to the first electrode layer; providing a second gate electrode connected to the second electrode layer; an impurity concentration of the first semiconductor layer is higher than an impurity concentration of the semiconductor substrate; the impurity concentration of the second semiconductor layer is higher than the impurity concentration of the first semiconductor layer; an impurity concentration of the second impurity layer is higher than an impurity concentration of the first impurity layer; the impurity concentration of the third impurity layer is higher than the impurity concentration of the second impurity layer; A method for manufacturing a semiconductor device.

14. 14. The method for manufacturing a semiconductor device according to claim 13, a first impurity layer formed in a region covered with the implantation mask and a second impurity layer formed in a region not covered with the implantation mask by ion implantation, the first impurity layer being formed in a region covered with the implantation mask and the second impurity layer being formed in a region not covered with the implantation mask, respectively, while the surface of the first semiconductor layer is covered with an implantation mask having a stripe pattern or a dot pattern; A method for manufacturing a semiconductor device.

15. 15. A method for manufacturing a semiconductor device according to any one of claims 11 to 14, a first trench formed in a region corresponding to the first opening and a second trench formed in a region corresponding to the second opening by etching, while the upper surface of the semiconductor substrate is covered with an etching mask having a first opening and a second opening whose opening width is wider than that of the first opening; A method for manufacturing a semiconductor device.

16. 15. A method for manufacturing a semiconductor device according to any one of claims 11 to 14, a control unit connected to the first gate electrode and the second gate electrode; the control unit controls the turn-off timing of the voltage signal of the first gate electrode to be later than the turn-off timing of the voltage signal of the second gate electrode; A method for manufacturing a semiconductor device.

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