Semiconductor device and method for manufacturing the same

Abstract

To provide a planar type semiconductor device employing trench structure in which a gate insulating film electric field is reduced, energization of a parasitic pn diode is reduced, and on-resistance is reduced, and a method of manufacturing the semiconductor device.SOLUTION: A semiconductor device comprises: a semiconductor substrate 1 of a first conductivity type; a first semiconductor layer 3 of the first conductivity type; a second semiconductor layer 4 of a second conductivity type; a first semiconductor region 14 of the first conductivity type; a second semiconductor region 8 of the first conductivity type; a third semiconductor region 12 of the first conductivity type; a trench 11; a gate insulating film 5; a gate electrode 6; a fourth semiconductor region 13 of the second conductivity type; and an inter-layer insulating film 9. The gate electrode 6 is separately provided in a region on the first semiconductor region 14.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] Silicon (Si) has traditionally been used as a constituent material for power semiconductor devices that control high voltages and large currents. There are several types of power semiconductor devices, including bipolar transistors, IGBTs (Insulated Gate Bipolar Transistors), and MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), and these are used according to their intended use.

[0003] For example, bipolar transistors and IGBTs have higher current densities and can handle larger currents than MOSFETs, but they cannot switch at high speeds. Specifically, bipolar transistors are limited to switching frequencies of a few kHz, while IGBTs are limited to switching frequencies of several tens of kHz. On the other hand, power MOSFETs have lower current densities than bipolar transistors and IGBTs, making it difficult to handle larger currents, but they are capable of high-speed switching operations up to a few MHz.

[0004] However, there is a strong demand in the market for power semiconductor devices that combine high current and high speed, and efforts have been made to improve IGBTs and power MOSFETs, with development currently approaching the material limits. From the perspective of power semiconductor devices, semiconductor materials to replace silicon are being considered, and silicon carbide (SiC) is attracting attention as a semiconductor material that can be used to fabricate (manufacture) next-generation power semiconductor devices with low on-voltage, high-speed characteristics, and excellent high-temperature characteristics.

[0005] The reason behind this is that SiC is a very chemically stable material, with a wide band gap of 3 eV, allowing it to be used extremely stably as a semiconductor even at high temperatures. In addition, its maximum electric field strength is more than one order of magnitude greater than that of silicon. As SiC has a high possibility of exceeding the material limits of silicon, there are high expectations for its future growth in power semiconductor applications, particularly in MOSFETs. In particular, its low on-resistance is expected. Vertical SiC-MOSFETs with even lower on-resistance while maintaining high breakdown voltage characteristics are expected.

[0006] The structure of a conventional silicon carbide semiconductor device will be described using a vertical MOSFET as an example. Fig. 26 is a cross-sectional view showing the structure of a conventional planar silicon carbide semiconductor device. As shown in Fig. 26, a vertical MOSFET 150 has n + The front surface of the silicon carbide substrate 101 is - A silicon carbide epitaxial layer 103 is deposited, - The surface of the silicon carbide epitaxial layer 103 is + A mold base layer 104 is optionally provided. + The surface layer of the mold base layer 104 is + type source region 108, p + A mold contact region 107 is optionally provided.

[0007] Also, p + The mold base layer 104, n - The portion on the silicon carbide epitaxial layer 103 has p + through the mold base layer 104 - An n-type JFET (Junction FET) region 114 is provided that reaches the silicon carbide epitaxial layer 103. + The base layer 104 and the n + A gate electrode 106 is provided on the surface of the n-type source region 108 via a gate insulating film 105. - Silicon carbide epitaxial layer 103, p + type contact region 107 and n + A source electrode 110 is provided on the surface of the n-type source region 108. +A drain electrode (not shown) is provided on the back surface of the silicon carbide substrate 101.

[0008] Also, a planar silicon carbide semiconductor device using a trench structure (TED (Trench-Etched Double-Diffused) MOSFET) is known to reduce the electric field strength and energy loss of a vertical MOSFET (see Patent Documents 1 to 3 below).

[0009] Fig. 27 is a perspective view showing the structure of a planar silicon carbide semiconductor device using a conventional trench structure. Fig. 28 is a cross-sectional view taken along line A-A' in Fig. 27 showing the structure of a planar silicon carbide semiconductor device using a conventional trench structure. Fig. 29 is a cross-sectional view taken along line B-B' in Fig. 27 showing the structure of a planar silicon carbide semiconductor device using a conventional trench structure. In Fig. 27, the structure from gate insulating film 105 (described below) to source electrode 110 (described below) is omitted.

[0010] As shown in FIGS. 27 to 29, the vertical MOSFET 151 has an n + The front surface of the silicon carbide substrate 101 is - A silicon carbide epitaxial layer 103 is deposited, - The surface of the silicon carbide epitaxial layer 103 is + A mold base layer 104 is optionally provided. + The surface layer of the mold base layer 104 is + type source region 108, p + Type contact region 107, n + A current spreading layer 112 is optionally provided.

[0011] Also, p + The mold base layer 104, n - The portion on the silicon carbide epitaxial layer 103 has p + through the mold base layer 104 - An n-type JFET region 114 is provided that reaches the silicon carbide epitaxial layer 103, and a p-type JFET region 114 is provided on the JFET region 114. - A type electric field relaxation layer 113 is provided. -By covering the entire JFET region 114 with the type electric field reduction layer 113, it is possible to reduce the electric field of the gate insulating film applied during the off state.

[0012] Also, n + The bottom surface is shallower than the p-type current diffusion layer 112. + A trench 111 is selectively provided in contact with the mold base layer 104. Fig. 28 is a cross-sectional view of a portion where the trench 111 is not provided, and Fig. 29 is a cross-sectional view of a portion where the trench 111 is provided. The inner wall of the trench 111, n + Current spreading layer 112, p + The base layer 104 and the n + A gate electrode 106 is provided on the surface of the p-type source region 108 via a gate insulating film 105, and an interlayer insulating film 109 is provided to cover the gate electrode 106. + type contact region 107 and n + A source electrode 110 is provided on the surface of the n-type source region 108. + A drain electrode (not shown) is provided on the back surface of the silicon carbide substrate 101.

[0013] In such a structure, the side surface of trench 111 becomes a channel region, thereby realizing a higher channel mobility than the channel region of a planar silicon carbide semiconductor device (see FIG. 26). Furthermore, forming trench 111 increases the channel width, thereby realizing a higher current density than that of a planar silicon carbide semiconductor device. [Prior art documents] [Patent documents]

[0014] [Patent Document 1] Patent No. 6290457 [Patent Document 2] Patent No. 6309656 [Patent Document 3] Patent No. 6336055 Summary of the Invention [Problem to be solved by the invention]

[0015] However, in conventional planar silicon carbide semiconductor devices using a trench structure, p - The electric field relaxation layer 113 becomes a resistance component, which increases the JFET resistance (resistance of the JFET region 114) and the on-resistance.

[0016] In addition, the vertical MOSFETs 150 and 151 are n - The silicon carbide epitaxial layer 103 and the p + When a current flows through the parasitic pn diode, p + Holes are injected from the n-type base layer 104 - type silicon carbide epitaxial layer 103 or n + Recombination of electrons and holes occurs in the silicon carbide substrate 101. The recombination energy (3 eV) generated at this time, equivalent to the band gap, moves basal plane dislocations, a type of crystal defect present in the silicon carbide substrate, and stacking faults sandwiched between two basal plane dislocations expand. When the stacking faults expand, they make it difficult for current to flow, which poses a problem of increasing the on-resistance of the vertical MOSFETs 150 and 151 and the forward voltage of the parasitic pn diode. In addition, because the parasitic pn diode is a bipolar device, there is a problem of large switching loss (Qrr).

[0017] In order to solve the above-mentioned problems associated with the conventional technology, an object of the present invention is to provide a planar semiconductor device using a trench structure in which the electric field of the gate insulating film is reduced, the conduction of current through a parasitic pn diode is reduced, and the on-resistance is reduced, and a method for manufacturing the semiconductor device. [Means for solving the problem]

[0018] In order to solve the above-mentioned problems and achieve the object of the present invention, a semiconductor device according to the present invention has the following features: A first semiconductor layer of a first conductivity type having a lower impurity concentration than the semiconductor substrate is provided on a semiconductor substrate of a first conductivity type. A second semiconductor layer of a second conductivity type is provided on the opposite side of the first semiconductor layer with respect to the semiconductor substrate. A first semiconductor region of the first conductivity type is provided from the surface of the second semiconductor layer, penetrating the second semiconductor layer and reaching the first semiconductor layer. A second semiconductor region of the first conductivity type having a higher impurity concentration than the semiconductor substrate is selectively provided in a surface layer of the second semiconductor layer opposite to the first semiconductor layer. A third semiconductor region of the first conductivity type is selectively provided in a surface layer of the second semiconductor layer opposite to the first semiconductor layer, spaced apart from the second semiconductor region and in contact with the first semiconductor region. A trench is provided from the surface of the second semiconductor layer, sandwiched between the second semiconductor region and the third semiconductor region and not reaching the first semiconductor layer. A gate insulating film is provided extending from the first semiconductor region to the second semiconductor region and on an inner wall of the trench. A gate electrode is provided on the gate insulating film. A fourth semiconductor region of the second conductivity type is provided between the third semiconductor region and the gate electrode and in contact with the inner wall of the trench. The fourth semiconductor region covers the first semiconductor region. An interlayer insulating film is provided on the gate electrode, and the gate electrode is separated by a region above the first semiconductor region.

[0019] In addition, in the semiconductor device according to the present invention, the width of the isolated region is wider than the thickness of the interlayer insulating film.

[0020] In addition, the semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, the first semiconductor region comprises a lower first semiconductor region that is deeper than the surface of the third semiconductor region facing the semiconductor substrate, and an upper first semiconductor region that is shallower than the surface of the third semiconductor region facing the semiconductor substrate, and the upper first semiconductor region has the same impurity concentration as the third semiconductor region and a higher impurity concentration than the lower first semiconductor region.

[0021] Furthermore, the semiconductor device according to the present invention is characterized in that, in the above-described invention, the first semiconductor region comprises a lower first semiconductor region provided on the first semiconductor layer and an upper first semiconductor region provided on the lower first semiconductor region, the interface between the lower first semiconductor region and the upper first semiconductor region is deeper than the surface of the third semiconductor region facing the semiconductor substrate, and the upper first semiconductor region has the same impurity concentration as the third semiconductor region but a higher impurity concentration than the lower first semiconductor region.

[0022] In addition, in the semiconductor device according to the present invention, the first semiconductor region has the same impurity concentration as the third semiconductor region.

[0023] To solve the above-mentioned problems and achieve the object of the present invention, a method for manufacturing a semiconductor device according to the present invention has the following features. First, a first step is performed in which a first semiconductor layer of a first conductivity type having an impurity concentration lower than that of the semiconductor substrate is formed on a semiconductor substrate of a first conductivity type. Next, a second step is performed in which a second semiconductor layer of a second conductivity type is formed on the side of the first semiconductor layer opposite the semiconductor substrate, and a first semiconductor region of the first conductivity type is formed from the surface of the second semiconductor layer, penetrating the second semiconductor layer and reaching the first semiconductor layer. Next, a third step is performed in which a second semiconductor region of the first conductivity type having an impurity concentration higher than that of the semiconductor substrate is selectively formed in a surface layer of the second semiconductor layer opposite the first semiconductor layer. Next, a fourth step is performed in which a third semiconductor region of the first conductivity type is selectively formed in a surface layer of the second semiconductor layer opposite the first semiconductor layer, spaced apart from the second semiconductor region and in contact with the first semiconductor region. Next, a fifth step is performed in which a fourth semiconductor region of the second conductivity type is formed in a surface layer of the third semiconductor region opposite the first semiconductor layer. Next, a sixth step is performed in which a trench is formed from the surface of the second semiconductor layer, sandwiched between the second semiconductor region and the third semiconductor region and not reaching the first semiconductor layer. Next, a seventh step is performed in which a gate insulating film is formed from the first semiconductor region to the second semiconductor region, and a gate insulating film is formed on the inner wall of the trench. Next, an eighth step is performed in which a gate electrode is formed on the gate insulating film. Next, a ninth step is performed in which an interlayer insulating film is formed on the gate electrode. In the fifth step, the fourth semiconductor region is formed between the third semiconductor region and the gate electrode, and is connected to the inner wall of the trench. The fourth semiconductor region covers the first semiconductor region. The eighth step includes the step of removing the gate electrode in a region above the first semiconductor region.

[0029] According to the above-mentioned invention, the gate electrode is removed in the region above the JFET region. By removing the gate electrode above the JFET region where the electric field tends to concentrate, the electric field applied to the gate insulating film can be alleviated. By alleviating the electric field, the impurity concentration in the JFET region can be increased, thereby reducing the on-resistance. [Effects of the Invention]

[0031] The semiconductor device and the method for manufacturing the semiconductor device according to the present invention have the advantage of being able to provide a planar semiconductor device using a trench structure that reduces the electric field of the gate insulating film, decreases the conduction of the parasitic pn diode, and reduces the on-resistance. [Brief explanation of the drawings]

[0032] [Figure 1] 1 is a perspective view showing a structure of a silicon carbide semiconductor device according to a first embodiment. [Figure 2] 2 is a cross-sectional view taken along line AA' of FIG. 1 showing the structure of the silicon carbide semiconductor device according to the first embodiment. [Figure 3] 2 is a cross-sectional view taken along line BB' of FIG. 1 showing the structure of the silicon carbide semiconductor device according to the first embodiment. [Figure 4] 1 is a top view showing a structure of a gate electrode of the silicon carbide semiconductor device in accordance with the first embodiment. [Figure 5] 1 is a cross-sectional view (part 1) showing a state during the manufacture of the silicon carbide semiconductor device according to the first embodiment. [Figure 6] 10 is a cross-sectional view (part 2) illustrating a state during manufacture of the silicon carbide semiconductor device according to the first embodiment. FIG. [Figure 7] 10 is a cross-sectional view (part 3) illustrating a state during the manufacture of the silicon carbide semiconductor device according to the first embodiment. FIG. [Figure 8] 10 is a cross-sectional view (part 4) illustrating a state during the manufacture of the silicon carbide semiconductor device according to the first embodiment. FIG. [Figure 9] 5 is a cross-sectional view showing a state during manufacture of the silicon carbide semiconductor device according to the first embodiment (part 5). FIG. [Figure 10] 10 is a cross-sectional view (part 1) showing a structure of a silicon carbide semiconductor device according to a second embodiment. FIG. [Figure 11] 10 is a cross-sectional view (part 2) showing a structure of a silicon carbide semiconductor device according to the second embodiment. FIG. [Figure 12] 10 is a cross-sectional view (part 1) showing a structure of a silicon carbide semiconductor device according to a third embodiment. FIG. [Figure 13]10 is a cross-sectional view (part 2) showing a structure of a silicon carbide semiconductor device according to the third embodiment. FIG. [Figure 14] 10 is a cross-sectional view (part 1) showing a structure of a silicon carbide semiconductor device according to a fourth embodiment. FIG. [Figure 15] 13 is a cross-sectional view (part 2) showing a structure of a silicon carbide semiconductor device according to a fourth embodiment. FIG. [Figure 16] 1 is another cross-sectional view (part 1) illustrating the structure of the silicon carbide semiconductor device in accordance with the first embodiment. [Figure 17] 10 is another cross-sectional view (part 2) illustrating the structure of the silicon carbide semiconductor device in accordance with the first embodiment. FIG. [Figure 18] 10 is a cross-sectional view (part 1) showing a structure of a silicon carbide semiconductor device according to a fifth embodiment. FIG. [Figure 19] 13 is a cross-sectional view (part 2) showing a structure of a silicon carbide semiconductor device according to a fifth embodiment. FIG. [Figure 20] 13 is a cross-sectional view (part 1) showing a structure of a silicon carbide semiconductor device according to a sixth embodiment. FIG. [Figure 21] 13 is a cross-sectional view (part 2) showing a structure of a silicon carbide semiconductor device according to a sixth embodiment. FIG. [Figure 22] FIG. 13 is a plan view showing a structure of a silicon carbide semiconductor device according to a sixth embodiment. [Figure 23] 13 is a cross-sectional view (part 1) showing a structure of a silicon carbide semiconductor device according to a seventh embodiment. FIG. [Figure 24] 13 is a cross-sectional view (part 2) showing a structure of a silicon carbide semiconductor device according to a seventh embodiment. FIG. [Figure 25] FIG. 13 is a plan view showing a structure of a silicon carbide semiconductor device according to a seventh embodiment. [Figure 26] FIG. 1 is a cross-sectional view showing the structure of a conventional planar silicon carbide semiconductor device. [Figure 27] FIG. 1 is a perspective view showing the structure of a planar silicon carbide semiconductor device using a conventional trench structure. [Figure 28] FIG. 28 is a cross-sectional view taken along the line AA' of FIG. 27, showing the structure of a planar silicon carbide semiconductor device using a conventional trench structure. [Figure 29] FIG. 28 is a cross-sectional view taken along the line BB' of FIG. 27, showing the structure of a planar silicon carbide semiconductor device using a conventional trench structure. DETAILED DESCRIPTION OF THE INVENTION

[0033] Preferred embodiments of a semiconductor device and a method for manufacturing a semiconductor device according to the present invention will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, layers and regions prefixed with n or p indicate that electrons or holes are the majority carriers, respectively. The + and - symbols attached to n or p indicate higher and lower impurity concentrations than layers and regions without these symbols, respectively. In the following description of the embodiments and the accompanying drawings, similar components are designated by the same reference symbols, and redundant explanations will be omitted. In this specification, in the notation of Miller indices, "-" refers to a bar attached to the index immediately following it, and adding "-" before an index indicates a negative index. It is preferable that the terms "same" or "equivalent" be used to include variations within 5% in consideration of variations in manufacturing.

[0034] (Embodiment 1) The semiconductor device according to the present invention is configured using a wide bandgap semiconductor. In the first embodiment, a silicon carbide semiconductor device fabricated using, for example, silicon carbide (SiC) as a wide bandgap semiconductor will be described using a MOSFET 50 as an example. FIG. 1 is a perspective view showing the structure of the silicon carbide semiconductor device according to the first embodiment. FIG. 2 is a cross-sectional view taken along line A-A' in FIG. 1 showing the structure of the silicon carbide semiconductor device according to the first embodiment. FIG. 3 is a cross-sectional view taken along line B-B' in FIG. 1 showing the structure of the silicon carbide semiconductor device according to the first embodiment. In FIG. 1, the structure from a gate insulating film 5 to a source electrode 10, which will be described below, is omitted.

[0035] As shown in FIGS. 1 to 3, the silicon carbide semiconductor device according to the first embodiment has n + On the main surface (front surface) of a silicon carbide substrate (first conductivity type semiconductor substrate) 1, -A silicon carbide epitaxial layer (first semiconductor layer of a first conductivity type) 3 is deposited on the silicon carbide epitaxial layer.

[0036] n + The silicon carbide substrate 1 is, for example, a silicon carbide single crystal substrate doped with nitrogen (N). - The silicon carbide epitaxial layer 3 is + The low-concentration n-type drift layer is doped with, for example, nitrogen at an impurity concentration lower than that of the silicon carbide substrate 1. + Silicon carbide substrate 1 alone or n + A silicon carbide substrate 1 and an n - The silicon carbide epitaxial layer 3 and the silicon carbide epitaxial layer 4 form a silicon carbide semiconductor substrate.

[0037] Furthermore, in the silicon carbide semiconductor device according to the first embodiment, the n + n-type silicon carbide substrate 1 - A drain electrode (not shown) is provided on the surface (back surface of the silicon carbide semiconductor substrate) opposite to the silicon carbide epitaxial layer 3. Also, a drain electrode pad (not shown) for connection to an external device is provided.

[0038] A MOS (metal-oxide-semiconductor insulated gate) structure (device structure) is formed on the front surface of the silicon carbide semiconductor substrate. - n type silicon carbide epitaxial layer 3 + The surface layer on the side opposite to the silicon carbide substrate 1 (the front surface side of the silicon carbide semiconductor base) is + A base layer (second semiconductor layer of a second conductivity type) 4 is selectively provided. + The mold base layer 4 is doped with, for example, aluminum (Al).

[0039] p + The surface layer of the mold base layer 4 is + A p-type source region (a second semiconductor region of the first conductivity type) 8 is provided. + A contact region 7 may be provided. + type source region 8 and p +The contact regions 7 are in contact with each other. + The source region 8 is p + It is disposed closer to the JFET region 14 described below than the contact region 7.

[0040] Also, n - n type silicon carbide epitaxial layer 3 + The surface layer on the opposite side to the silicon carbide substrate 1 side is p + On the surface of the portion where the mold base layer 4 is not provided, a layer is formed in the depth direction (from the source electrode (first electrode) 10 to n + Towards the silicon carbide substrate 1 + From the surface of the mold base layer 4 + Penetrating the mold base layer 4 - An n-type JFET (Junction FET) region (first semiconductor region of the first conductivity type) 14 is provided, which reaches the silicon carbide epitaxial layer 3. The JFET region 14 is an n-type - The p-type silicon carbide epitaxial layer 3 and the p-type silicon carbide epitaxial layer 4 form a drift region. + The surface layer of the mold base layer 4 is + Apart from the n-type source region 8, the n-type source region 8 is in contact with the JFET region 14. + A first conductivity type current diffusion layer (third semiconductor region) 12 is provided. + The current spreading layer 12 is a so-called current spreading layer (CSL) that reduces the spreading resistance of carriers.

[0041] The first main surface side (p + A trench structure is selectively provided on the side of the silicon base layer 4. Specifically, the trench 11 is formed by p + n of the mold base layer 4 + The n-type silicon carbide substrate 1 is formed on the surface opposite to the first main surface of the silicon carbide semiconductor substrate. - The trench 11 is provided at a depth not reaching the n-type silicon carbide epitaxial layer 3. + Current spreading layer 12 and p + It is preferable that the trench 11 is provided to a position shallower than the interface with the mold base layer 4. +Current spreading layer 12 and p + This is because a channel is no longer formed at the bottom of trench 11 when the trench reaches a position deeper than the interface with mold base layer 4. Fig. 2 is a cross-sectional view of a portion where no trench structure is provided, and Fig. 3 is a cross-sectional view of a portion where a trench structure is provided.

[0042] A gate insulating film 5 is provided along the inner wall of the trench 11, on the bottom and side walls of the trench 11, and a gate electrode 6 is provided inside the gate insulating film 5 in the trench 11. + Type base layer 4, n + A gate electrode 6 is also provided on the surface of the portion sandwiched between the source region 8 and the JFET region 14 via a gate insulating film 5. The gate electrode 6 is formed by the gate insulating film 5 and a p - through the n-type electric field relaxation layer 13 + The gate electrode 6 is connected to the JFET region 14 and the p-type current diffusion layer 12 by the gate insulating film 5. + It is insulated from the mold base layer 4 .

[0043] As shown in Figures 2 and 3, the gate electrode 6 is not provided in the region above the JFET region 14. Therefore, in the cross-sectional view, the gate electrode 6 is divided into two regions. The gate electrode 6 has at least n + Type source region 8 and p + n from the surface in contact with the mold base layer 4 + It is sufficient that the gate electrode 6 is provided in the region up to the surface where the gate-type current spreading layer 12 and the JFET region 14 contact each other, and it may be removed from the entire region above the JFET region 14. In this way, by removing the gate electrode 6 above the JFET region 14 where the electric field is likely to concentrate, it is possible to alleviate the electric field applied to the gate insulating film 5. Here, the impurity concentration in the JFET region 14 can be increased by the amount of the electric field alleviated, and the on-resistance can be reduced.

[0044] Furthermore, the width of the removed isolation region, i.e., the distance w between the gate electrode 6 divided into two regions, is preferably wider than the height h of the interlayer insulating film 9 (w>h). If the distance is narrower than the height h, the effect of alleviating the electric field will be reduced.

[0045] 4 is a top view showing the structure of the gate electrode of the silicon carbide semiconductor device according to the first embodiment. Gate electrode 6 is divided into two regions in the cross-sectional view, but it is preferable that the distributed gate electrodes 6 are connected in edge termination region 30, for example, to have the same potential. In FIG. 4, gate electrodes 6 within the same cell are connected, but gate electrodes 6 of other cells may also be connected. Edge termination region 30 surrounds active region 40, through which current flows when the device is on, and has the function of alleviating electric field concentration at the edge of active region 40 to maintain a predetermined breakdown voltage (withstand voltage).

[0046] Also, n + The p-type current diffusion layer 12 is in contact with the inner wall of the trench 11 between the gate electrode 6 and the p-type current diffusion layer 12. - A second conductivity type electric field relaxation layer (fourth semiconductor region of the second conductivity type) 13 is provided. - The electric field relaxation layer 13 may be provided between the JFET region 14 and the gate insulating film 5. - The gate electrode 6 and the JFET region 14 are separated by the n-type electric field relaxation layer 13 without contacting each other. - Therefore, it is possible to reduce the electrical capacitance between the silicon carbide epitaxial layer 3 and the silicon carbide epitaxial layer 3 .

[0047] Although only one MOS structure is shown in FIG. 1, multiple MOS structures may be arranged in parallel.

[0048] The interlayer insulating film 9 is provided on the entire front surface side of the silicon carbide semiconductor substrate so as to cover the gate electrode 6. The source electrode 10 is connected to the n-type semiconductor layer 10 via a contact hole opened in the interlayer insulating film 9. + type source region 8 and p + It contacts the mold base layer 4. + When the contact region 7 is provided, + type source region 8 and p +The source electrode 10 is in contact with the type contact region 7. The source electrode 10 is electrically insulated from the gate electrode 6 by an interlayer insulating film 9. An electrode pad (not shown) is provided on the source electrode 10.

[0049] (Method for Manufacturing Silicon Carbide Semiconductor Device According to First Embodiment) Next, a method for manufacturing the silicon carbide semiconductor device according to the first embodiment will be described. Figures 5 to 9 are cross-sectional views showing states during the manufacturing process of the silicon carbide semiconductor device according to the first embodiment. First, for example, 2 × 10 19 / cm 3 Nitrogen doped with an impurity concentration of about + A silicon carbide substrate 1 is prepared. + The main surface of the silicon carbide substrate 1 may be, for example, a (000-1) plane having an off angle of about 4 degrees in the <11-20> direction. + On the (000-1) plane of the silicon carbide substrate 1, 1.0 × 10 16 / cm 3 The thickness of the n - A silicon carbide epitaxial layer 3 is grown on the substrate, resulting in the structure shown in FIG.

[0050] Next, an oxide film mask for ion implantation is formed by photolithography and etching, and n is formed by ion implantation. - The surface layer of the silicon carbide epitaxial layer 3 is provided with p + The mold base layer 4 is selectively formed. + n sandwiched between mold base layers 4 - The region of the silicon carbide epitaxial layer 3 becomes the JFET region 14. In this ion implantation, for example, aluminum is used as the dopant, and p + The impurity concentration of the mold base layer 4 is 2.0×10 16 / cm 3 The dose may be set so that: Here, the structure shown in FIG.

[0051] Next, p + The surface layer of the mold base layer 4 is +Then, p type source regions 8 are selectively formed by photolithography and ion implantation. + The surface layer of the mold base layer 4 is + Then, p-type contact regions 7 may be selectively formed by photolithography and ion implantation. + The surface layer of the mold base layer 4 is + Next, the n-type current diffusion layer 12 is selectively formed by photolithography and ion implantation. + The surface layer of the JFET region 14 and the current spreading layer 12 are provided with p - Then, the electric field buffer layer 13 is selectively formed, resulting in the structure shown in FIG.

[0052] p + Mold base layer 4, n + Type source region 8, p + Type contact region 7, n + Current spreading layer 12 and p - A heat treatment (annealing) is performed to activate the electric field buffer layer 13. The heat treatment temperature and the heat treatment time may be 1620° C. and 10 minutes, respectively.

[0053] p + Mold base layer 4, n + Type source region 8, p + Type contact region 7, n + Current spreading layer 12 and p - The order in which the p-type electric field buffer layer 13 is formed can be changed in various ways. - The electric field relaxation layer 13 can also be formed by epitaxial growth.

[0054] Next, p + A trench forming mask having a predetermined opening is formed by photolithography on the surface of the mold base layer 4, using, for example, an oxide film. Next, p + From the surface of the mold base layer 4, n + Current spreading layer 12 and p + The n -A trench 11 is selectively formed so as not to reach the silicon carbide epitaxial layer 3 .

[0055] Next, the front surface side of the silicon carbide semiconductor substrate is thermally oxidized to form a gate insulating film 5 with a thickness of 100 nm. This thermal oxidation may be performed by heat treatment at a temperature of about 1000°C in a mixed atmosphere of oxygen (O2) and hydrogen (H2). + Each region formed on the surface of the mold base layer 4 and p - The surface of the electric field relaxation layer 13 and the bottom and sidewalls of the trench 11 are covered with the gate insulating film 5. At this point, the structure shown in Fig. 8 is obtained. Fig. 8 shows a cross-sectional view taken along line B-B' in Fig. 1 in which the trench 11 has been formed. The same applies to Fig. 9 below.

[0056] Next, a polycrystalline silicon layer (polysilicon (poly-Si) layer) doped with, for example, phosphorus (P) or boron (B) is formed as a gate electrode 6 on the gate insulating film 5. Next, the polycrystalline silicon layer is patterned and selectively removed, and the inside of the gate insulating film 5 in the trench 11 and the p + Type base layer 4, n + The polycrystalline silicon layer is left on the portion sandwiched between the type source region 8 and the JFET region 14. At this time, the polycrystalline silicon layer is not left on the JFET region 14. At this point, the structure shown in FIG. 9 is obtained.

[0057] Next, for example, phosphosilicate glass (PSG) is deposited as an interlayer insulating film 9 so as to cover the gate insulating film 5. The thickness of the interlayer insulating film 9 may be 1.0 μm. Next, the interlayer insulating film 9 and the gate insulating film 5 are patterned and selectively removed to form contact holes, and n + type source region 8 and p + This exposes the mold contact region 7. Next, a heat treatment (reflow) is performed to flatten the interlayer insulating film 9.

[0058] Next, the source electrode 10 is formed on the surface of the interlayer insulating film 9. At this time, the source electrode 10 is also embedded in the contact hole, and n +type source region 8 and p + The type contact region 7 is in contact with the source electrode 10. The thickness of the portion of the source electrode 10 on the interlayer insulating film 9 may be, for example, 5 μm. The source electrode 10 may be made of, for example, aluminum containing 1 wt % silicon (Al—Si).

[0059] Next, n + A nickel film, for example, is formed as a drain electrode (not shown) on the surface of the silicon carbide substrate 1 (the back surface of the silicon carbide semiconductor base). Then, a heat treatment is performed at a temperature of, for example, 970° C. to form an n + An ohmic junction is formed between the silicon carbide substrate 1 and the drain electrode. Next, an electrode pad is deposited by, for example, sputtering on the entire front surface of the silicon carbide semiconductor substrate so as to cover the source electrode 10 and the interlayer insulating film 9. The thickness of the portion of the electrode pad on the interlayer insulating film may be, for example, 5 μm. The electrode pad may be made of, for example, aluminum containing 1 wt % silicon (Al-Si). Next, the electrode pad is selectively removed.

[0060] Next, a drain electrode pad is formed on the surface of the drain electrode by depositing, for example, titanium (Ti), nickel (Ni), and gold (Au) in this order. A protective film may then be formed on the surface. This completes the MOSFET 50 shown in FIGS. 1 to 3.

[0061] As described above, according to the first embodiment, the gate electrode is removed in the region above the JFET region. By removing the gate electrode above the JFET region where the electric field tends to concentrate, the electric field applied to the gate insulating film can be alleviated. By alleviating the electric field, the impurity concentration in the JFET region can be increased, thereby reducing the on-resistance.

[0062] (Embodiment 2) Figures 10 and 11 are cross-sectional views showing the structure of a silicon carbide semiconductor device according to embodiment 2. Figure 10 is a cross-sectional view of a portion corresponding to Figure 2 of embodiment 1, and Figure 11 is a cross-sectional view of a portion corresponding to Figure 3 of embodiment 1.

[0063] The silicon carbide semiconductor device according to the second embodiment differs from the silicon carbide semiconductor device according to the first embodiment in that the JFET region 14 is made up of a lower JFET region (lower first semiconductor region) 14a and an upper JFET region (upper first semiconductor region) 14b. As shown in FIGS. 10 and 11, the lower JFET region 14a is made up of n + n-type current diffusion layer 12 + A region deeper than the surface on the silicon carbide substrate 1 side (n + The upper JFET region 14b is provided in the n-type silicon carbide substrate 1. + n-type current diffusion layer 12 + The source electrode 10 is provided in a region shallower than the surface on the silicon carbide substrate 1 side (a region closer to the source electrode 10 than the surface).

[0064] The lower JFET region 14a is n - The upper JFET region 14b has an impurity concentration similar to that of the n-type silicon carbide epitaxial layer 3. - The impurity concentration is higher than that of the n-type silicon carbide epitaxial layer 3. + The impurity concentration is approximately the same as that of the upper JFET region 14b. By providing the upper JFET region 14b with a high impurity concentration in this way, the JFET resistance can be made lower than in the first embodiment, and the on-resistance can be further reduced. Also, in the second embodiment, as in the first embodiment, the gate electrode 6 is removed in the region above the JFET region 14. Therefore, the same effects as those in the first embodiment are achieved.

[0065] (Method for manufacturing a silicon carbide semiconductor device according to the second embodiment) The silicon carbide semiconductor device according to the second embodiment is a silicon carbide semiconductor device manufactured by the method of the first embodiment, except that p + The surface layer of the mold base layer 4 is + This can be achieved by forming the upper JFET region 14b on the surface layer of the JFET region 14 when selectively forming the current spreading layer 12.

[0066] As described above, according to the second embodiment, it is possible to obtain the same effects as those of the first embodiment. + n-type current spreading layer + In a region shallower than the surface on the silicon carbide substrate side, + In this embodiment, the upper JFET region has an impurity concentration similar to that of the upper current diffusion layer, which makes it possible to reduce the JFET resistance compared to the first embodiment, and further reduce the on-resistance.

[0067] (Embodiment 3) Figures 12 and 13 are cross-sectional views showing a structure of a silicon carbide semiconductor device according to embodiment 3. Figure 12 is a cross-sectional view of a portion corresponding to Figure 2 of embodiment 1, and Figure 13 is a cross-sectional view of a portion corresponding to Figure 3 of embodiment 1.

[0068] The silicon carbide semiconductor device according to the third embodiment differs from the silicon carbide semiconductor device according to the second embodiment in that the interface between the lower JFET region 14a and the upper JFET region 14b is + n-type current diffusion layer 12 + The upper JFET region 14b is deeper than the surface on the silicon carbide substrate 1 side. That is, the thickness of the upper JFET region 14b is thicker than that in the second embodiment.

[0069] The impurity concentrations of the lower JFET region 14a and the upper JFET region 14b are the same as those in the second embodiment. By providing the upper JFET region 14b with a thickness thicker than that in the second embodiment, the JFET resistance can be made lower than that in the second embodiment, and the on-resistance can be further reduced. Also, in the third embodiment, as in the first embodiment, the gate electrode 6 is removed in the region above the JFET region 14. Therefore, the same effects as those in the first embodiment are obtained.

[0070] (Method for manufacturing silicon carbide semiconductor device according to third embodiment) The silicon carbide semiconductor device according to the third embodiment is a silicon carbide semiconductor device manufactured by the method of the first embodiment, except that p +The surface layer of the mold base layer 4 is + After selectively forming the current spreading layer 12, the upper JFET region 14b can be formed in the surface layer of the JFET region 14 by photolithography and ion implantation.

[0071] As described above, according to the third embodiment, it is possible to obtain the same effects as those of the first embodiment. Furthermore, in the third embodiment, the film thickness of the upper JFET region is greater than that of the second embodiment. This makes it possible to reduce the JFET resistance more than that of the second embodiment, and to further reduce the on-resistance.

[0072] (Fourth embodiment) Figures 14 and 15 are cross-sectional views showing the structure of a silicon carbide semiconductor device according to embodiment 4. Figure 14 is a cross-sectional view of a portion corresponding to Figure 2 of embodiment 1, and Figure 15 is a cross-sectional view of a portion corresponding to Figure 3 of embodiment 1.

[0073] The silicon carbide semiconductor device according to the fourth embodiment differs from the silicon carbide semiconductor device according to the first embodiment in that the JFET region 14 is n + The impurity concentration is the same as that of the upper current spreading layer 12. In this embodiment, the JFET region 14 is replaced with the upper JFET region 14b of the second and third embodiments. Hereinafter, the same impurity concentration means, for example, an impurity concentration including manufacturing variations when formed simultaneously, that is, substantially the same.

[0074] The thickness is thicker than the upper JFET region 14b in the second and third embodiments, and n + By providing a JFET region 14 having the same impurity concentration as the type current spreading layer 12, the JFET resistance can be made lower than in the second and third embodiments, and the on-resistance can be further reduced. Also, in the fourth embodiment, as in the first embodiment, the gate electrode 6 is removed in the region above the JFET region 14. Therefore, the same effects as in the first embodiment are obtained.

[0075] (Method for manufacturing a silicon carbide semiconductor device according to a fourth embodiment) The silicon carbide semiconductor device according to the fourth embodiment is a silicon carbide semiconductor device manufactured by the method of the first embodiment, except that p + The surface layer of the mold base layer 4 is + After selectively forming the current diffusion layer 12, the impurity concentration of the JFET region 14 is adjusted to n by photolithography and ion implantation. + It is possible to manufacture the semiconductor device by making the impurity concentration of the semiconductor device the same as that of the current diffusion layer 12.

[0076] As described above, according to the fourth embodiment, it is possible to obtain the same effects as those of the first embodiment. Furthermore, in the fourth embodiment, the JFET region is + The impurity concentration of the JFET region is the same as that of the upper current diffusion layer 12, and the JFET region is thicker than the upper JFET region of the second and third embodiments. This makes it possible to reduce the JFET resistance compared to the second embodiment, and further reduce the on-resistance.

[0077] In the first to fourth embodiments, n + Current spreading layer 12 and p - The type electric field relaxation layer 13 may have other shapes. Figs. 16 and 17 are other cross-sectional views showing the structure of the silicon carbide semiconductor device according to the first embodiment. In Figs. 16 and 17, n + Current spreading layer 12 and p - The structure of the n-type electric field relaxation layer 13 is shown, but the JFET region 14 of the second to fourth embodiments also has the same shape. + Current spreading layer 12 and p - It is also possible to use the layer 13 as a type electric field relaxation layer.

[0078] For example, as shown in Figure 16, + The current spreading layer 12 is p - The width of the n-type electric field buffer layer 13 side is wide, + The width of the silicon carbide substrate 1 side may be narrow. Even in this shape, the electric field concentration can be alleviated. -The width of the electric field relaxation layer 13 and n + The width of the silicon carbide substrate 1 is approximately the same as that of the n-type silicon carbide substrate 1. + This narrows the area of ​​the gate current diffusion layer 12. This improves the tradeoff between the on-resistance and the electric field of the gate insulating film, thereby reducing the electric field of the gate insulating film while maintaining a low on-resistance.

[0079] Also, as shown in Figure 17, p - The electric field buffer layer 13 may be removed in the region where the gate electrode 6 is not provided. - The distance w' between the adjacent electric field buffer layers 13 is equal to or narrower than the distance w between the adjacent gate electrodes 6 (w'≦w). - The electric field buffer layer 13 is provided to reduce the electric field of the gate insulating film applied during the off state, and therefore may not be provided in the region where the gate electrode 6 is not provided.

[0080] Also, by combining Fig. 16 and Fig. 17, n + The current spreading layer 12 is p - The width of the n-type electric field buffer layer 13 side is wide, + The width of the silicon carbide substrate 1 side is narrow, and - The electric field buffer layer 13 may be removed in the region where the gate electrode 6 is not provided.

[0081] (Embodiment 5) Figures 18 and 19 are cross-sectional views showing the structure of a silicon carbide semiconductor device according to embodiment 5. Figure 18 is a cross-sectional view of a portion corresponding to Figure 2 of embodiment 1, and Figure 19 is a cross-sectional view of a portion corresponding to Figure 3 of embodiment 1.

[0082] The silicon carbide semiconductor device according to the fifth embodiment differs from the silicon carbide semiconductor device according to the first embodiment in that an opening is formed in the interlayer insulating film 9 above the JFET region 14, a Schottky metal 15 is disposed in the opening, and an SBD (Schottky Barrier Diode) is incorporated.

[0083] In the region where the gate electrode 6 is separated, the interlayer insulating film 9 is opened up to the surface of the JFET region 14, and a metal that forms a Schottky contact with SiC, such as Ti (titanium) or Mo (molybdenum), is embedded in the opening, thereby forming a Schottky contact between the source electrode 10 and the JFET region 14.

[0084] Because the SBD has a lower forward voltage Vf than the parasitic pn diode, it turns on at a lower voltage than the parasitic pn diode. As a result, during commutation, current flows through the SBD, reducing the current flow through the parasitic pn diode. This prevents the on-resistance of the vertical MOSFET from increasing. Also, because the SBD operates in unipolar mode, Qrr is smaller than that of a parasitic pn diode in bipolar operation, reducing switching loss.

[0085] The width of the Schottky metal 15 is narrower than the width of the opening of the interlayer insulating film 9, and - It is preferable that the electric field relaxation layer 13 protrudes beyond the opening. The edge of the JFET region 14 is a place where leakage is likely to occur, so - By providing the type electric field relaxation layer 13, the electric field at the Schottky interface can be relaxed to reduce the leakage current.

[0086] (Method for manufacturing a silicon carbide semiconductor device according to a fifth embodiment) The silicon carbide semiconductor device according to the fifth embodiment can be manufactured by adding the following process to the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. First, the interlayer insulating film 9 is opened up to the surface of the JFET region 14 in the region where the gate electrode 6 is separated. -When forming the electric field relaxation layer 13, it is not formed on the opening of the JFET region 14. Next, a metal film made of, for example, Ti or Mo is formed along the surface of the JFET region 14 in the opening. Next, a heat treatment (annealing) is performed in a nitrogen (N2) atmosphere at a temperature of, for example, about 500°C or less, thereby forming a Schottky junction between the metal film and the semiconductor region on the surface of the JFET region 14. Other than this, the method for manufacturing the silicon carbide semiconductor device can be the same as that for manufacturing the silicon carbide semiconductor device according to the first embodiment.

[0087] As described above, according to the fifth embodiment, the same effects as those of the first embodiment can be obtained. Furthermore, in the fifth embodiment, an opening is made in the interlayer insulating film above the JFET region, and a Schottky metal is disposed in the opening, thereby incorporating an SBD. As a result, during commutation, current flows through the SBD, reducing the current flow through the parasitic pn diode. This prevents an increase in the on-resistance of the vertical MOSFET. Furthermore, because the SBD operates in unipolar mode, Qrr is smaller than that of a parasitic pn diode operating in bipolar mode, thereby reducing switching loss.

[0088] (Sixth embodiment) 20 and 21 are cross-sectional views showing a structure of a silicon carbide semiconductor device according to embodiment 6. Fig. 20 is a cross-sectional view of a portion corresponding to Fig. 2 of embodiment 1, and Fig. 21 is a cross-sectional view of a portion corresponding to Fig. 3 of embodiment 1.

[0089] The silicon carbide semiconductor device according to the sixth embodiment differs from the silicon carbide semiconductor device according to the fifth embodiment in that an opening is formed in the interlayer insulating film 9 above the JFET region 14, a Schottky trench (second trench) 16 is formed above the JFET region 14, and a Schottky metal 15 is disposed on the bottom and sidewalls of the Schottky trench 16 to incorporate an SBD.

[0090] A Schottky junction is formed between the source electrode 10 and the JFET region 14 by embedding a metal that forms a Schottky junction with SiC, such as Ti (titanium) or Mo (molybdenum), in the bottom and sidewalls of the Schottky trench 16. In the sixth embodiment, a Schottky junction is formed in the bottom and sidewalls of the Schottky trench 16, so the area of ​​the Schottky junction can be increased compared to the fifth embodiment.

[0091] Here, Schottky trench 16 preferably has a tapered shape in which the width of the opening is wider than the width of the bottom. This is because if Schottky trench 16 has an inverse tapered shape in which the angle θ between the sidewall and the bottom of Schottky trench 16 is 90° or more, an electric field will concentrate at the corner between the sidewall and the bottom of Schottky trench 16.

[0092] Furthermore, the larger the angle θ, the larger the area of ​​the sidewall, and the larger the area of ​​the Schottky junction. On the other hand, the larger the angle θ, the more difficult it becomes to narrow the width of Schottky trench 16. For this reason, the angle θ between the sidewall and the bottom of Schottky trench 16 is preferably 82° or more and less than 90°, and more preferably 85° or more and 88° or less.

[0093] Furthermore, the Schottky trench 16 can be formed simultaneously in a self-aligned manner when the trench 11 is formed. Therefore, the Schottky trench 16 has the same depth as the trench 11. Although it is preferable that both the trench 11 and the Schottky trench 16 are deep, if they are deep, an electric field will be concentrated at the bottom of the trench 11 and the Schottky trench 16. The trench 11 has a p + A mold base layer 4 is provided, the bottom of which is p + Because the trench 11 is protected by the mold base layer 4, the electric field is less likely to concentrate at the bottom than in the Schottky trench 16. For this reason, the trench 11 may be made deeper than the Schottky trench 16.

[0094] FIG. 22 is a plan view showing the structure of a silicon carbide semiconductor device according to the sixth embodiment. The A-A' cross section of FIG. 22 corresponds to the cross section of FIG. 20, and the B-B' cross section of FIG. 22 corresponds to the cross section of FIG. 21. FIG. 22 is also a plan view of the C-C' cross section of FIGS. 20 and 21. As shown in FIG. 22, trench 11 is formed in a plan view (vertical MOSFET 50 from the source electrode 10 side to the n + The Schottky trench 16 has a rectangular shape in plan view (as viewed toward the silicon carbide substrate 1 side), and the Schottky trench 16 has a stripe shape in plan view.

[0095] In this case, it is preferable that the width w1 of trench 11 is wider than the width w2 of Schottky trench 16. The wider the width, the deeper the trench tends to be. For this reason, Schottky trench 16 is made narrower and shallower than trench 11.

[0096] (Method for manufacturing a silicon carbide semiconductor device according to a sixth embodiment) The silicon carbide semiconductor device according to the sixth embodiment can be manufactured by adding the following process to the method for manufacturing a silicon carbide semiconductor device according to the first embodiment. First, the interlayer insulating film 9 is formed into a p - The opening reaches the surface of the p-type electric field buffer layer 13. + A trench forming mask having predetermined openings is formed by photolithography on the surfaces of the mold base layer 4 and the JFET region 14, using, for example, an oxide film. Next, p + From the surface of the mold base layer 4, n + Current spreading layer 12 and p + The n - The trench 11 does not reach the silicon carbide epitaxial layer 3, and -A Schottky trench 16 is selectively formed from the surface of the type-type electric field buffer layer 13 to reach the JFET region 14. Next, a metal film is formed along the sidewalls and bottom of the Schottky trench 16, for example, using Ti or Mo. Next, a heat treatment (annealing) is performed in a nitrogen (N2) atmosphere at a temperature of about 500°C or less, for example, to form a Schottky junction between the metal film and the semiconductor region on the sidewalls and bottom of the Schottky trench 16. Other than this, the manufacturing method can be the same as that of the silicon carbide semiconductor device according to the first embodiment. In this way, the Schottky trench 16 can be formed simultaneously with the trench 11, and no additional process is required.

[0097] As described above, according to the sixth embodiment, it is possible to obtain the same effects as those of the fifth embodiment. Furthermore, in the sixth embodiment, a Schottky trench is provided, and a Schottky metal is disposed on the bottom and sidewalls of the Schottky trench to incorporate an SBD. Therefore, the sixth embodiment can increase the area of ​​the Schottky junction more than the fifth embodiment.

[0098] (Embodiment 7) 23 and 24 are cross-sectional views showing a structure of a silicon carbide semiconductor device according to a seventh embodiment. FIG. 23 is a cross-sectional view of a portion corresponding to FIG. 2 of the first embodiment, and FIG. 24 is a cross-sectional view of a portion corresponding to FIG. 3 of the first embodiment. FIG. 25 is a plan view showing a structure of a silicon carbide semiconductor device according to the seventh embodiment. The A-A' cross section of FIG. 25 is the cross section of FIG. 23, and the B-B' cross section of FIG. 25 is the cross section of FIG. 24. FIG. 25 is a plan view of the C-C' cross section of FIGS. 23 and 24.

[0099] The silicon carbide semiconductor device according to the seventh embodiment differs from the silicon carbide semiconductor device according to the sixth embodiment in that Schottky trench 16 has a rectangular shape. Therefore, in the seventh embodiment, by making Schottky trench 16 finer, the sidewall portion of Schottky trench 16 can be increased, and the area of ​​the Schottky junction can be increased more than in the sixth embodiment. Making Schottky trench 16 finer means shortening length 1 of the rectangle (see FIG. 25 ). By shortening it, the sidewall portion in the direction in which the rectangles are arranged (the direction perpendicular to A-A' in FIG. 25 ) can be increased.

[0100] The shape of the Schottky trench 16 can be a rectangle with rounded corners or a circle. In this case, the concentration of the electric field at the corners of the rectangle can be reduced. Also, a circle shape is easier to fabricate than a rectangle shape.

[0101] 25, the trenches 11 and the Schottky trenches 16 are preferably alternated. That is, the trenches 11 and the Schottky trenches 16 are arranged in a p + The type base layer 4 and the JFET region 14 are not provided on the same cross section in the direction in which they are aligned (the direction parallel to A-A' in FIG. 25). This allows the trench 11 and the Schottky trench 16 to be spaced apart, which can suppress localized heat generation and also facilitates miniaturization.

[0102] (Method for manufacturing a silicon carbide semiconductor device according to a seventh embodiment) The silicon carbide semiconductor device according to the seventh embodiment can be manufactured by using the method for manufacturing the silicon carbide semiconductor device according to the sixth embodiment, but by forming Schottky trench 16 in a rectangular shape.

[0103] As described above, according to the seventh embodiment, it is possible to obtain the same effects as those of the sixth embodiment. Furthermore, in the seventh embodiment, by making the Schottky trenches finer, it is possible to increase the area of ​​the Schottky junction more than in the sixth embodiment. Furthermore, by staggering the trenches and the Schottky trenches, it is possible to separate the trenches and the Schottky trenches, which makes it possible to suppress localized heat generation and further facilitates miniaturization.

[0104] In the above, in the fifth to seventh embodiments, an SBD is added to the first embodiment shown in FIGS. 1 to 3, but an SBD can also be added to the second to fourth embodiments. That is, in the second embodiment, in which the JFET region 14 is made up of the lower JFET region 14a and the upper JFET region 14b, a Schottky metal 15 can also be disposed on the surface of the JFET region 14. In addition, the interface between the lower JFET region 14a and the upper JFET region 14b can be formed by the n + n-type current diffusion layer 12 + In the third embodiment, which is deeper than the surface on the side of the silicon carbide substrate 1, the Schottky metal 15 can also be disposed on the surface of the JFET region 14. + In the fourth embodiment, in which the impurity concentration is the same as that of the current diffusion layer 12, the Schottky metal 15 can also be disposed on the surface of the JFET region .

[0105] Furthermore, in the fifth to seventh embodiments, n + The shape of the current diffusion layer 12 can be the shape shown in FIG. + The current spreading layer 12 is p - The width of the n-type electric field buffer layer 13 side is wide, + The width of the silicon carbide substrate 1 side may be narrower.

[0106] Although the above has been described using a MOSFET as an example of an embodiment, the present invention can also be applied to an IGBT in which a p-type region is provided on the back surface side of a silicon carbide semiconductor substrate. In this case, the resistance of the surface of the silicon carbide semiconductor substrate can be reduced by the injection enhancement effect (IE effect), enabling an IGBT with high breakdown voltage.

[0107] The present invention can be modified in various ways without departing from the spirit of the present invention. In each of the above-described embodiments, for example, the dimensions of each component and the impurity concentration are variously set according to the required specifications. Furthermore, while each of the above-described embodiments has been described using silicon carbide as the wide bandgap semiconductor, the present invention can also be applied to wide bandgap semiconductors other than silicon carbide, such as gallium nitride (GaN). Furthermore, the present invention can also be applied to semiconductors other than wide bandgap semiconductors, such as silicon (Si) and germanium (Ge). Furthermore, while each of the embodiments describes the first conductivity type as n-type and the second conductivity type as p-type, the present invention is equally valid even if the first conductivity type is p-type and the second conductivity type is n-type. [Industrial Applicability]

[0108] INDUSTRIAL APPLICABILITY As described above, the silicon carbide semiconductor device and method for manufacturing a silicon carbide semiconductor device according to the present invention are useful for power semiconductor devices used in power conversion devices such as inverters, power supply devices for various industrial machines, automobile igniters, and the like. [Explanation of symbols]

[0109] 1, 101 n + Silicon carbide substrate 3, 103 n - Silicon carbide epitaxial layer 4, 104 pages + Mold base layer 5, 105 Gate insulating film 6, 106 gate electrode 7, 107 pages + Mold contact area 8, 108 n + Type Source Area 9, 109 Interlayer insulating film 10, 110 Source electrode 11, 111 trenches 12, 112 n + Current diffusion layer 13, 113 p. - Type electric field relaxation layer 14, 114 JFET area 14a Lower JFET area 14b Upper JFET area 15 Schottky Metal 16 Schottky trench 30 Edge Termination Area 40 active area 50, 150, 151 vertical MOSFET

Claims

1. a semiconductor substrate of a first conductivity type; a first conductivity type second insulating film provided on the semiconductor substrate and having a lower impurity concentration than the semiconductor substrate; a semiconductor layer; a second semiconductor layer of a second conductivity type provided on the opposite side of the first semiconductor layer with respect to the semiconductor substrate; a first semiconductor region of a first conductivity type extending from a surface of the second semiconductor layer through the second semiconductor layer to reach the first semiconductor layer; a second semiconductor region of the first conductivity type selectively provided in a surface layer of the second semiconductor layer opposite to the first semiconductor layer and having a higher impurity concentration than the semiconductor substrate; a third semiconductor region of the first conductivity type selectively provided on a surface layer of the second semiconductor layer opposite to the first semiconductor layer, the third semiconductor region being spaced apart from the second semiconductor region and in contact with the first semiconductor region; a trench provided from the surface of the second semiconductor layer, sandwiched between the second semiconductor region and the third semiconductor region, and not reaching the first semiconductor layer; a gate insulating film provided from the first semiconductor region to the second semiconductor region and on an inner wall of the trench; a gate electrode provided on the gate insulating film; a fourth semiconductor region of the second conductivity type provided between the third semiconductor region and the gate electrode and in contact with an inner wall of the trench; an interlayer insulating film provided on the gate electrode; Equipped with a fourth semiconductor region covering the first semiconductor region, and a gate electrode separated by a region above the first semiconductor region;

2. 4. The width of the isolated region is greater than the thickness of the interlayer insulating film.

2. The semiconductor device according to claim 1.

3. the first semiconductor region comprises a lower first semiconductor region that is deeper than a surface of the third semiconductor region that faces the semiconductor substrate, and an upper first semiconductor region that is shallower than a surface of the third semiconductor region that faces the semiconductor substrate, 3. The semiconductor device according to claim 1, wherein the upper first semiconductor region has the same impurity concentration as the third semiconductor region and a higher impurity concentration than the lower first semiconductor region.

4. the first semiconductor region includes a lower first semiconductor region provided on the first semiconductor layer and an upper first semiconductor region provided on the lower first semiconductor region, an interface between the lower first semiconductor region and the upper first semiconductor region is deeper than a surface of the third semiconductor region on the semiconductor substrate side; 3. The semiconductor device according to claim 1, wherein the upper first semiconductor region has the same impurity concentration as the third semiconductor region and a higher impurity concentration than the lower first semiconductor region.

5. 3. The semiconductor device according to claim 1, wherein the first semiconductor region has the same impurity concentration as the third semiconductor region.

6. a first step of forming a first semiconductor layer of a first conductivity type on a semiconductor substrate of a first conductivity type, the first semiconductor layer having an impurity concentration lower than that of the semiconductor substrate; a second step of forming a second semiconductor layer of a second conductivity type on the opposite side of the first semiconductor layer with respect to the semiconductor substrate, and forming a first semiconductor region of the first conductivity type that penetrates the second semiconductor layer from a surface of the second semiconductor layer and reaches the first semiconductor layer; a third step of selectively forming a second semiconductor region of the first conductivity type having a higher impurity concentration than the semiconductor substrate in a surface layer of the second semiconductor layer opposite to the first semiconductor layer; a fourth step of selectively forming a third semiconductor region of the first conductivity type in a surface layer of the second semiconductor layer opposite to the first semiconductor layer, the third semiconductor region being spaced apart from the second semiconductor region and in contact with the first semiconductor region; a fifth step of forming a fourth semiconductor region of the second conductivity type in a surface layer of the third semiconductor region; a sixth step of forming a trench from the surface of the second semiconductor layer, the trench being sandwiched between the second semiconductor region and the third semiconductor region and not reaching the first semiconductor layer; a seventh step of forming a gate insulating film from the first semiconductor region to the second semiconductor region and forming the gate insulating film on an inner wall of the trench; an eighth step of forming a gate electrode on the gate insulating film; a ninth step of forming an interlayer insulating film on the gate electrode; Including, In the fifth step, the fourth semiconductor region is formed between the third semiconductor region and the gate electrode, in contact with an inner wall of the trench, and the fourth semiconductor region covers the first semiconductor region; a step of removing the gate electrode from a region above the first semiconductor region;

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