Semiconductor device and electronic system including the same

Abstract

To provide a semiconductor device in which reliability and integration are further improved.SOLUTION: There are provided a semiconductor device and an electronic system including the semiconductor device. The semiconductor device includes: a peripheral circuit integrated on a semiconductor substrate; a peripheral circuit structure containing a landing pad connected to the peripheral circuit; a semiconductor film arranged on the peripheral circuit structure; a metal structure which is connected to a part of the semiconductor film, includes a first part extended in a first direction, a second part coupled with the first part and extended in a second direction crossing the first direction, and a via part which are extended from at least one of the first part and the second part orthogonally and coupled to the landing pad; and a lamination structure including an insulation film and an electrode which are laminated on the metal structure while normally crossing with each other.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and an electronic system including the same. [Background technology]

[0002] Electronic systems requiring data storage require semiconductor devices capable of storing large amounts of data. Accordingly, methods for increasing the data storage capacity of semiconductor devices have been researched. For example, as one method for increasing the data storage capacity of semiconductor devices, a semiconductor device including memory cells arranged three-dimensionally instead of two-dimensionally has been proposed. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Patent No. 9,876,031 [Patent Document 2] U.S. Patent No. 9,985,048 Summary of the Invention [Problem to be solved by the invention]

[0004] One of the technical objects to be achieved by the technical idea of ​​the present invention is to provide a semiconductor device with improved reliability and integration density.

[0005] One of the technical problems that the technical idea of ​​the present invention aims to achieve is to provide an electronic system including a semiconductor device.

[0006] The problems to be solved by the present invention are not limited to those mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0007] In order to achieve the above-mentioned problem, a semiconductor device according to an embodiment of the present invention includes: a peripheral circuit structure including a semiconductor substrate, a peripheral circuit integrated on the semiconductor substrate, and a landing pad connected to the peripheral circuit; a semiconductor film disposed on the peripheral circuit structure; a metal structure in contact with a portion of the semiconductor film, the metal structure including a first portion extending in a first direction, a second portion connected to the first portion and extending in a second direction intersecting the first direction, and a via portion extending vertically from at least one of the first and second portions and connected to the landing pad; and a stacked structure including insulating films and electrodes stacked vertically and alternately on the metal structure.

[0008] In order to achieve the above-mentioned problem, a semiconductor device according to an embodiment of the present invention includes a peripheral circuit structure including a semiconductor substrate, a peripheral circuit integrated on the semiconductor substrate, and landing pads connected to the peripheral circuit; a semiconductor film disposed on the peripheral circuit structure; a first insulating pattern penetrating a portion of the semiconductor film and extending in a first direction; a metal structure in contact with a portion of the semiconductor film, the metal structure including a first portion extending in the first direction and a second portion connected to the first portion and extending in a second direction intersecting the first direction; and a stacked structure including insulating films and electrodes stacked vertically and alternately on the metal structure, wherein the second portion of the metal structure can cross the first insulating pattern.

[0009] In order to achieve the above object, a semiconductor device according to an embodiment of the present invention includes a peripheral circuit structure including a semiconductor substrate, a peripheral circuit integrated on the semiconductor substrate, and a landing pad connected to the peripheral circuit; a semiconductor film disposed on the peripheral circuit structure; a metal structure in contact with a portion of the semiconductor film, the metal structure including a second portion connected to the first portion and extending in a second direction intersecting the first direction, and a via portion extending vertically from at least one of the first and second portions and connected to the landing pad; a stacked structure including insulating films and electrodes stacked vertically and alternately on the metal structure; a vertical semiconductor pattern penetrating the stacked structure; and a source structure provided between the semiconductor film and the stacked structure, the source structure being provided in order on the semiconductor film. the first source conductive pattern may include a source structure contacting a portion of a sidewall of the vertical semiconductor pattern; a data storage pattern between the vertical semiconductor pattern and the stacked structure; a first insulation pattern penetrating the semiconductor film under the stacked structure; a first pad pattern provided in the first insulation pattern and electrically connected to the peripheral circuit; a second pad pattern disposed spaced apart from the stacked structure and the semiconductor film and electrically connected to the peripheral circuit; a first via plug penetrating the stacked structure and connected to the first pad pattern; a second via plug spaced apart from the stacked structure and connected to the second pad pattern; and a third via plug spaced apart from the stacked structure and connected to the metal structure.

[0010] In order to achieve the above-mentioned problem, an electronic system according to an embodiment of the present invention may include a semiconductor device including: a peripheral circuit integrated on a semiconductor substrate; a peripheral circuit structure including landing pads connected to the peripheral circuit; a semiconductor film disposed on the peripheral circuit structure; a metal structure in contact with a portion of the semiconductor film, the metal structure including a first portion extending in a first direction, a second portion connected to the first portion and extending in a second direction intersecting the first direction, and a via portion extending vertically from at least one of the first and second portions and connected to the landing pad; a stacked structure including insulating films and electrodes stacked vertically and alternately on the metal structure; and input / output pads electrically connected to the peripheral circuit; and a controller electrically connected to the semiconductor device through the input / output pads and configured to control the semiconductor device.

[0011] Specific details of other embodiments are included in the detailed description and drawings. [Effects of the Invention]

[0012] According to an embodiment of the present invention, since a metal structure in contact with a semiconductor film is provided, when a current is generated through the semiconductor film, the resistance of the semiconductor film increases due to the first and second insulating patterns provided in the semiconductor film, which reduces the decrease in operating speed. That is, since a high-speed current path can be formed through the semiconductor film and the metal structure between the via plug and the vertical structure, the electrical characteristics and reliability of the semiconductor device can be improved.

[0013] According to the embodiment, the first, second, and third pad patterns and the metal structure MRS are provided at the same level, which facilitates the process of forming the first to fourth via plugs connected thereto. [Brief explanation of the drawings]

[0014] [Figure 1] 1 is a diagram schematically illustrating an electronic system including a semiconductor device according to an exemplary embodiment of the present invention; [Figure 2] 1 is a perspective view schematically illustrating an electronic system including a semiconductor device according to an exemplary embodiment of the present invention. [Figure 3] 1 is a cross-sectional view schematically illustrating a semiconductor package according to an exemplary embodiment of the present invention. [Figure 4] 1 is a cross-sectional view schematically illustrating a semiconductor package according to an exemplary embodiment of the present invention. [Figure 5] 1 is a plan view of a semiconductor device according to an exemplary embodiment of the present invention; [Figure 6] 1 is a plan view showing a semiconductor film, a metal structure, and a pad pattern of a semiconductor device according to an exemplary embodiment of the present invention; [Figure 7] 1 is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the present invention; [Figure 8] 1 is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the present invention; [Figure 9] 1 is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the present invention; [Figure 10] 1A-1D are enlarged views illustrating various examples of semiconductor devices according to exemplary embodiments of the present invention. [Figure 11] 1A-1C are enlarged views illustrating various examples of semiconductor devices according to exemplary embodiments of the present invention. [Figure 12] 1A-1D are enlarged views illustrating various examples of semiconductor devices according to exemplary embodiments of the present invention. [Figure 13] 1A-1D are enlarged views illustrating various examples of semiconductor devices according to exemplary embodiments of the present invention. [Figure 14] 1A-1D are enlarged views illustrating various examples of semiconductor devices according to exemplary embodiments of the present invention. [Figure 15] 1 is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the present invention; [Figure 16] 1 is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the present invention; [Figure 17] 1 is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the present invention; [Figure 18]1A-1D are enlarged views illustrating various examples of semiconductor devices according to exemplary embodiments of the present invention. [Figure 19] 1 is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the present invention; [Figure 20] 1 is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the present invention; [Figure 21] 1 is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the present invention; [Figure 22] 1A-1D are enlarged views illustrating various examples of semiconductor devices according to exemplary embodiments of the present invention. [Figure 23] 1 is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the present invention; [Figure 24] 1 is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the present invention; [Figure 25] 1 is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the present invention; [Figure 26] 1A-1D are enlarged views illustrating various examples of semiconductor devices according to exemplary embodiments of the present invention. [Figure 27A] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment of the present invention. [Figure 27B] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment of the present invention. [Figure 28A] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment of the present invention. [Figure 28B] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment of the present invention. [Figure 29A] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment of the present invention. [Figure 29B] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment of the present invention. [Figure 30A] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment of the present invention. [Figure 30B]1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment of the present invention. [Figure 31A] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment of the present invention. [Figure 31B] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment of the present invention. [Figure 32A] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment of the present invention. [Figure 32B] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment of the present invention. [Figure 33A] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment of the present invention. [Figure 33B] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment of the present invention. [Figure 34A] 1A to 1C are cross-sectional views illustrating methods for manufacturing a semiconductor device according to various embodiments of the present invention. [Figure 34B] 1A to 1C are cross-sectional views illustrating methods for manufacturing a semiconductor device according to various embodiments of the present invention. [Figure 35A] 1A to 1C are cross-sectional views illustrating methods for manufacturing a semiconductor device according to various embodiments of the present invention. [Figure 35B] 1A to 1C are cross-sectional views illustrating methods for manufacturing a semiconductor device according to various embodiments of the present invention. [Figure 36A] 1A to 1C are cross-sectional views illustrating methods for manufacturing a semiconductor device according to various embodiments of the present invention. [Figure 36B] 1A to 1C are cross-sectional views illustrating methods for manufacturing a semiconductor device according to various embodiments of the present invention. [Figure 37A] 1A to 1C are cross-sectional views illustrating methods for manufacturing a semiconductor device according to various embodiments of the present invention. [Figure 37B] 1A to 1C are cross-sectional views illustrating methods for manufacturing a semiconductor device according to various embodiments of the present invention. [Figure 38A]1A to 1C are cross-sectional views illustrating methods for manufacturing a semiconductor device according to various embodiments of the present invention. [Figure 38B] 1A to 1C are cross-sectional views illustrating methods for manufacturing a semiconductor device according to various embodiments of the present invention. [Figure 39A] 1A to 1C are cross-sectional views illustrating methods for manufacturing a semiconductor device according to various embodiments of the present invention. [Figure 39B] 1A to 1C are cross-sectional views illustrating methods for manufacturing a semiconductor device according to various embodiments of the present invention. [Figure 40A] 1A to 1C are cross-sectional views illustrating methods for manufacturing a semiconductor device according to various embodiments of the present invention. [Figure 40B] 1A to 1C are cross-sectional views illustrating methods for manufacturing a semiconductor device according to various embodiments of the present invention. [Figure 41A] 1A to 1C are cross-sectional views illustrating methods for manufacturing a semiconductor device according to various embodiments of the present invention. [Figure 41B] 1A to 1C are cross-sectional views illustrating methods for manufacturing a semiconductor device according to various embodiments of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0015] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0016] FIG. 1 is a diagram schematically illustrating an electronic system including a semiconductor device according to an exemplary embodiment of the present invention.

[0017] 1, an electronic system 1000 according to an exemplary embodiment of the present invention may include a semiconductor device 1100 and a controller 1200 electrically coupled to the semiconductor device 1100. The electronic system 1000 may be a storage device including one or more semiconductor devices 1100 or an electronic device including a storage device. For example, the electronic system 1000 may be a solid state drive device (SSD), a Universal Serial Bus (USB), a computing system, a medical device, or a communication device including one or more semiconductor devices 1100.

[0018] The semiconductor device 1100 is a nonvolatile memory device and may be a NAND flash memory device. The semiconductor device 1100 may include a first structure 1100F and a second structure 1100S on the first structure 1100F. In an exemplary embodiment, the first structure 1100F may be disposed beside the second structure 1100S. The first structure 1100F may be a peripheral circuit structure including a decoder circuit 1110, a page buffer 1120, and a logic circuit 1130. The second structure 1100S is a memory cell structure including a bit line BL, a common source line CSL, a word line WL, first and second gate upper lines UL1 and UL2, first and second gate lower lines LL1 and LL2, and a memory cell string CSTR between the bit line BL and the common source line CSL.

[0019] In the second structure 1100S, each memory cell string CSTR may include lower transistors LT1 and LT2 adjacent to a common source line CSL, upper transistors UT1 and UT2 adjacent to a bit line BL, and a plurality of memory cell transistors MCT disposed between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. The number of lower transistors LT1 and LT2 and the number of upper transistors UT1 and UT2 may vary depending on the embodiment.

[0020] In an exemplary embodiment, the upper transistors UT1 and UT2 may comprise string select transistors, and the lower transistors LT1 and LT2 may comprise ground select transistors. The lower gate lines LL1 and LL2 may be gate electrodes of the lower transistors LT1 and LT2, respectively. The word line WL may be the gate electrode of the memory cell transistor MCT, and the upper gate lines UL1 and UL2 may be gate electrodes of the upper transistors UT1 and UT2, respectively.

[0021] In an exemplary embodiment, the lower transistors LT1 and LT2 may include a lower erase control transistor LT1 and a ground selection transistor LT2 connected in series. The upper transistors UT1 and UT2 may include a string selection transistor UT1 and an upper erase control transistor UT2 connected in series. At least one of the lower erase control transistor LT1 and the upper erase control transistor UT2 may be used in an erase operation that erases data stored in the memory cell transistor MCT using a gate-induced drain leakage (GIDL) phenomenon.

[0022] The common source line CSL, the first and second gate lower lines LL1 and LL2, the word line WL, and the first and second gate upper lines UL1 and UL2 may be electrically connected to the decoder circuit 1110 through a first connecting line 1115 extending from the first structure 1100F to the second structure 1100S. The bit line BL may be electrically connected to the page buffer 1120 through a second connecting line 1125 extending from the first structure 1100F to the second structure 1100S.

[0023] In the first structure 1100F, the decoder circuit 1110 and the page buffer 1120 can perform a control operation on at least one selected memory cell transistor among the plurality of memory cell transistors MCT. The decoder circuit 1110 and the page buffer 1120 can be controlled by a logic circuit 1130. The semiconductor device 1100 can communicate with the controller 1200 through an input / output pad 1101 electrically connected to the logic circuit 1130. The input / output pad 1101 can be electrically connected to the logic circuit 1130 through an input / output connecting wiring 1135 extending from within the first structure 1100F to the second structure 1100S.

[0024] The controller 1200 may include a processor 1210, a NAND controller 1220, and a host interface 1230. Depending on the embodiment, the electronic system 1000 may include multiple semiconductor devices 1100, in which case the controller 1200 may control multiple semiconductor devices 1000.

[0025] The processor 1210 can control the overall operation of the electronic system 1000, including the controller 1200. The processor 1210 can operate according to predetermined firmware and can control the NAND controller 1220 to access the semiconductor device 1100. The NAND controller 1220 can include a NAND interface 1221 that handles communication with the semiconductor device 1100. Control commands for controlling the semiconductor device 1100, data to be stored in the memory cell transistors MCT of the semiconductor device 1100, data to be read from the memory cell transistors MCT of the semiconductor device 1100, etc. can be transmitted through the NAND interface 1221. The host interface 1230 can provide a communication function between the electronic system 1000 and an external host. When a control command is received from the external host through the host interface 1230, the processor 1210 can control the semiconductor device 1100 in response to the control command.

[0026] FIG. 2 is a perspective view schematically illustrating an electronic system including a semiconductor device according to an exemplary embodiment of the present invention.

[0027] 2, an electronic system 2000 according to an exemplary embodiment of the present invention may include a main substrate 2001, a controller 2002 mounted on the main substrate 2001, one or more semiconductor packages 2003, and a DRAM 2004. The semiconductor packages 2003 and the DRAM 2004 may be connected to the controller 2002 by a wiring pattern 2005 formed on the main substrate 2001.

[0028] The main board 2001 may include a connector 2006 including a plurality of pins coupled to an external host. The number and arrangement of the pins in the connector 2006 may vary depending on the communication interface between the electronic system 2000 and the external host. In an exemplary embodiment, the electronic system 2000 may communicate with the external host using any one of interfaces such as Universal Serial Bus (USB), Peripheral Component Interconnect Express SS (PCI-ExprSS), Serial Advanced Technology Attachment (SATA), and M-Phy for Universal Flash Storage (UFS). In an exemplary embodiment, the electronic system 2000 may operate using power supplied from the external host through the connector 2006. The electronic system 2000 may further include a Power Management Integrated Circuit (PMIC) that distributes power supplied from the external host to the controller 2002 and the semiconductor package 2003.

[0029] The controller 2002 can read data to or from the semiconductor package 2003, which can improve the operating speed of the electronic system 2000.

[0030] The DRAM 2004 may be a buffer memory for mitigating the difference in speed between the semiconductor package 2003, which is a data storage space, and an external host. The DRAM 2004 included in the electronic system 2000 may also operate as a type of cache memory and may provide space for temporarily storing data in a control operation for the semiconductor package 2003. When the electronic system 2000 includes the DRAM 2004, the controller 2002 may further include a DRAM controller for controlling the DRAM 2004 in addition to a NAND controller for controlling the semiconductor package 2003.

[0031] The semiconductor package 2003 may include first and second semiconductor packages 2003a and 2003b spaced apart from each other. The first and second semiconductor packages 2003a and 2003b may each include a plurality of semiconductor chips 2200. Each of the first and second semiconductor packages 2003a and 2003b may include a package substrate 2100, a semiconductor chip 2200 on the package substrate 2100, an adhesive layer 2300 disposed on a lower surface of each semiconductor chip 2200, a connecting structure 2400 electrically connecting the semiconductor chip 2200 and the package substrate 2100, and a molding layer 2500 covering the semiconductor chip 2200 and the connecting structure 2400 on the package substrate 2100.

[0032] The package substrate 2100 may be a printed circuit board including package top pads 2130. Each semiconductor chip 2200 may include input / output pads 2210. The input / output pads 2210 may correspond to the input / output pads 1101 in FIG. 1. Each semiconductor chip 2200 may include a stacked structure 3210 and a vertical structure 3220. Each semiconductor chip 2200 may include a semiconductor device according to an embodiment of the present invention, as described below.

[0033] In an exemplary embodiment, the connecting structure 2400 may be a bonding wire that electrically connects the I / O pad 2210 and the package upper pad 2130. Therefore, in each of the first and second semiconductor packages 2003a and 2003b, the semiconductor chips 2200 may be electrically connected to each other by a bonding wire method and may be electrically connected to the package upper pad 2130 of the package substrate 2100. According to an embodiment, in each of the first and second semiconductor packages 2003a and 2003b, the semiconductor chips 2200 may be electrically connected to each other by a connecting structure including a through silicon via (TSV), instead of the connecting structure 2400 using a bonding wire method.

[0034] In an exemplary embodiment, the controller 2002 and the semiconductor chip 2200 may be included in one package. In an exemplary embodiment, the controller 2002 and the semiconductor chip 2200 may be mounted on an interposer substrate separate from the main substrate 2001, and the controller 2002 and the semiconductor chip 2200 may be connected to each other by wiring formed on the interposer substrate.

[0035] 3 and 4 are cross-sectional views schematically illustrating a semiconductor package according to an exemplary embodiment of the present invention, each illustrating an exemplary embodiment of the semiconductor package 2003 of FIG. 2 and conceptually illustrating a region obtained by cutting the semiconductor package 2003 of FIG. 2 along cutting line II'.

[0036] 3, in the semiconductor package 2003, the package substrate 2100 may be a printed circuit board. The package substrate 2100 may include a package substrate body 2120, package upper pads (2130 in FIG. 2) disposed on the upper surface of the package substrate body 2120, lower pads 2125 disposed on the lower surface of the package substrate body 2120 or exposed through the lower surface, and internal wiring 2135 electrically connecting the upper pads 2130 and the lower pads 2125 inside the package substrate body 2120. The upper pads 2130 may be electrically connected to a connecting structure 2400. The lower pads 2125 may be connected to a wiring pattern 2005 of a main board 2010 of the electronic system 2000 via a conductive connecting portion 2800, as shown in FIG. 2.

[0037] Each of the semiconductor chips 2200 may include a semiconductor substrate 3010 and a first structure 3100 and a second structure 3200 stacked in order on the semiconductor substrate 3010. The first structure 3100 may include a peripheral circuit region including peripheral wiring 3110. The second structure 3200 may include a source structure 3205, a stacked structure 3210 on the source structure 3205, a vertical structure 3220 and an isolation structure 3230 penetrating the stacked structure 3210, a bit line 3240 electrically connected to the vertical structure 3220, and a cell contact plug 3235 electrically connected to a word line (WL in FIG. 1) of the stacked structure 3210. Each of the first structure 3100, the second structure 3200, and the semiconductor chip 2200 may further include a metal structure, which will be described later.

[0038] Each of the semiconductor chips 2200 may include through wiring 3245 electrically connected to the peripheral wiring 3110 of the first structure 3100 and extending into the second structure 3200. The through wiring 3245 may be disposed outside the stacked structure 3210, or may be further disposed to penetrate the stacked structure 3210. Each of the semiconductor chips 2200 may further include input / output pads (2210 in FIG. 2) electrically connected to the peripheral wiring 3110 of the first structure 3100.

[0039] Referring to FIG. 4, in the semiconductor package 2003a, each of the semiconductor chips 2200a may include a semiconductor substrate 4010, a first structure 4100 on the semiconductor substrate 4010, and a second structure 4200 bonded to the first structure 4100 on the first structure 4100 using a wafer bonding method.

[0040] The first structure 4100 may include a peripheral circuit region including peripheral wiring 4110 and a first junction structure 4150. The second structure 4200 may include a source structure 4205, a stack structure 4210 between the source structure 4205 and the first structure 4100, a vertical structure 4220 and an isolation structure 4230 penetrating the stack structure 4210, and a second junction structure 4250 electrically connected to the vertical structure 4220 and the word line (WL in FIG. 1) of the stack structure 4210. For example, the second junction structure 4250 may be electrically connected to the vertical structure 4220 and the word line (WL in FIG. 1) through a cell contact plug 4235 electrically connected to the bit line 4240 and the word line (WL in FIG. 1) electrically connected to the vertical structure 4220, respectively. The first junction structure 4150 of the first structure 4100 and the second junction structure 4250 of the second structure 4200 may be bonded while being in contact with each other. The bonded portions of the first junction structure 4150 and the second junction structure 4250 may be made of copper (Cu).

[0041] Each of the first structure 4100, the second structure 4200, and the semiconductor chip 2200a may further include a metal structure according to an embodiment described below. Each of the semiconductor chips 2200a may further include an input / output pad (2210 in FIG. 2) electrically connected to the peripheral wiring 4110 of the first structure 4100.

[0042] The semiconductor chip 2200 of Fig. 3 and the semiconductor chip 2200a of Fig. 4 may be electrically connected to each other by a bonding wire-type connecting structure 2400. However, in an exemplary embodiment, semiconductor chips within one semiconductor package, such as the semiconductor chip 2200 of Fig. 3 and the semiconductor chip 2200a of Fig. 4, may be electrically connected to each other by a connecting structure including a through-silicon via TSV.

[0043] The first structure 3100 in FIG. 3 and the first structure 4100 in FIG. 4 may correspond to a peripheral circuit structure in the embodiments described below, and the second structure 3200 in FIG. 3 and the second structure 4200 in FIG. 4 may correspond to a cell array structure in the embodiments described below.

[0044] FIG. 5 is a plan view of a semiconductor device according to an exemplary embodiment of the present invention. FIG. 6 is a plan view showing a semiconductor film, a metal structure, and a pad pattern of a semiconductor device according to an exemplary embodiment of the present invention. FIGS. 7, 8, and 9 are cross-sectional views of a semiconductor device according to an exemplary embodiment of the present invention, taken along lines A-A', B-B', and C-C' in FIG. 5. FIGS. 10 and 11 are enlarged views of a portion P1 in FIG. 7, FIG. 12 is an enlarged view of a portion P2 in FIG. 8, FIG. 13 is an enlarged view of a portion P3 in FIG. 9, and FIG. 14 is an enlarged view of a portion P4 in FIG. 9.

[0045] 5, 7, 8, and 9, a semiconductor device according to an embodiment of the present invention may include a peripheral circuit structure PS and a cell array structure CS on the peripheral circuit structure PS.

[0046] The peripheral circuit structure PS may include a peripheral circuit PTR integrated on the entire surface of the semiconductor substrate 10 and a lower insulating film 50 covering the peripheral circuit PTR.

[0047] The semiconductor substrate 10 may include a cell array region CAR and first and second connection regions CNR1 and CNR2, and the first connection region CNR1 may be located between the cell array region CAR and the second connection region CNR2 in a first direction D1. The semiconductor substrate 10 may be a silicon substrate.

[0048] The peripheral circuit PTR may include row and column decoders, a page buffer, and a control circuit. More specifically, the peripheral circuit PTR may include NMOS and PMOS transistors. The peripheral circuit wiring may be electrically connected to the peripheral circuit PTR through peripheral contact plugs.

[0049] A lower insulating film 50 may be provided on the entire surface of the semiconductor substrate 10. The lower insulating film 50 may cover the peripheral circuit PTR, peripheral contact plugs, peripheral circuit wiring, and landing pads PLP on the semiconductor substrate 10. The peripheral contact plugs, peripheral circuit wiring, and landing pads PLP may be electrically connected to the peripheral circuit PTR.

[0050] The lower insulating film 50 may include multiple insulating films. For example, the lower insulating film 50 may include a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and / or a low dielectric film. As an example, the lower insulating film 50 may include a first lower insulating film 51, a second lower insulating film 55, and an etch stop film 53 between the first and second lower insulating films 51 and 55. The etch stop film 53 may include an insulating material different from that of the first and second lower insulating films 51 and 55 and may cover the upper surface of the landing pad PLP.

[0051] A cell array structure CS may be disposed on the lower insulating film 50. The cell array structure CS may include a semiconductor film 100, a metal structure MRS, a source structure CST, a stack structure ST, a vertical structure VS, cell contact plugs CPLG, through plugs TP1 to TP4, bit lines BL, and conductive lines CL. According to the embodiment, the cell string illustrated in FIG. 1 (CSTR of FIG. 1) may be integrated on the semiconductor film 100. The stack structure ST and the vertical structure VS may constitute the cell string illustrated in FIG. 1 (CSTR of FIG. 1).

[0052] The semiconductor film 100 may be disposed on the upper surface of the lower insulating film 50. The semiconductor film 100 may be made of a semiconductor material, an insulating material, or a conductive material. The semiconductor film 100 may include a semiconductor doped with a dopant having a first conductivity type (e.g., n-type) and / or an intrinsic semiconductor that is not doped with impurities. The semiconductor film 100 may have a crystalline structure including at least one selected from single crystal, amorphous, and polycrystalline.

[0053] The source structure CST may include a source conductive pattern SC and a support conductive pattern SP on the source conductive pattern SC. The source structure CST may be parallel to the top surface of the semiconductor film 100 and may extend in the first direction D1 alongside the stack structure ST in the cell array region CAR.

[0054] The source conductive pattern SC may be made of a semiconductor material doped with a dopant having a first conductivity type (e.g., phosphorus (P) or arsenic (As)). For example, the source conductive pattern may be made of a semiconductor film 100 doped with an N-type dopant.

[0055] The support conductive pattern SP may cover the top surface of the source conductive pattern SC and may include a semiconductor doped with a dopant having a first conductivity type (e.g., n-type) and / or an intrinsic semiconductor not doped with impurities. A portion of the support conductive pattern SP may contact the semiconductor film 100 through the source conductive pattern SC in the cell array region CAR.

[0056] A buried insulating film 110 may be disposed in the second connection region CNR2, covering the sidewalls of the semiconductor film 100 and the sidewalls of the source structures CST. The buried insulating film 110 may have an upper surface that is substantially coplanar with an upper surface of the source structures CST.

[0057] In the first connection region CNR1, a first insulating pattern 111 may be provided in a first through hole TOP1 penetrating the source structure CST and the semiconductor layer 100. In the cell array region CAR, a second insulating pattern 113 may be provided in a second through hole TOP2 penetrating the source structure CST and the semiconductor layer 100. The second insulating pattern 113 may extend in a first direction D1. The first and second insulating patterns 111 and 113 may have top surfaces that are substantially coplanar with the top surface of the source structure CST.

[0058] The stacked structure ST may include electrodes GE and insulating films ILD alternately stacked along a third direction (D3; i.e., a vertical direction) perpendicular to the first and second directions D1 and D2 intersecting each other. The electrodes GE may include at least one selected from, for example, a doped semiconductor (e.g., doped silicon), a metal (e.g., tungsten, copper, aluminum), a conductive metal nitride (e.g., titanium nitride, tantalum nitride), or a transition metal (e.g., titanium, tantalum), etc. The insulating films ILD may include a silicon oxide film and / or a low-k film. According to an embodiment, the semiconductor device is a vertical NAND flash memory device. In this case, the electrodes GE of the stacked structure ST may be used as the lower gate lines LL1 and LL2, the word lines WL, and the upper gate lines UL1 and UL2 described with reference to FIG. 1.

[0059] Each of the electrodes GE may include a pad portion in the first connection region CNR1. As an example, the pad portion of the 4n-th electrode GE (n is a positive integer) among the electrodes GE of the stacked structure ST may be arranged along the first direction D1. Sidewalls of the 4n-th, 4n-2, and 4n-3-th electrodes GE may be aligned with the sidewall of the 4n-th electrode GE. The cell contact plug CPLG may be connected to the pad portion of the 4n-th electrode GE. Alternatively, the pad portions of the even-numbered or odd-numbered electrodes GE among the electrodes GE of the stacked structure ST may be arranged along the first direction D1, and the cell contact plug CPLG may be connected to the pad portion of the even-numbered electrode GE. As another example, the pad portions of the electrodes GE may be positioned at different positions horizontally and vertically.

[0060] According to the embodiment, the stacked structure ST may include a first mold pattern MP1 located at the same level as the electrodes GE in the first connection region CNR1 and disposed between the insulating layers ILD. The first mold pattern MP1 may be closer to the cell array region CAR than a pad portion of the electrodes GE. The first mold pattern MP1 may overlap the first insulating pattern 111 in a plan view. The stacked structure ST may also include a second mold pattern MP2 located at the same level as the electrodes GE in the cell array region CAR and disposed between the insulating layers ILD. The second mold pattern MP2 may extend in the first direction D1 and overlap the second insulating pattern 113. The first and second mold patterns MP1 and MP2 may include an insulating material having etch selectivity with respect to the insulating layer ILD.

[0061] A plurality of vertical structures VS may penetrate the stacked structure ST in the cell array region CAR. Each of the vertical structures VS may include a lower vertical structure penetrating a lower region of the stacked structure ST and an upper vertical structure penetrating an upper region of the stacked structure ST.

[0062] 14, each vertical structure VS may include a vertical semiconductor pattern VP and a data storage pattern DSP surrounding the sidewall of the vertical semiconductor pattern. Specifically, the vertical semiconductor pattern VP may have a pipe shape or a macaroni shape with a closed bottom. The vertical semiconductor pattern VP may have a U-shape and may be filled with an insulating material. The vertical semiconductor pattern VP may include a semiconductor material such as silicon (Si), germanium (Ge), or a mixture thereof. The vertical semiconductor pattern VP including the semiconductor material may be used as the channels of the upper transistors UT1 and UT2, memory cell transistor MCT, and lower transistors LT1 and LT2 described with reference to FIG. 1.

[0063] The data storage patterns DSP may extend in the third direction D3 and surround the sidewalls of each vertical semiconductor pattern VP. The data storage patterns DSP may have a pipe or macaroni shape with open top and bottom ends. The data storage patterns DSP may be formed of one thin film or multiple thin films. In this embodiment, the data storage patterns DSP may include a tunnel insulating film TIL, a charge storing film CIL, and a blocking insulating film BIL, which are sequentially stacked on the sidewalls of the vertical semiconductor patterns VP as a data storage film of the NAND flash memory device. The charge storing film SN may be a trap insulating film, a floating gate electrode, or an insulating film including conductive nanodots. In addition, dummy data storage patterns RDSP may be disposed in the semiconductor film 100, vertically spaced apart from the data storage patterns DSP. The dummy data storage patterns RDSP may have the same thin film structure as the data storage patterns DSP.

[0064] A horizontal insulating pattern HP may be provided between one sidewall of the electrode GE and the data storage pattern DSP, and may extend on the one sidewall of the electrode GE to its upper and lower surfaces.

[0065] A portion of the sidewall of the vertical semiconductor pattern VP of each vertical structure VS may be in contact with the source conductive pattern SC. The bottom surface of the data storage pattern DSP of each vertical structure VS may be located at a level lower than the bottom surface of the bottom electrode GE and higher than the top surface of the source conductive pattern SC.

[0066] 5, 7, 8, and 9, a planar insulating film 120 may cover the pad portion of the stepped stack structure ST. The planar insulating film 120 may have a substantially flat upper surface. The planar insulating film 120 may include one insulating film or a plurality of stacked insulating films. First to fourth interlayer insulating films 130, 140, 150, and 160 may be sequentially stacked on the planar insulating film 120.

[0067] First and second isolation structures SS1 and SS2 may penetrate the stacked structure ST on the semiconductor film 100. The first isolation structure SS1 may extend in the first connecting region CNR1 in the cell array region CAR along a first direction D1 and be spaced apart in a second direction D2 intersecting the first direction D1. The second isolation structures SS2 may penetrate the stacked structure ST in the cell array region CAR. The second isolation structures SS2 may be disposed between the first isolation structures SS1. The length of the second isolation structures SS2 in the first direction D1 may be smaller than the length of the first isolation structures SS1. As another example, a plurality of second isolation structures SS2 may be provided between the first isolation structures SS1. Each of the first and second isolation structures SS1 and SS2 may include an insulating film covering a sidewall of the stacked structure ST.

[0068] The third isolation structure SS3 may be spaced apart from the first and second isolation structures SS1 and SS2 in the first connection region CNR1 and may penetrate the planar insulating film 120 and the stack structure ST. The third isolation structure SS3 may extend along the first direction D1.

[0069] In the cell array region CAR, a memory block BLK may be defined between a pair of adjacent first isolation structures SS1. The memory block BLK may be composed of a stack structure ST and a vertical structure VS. A plurality of the memory blocks BLK may be arranged along the second direction D2. A dummy memory block DBLK may be provided between adjacent memory blocks BLK in the second direction D2. The dummy memory block DBLK includes a stack structure ST and a vertical structure VS similar to the memory blocks BLK, and the stack structure ST of the dummy memory block DBLK may include a second mold pattern MP2 in the cell array region CAR.

[0070] According to the embodiment, a first pad pattern LP1 may be disposed in the first insulating pattern 111 and electrically connected to the landing pad PLP of the peripheral circuit structure PS. A second pad pattern LP2 may be disposed in the second insulating pattern 113 and connected to the landing pad PLP of the peripheral circuit structure PS. A third pad pattern LP3 may be disposed in the buried insulating film 110, spaced apart from the stack structure ST and the semiconductor film 100. The third pad pattern LP3 may be electrically connected to the landing pad PLP of the peripheral circuit structure PS.

[0071] 10, the first pad pattern LP1 may include a via portion that vertically penetrates the first insulation pattern 111, the second lower insulation film 55, and the etch stop film 53 and is connected to the landing pad PLP, and a pad portion that is connected to the via portion and is located in the first insulation pattern. The first pad pattern LP1 may include a first metal pattern ME1 and a first barrier metal pattern BM1 that surrounds sidewalls and a bottom surface of the first metal pattern ME1.

[0072] 12, the second pad pattern LP2 may include a via portion that vertically penetrates the first insulation pattern 113, the second lower insulation film 55, and the etch stop film 53 and is connected to the landing pad PLP, and a pad portion that is connected to the via portion and is located in the second insulation pattern 113. The second pad pattern LP2 may include a second metal pattern ME2 and a second barrier metal pattern BM2 that surrounds sidewalls and a bottom surface of the second metal pattern ME2.

[0073] 10, the third pad pattern LP3 may include a via portion that vertically penetrates the buried insulating layer 110, the second lower insulating layer 55, and the etch stop layer 53 and is connected to the landing pad PLP, and a pad portion that is connected to the via portion and is located in the buried insulating layer 110. The third pad pattern LP3 may include a third metal pattern ME3 and a third barrier metal pattern BM3 that surrounds sidewalls and a bottom surface of the third metal pattern ME3.

[0074] The top surfaces of the first, second, and third pad patterns LP1, LP2, and LP3 may be located at substantially the same level. For example, the top surfaces of the first, second, and third pad patterns LP1, LP2, and LP3 may be substantially coplanar with the top surface of the support conductive pattern SP.

[0075] The first, second, and third barrier metal patterns BM1, BM2, and BM3 may include the same metal material, and the first, second, and third metal patterns ME1, ME2, and ME3 may include the same metal material. The first, second, and third barrier metal patterns BM1, BM2, and BM3 may include, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, cobalt, manganese, tungsten nitride, nickel, nickel boride, or a bilayer or a mixed layer of a different type from a bilayer, such as titanium / titanium nitride. The first, second, and third metal patterns ME1, ME2, and ME3 may include titanium, tantalum, ruthenium, cobalt, manganese, tungsten, nickel, or copper.

[0076] 5, 6, 7, 8 and 9, a metal structure MRS may be provided between the semiconductor film 100 and the source structure CST and in contact with a portion of the semiconductor film 100.

[0077] The metal structure MRS may include a first portion R1 extending in a first direction D1 in the cell array region CAR and the first connection region CNR1, and second portions R2 and R3 connected to the first portion R1 and extending in a second direction D2 intersecting the first direction D1. Here, the second portions R2 and R3 may include a first region R2 connected to a pair of adjacent first portions R1 in the cell array region CAR and crossing the second insulating pattern 113, and a second region R3 connecting the first portions to each other in the first connection region CNR1. The first and second portions R1, R2, and R3 of the metal structure MRS may overlap with the stack structure ST in a plan view.

[0078] The metal structure MRS may further include a pad portion R4 extending from the second region R3 of the second portion in the first direction D1. The metal structure MRS may further include at least one fifth portion R5 extending in the first direction D1 under the memory block BLK.

[0079] Furthermore, the metal structure MRS may include a via portion extending vertically from at least one of the first and second portions R1, R2, and R3 and connected to the landing pad PLP. The via portion of the metal structure MRS may be laterally spaced apart from the semiconductor film 100 and may be connected to each pad portion R4 of the metal structure MRS.

[0080] 10, 12, and 13, the metal structure MRS may have a substantially flat upper surface. For example, the upper surface of the metal structure MRS may be located at substantially the same level as the upper surface of the source structure CST, i.e., the upper surface of the support conductive pattern SP. In addition, the upper surface of the metal structure MRS may be substantially coplanar with the upper surfaces of the first to third pad patterns LP1, LP2, and LP3.

[0081] A sidewall of the metal structure MRS may be in contact with the source structure CST. A portion of the metal structure MRS may be in direct contact with the buried insulating film 110 and the second insulating pattern 113. The metal structure MRS may have a first thickness in the third direction D3 on the semiconductor film 100 and a second thickness on the buried insulating film 110 and the second insulating pattern 113 that is greater than the first thickness.

[0082] 11, the metal structure MRS may have a protruding portion PP in a region where the buried insulating film 110 contacts the semiconductor film 100. The protruding portion PP may have a non-uniform thickness.

[0083] 10, 12, and 13, the metal structure MRS may include a fourth barrier metal pattern BM4 and a fourth metal pattern ME4. The fourth barrier metal pattern BM4 may surround the bottom and sidewalls of the fourth metal pattern ME4. The fourth barrier metal pattern BM4 may include, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, cobalt, manganese, tungsten nitride, nickel, nickel boride, or a bilayer or a mixed layer having a different form from the bilayer, such as titanium / titanium nitride. The fourth metal pattern ME4 may include titanium, tantalum, ruthenium, cobalt, manganese, tungsten, nickel, or copper.

[0084] The fourth barrier metal pattern BM4 may include the same metal material as the first, second, and third barrier metal patterns BM1, BM2, and BM3, and the fourth metal pattern ME4 may include the same metal material as the first, second, and third metal patterns ME1, ME2, and ME3.

[0085] Furthermore, the metal structure MRS may further include a metal-semiconductor compound layer MSC between the semiconductor film 100 and a portion of the metal structure MRS, and between the source structure CST and the metal structure MRS. For example, a metal silicide film such as tungsten silicide, cobalt silicide, or titanium silicide may be interposed between the semiconductor film 100 and a portion of the metal structure MRS.

[0086] In the embodiment, the metal structure MRS can improve a decrease in operating speed due to an increase in resistance of the semiconductor film 100 caused by the first and second insulating patterns 111 and 113 provided in the semiconductor film 100 when a current flows through the semiconductor film 100. That is, a high-speed current path can be formed between the fourth through plug TP4 and the vertical structure VS through the semiconductor film 100 and the metal structure MRS.

[0087] 5, 7, 8, and 9, the cell contact plugs CPLG may be connected to the pad portions of the electrodes GE through the first and second interlayer insulating films 130 and 140 and the planar insulating film 120. The vertical length of the cell contact plugs CPLG may be reduced as they approach the cell array region CAR. The upper surfaces of the cell contact plugs CPLG may be substantially coplanar. A conductive line CL may be disposed on the fourth interlayer insulating film 160 in the first connection region CNR1 and may be connected to the cell contact plugs CPLG through lower and upper contact plugs LCT and UCT.

[0088] 7, 8, and 9, the bit lines BL may be disposed on the fourth interlayer insulating film 160 in the cell array region CAR and may extend in the second direction D2 across the stack structure ST. The bit lines BL may be electrically connected to the vertical structures VS through lower and upper bit line contact plugs BCTa and BCTb.

[0089] A first through plug TP1 may vertically penetrate the first mold pattern MP1 of the stacked structure ST in the first connection region CNR1 and be connected to the first pad pattern LP1, and may be electrically connected to the cell contact plug CPLG through a conductive line CL.

[0090] A second through plug TP2 may be connected to the second pad pattern LP2 by vertically passing through the second mold pattern MP2 of the stack structure ST in the cell array region CAR, and may be electrically connected to the bit line BL through the upper and lower contact plugs LCT and UCT.

[0091] A third through plug TP3 may be connected to the third pad pattern LP3 in the second connection region CNR2 through the planar insulating layer 120. The third through plug TP3 may be horizontally spaced apart from the stack structure ST.

[0092] The fourth through plug TP4 may be connected to the metal structure MRS through the planar insulating film 120 in the second connection region CNR2. The fourth through plug TP4 may be horizontally spaced apart from the stack structure ST.

[0093] The first to fourth through plugs TP1, TP2, TP3, and TP4 may have substantially the same vertical length and may include the same conductive material. Each of the first to fourth through plugs TP1, TP2, TP3, and TP4 may include a barrier metal film BMa, BMb, BMc, or BMd including a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.) and a metal film MPa, MPb, MPc, or MPd including a metal (e.g., tungsten, titanium, tantalum, etc.).

[0094] A connecting conductive pattern ICT may be disposed on the second interlayer insulating film 140 in the second connecting region CNR2 and may be commonly connected to the plurality of third through plugs TP3.

[0095] According to the embodiment, the first, second, and third pad patterns LP1, LP2, and LP3 and the metal structure MRS are provided at the same level, which may facilitate the process of forming the first to fourth through plugs TP1, TP2, TP3, and TP4 connected thereto.

[0096] Semiconductor devices according to various embodiments of the present invention will now be described with reference to Figures 15 to 26. For the sake of simplicity, descriptions of technical features that are the same as those in the semiconductor devices previously described may be omitted, and differences between the embodiments will be described.

[0097] Figures 15, 16, and 17 are cross-sectional views of a semiconductor device according to an exemplary embodiment of the present invention, taken along lines A-A', B-B', and C-C' in Figure 5. Figure 18 is an enlarged view of part P5 in Figure 15.

[0098] 15, 16, and 17, the top surfaces of the first, second, and third pad patterns LP1, LP2, and LP3 and the metal structure MRS may be located at substantially the same level as the top surface of the semiconductor layer 100.

[0099] A first pad pattern LP1 may be provided in the first insulating pattern 111, and a third insulating pattern 115 penetrating the source structure CST may be disposed on the first insulating pattern 111. The third insulating pattern 115 may cover an upper surface of the first pad pattern LP1.

[0100] The first through plug TP1 may be connected to the first pad pattern LP1 through the third and first insulating patterns 115 and 111 in the first connection region CNR1.

[0101] A portion of the metal structure MRS may be embedded in the semiconductor film 100. A source structure CST may be disposed on a portion of the metal structure MRS.

[0102] The source structure CST may further include a residual insulating pattern between the semiconductor film 100 and the support conductive pattern SP. Specifically, the residual insulating pattern may include a first buffer insulating pattern 101, a lower sacrificial pattern 103, and a second buffer insulating pattern 105, which are stacked in order. Here, the lower sacrificial pattern 103 may be made of an insulating material different from that of the first and second buffer insulating patterns 101 and 105. The residual insulating pattern may also cover a portion of the top surface of the metal structure MRS. That is, a portion of the top surface of the metal structure MRS may be in direct contact with the first buffer insulating pattern 101.

[0103] 19, 20, and 21 are cross-sectional views of a semiconductor device according to an exemplary embodiment of the present invention, taken along lines A-A', B-B', and C-C' in Fig. 5. Fig. 22 is an enlarged view of part P6 in Fig. 19.

[0104] 19, 20, and 21, the top surfaces of the first, second, and third pad patterns LP1, LP2, and LP3 and the metal structure MRS may be located at substantially the same level as the top surface of the source conductive pattern SC.

[0105] An upper surface of a portion of the metal structure MRS can be in direct contact with the support conductive pattern SP. A third insulating pattern 115 can be disposed on the first insulating pattern 111 and penetrating the support conductive pattern SP.

[0106] The source structure CST may further include a remaining insulating pattern between the semiconductor layer 100 and the third insulating pattern 115. In detail, the remaining insulating pattern may include a first buffer insulating pattern 101, a lower sacrificial pattern 103, and a second buffer insulating pattern 105, which are stacked in order. A portion of the remaining insulating pattern may contact a sidewall of the second pad pattern LP2 in the cell array region CAR.

[0107] Figures 23, 24, and 25 are cross-sectional views of a semiconductor device according to an exemplary embodiment of the present invention, taken along lines A-A', B-B', and C-C' in Figure 5. Figure 26 is an enlarged view of part P7 in Figure 19.

[0108] 23, 24, and 25, unlike the previous embodiments, the source structure may be omitted. In this embodiment, the vertical semiconductor patterns of the vertical structures VS may be in direct contact with the semiconductor film 100.

[0109] A bottom insulating film ILD of the stacked structure ST may be disposed on the top surfaces of the first, second, and third pad patterns LP1, LP2, and LP3 and the metal structure MRS.

[0110] 27A to 33A and 27B to 33B are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment of the present invention.

[0111] 5, 27A, and 27B, a peripheral circuit structure PS may be formed on a semiconductor substrate.

[0112] Forming the peripheral circuit structure PS may include forming a peripheral circuit PTR on the semiconductor substrate 10, forming a peripheral wiring structure PCP connected to the peripheral circuit PTR, and forming a lower insulating film 50. Here, the peripheral circuit PTR may include a MOS transistor using the semiconductor substrate 10 as a channel.

[0113] The lower insulating film 50 may include one insulating film or multiple stacked insulating films covering the peripheral circuit PTR. The lower insulating film 50 may include, for example, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and / or a low dielectric film.

[0114] Forming the peripheral wiring structure PCP may include forming peripheral contact plugs that penetrate a portion of the lower insulating film 50, and forming peripheral circuit wirings that are connected to the peripheral contact plugs.

[0115] Subsequently, a semiconductor material may be deposited on the lower insulating film 50 to form the semiconductor film 100. The semiconductor film 100 may be made of a semiconductor material, such as silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), or a mixture thereof. The semiconductor film 100 may include a semiconductor doped with impurities and / or an intrinsic semiconductor that is not doped with impurities. The semiconductor film 100 may have a crystalline structure selected from the group consisting of single crystal, amorphous, and polycrystalline.

[0116] A first buffer insulating layer 101, a lower sacrificial layer 103, and a second buffer insulating layer 105 may be stacked in this order on the semiconductor layer 100. The first buffer insulating layer 101 may be formed by thermally oxidizing the surface of the semiconductor layer 100 or by depositing a silicon oxide layer. The lower sacrificial layer 103 may be formed of a material having etch selectivity with respect to the first buffer insulating layer 101. For example, the lower sacrificial layer 103 may be at least one of a silicon nitride layer, a silicon oxynitride layer, silicon carbide, and silicon germanium. The second buffer insulating layer 105 may be formed by depositing a silicon oxide layer.

[0117] The first buffer insulating film 101, the lower sacrificial film 103, and the second buffer insulating film 105 may have openings exposing portions of the semiconductor film 100 in the cell array region CAR. After forming the openings, a support conductive film SP may be deposited to a uniform thickness on the second buffer insulating film 105. The support conductive film SP may fill the openings in the first buffer insulating film 101, the lower sacrificial film 103, and the second buffer insulating film 105 in the cell array region CAR. The support conductive film SP may be in direct contact with the semiconductor film 100 within the openings. The support conductive film SP may be a polysilicon film doped with an N-type dopant and / or carbon (C).

[0118] Subsequently, the support conductive layer SP, the second buffer insulating layer 105, the lower sacrificial layer 103, the first buffer insulating layer 101, and the semiconductor layer 100 may be patterned to expose a portion of the lower insulating layer 50. Accordingly, a first through hole TOP1 may be formed in the first connection region CNR1, and a second through hole TOP2 may be formed in the cell array region CAR.

[0119] Thereafter, first and second insulating patterns 111 and 113 may be formed to fill the first and second through holes TOP1 and TOP2, respectively, and a buried insulating layer 110 may be formed to cover the sidewalls of the semiconductor layer 100, the first buffer insulating layer 101, the lower sacrificial layer 103, the second buffer insulating layer 105, and the support conductive layer SP. That is, the intermediate insulating layer may include the first and second insulating patterns 111 and 113 and the buried insulating layer 110.

[0120] 5, 28A, and 28B, via holes VH1, VH2, VH3, and VH4 exposing landing pads PLP of the peripheral circuit structure PS, and trenches T1, T2, T3, and T4 connected to the via holes VH1, VH2, VH3, and VH4 may be formed. The via holes VH1, VH2, VH3, and VH4 may vertically penetrate a portion of the semiconductor layer 100 and a portion of the lower insulating layer 50, and the trenches T1, T2, T3, and T4 may be formed in a portion of the first and second insulating patterns 111 and 113 and the buried insulating layer 110.

[0121] In detail, forming the via holes and trenches may include forming a mask pattern (not shown), etching the first and second insulating patterns 111 and 113 and portions of the buried insulating film 110 using the mask pattern as an etching mask to form the first, second, third, and fourth trenches T1, T2, T3, and T4, filling the first, second, third, and fourth trenches T1, T2, T3, and T4 with a sacrificial layer (not shown), and etching portions of the sacrificial layer in the first, second, third, and fourth trenches T1, T2, T3, and T4, the first and second insulating patterns 111 and 113, the buried insulating film 110, and the lower insulating film 50 to form the first, second, third, and fourth via holes VH1, VH2, VH3, and VH4. In another example, the first, second, third, and fourth trenches T1, T2, T3, and T4 may be formed after first forming the first, second, third, and fourth via holes VH1, VH2, VH3, and VH4.

[0122] The first via hole VH1 may penetrate the first insulating pattern 111 and the underlying lower insulating film 50 to expose the landing pad PLP of the peripheral circuit structure PS, and the first trench T1 may be connected to the first via hole VH1 in the first insulating pattern 111. The bottom surface of the first trench T1 may be spaced apart from the bottom surface of the semiconductor film 100.

[0123] The first via hole VH1 may penetrate the first insulating pattern 111 and the underlying lower insulating film 50 to expose the landing pad PLP of the peripheral circuit structure PS, and the first trench T1 may be connected to the first via hole VH1 in the first insulating pattern 111. The bottom surface of the first trench T1 may be spaced apart from the bottom surface of the semiconductor film 100.

[0124] The third via hole VH3 may penetrate the buried insulating film 110 and the lower insulating film 50 thereunder to expose the landing pad PLP of the peripheral circuit structure PS, and the third trench T3 may be connected to the third via hole VH3 within the buried insulating film 110.

[0125] The fourth via hole VH4 may penetrate the buried insulating layer 110 and the underlying lower insulating layer 50 to expose the landing pad PLP of the peripheral circuit structure PS, and the fourth trench T4 may expose the semiconductor layer 100 and be connected to the fourth via hole VH4 within the buried insulating layer 110. Forming the fourth trench T4 may include sequentially etching the support conductive layer, the second buffer insulating layer 105, the lower sacrificial layer 103, and a portion of the first buffer insulating layer 101. In addition, when forming the fourth trench T4, a portion of the buried insulating layer 110 may be etched, and a dent may be formed in a region adjacent to the semiconductor layer 100.

[0126] As shown in FIG. 5, the fourth trench T4 may include a first portion extending in a first direction D1 in the cell array region CAR and a second portion extending in a second direction D2.

[0127] Referring to Figures 5, 29A, and 29B, first, second, and third pad patterns LP1, LP2, and LP3 may be formed in the first, second, and third via holes VH1, VH2, and VH3 and the first, second, and third trenches T1, T2, and T3, and a metal structure MRS may be formed in the fourth via hole VH4 and the fourth trench T4.

[0128] Forming the first, second, and third pad patterns LP1, LP2, and LP3 and the metal structure MRS may include sequentially depositing a barrier metal film and a metal film in the first to fourth via holes VH1 to VH4 and the first to fourth trenches T1 to T4, and performing a planarization process on the barrier metal film and the metal film so that the top surface of the support conductive film is exposed.

[0129] In the fourth trench T4, the barrier metal film may be in direct contact with a portion of the semiconductor film 100, and the metal material in the barrier metal film may react with the silicon in the semiconductor film 100 to form a metal-semiconductor compound layer MSC.

[0130] 5, 30A, and 30B, a mold structure PST may be formed on a support conductive layer SP, in which upper sacrificial layers SL and insulating layers ILD are vertically alternately stacked. The mold structure PST may have a stepped structure in a first connection region CNR1.

[0131] In the mold structure PST, the upper sacrificial layer SL may be formed of a material that has etch selectivity with respect to the insulating layer ILD and can be etched. For example, the upper sacrificial layer SL may be formed of a different insulating material from the insulating layer ILD. The upper sacrificial layer SL may be formed of the same material as the lower sacrificial layer 103. For example, the upper sacrificial layer SL may be formed of a silicon nitride layer, and the insulating layer ILD may be formed of a silicon oxide layer.

[0132] After forming the mold structure PST, a planar insulating film 120 may be formed on the buried insulating film 110 to cover the stepped structure of the mold structure PST.

[0133] Subsequently, vertical structures VS may be formed that penetrate the mold structure PST.

[0134] Forming the vertical structures VS may include anisotropically etching the mold structure PST, the support conductive layer SP, and the lower sacrificial layer 103 to form vertical holes penetrating the mold structure PST, the support conductive layer SP, and the lower sacrificial layer 103, and sequentially depositing a data storage pattern (DSP of FIG. 14) and a vertical semiconductor pattern (VP of FIG. 14) in each vertical hole. During the anisotropic etching process for forming the vertical holes, over-etching may occur up to the top surface of the semiconductor layer 100, and the lower portions of the vertical structures VS may be located within the semiconductor layer 100.

[0135] The data storage pattern DSP may conformally cover the inner wall of the vertical hole with a uniform thickness. The data storage pattern DSP may include a tunneling insulating layer, a charge storing layer, and a blocking insulating layer, which are sequentially stacked.

[0136] A vertical semiconductor pattern VP may be formed in the vertical hole in which the data storage pattern DSP is formed, and a bit line conductive pad may be formed on the upper end of the vertical semiconductor pattern VP.

[0137] 5, 31A, and 31B, after forming the vertical structures VS, a first interlayer insulating film 130 covering the upper surfaces of the vertical structures VS may be formed on the planar insulating film 120. Isolation trenches SR may be formed through the mold structure PST and the support conductive layer SP to expose the lower sacrificial layer 103. The isolation trenches SR may be parallel to the first direction D1 and may have different lengths in different regions.

[0138] After forming the isolation trenches SR, a process of replacing the first buffer insulating layer 101, the lower sacrificial layer 103, and the second buffer insulating layer 105 with the source conductive pattern SC may be performed.

[0139] The process of forming the source conductive pattern SC may include performing an isotropic etching process on the lower sacrificial layer 103 exposed in the isolation trench and the first and second buffer insulating layers 101 and 105. During the isotropic etching process, a portion of the data storage pattern (DSP of FIG. 14) may also be isotropically etched to expose a portion of the vertical semiconductor pattern (VP of FIG. 14). After exposing the portion of the vertical semiconductor pattern (VP of FIG. 14), a polycrystalline silicon layer doped with impurities may be deposited to form the source conductive pattern SC. Thus, a source structure CST may be formed between the semiconductor layer 100 and the mold structure PST.

[0140] After forming the source structure CST, the stack structure ST described above can be formed by replacing the upper sacrificial layer SL with the electrode GE. Forming the stack structure ST can include isotropically etching the upper sacrificial layer SL using an etching recipe having etching selectivity with respect to the insulating film ILD, the vertical structure VS, and the source structure CST. During the isotropic etching process on the upper sacrificial layer SL, portions of the upper sacrificial layer SL remain, forming first and second mold patterns MP1 and MP2.

[0141] 5, 32A, and 32B, after forming the stack structure ST, an insulating material may be filled into the isolation trench SR to form first, second, and third isolation structures SS1, SS2, and SS3.

[0142] 5, 33A, and 33B, a second interlayer insulating film 140 may be formed on the first interlayer insulating film 130, and a cell contact plug CPLG connected to the stack structure ST may be formed.

[0143] Subsequently, first to fourth through plugs TP1, TP2, TP3, and TP4 may be simultaneously formed. The first to fourth through plugs TP1, TP2, TP3, and TP4 may include metal and / or metal nitride.

[0144] 7, 8, and 9, lower and upper contact plugs LCT, UCT, and connecting conductive patterns ICT may be formed in the third and fourth interlayer insulating layers 150 and 160. Bit lines BL and conductive lines CL may be formed on the fourth interlayer insulating layer.

[0145] Hereinafter, a method for manufacturing a semiconductor device according to various embodiments of the present invention will be described. For the sake of simplicity, a description of the same technical features as those in the previously described method for manufacturing a semiconductor device may be omitted, and differences between the embodiments will be described.

[0146] 34A to 37A and 34B to 37B are cross-sectional views illustrating methods for manufacturing semiconductor devices according to various embodiments of the present invention.

[0147] Referring to FIGS. 34A and 34B, via holes and trenches may be formed before forming the support conductive layer SP.

[0148] In detail, after forming the semiconductor film 100 on the peripheral circuit structure PS, first and second insulating patterns 111, 113 may be formed in the first and second through holes TOP1, TOP2 penetrating the semiconductor film 100, and a buried insulating film 110 covering the sidewalls of the semiconductor film 100 may be formed on the lower insulating film 50.

[0149] Subsequently, a first buffer insulating film 101, a lower sacrificial film 103, and a second buffer insulating film 105 may be sequentially stacked on the semiconductor film 100, the first and second insulating patterns 111 and 113, and the buried insulating film 110.

[0150] A via hole exposing the landing pad PLP of the peripheral circuit structure PS and a trench connected to the via hole may be formed.

[0151] The via holes and trenches may be formed by patterning the first buffer insulating film 101, the lower sacrificial film 103, the second buffer insulating film 105, the first and second insulating patterns 111 and 113, and the buried insulating film 110. As described above, the via holes and trenches may include the first, second, third, and fourth via holes VH1 to VH4 and the first, second, third, and fourth trenches T1 to T4.

[0152] 35A and 35B, a barrier metal layer and a metal layer may be sequentially formed in the via holes VH1 to VH4 and the trenches T1 to T4, and the barrier metal layer and the metal layer may be planarized to expose the second buffer insulating layer 105 or the lower sacrificial layer 103. Therefore, the first, second, and third pad patterns LP1, LP2, and LP3 and the metal structure MRS may be simultaneously formed. Here, the top surfaces of the first, second, and third pad patterns LP1, LP2, and LP3 and the metal structure MRS may be located at substantially the same level as the top surface of the second buffer insulating layer 105 or the top surface of the lower sacrificial layer 103.

[0153] 36A and 36B, the first buffer insulating layer 101, the lower sacrificial layer 103, and the second buffer insulating layer 105 may have openings that expose portions of the semiconductor layer 100 in the cell array region CAR.

[0154] After forming the opening, a support conductive layer SP may be deposited to a uniform thickness on the second buffer insulating layer 105. After forming the support conductive layer SP, a third insulating pattern 115 may be formed penetrating the support conductive layer SP. The third insulating pattern 115 may be disposed on the first and second insulating patterns 111 and 113 and the buried insulating layer 110.

[0155] 37A and 37B, the mold structure PST, the buried insulating layer 110, and the vertical structure VS, which have been described above with reference to FIGS. 30A and 30B, may be formed on the support conductive layer.

[0156] Next, as described with reference to Figures 31A and 31B, a process of replacing the lower sacrificial layer 103 with a source conductive pattern SC may be performed, and during an isotropic etching process on the lower sacrificial layer 103 to form the source conductive pattern SC, portions of the lower sacrificial layer 103 and the first and second buffer insulating layers 101 and 105 may remain around the first insulating pattern 111.

[0157] Thereafter, as described with reference to FIGS. 31 and 32, the stacked structure ST, the cell contact plug CPLG, and the first to fourth through plugs TP1 to TP4 can be formed.

[0158] 38A to 41A and 38B to 41B are cross-sectional views illustrating methods for manufacturing semiconductor devices according to various embodiments of the present invention.

[0159] 38A and 38B, the via holes VH1 to VH4 and the trenches T1 to T4 may be formed before the first buffer insulating film 101, the lower sacrificial film 103, and the second buffer insulating film 105 are formed.

[0160] In detail, after forming the semiconductor film 100 on the lower insulating film 50, first and second insulating patterns 111, 113 may be formed in the first and second through holes TOP1, TOP2 penetrating the semiconductor film 100, and a buried insulating film 110 covering the sidewalls of the semiconductor film 100 may be formed on the lower insulating film 50.

[0161] Subsequently, via holes VH1 to VH4 exposing the landing pads PLP of the peripheral circuit structure PS, and trenches T1 to T4 connected to the via holes may be formed. The via holes VH1 to VH4 and the trenches T1 to T4 may be formed by patterning the first and second insulating patterns 111, 113, the buried insulating film 110, and a portion of the lower insulating film 50. As described above, the via holes VH1 to VH4 and the trenches T1 to T4 may include the first, second, third, and fourth via holes VH1 to VH4 and the first, second, third, and fourth trenches T1 to T4.

[0162] 39A and 39B, a barrier metal layer and a metal layer may be sequentially formed in the via holes VH1 to VH4 and the trenches T1 to T4, and the barrier metal layer and the metal layer may be planarized to expose the second buffer insulating layer 105 or the lower sacrificial layer 103. Therefore, the first, second, and third pad patterns LP1, LP2, and LP3, and the metal structure MRS may be simultaneously formed. Here, the top surfaces of the first, second, and third pad patterns LP1, LP2, and LP3, and the metal structure MRS may be located at substantially the same level as the top surface of the semiconductor layer 100.

[0163] Referring to Figures 40A and 40B, a first buffer insulating film 101, a lower sacrificial film 103, and a second buffer insulating film 105 may be stacked in sequence on the semiconductor film 100, the first, second, and third pad patterns LP1, LP2, and LP3, and the metal structure MRS.

[0164] After forming an opening that penetrates the first buffer insulating film 101, the lower sacrificial film 103, and the second buffer insulating film 105 to expose a portion of the semiconductor film 100, a support conductive film SP can be deposited to a uniform thickness on the second buffer insulating film 105.

[0165] After forming the support conductive film SP, a third insulating pattern 115 may be formed through the support conductive film SP. The third insulating pattern 115 may be disposed on the first and second insulating patterns 111 and 113 and the buried insulating film 110.

[0166] Meanwhile, in another embodiment, after forming the first, second, and third pad patterns LP1, LP2, LP3, and the metal structure MRS, forming the first buffer insulating film 101, the lower sacrificial film 103, the second buffer insulating film 105, and the support conductive film SP may be omitted.

[0167] 41A and 41B, the mold structure PST, the buried insulating film 110, and the vertical structure VS, which have been described above with reference to FIGS. 30A and 30B, may be formed on the support conductive layer.

[0168] Then, as described with reference to FIGS. 32A and 32B, a process of replacing the lower sacrificial layer 103 with the source conductive pattern SC may be performed.

[0169] Thereafter, as described with reference to FIGS. 32A, 32B, 33A, and 33B, the stacked structure ST, the cell contact plug CPLG, and the first to fourth through plugs TP1 to TP4 may be formed.

[0170] Although the embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art will understand that the present invention may be embodied in other specific forms without changing the technical spirit or essential features thereof. Therefore, it should be understood that the above-described embodiments are illustrative in all respects and are not limiting. [Explanation of symbols]

[0171] 10. Semiconductor substrate 50, 51, 55 Lower insulating film 53 Etch stop film 100 Semiconductor film 110 buried insulating film 120 Flat insulating film BIL Blocking insulating film CAR Cell Array CIL Charge storage membrane CL Conductive Line CPLG cell contact plug CS cell array structure CST source structure CSTR Cell String CNR1, CNR2 connection region CST source structure GE electrode ILD insulating film MRS metal structure TP1~TP4 Penetration plugs PLP Landing Pad PCP peripheral wiring structure PS peripheral circuit structure PTR peripheral circuit SS1, SS2 separation structure ST laminated structure TIL tunnel insulating film VS vertical structure

Claims

1. a semiconductor substrate; a peripheral circuit structure including a peripheral circuit integrated on the semiconductor substrate and a landing pad connected to the peripheral circuit; a semiconductor film disposed on the peripheral circuit structure; a metal structure connected to a portion of the semiconductor film, a first portion extending in a first direction, the first direction being parallel to an upper surface of the semiconductor substrate; a second portion connected to the first portion and extending in a second direction intersecting the first direction, the second direction being parallel to the top surface of the semiconductor substrate and perpendicular to the first direction; and a via portion extending from at least one of the first portion and the second portion in a third direction and connected to the landing pad, the third direction being perpendicular to the top surface of the semiconductor substrate; A metal structure; a laminated structure including insulating films and electrodes alternately laminated on the metal structure in the third direction; Including, the semiconductor film and the metal structure are disposed in the third direction between the peripheral circuit structure and the stacked structure, and the first portion and the second portion of the metal structure are in contact with the portion of the semiconductor film. Semiconductor device.

2. the laminated structure overlaps the first portion and the second portion of the metal structure in a plan view; The semiconductor device according to claim 1 .

3. The semiconductor device further comprises: a first insulating pattern extending in the first direction under the stacked structure and penetrating the semiconductor layer; the second portion of the metal structure crosses the first insulating pattern; 3. The semiconductor device according to claim 1.

4. the metal structure has a first thickness on the semiconductor film and a second thickness on the first insulating pattern that is greater than the first thickness; the metal structure has a substantially flat upper surface; The semiconductor device according to claim 3 .

5. the via portion of the metal structure is separated from the semiconductor film; The semiconductor device according to claim 1 .

6. The semiconductor device further comprises: a metal-semiconductor compound layer between a portion of the semiconductor film and the metal structure; The semiconductor device according to claim 1 .

7. the metal structure includes a first metal pattern and a first barrier metal pattern surrounding a sidewall and a bottom surface of the first metal pattern; The semiconductor device according to claim 1 .

8. an upper surface of the first portion and the second portion of the metal structure being located at substantially the same level as an upper surface of the semiconductor film; The semiconductor device according to claim 1 .

9. The semiconductor device further comprises: a source structure provided between the semiconductor film and the stack structure; a vertical semiconductor pattern penetrating the stacked structure, the source structure includes a first source conductive pattern and a second source conductive pattern sequentially stacked on the semiconductor layer; the first source conductive pattern contacts a portion of a sidewall of the vertical semiconductor pattern; The semiconductor device according to claim 1 .

10. an upper surface of the first portion and the second portion of the metal structure being located at substantially the same level as an upper surface of the second source conductive pattern; The semiconductor device according to claim 9 .

11. The semiconductor device further comprises: a flat insulating film covering the laminated structure; a via plug spaced apart from the stack structure, passing through the flat insulating film and connected to the metal structure; The semiconductor device according to claim 1 .

12. The semiconductor device further comprises: a first insulating pattern overlapping a portion of the stacked structure in the third direction and penetrating the semiconductor film; a first pad pattern provided within the first insulating pattern and electrically connected to the landing pad; a second pad pattern disposed apart from the stacked structure and the semiconductor film and electrically connected to the landing pad; the first pad pattern and the second pad pattern include the same metal material as the metal structure; The semiconductor device according to claim 1 .

13. an upper surface of the first pad pattern and an upper surface of the second pad pattern being located at substantially the same level as an upper surface of the metal structure; The semiconductor device according to claim 12.

14. The semiconductor device further comprises: a first through plug that penetrates the stacked structure and is connected to the first pad pattern; a second through plug spaced apart from the stacked structure and connected to the second pad pattern; The semiconductor device according to claim 12.

15. a semiconductor substrate; a peripheral circuit structure including a peripheral circuit integrated on the semiconductor substrate and a landing pad connected to the peripheral circuit; a semiconductor film disposed on the peripheral circuit structure; a first insulating pattern extending in a first direction through a portion of the semiconductor layer, the first direction being parallel to an upper surface of the semiconductor substrate; a metal structure connected to another portion of the semiconductor film; a first portion extending in the first direction; and a second portion connected to the first portion and extending in a second direction intersecting the first direction, the second direction being parallel to the top surface of the semiconductor substrate and perpendicular to the first direction; A metal structure; a stacked structure including insulating films and electrodes alternately stacked on the metal structure in a third direction, the third direction being perpendicular to the top surface of the semiconductor substrate; Including, the second portion of the metal structure crosses the first insulating pattern; the semiconductor film and the metal structure are disposed in the third direction between the peripheral circuit structure and the stack structure, and the first portion and the second portion of the metal structure are in contact with the other portion of the semiconductor film; Semiconductor device.

16. The metal structure further comprises: a via portion extending from at least one of the first portion and the second portion in the third direction and connected to the landing pad, the via portion is separated from the semiconductor film. The semiconductor device according to claim 15.

17. the metal structure includes a first metal pattern and a first barrier metal pattern surrounding the first metal pattern; 17. The semiconductor device according to claim 15 or 16.

18. The semiconductor device further comprises: a metal-semiconductor compound layer between a portion of the semiconductor film and the metal structure; The semiconductor device according to claim 15.

19. a semiconductor substrate; a peripheral circuit structure including a peripheral circuit integrated on the semiconductor substrate and a landing pad connected to the peripheral circuit; a semiconductor film disposed on the peripheral circuit structure; a metal structure connected to a portion of the semiconductor film, a first portion extending in a first direction, the first direction being parallel to an upper surface of the semiconductor substrate; a second portion connected to the first portion and extending in a second direction intersecting the first direction, the second direction being parallel to the top surface of the semiconductor substrate and perpendicular to the first direction; and a via portion extending from at least one of the first portion and the second portion in a third direction and connected to the landing pad, the third direction being perpendicular to the top surface of the semiconductor substrate; A metal structure; a laminated structure including insulating films and electrodes alternately laminated on the metal structure in the third direction; A semiconductor device comprising: a vertical semiconductor pattern penetrating the stacked structure; a source structure provided between the semiconductor film and the stack structure, a first source conductive pattern and a second source conductive pattern sequentially stacked on the semiconductor layer; the first source conductive pattern contacts a portion of a sidewall of the vertical semiconductor pattern; a source structure; a first insulating pattern penetrating the semiconductor film under the stacked structure; a first pad pattern provided within the first insulating pattern and electrically connected to the peripheral circuit; a second pad pattern disposed apart from the stacked structure and the semiconductor layer and electrically connected to the peripheral circuit; a first through plug that penetrates the stacked structure and is connected to the first pad pattern; a second through plug spaced apart from the stacked structure and connected to the second pad pattern; a third through plug spaced apart from the stack structure and connected to the metal structure; Including, the semiconductor film and the metal structure are disposed in the third direction between the peripheral circuit structure and the stack structure, and the first portion and the second portion of the metal structure are in contact with the portion of the semiconductor film. Semiconductor device.

20. the first pad pattern and the second pad pattern include the same metal material as the metal structure; the second portion of the metal structure crosses the first insulating pattern; 20. The semiconductor device according to claim 19.

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