Flash memory device and programming method thereof

Abstract

A flash memory device and a programming method thereof are provided. [Solution] A flash memory device includes a memory array and a memory control circuit. The memory array has a plurality of bit groups. The memory control circuit sequentially performs programming operations on the bit groups, and if a target bit group among the bit groups fails programming verification, the memory control circuit performs one or more programming verify cycles on the target bit group. Here, the target bit group is divided into M portions, where M is a positive integer greater than 1, and it is determined whether the programming verify cycle performed on the target bit group is a first programming verify cycle. If the first programming verify cycle is performed on the target bit group, the memory control circuit sequentially programs the M portions in a first programming time.

Description

[Technical Field]

[0001] The present invention relates to a control technique for a memory device, and more particularly to a flash memory device and a programming method thereof for reducing programming current generated during a programming operation. [Background technology]

[0002] In addition to programming time, the programming current flowing from the drain to the source of a memory cell during programming is also an important parameter that can be used to reduce power consumption and is also important for green and sustainable semiconductor manufacturing. When programming a certain number of memory cells, a regulator with a charge pump circuit can be used to provide a stable drain voltage (e.g., 4 volts) to the memory cells and generate the programming current to ensure successful programming. However, the area occupied by the charge pump circuit is proportional to the peak programming current generated by all memory cells during programming, which also affects the manufacturing cost of the product. Therefore, how to reduce the programming current generated during programming operations of NOR flash memory devices has become a key challenge in this field. Summary of the Invention [Problem to be solved by the invention]

[0003] The present invention provides a flash memory device and a programming method thereof that can dynamically adjust the number of bits (memory cells) simultaneously programmed and the programming time used during a programming verify cycle to reduce the programming current generated by the programming operation. [Means for solving the problem]

[0004] The flash memory device of the present invention includes a memory array and a memory control circuit. The memory array has a plurality of bit groups. The memory control circuit is coupled to the memory array and configured to sequentially perform programming operations on the bit groups. If target bits among the bit groups fail programming verification, the memory control circuit performs one or more programming verify cycles on the target bits, where the target bits are divided into M portions, where M is a positive integer greater than 1. The memory control circuit determines whether the programming verify cycle performed on the target bits is a first programming verify cycle. If the first programming verify cycle is performed on the target bits, the memory control circuit sequentially programs the M portions at a first programming time.

[0005] The programming method for a flash memory device of the present invention includes: sequentially performing programming operations on a plurality of bit groups; if a target bit group among the bit groups fails programming verification, performing one or more programming verification cycles on the target bit group, where the target bit group is divided into M parts, where M is a positive integer greater than 1; determining whether the programming verification cycle performed on the target bit group is a first programming verification cycle; and if the first programming verification cycle is performed on the target bit group, sequentially performing programming on the M parts in a first programming time. [Effects of the Invention]

[0006] Based on the above, the flash memory device and programming method of the present invention can sequentially program only one portion of the target bit group at a time in a shorter programming time than conventional methods when performing a first programming verify cycle on the target bit group, thereby reducing the peak value of the program current generated during the program operation and the area occupied by the charge pump circuit.

[0007] In order to make the above features and advantages of the present invention clearer and easier to understand, the following detailed description is given by way of example and with reference to the accompanying drawings. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a schematic diagram of a flash memory device according to an embodiment of the present invention; [Figure 2] 4 is a flowchart of method steps for programming a flash memory device according to some embodiments of the present invention. [Figure 3] 4 is a flowchart of method steps for programming a flash memory device according to some embodiments of the present invention. [Figure 4] 4 is a flowchart of method steps for programming a flash memory device according to some embodiments of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0009] Referring to FIG. 1, a flash memory device 100 according to an embodiment of the present invention is, for example, a NOR type, and includes a memory array 110 and a memory control circuit 120. The memory array 110 includes a plurality of bit groups 112. Each bit group 112 consists of a plurality of bits to be programmed in a specific data pattern. Structurally, one bit corresponds to a memory cell having, for example, a memory tunnel oxide (ETOX) structure. Note that the present invention does not limit the number of bit groups 112 or the number of bits (memory cells) that make up one bit group 112.

[0010] The memory control circuit 120 is coupled to the memory array 110. The memory control circuit 120 can sequentially perform programming operations on all bit groups 112. Specifically, the memory control circuit 120 can select a target bit group 114 from the multiple bit groups 112 in the memory array 110 according to the received selection command CMD and perform the programming operation. In this embodiment, the target bit group 114 can be divided into M portions G1 to GM, where M is a positive integer greater than 1. For example, each portion G1 to GM can include 16 bits. The portion G1 includes the most significant 16 bits of the target bit group 114, the portion G2 includes the 16 bits immediately following the bits of the portion G1 of the target bit group 114, and so on. However, the present invention does not limit the number of bits in each portion G1 to GM, and those skilled in the art can make appropriate adjustments according to actual needs.

[0011] Memory control circuit 120 may be, for example, a state machine, a central processing unit, or other programmable general-purpose or special-purpose microprocessor, a digital signal processor, a programmable controller, a special-purpose integrated circuit, a programmable logic device, or other similar device, or a combination of these devices, or may be a hardware circuit designed using a hardware description language or other conventional digital circuit design method and implemented using a field programmable logic gate array, a composite programmable logic device, or the like. Also, although memory control circuit 120 is shown in Figure 1 as being located within flash memory device 100, memory control circuit 120 may be a device separate from flash memory device 100.

[0012] Optionally, flash memory device 100 may further include a flag register 130. Flag register 130 is coupled to memory control circuit 120 and is used to store a time flag FT. Memory control circuit 120 may set the initial value of time flag FT to a first value (e.g., "0") each time a programming verify cycle is performed. Also, although flag register 130 is shown in FIG. 1 as being independent from memory array 110 and memory control circuit 120, flag register 130 may be integrated into memory array 110 or memory control circuit 120.

[0013] 1 and 2, the programming method for a flash memory device according to the present embodiment can be applied to the flash memory device 100 of Fig. 1. Hereinafter, each step of the programming method according to the embodiment of the present invention will be described with reference to each component of the flash memory device 100.

[0014] First, in step S200, the memory control circuit 120 sequentially executes programming operations on the plurality of bit groups 112. For example, the memory control circuit 120 executes initialization and can set one (e.g., a first bit group) of all bit groups 112 to be programmed in the memory array 110 as the target bit group 114.

[0015] The memory control circuit 120 may then compare the bit data (e.g., 32 bits) formed by the target bit group 114 with a specific data pattern (e.g., 32 bits) to determine whether the target bit group 114 passes programming verification. More specifically, in one example of programming verification, the memory control circuit 120 may determine whether the threshold voltage (Vth) of each bit (memory cell) in the target bit group 114 satisfies a predetermined range for each bit value in the specific data pattern. For example, if the bit value in the data pattern is "0," the corresponding threshold voltage must be greater than a predetermined programming verification reference voltage, and if the bit value in the data pattern is "1," the corresponding threshold voltage must be less than the predetermined programming verification reference voltage. The data patterns corresponding to each bit group 112 may be the same or different.

[0016] Thus, in step S202, if the target bit group 114 fails programming verification, the memory control circuit 120 may perform one or more programming verification cycles on the target bit group 114.

[0017] Next, in step S204, the memory control circuit 120 determines whether the programming verify cycle to be executed on the target bit group 114 is the first programming verify cycle. If the first programming verify cycle is to be executed on the target bit group 114, in step S206, the memory control circuit 120 sequentially executes programming on M portions G1 to GM of the target bit group 114 during a first programming time. For example, the memory control circuit 120 may set an initial value of K to 1 and determine whether the Kth portion GK of the target bit group 114 has one or more failed bits. If so, the memory control circuit 120 applies the programming voltage Vprg to the failed bits in the Kth portion GK during the first programming time, increments K (K=K+1), and continues to determine the next portion. If not, the memory control circuit 120 directly increments K (K=K+1) and continues to determine the next portion. In this embodiment, the so-called "failed bit" refers to a bit (memory cell) that has failed programming verification within the target bit group 114. The programming voltage Vprg includes voltages applied to the gate node, drain node, source node, and well region of the failed bit, particularly the voltage applied to the drain node. For example, the voltage applied to the gate node may be 9 volts, the voltage applied to the drain node may be 4 volts, and the voltage applied to the source node and well region may be 0 volts, but the present invention is not limited thereto.

[0018] Furthermore, the memory control circuit 120 may repeat the process of determining whether the Kth part GK has one or more defective bits and the above process of incrementing K, thereby continuing to determine the next part until K becomes greater than M (all parts G1 to GM have been determined).

[0019] On the other hand, when a programming verify cycle other than the first (e.g., second or third) is performed on the target bit group 114, in step S208, the memory control circuit 120 simultaneously programs the M portions G1-GM of the target bit group 114 for a second programming time longer than the first programming time. Specifically, the memory control circuit 120 can simultaneously apply the programming voltage Vprg to the defective bits of all M portions G1-GM during the second programming time. In practical applications, the first programming time is, for example, 0.2 microseconds, and the second programming time is, for example, 0.8 microseconds, both of which are shorter than the conventional programming time (e.g., 1 microsecond) used for a 32-bit bit group.

[0020] According to the characteristics of a NOR flash memory device, the programming current generated by all bits (memory cells) during programming decreases over time. In this embodiment, since the number of defective bits is the largest in the first programming verification cycle, in the first programming verification cycle, the memory control circuit 120 applies the programming voltage Vprg to only the defective bits in one portion GK of the target bit group 114 at a time during the first programming time, thereby reducing the peak value of the programming current generated by all the defective bits to which the programming voltage Vprg is simultaneously applied.

[0021] Since the number of failing bits in the programming verify cycles other than the first one decreases as the number of programming verify cycles increases, in the programming verify cycles other than the first one, the memory control circuit 120 simultaneously applies the programming voltage Vprg to the failing bits in all M portions G1 to GM of the target bit group 114 at once during the second programming time, thereby improving the speed of the programming verify. In this way, the time spent on the programming operation can be shortened while taking the programming current into consideration.

[0022] The programming method of the present invention will be described in more detail below using the embodiment shown in FIG. 3. With reference to FIGS. 1 and 3 simultaneously, the programming method for a flash memory device of this embodiment can be applied to the flash memory device 100 of FIG. 1. Hereinafter, each step of the programming method according to the embodiment of the present invention will be described with reference to each component of the flash memory device 100. In this embodiment, a description of parts that are the same as or similar to the description of FIG. 2 will be omitted. For ease of description, this embodiment assumes that the target bit group 114 is divided into two parts G1-G2 (M is equal to 2).

[0023] First, in step S300, the memory control circuit 120 performs initialization and sets the first bit group of all the programming target bit groups 112 in the memory array 110 as the target bit group 114.

[0024] Next, in step S302, the memory control circuit 120 determines whether the target bit group 114 has passed the programming verification. If the target bit group 114 has failed the programming verification, in step S304, the memory control circuit 120 determines whether the programming verification cycle performed on the target bit group 114 is the first programming verification cycle. Specifically, the memory control circuit 120 determines whether the programming verification cycle performed on the current target bit group 114 is the first programming verification cycle according to the time flag FT.

[0025] If the time flag FT is a first value (e.g., "0"), the memory control circuit 120 can determine that the programming verify cycle performed on the current target bit group 114 is the first programming verify cycle, and therefore, in step S306, the memory control circuit 120 determines whether the first portion G1 of the target bit group 114 has one or more failed bits. If so, in step S308, the memory control circuit 120 applies the programming voltage Vprg to the failed bits in the first portion G1 for the first programming time, and then proceeds to S310. If not, after step S306, proceed directly to S310.

[0026] In step S310, the memory control circuit 120 determines whether the second portion G2 of the target bit group 114 has one or more failed bits. If so, in step S312, the memory control circuit 120 applies the programming voltage Vprg to the failed bits in the second portion G2 for a first programming time. Then, the memory control circuit 120 sets the time flag FT to a second value (e.g., "1") and returns to step S302 to continue the second programming verify cycle. If not, after step S310, the memory control circuit 120 sets the time flag FT to the second value and returns to step S302.

[0027] If the memory control circuit 120 determines in step S304 that the time flag FT stored in the flag register 130 is not the first value (is the second value), the memory control circuit 120 can determine that the programming verify cycle being performed on the current target bit group 114 is a programming verify cycle other than the first (e.g., the second, third, etc.), and therefore, in step S314, the memory control circuit 120 simultaneously programs the two portions G1-G2 of the target bit group 114 for a second programming time that is longer than the first programming time. Specifically, the memory control circuit 120 can simultaneously apply the programming voltage Vprg to the fail bits in all two portions G1-G2 during the second programming time. Then, the process returns to step S302 and continues with the next programming verify cycle.

[0028] On the other hand, if the memory control circuit 120 determines in step S302 that the target bit group 114 passes the programming verification, then in step S316, the memory control circuit 120 determines whether the target bit group 114 is the last bit group of all the bit groups 112 to be programmed. If so, the process proceeds to S318, where the programming operation of the memory array 110 is terminated. If not, in step S320, the memory control circuit 120 sets the next bit group of the bit groups 112 as the target bit group 114, and then proceeds to S302, where the programming operation continues.

[0029] A programming method will be described below with reference to yet another embodiment. Referring to FIGS. 1 and 4 simultaneously, the programming method for a flash memory device according to this embodiment can be applied to the flash memory device 100 of FIG. 1. Hereinafter, each step of the programming method according to this embodiment will be described with reference to each component of the flash memory device 100. In this embodiment, descriptions of parts that are the same as or similar to those in FIGS. 2 and 3 will be omitted. Similarly, in this embodiment, it is assumed that the target bit group 114 is divided into two parts G1-G2 (M is equal to 2).

[0030] First, in step S400, the memory control circuit 120 performs initialization and sets the first bit group of all the bit groups 112 to be programmed in the memory array 110 as the target bit group 114.

[0031] Next, in step S402, the memory control circuit 120 determines whether the target bit group 114 has passed the programming verify. If the target bit group 114 has failed the programming verify, in step S404, the memory control circuit 120 determines whether the programming verify cycle performed on the target bit group 114 is the first programming verify cycle.

[0032] If the memory control circuit 120 determines that the programming verify cycle performed on the current target bit group 114 is the first programming verify cycle, in step S406, the memory control circuit 120 determines whether the first portion G1 of the target bit group 114 has one or more failed bits. If so, in step S408, the memory control circuit 120 applies the programming voltage Vprg to the failed bits in the first portion G1 for a first programming time, and then proceeds to step S410. If not, after step S406, proceed directly to step S410.

[0033] In step S410, the memory control circuit 120 determines whether the second portion G2 of the target bit group 114 has one or more failed bits. If so, in step S412, the memory control circuit 120 applies the programming voltage Vprg to the failed bits in the second portion G2 for a first programming time, and then proceeds to step S414. If not, after step S410, the memory control circuit 120 proceeds directly to step S414.

[0034] Unlike the previous embodiment, after determining whether the second portion G2 of the target bit group 114 has one or more failed bits, in step S414, the memory control circuit 120 simultaneously programs the two portions G1-G2 of the target bit group 114 for a third programming time. The third programming time in this embodiment is, for example, longer than the first programming time and shorter than the second programming time. Specifically, the memory control circuit 120 can simultaneously apply the programming voltage Vprg to the failed bits in all two portions G1-G2 for the third programming time. Then, the process returns to step S402 to continue with the next programming verify cycle.

[0035] In step S404, if the memory control circuit 120 determines that the programming verification cycle being performed on the current target bit group 114 is a programming verification cycle other than the first (e.g., the second, third, etc.), in step S416, the memory control circuit 120 simultaneously performs programming on two portions G1-G2 of the target bit group 114 for a second programming time that is longer than the first programming time.

[0036] On the other hand, if the memory control circuit 120 determines in step S402 that the target bit group 114 passes the programming verification, then in step S418 the memory control circuit 120 determines whether the target bit group 114 is the last bit group of all the bit groups 112 to be programmed. If so, the process proceeds to step S420, where the programming operation of the memory array 110 is terminated. If not, in step S422 the memory control circuit 120 sets the next bit group of the bit groups 112 as the target bit group 114, and then proceeds to step S402, where the programming operation continues.

[0037] In summary, the flash memory device and programming method thereof of the present invention can reduce the programming current generated by the programming operation. Although the total programming time increases slightly, the peak value of the generated programming current is significantly reduced, which significantly reduces the area occupied by the charge pump circuit and reduces the manufacturing cost of the product, and is useful for the Internet of Things (IoT). This is beneficial for IoT and battery applications. Therefore, the present invention provides a green and sustainable semiconductor manufacturing technology. [Industrial Applicability]

[0038] The flash memory device and programming method thereof of the present invention can be applied to perform programming operations of the memory. [Explanation of symbols]

[0039] 100: Flash memory device 110: Memory array 112: Bit group 114: Target bit group 120: Memory control circuit 130: Flag register CMD:Select command FT: Time Flag G1, G2, GM: Partial Vprg: Programming voltage S200~S208, S300~S320, S400~S422: Process

Claims

1. a memory array having a plurality of bit groups; a memory control circuit coupled to the memory array and configured to sequentially perform programming operations on the plurality of bit groups; If a target bit group among the plurality of bit groups fails programming verification, the memory control circuit performs one or more programming verification cycles on the target bit group; The set of bits of interest is divided into M parts, where M is a positive integer greater than 1; the memory control circuit determines whether the programming verify cycle performed on the target bit group is the first programming verify cycle, and if the programming verify cycle is the first programming verify cycle performed on the target bit group, the memory control circuit sequentially programs the M portions in a first programming time; When the programming verify cycle other than the first one is performed on the target bit group, the memory control circuit simultaneously programs the M portions for a second programming time longer than the first programming time. Flash memory device.

2. When performing the programming verify cycle for the target bit group for the first time, the memory control circuit sets an initial value of K to 1, determines whether the Kth portion of the target bit group has one or more failed bits, and if so, applies a programming voltage to the one or more failed bits in the Kth portion for the first programming time.

10. The flash memory device of claim 1.

3. the memory control circuit increments K and continues determining the next portion, repeating determining whether the K portion has the one or more failing bits and incrementing K until K is greater than M; 3. The flash memory device of claim 2.

4. After determining whether the M-th portion of the target bit set has the one or more failing bits, the memory control circuit simultaneously programs the M portions for a third programming time, wherein the third programming time is longer than the first programming time and less than or equal to the second programming time.

4. The flash memory device of claim 3.

5. the flash memory device further includes a flag register used to store a time flag, the flag register being coupled to the memory control circuit, and the memory control circuit determining, based on the time flag, whether the programming verify cycle performed on the target bit group is the first programming verify cycle; 10. The flash memory device of claim 1.

6. If the target bit group passes programming verification, the memory control circuit determines whether the target bit group is the last bit group; if not, the memory control circuit sets a next bit group as the target bit group and performs the programming operation.

10. The flash memory device of claim 1.

7. 1. A method for programming a flash memory device, comprising: the flash memory device includes a memory array of a plurality of bit groups; The programming method comprises: sequentially performing programming operations on the plurality of bit groups; performing one or more programming verify cycles on a set of target bits of the plurality of sets of bits if the set of target bits fails programming verify, wherein the set of target bits is divided into M portions, where M is a positive integer greater than 1; determining whether the programming verify cycle performed on the target bits is a first programming verify cycle; When performing the programming verify cycle for the target bits for a first time, sequentially programming the M portions for a first programming time; When performing the programming verify cycle other than the first time for the target bits, simultaneously programming the M portions for a second programming time longer than the first programming time; 10. A method for programming a flash memory device, comprising:

8. Sequentially programming the M portions at the first programming time includes: setting an initial value of K to 1; determining whether the Kth portion of the target bits has one or more failing bits; If the K portion has one or more failed bits, applying a programming voltage to the one or more failed bits for the first programming time; 8. The programming method of claim 7, comprising:

9. Sequentially programming the M portions at the first programming time includes: incrementing K and continuing to evaluate the next part; repeating determining whether the K portion has the one or more failing bits and incrementing K until K is greater than M; 9. The programming method of claim 8, further comprising:

10. after determining whether the M-th portion of the target bit set has the one or more failing bits, simultaneously programming the M portions for a third programming time, wherein the third programming time is longer than the first programming time and less than or equal to the second programming time; 10. The programming method of claim 9, further comprising:

11. The flash memory device further includes a flag register used to store a time flag, and determining whether the programming verify cycle performed on the target bit group is the first programming verify cycle includes: determining whether the programming verify cycle executed on the target bit group is a first programming verify cycle based on the time flag; 8. The programming method of claim 7.

12. If the target set of bits passes programming verification, determining whether the target set of bits is the last set of bits; otherwise, setting the next group of bits as the target group of bits and performing the programming operation; The programming method of claim 7 further comprising:

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