Clock recovery method and wireless communication system

Abstract

To provide a clock recovery method which can improve the pull-in performance of clock timing synchronization and a wireless communication system that implements the clock recovery method.SOLUTION: In a wireless communication system, a clock recovery method executed by a transmission device 2 includes: transmitting a data pattern having the same symbol point for two consecutive symbols as a synchronizing signal; a receiving device receiving the synchronizing signal and synchronizing clock timing by using the synchronizing signal; and the receiving device synchronizing clock timing by using a phase error stored before the line disconnection, when a line disconnection occurs after the clock timing synchronization is established.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a clock recovery method that is applied to radio communication performed via a communication satellite, for example, to recover a clock, and to a radio communication system that executes such a clock recovery method. [Background technology]

[0002] In a receiving device of a wireless communication system, a process is performed to synchronize the timing of a clock used when demodulating a modulated signal transmitted from a transmitting device with the timing of the clock used when modulating the signal at the transmitting device. One method for synchronizing the clock timing is to estimate the phase of the modulation at the transmitting device from the analog signal received by the receiving device, and establish synchronization of the clock timing based on the estimated phase.

[0003] A known conventional mechanism for estimating the phase of a clock used for demodulation is a clock phase estimation device that includes limiter means for individually limiting the in-phase and quadrature components of a signal used for clock phase estimation, which is obtained from a signal obtained after quadrature detection of a received signal; clock component extraction means for extracting clock components individually from each limiter-processed signal by performing waveform shaping using a filter with a higher roll-off rate than in normal communications; clock phase estimation signal calculation means for squaring each of the clock components extracted by the clock component extraction means, adding the squared values, and using the result as a clock phase estimation signal; and phase estimation means for estimating the clock phase based on the clock phase estimation signal (see Patent Document 1). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2010-88035 Summary of the Invention [Problem to be solved by the invention]

[0005] Narrowing the spacing between communication channels is an effective way to achieve efficient frequency utilization. In digital modulation, channel spacing can be narrowed by lowering the roll-off rate. However, a low roll-off rate reduces the accuracy of clock timing detection, resulting in a problem of degraded clock timing synchronization performance. In particular, in environments with a low C / N (Carrier to Noise) ratio, there is a problem of significant degradation in clock timing synchronization pull-in performance.

[0006] The technology in Patent Document 1 aims to improve detection accuracy by inserting a limiter into the clock timing detection signal to equalize timing variations, but this process also equalizes the effect of noise, so there is a problem in that the degree of improvement in noise is small.

[0007] SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a clock recovery method and a wireless communication system that executes such a clock recovery method, which are capable of improving the pull-in performance of clock timing synchronization. [Means for solving the problem]

[0008] In order to solve the above problem, a clock recovery method according to the present invention is a method in which a transmitting device transmits a data pattern in which two consecutive symbols have the same symbol point as a synchronization signal, and a receiving device receives the synchronization signal and uses the synchronization signal to By zero cross detection method Handles clock timing synchronization stomach , The frequency component of the synchronization signal is equal to or less than half the symbol frequency. It is characterized by:

[0009] The clock recovery method according to the present invention may be configured such that, when a line disconnection occurs after the clock timing synchronization has been established, the receiving device performs clock timing synchronization processing using the phase error stored before the line disconnection occurred.

[0010] The clock recovery method of the present invention may be configured such that, if clock timing synchronization cannot be established even after a predetermined time has elapsed since the line disconnection occurred, the receiving device requests the transmitting device to transmit the synchronization signal.

[0011] In the clock recovery method according to the present invention, the transmitting device may perform filtering on the synchronization signal.

[0012] A radio communication system according to the present invention is characterized in that it executes the clock recovery method described above. [Effects of the Invention]

[0013] According to the clock recovery method and wireless communication system of the present invention, clock timing synchronization is performed using a data pattern in which two consecutive symbols have the same symbol point. Since a signal with the same symbol point for two consecutive symbols is less susceptible to the effects of differences in the roll-off rates of the roll-off filters, it is possible to improve the pull-in performance of clock timing synchronization.

[0014] According to the clock recovery method and wireless communication system of the present invention, if the clock timing synchronization process is performed using the phase error stored before the line disconnection occurs, it becomes possible to quickly perform the clock synchronization process when the line disconnection occurs.

[0015] According to the clock recovery method and wireless communication system of the present invention, if a synchronization signal is transmitted when a predetermined time has elapsed since a line disconnection occurred, it becomes possible to properly perform clock synchronization processing in the event of a line disconnection without taking unnecessary time.

[0016] According to the clock recovery method and wireless communication system of the present invention, when filtering is performed on a synchronization signal, it is possible to improve the spectral mask when transmitting a data pattern in which the same symbol point occurs in two consecutive symbols. [Brief explanation of the drawings]

[0017] [Figure 1] 1 is a functional block diagram showing a schematic configuration of a transmitting side device that constitutes a wireless communication system that executes a clock recovery method according to an embodiment of the present invention; [Figure 2] 1 is a functional block diagram showing a schematic configuration of a receiving side device that constitutes a wireless communication system that executes a clock recovery method according to an embodiment of the present invention; [Figure 3] 3 is a diagram for explaining an outline of a procedure for clock synchronization processing between the transmitting-side device in FIG. 1 and the receiving-side device in FIG. 2. FIG. [Figure 4] FIG. 10 is a diagram showing an example of a data pattern in which the same symbol point occurs in two consecutive symbols. [Figure 5] These are typical examples of eye pattern waveforms of output after quadrature detection processing. (A) is an example of an eye pattern waveform when the roll-off rate is 0.5. (B) is an example of an eye pattern waveform when the roll-off rate is 0.05. [Figure 6] FIG. 10 is a diagram illustrating differences in frequency characteristics of a roll-off filter due to differences in roll-off rate. [Figure 7] These figures show examples of waveform diagrams of eye patterns of output after quadrature detection processing when a data pattern is used in which the same symbol point occurs for two consecutive symbols. (A) is an example of a waveform diagram of an eye pattern when the roll-off rate is 0.5. (B) is an example of a waveform diagram of an eye pattern when the roll-off rate is 0.05. [Figure 8] 3 is a diagram for explaining an outline of a procedure for clock synchronization processing when a line is disconnected between the transmitting device in FIG. 1 and the receiving device in FIG. 2. FIG. [Figure 9] 9 is a functional block diagram for explaining the processing contents in the receiving side device of FIG. 2 related to the clock synchronization processing when the line is disconnected in FIG. 8. [Figure 10] 1 shows the frequency spectrum shape of a signal output from a roll-off filter, where (A) shows a typical frequency spectrum shape, and (B) shows the frequency spectrum shape when a data pattern is used in which the same symbol point occurs in two consecutive symbols. [Figure 11] FIG. 10 is a functional block diagram showing another example of a schematic configuration of a transmitting side device that constitutes a wireless communication system that executes a clock recovery method according to the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0018] The present invention will be described below based on the illustrated embodiments.

[0019] In this embodiment, an example will be described in which a clock recovery method is performed in a wireless communication system 1 that performs wireless communication via a communication satellite (in other words, using a satellite communication line) between a transmitting device 2 and a receiving device 3 (including between two communication devices that are capable of transmitting and receiving and perform bidirectional communication). Note that illustrations and descriptions of circuit elements that are not related to the gist of this invention will be omitted, and it will be assumed that the transmitting device 2, receiving device 3, and wireless communication system 1 are provided with the necessary circuit elements as appropriate, even if they are not illustrated or described.

[0020] FIG. 1 is a functional block diagram showing a schematic configuration of a transmitting side device 2 constituting a wireless communication system 1 that executes a clock recovery method according to an embodiment of the present invention.

[0021] The transmitting device 2 has a synchronization data generating section 21, a changeover switch 22, a header adding section 23, a mapping section 24, and a modulation section 25 as components particularly related to the present invention.

[0022] The synchronization data generator 21 generates and outputs a signal (called a "synchronization signal") used in a process (called "clock synchronization process") to synchronize the clock timing used by the receiving device 3 when demodulating with the clock timing used when modulating by the transmitting device 2.

[0023] The changeover switch 22 switches so that one end (specifically, the output side) is connected to the header adding unit 23 and the other end (specifically, the input side) is connected to the synchronization data generating unit 21 or to a transmission system for normal signals (i.e., transmission signals consisting of information / data transmitted from the transmitting device 2 to the receiving device 3).

[0024] The header adding unit 23 adds a header (including a unique word) containing information identifying the signal frame as a synchronization signal when the signal frame is data output from the synchronization data generating unit 21 to the signal frame transmitted from the transmitting device 2 to the receiving device 3, and also adds a header (including a unique word) containing information identifying the signal frame as a normal signal (i.e., information similar to that of a normal signal) when the signal frame is information / data from a transmission system for a normal signal, and outputs the signal frame.

[0025] It is not essential that the header contains information identifying the signal as a synchronization signal, and the header may not contain information identifying the signal as a synchronization signal.

[0026] The mapping unit 24 performs a mapping process by mapping the signal frame (bit string signal) output from the header adding unit 23 to a signal point on a constellation defined by a predetermined digital orthogonal modulation method such as QPSK (Quadrature Phase Shift Keying) or QAM (Quadrature Amplitude Modulation) in units of symbols, which are a predetermined number of bits, and outputs the symbols resulting from the mapping process in units of signal frames.

[0027] The modulation unit 25 performs digital-to-analog conversion on the signal frame output from the mapping unit 24 to obtain an analog signal, which is then modulated into a radio frequency (RF) wireless signal and output.

[0028] The radio signal output from the modulation unit 25 is subjected to amplification processing, etc., if necessary, and then input to an antenna (not shown), from which it is radiated into space as a radio wave.

[0029] FIG. 2 is a functional block diagram showing a schematic configuration of the receiving side device 3 that constitutes the wireless communication system 1 that executes the clock recovery method according to the embodiment of the present invention.

[0030] The receiving device 3 has a roll-off filter 31, a phase error detector 32, a low-pass filter 33, a numerically controlled oscillator 34, a multiplier 35, a demapping unit 36, and a synchronization detector 37 as components particularly relevant to the present invention.

[0031] The roll-off filter 31, phase error detection unit 32, low-pass filter 33, numerically controlled oscillator 34, and multiplier 35 of the receiving device 3 constitute a clock recovery circuit that recovers a clock signal (in other words, a sampling clock) from the received signal (i.e., the modulated signal transmitted from the transmitting device 2) to be used when demodulating the received signal.

[0032] The clock recovery circuit (including multiplier 35) receives as input an in-phase baseband signal and a quadrature-phase baseband signal (both analog signals) whose phases are orthogonal to each other, which are obtained by performing quadrature detection processing on an intermediate frequency (IF) signal that is frequency-converted from a radio frequency (RF) radio signal (received wave signal) received via an antenna (not shown). In the description of the embodiment, the in-phase component and the quadrature component are not particularly distinguished from each other and are described as being common to both, and in the drawings, the in-phase component signal and the quadrature component signal are represented by a single signal line.

[0033] The roll-off filter 31 (ROF: Roll-Off Filter) is configured by a low-pass filter (LPF: Low Pass Filter) realized as a finite-length impulse response, receives the in-phase component and quadrature component digital signals output from the multiplier 35, performs band-limiting processing on each of the digital signals, and outputs the resulting signals.

[0034] The phase error detection unit 32 receives the digital signals of the in-phase and quadrature components output from the roll-off filter 31, detects the phase error of each of the digital signals (i.e., the phase error / deviation of the digital signal relative to the ideal phase), and outputs a signal indicating the phase error.

[0035] Specifically, the phase error detection unit 32 detects the deviation of the sampling phase in the multiplier 35 from the optimum point as a phase error by detecting the timing at which the amplitude passes zero in the eye pattern of the signal amplitude (also called an "eye diagram"; see FIG. 5) (in other words, the timing at which the sign of the baseband signal is inverted; also called a "zero-crossing point"), and outputs a signal indicating the phase error. The phase error detection unit 32 synchronizes the symbol timing by adjusting the sampling timing so that the zero-crossing point, which is the midpoint of a predetermined time interval (i.e., one symbol period), comes at an amplitude of zero (or near zero).

[0036] The low pass filter (LPF) 33 receives the signal indicating the phase error output from the phase error detection unit 32, performs band limiting processing on the signal indicating the phase error, and outputs the result (specifically, removes high frequency components and passes only low frequency components).

[0037] A numerically controlled oscillator (NCO) 34 receives the signal indicating the phase error output from the low-pass filter 33, and outputs a clock having a frequency according to the value of the phase error as a sampling clock.

[0038] The multiplier 35 receives the baseband signals (note that they are analog signals) of the in-phase and quadrature components that are input to the clock recovery circuit, as well as the sampling clock output from the numerically controlled oscillator 34, and performs sampling processing on each of the baseband signals based on the sampling clock, converting them into digital signals of the in-phase and quadrature components and outputting them.

[0039] The demapping unit 36 ​​receives the digital signal output from the clock recovery circuit (including the roll-off filter 31), performs demapping processing on the digital signal on a constellation determined by a predetermined digital orthogonal modulation method (i.e., the inverse processing of the mapping processing in the mapping unit 24 of the transmitting device 2), and then performs demodulation processing on the digital signal, outputting it as a signal frame (a bit string signal).

[0040] The synchronization detection unit 37 receives the signal frame output from the demapping unit 36 ​​and performs a process of detecting and determining whether the phase is synchronized or not by detecting a known pattern such as a unique word (UW) for clock synchronization processing contained in the header of the signal frame.

[0041] (Clock synchronization processing) In the clock recovery method according to the embodiment, a transmitting device 2 transmits a data pattern in which two consecutive symbols have the same symbol point as a synchronization signal, and a receiving device 3 receives the synchronization signal and uses the synchronization signal to synchronize the clock timing.

[0042] FIG. 3 is a diagram for explaining an outline of a procedure for clock synchronization processing between a transmitting device 2 and a receiving device 3 that constitute a wireless communication system 1 that executes a clock recovery method according to an embodiment.

[0043] During clock synchronization processing, the synchronization data generator 21 of the transmitting device 2 generates and outputs, as a synchronization signal, a data pattern in which two consecutive symbols have the same symbol point.

[0044] An example of a data pattern in which two consecutive symbols have the same symbol point is shown in Fig. 4. As shown in the example of Fig. 4, synchronization data generating unit 21 includes, for example, signal generator 211 that generates data that enables symbol mapping once every two symbol periods, and S / P converter 212 (Serial-to-Parallel converter). Specifically, a PN (Pseudo Random Noise) code generator may be used as signal generator 211 in consideration of randomization.

[0045] The input side of the changeover switch 22 is connected to the synchronization data generating unit 21 during clock synchronization processing.

[0046] Then, a synchronization signal is transmitted from the transmitting device 2 to the receiving device 3 .

[0047] The receiving device 3 performs clock synchronization processing using the synchronization signal transmitted from the transmitting device 2, and when the synchronization detection unit 37 determines that the phases are synchronized, it transmits a signal (called a "synchronization completion notification signal") to the transmitting device 2 notifying that clock synchronization in the receiving device 3 has been completed.

[0048] Since clock synchronization is established, the receiving device 3 can obtain information in the header of the received signal. Therefore, if the header of the received signal contains information identifying it as a synchronization signal, the receiving device 3 may receive the synchronization signal and transmit a synchronization completion notification signal to the transmitting device 2, indicating that clock synchronization has been completed.

[0049] Here, the receiving device 3 establishes symbol synchronization using a zero-crossing detection method that detects the timing at which the amplitude passes zero in the signal amplitude eye pattern (see FIG. 5) (in other words, the timing at which the sign of the baseband signal is inverted; called the "zero-crossing point"). Specifically, the phase error detection unit 32 of the receiving device 3 sets the midpoint of a predetermined time interval (i.e., one symbol period) as the zero-crossing point, and establishes symbol timing synchronization by adjusting the sampling timing so that the zero-crossing point is at an amplitude of zero (or near zero).

[0050] As shown in Figure 5(A), when the roll-off rate is high, the zero-crossing points are clear and can be easily detected. On the other hand, as shown in Figure 5(B), when the roll-off rate is low, the zero-crossing points become unclear because jitter causes large fluctuations in the zero-crossing points, making detection difficult, and as a result, stable symbol synchronization may not be achieved.

[0051] The difference in the frequency characteristics of the roll-off filter due to differences in the roll-off rate (specifically, the difference in the shape of the frequency function H(f)) is shown in Figure 6. Figure 6 confirms that the roll-off rate α has little effect when the frequency components of the signal pattern are equal to or less than half the symbol frequency f0 (i.e., between -f0 / 2 and f0 / 2). This is also advantageous for noise reduction.

[0052] According to the characteristics shown in Fig. 6, when a data pattern in which the same symbol point occurs for two consecutive symbols is transmitted from transmitting-side device 2 as a synchronization signal, the signal in which the same symbol point occurs for two consecutive symbols mainly consists of signals in the vicinity of zero frequency f in Fig. 6, so that even when filtered by a roll-off filter, the region that is cut off is small and no significant change occurs, making the signal less susceptible to the effects of differences in the roll-off rate α of the roll-off filter. In other words, by transmitting a data pattern in which the same symbol point occurs for two consecutive symbols as a synchronization signal from transmitting-side device 2, the frequency component at 1 / 2 the symbol frequency f0 is a signal that is less susceptible to the effects of a low roll-off rate α, making it possible to easily detect the zero-crossing points without relying on the roll-off rate α.

[0053] Specifically, for example, when a data pattern in which the same symbol point occurs for two consecutive symbols is transmitted from the transmitting device 2 as a synchronization signal, the difference in the zero crossing point due to differences in the roll-off rate is small, as shown in FIG. 7, and the difference is clear whether the roll-off rate is high (see FIG. 7(A)) or low (see FIG. 7(B)), making it possible to easily detect it.

[0054] The frequency spectrum shape of the signal output from the roll-off filter is shown below. 10 The figure (A) shows a typical frequency spectrum shape. The figure (B) shows a frequency spectrum shape when a data pattern is used in which the same symbol point is used for two consecutive symbols. Note that the roll-off rate in both figures (A) and (B) is 0.05.

[0055] When the transmitting device 2 receives the synchronization completion notification signal transmitted from the receiving device 3, it switches the connection of the input side of the changeover switch 22 from the connection with the synchronization data generator 21 to the connection with the transmission system for normal signals.

[0056] The changeover switch 22 may be configured to switch to connection with the transmission system for normal signals after a predetermined time has elapsed since connection with the synchronization data generator 21. In this case, the predetermined time is appropriately set to an appropriate time length [seconds], taking into consideration, for example, the time length [seconds] expected to be required for clock synchronization in the receiving device 3. In this case, information identifying the synchronization signal may not be included in the header.

[0057] Then, a normal signal is transmitted from the transmitting device 2 to the receiving device 3 .

[0058] The clock synchronization process may be performed only at the start of each communication, or may be performed repeatedly at predetermined time intervals in addition to at the start of communication.

[0059] (Clock synchronization process when the line is disconnected) In the clock recovery method according to the embodiment, when a line disconnection occurs after clock timing synchronization has been established, the receiving device 3 performs clock timing synchronization processing using the phase error stored before the line disconnection occurred.

[0060] Figure 8 is a diagram illustrating an overview of the procedure for clock synchronization processing when a line disconnection (e.g., momentary disconnection) occurs between a transmitting device 2 and a receiving device 3 that constitute a wireless communication system 1 that executes a clock recovery method related to an embodiment (specifically, for example, when header information of a received signal cannot be obtained).

[0061] FIG. 9 is a functional block diagram for explaining the processing contents, particularly in the receiving side device 3, related to the clock synchronization processing when the line is disconnected as shown in FIG.

[0062] The receiving device 3 also has a memory 38 and a changeover switch 39 as components for performing clock synchronization processing especially when the line is disconnected.

[0063] The low-pass filter 33 includes a multiplier 331 , an adder 332 , and a delay unit 333 .

[0064] Multiplier 331 receives the signal indicating the phase error output from phase error detector 32, multiplies the signal indicating the phase error by a predetermined filter coefficient set in advance, and outputs the result.

[0065] Adder 332 receives the signal output from multiplier 331 as an input, and also receives the signal output from delay unit 333 via changeover switch 39, adds the two signals together, and outputs the result.

[0066] Alternatively, the adder 332 receives the signal output from the multiplier 331 as an input, and also receives the signal stored in the memory 38 via the changeover switch 39, adds the two signals together, and outputs the result.

[0067] Delay unit 333 receives the signal output from adder 332, delays the signal by a predetermined time, and outputs the delayed signal. The predetermined time is set to a time length equivalent to one sampling period / one symbol period based on the sampling clock, for example.

[0068] The memory 38 receives the signal output from the delay device 333 and stores the signal.

[0069] The changeover switch 39 has one end (specifically, the output side) connected to the adder 332, and the other end (specifically, the input side) switched so as to be connected to the output side of the delay unit 333 or to the memory 38.

[0070] When clock synchronization processing is performed, the input side of the changeover switch 39 is connected to the output side of the delay device 333 , and the output side of the delay device 333 is connected to the adder 332 .

[0071] When clock synchronization is established by the clock synchronization process (specifically, for example, when the header information of the received signal can be obtained), the receiving device 3 stores the value (specifically, the phase error) output from the low-pass filter 33 in memory 38.

[0072] The value to be stored in memory 38 (specifically, the phase error) is the value at the start of communication, which is stored when clock synchronization processing using a synchronization signal transmitted from the transmitting device 2 is performed at the start of each communication.

[0073] The value (specifically, the phase error) stored in memory 38 may also be a value obtained by normal clock synchronization processing (i.e., without using a synchronization signal transmitted from transmitting device 2) stored at a predetermined time interval and updated at the predetermined time interval.

[0074] The value (specifically, the phase error) to be stored in memory 38 may also be updated each time the clock synchronization process using the synchronization signal transmitted from the transmitting device 2 is repeated at a predetermined time interval in addition to at the start of each communication.

[0075] If a line disconnection occurs after clock synchronization has been established, the receiving device 3 attempts to recover the clock by performing clock synchronization processing using the value (specifically, the phase error) stored in memory 38. At this time, the input side of the changeover switch 39 is connected to the memory 38, and the value stored in memory 38 is supplied to the low-pass filter 33 (specifically, the adder 332).

[0076] Although clock synchronization processing is performed using the values ​​stored in memory 38, if clock synchronization cannot be established by processing using the values ​​stored in memory 38 even after a predetermined time has passed since the line was disconnected (specifically, for example, if information on the header of the received signal cannot be obtained), the receiving device 3 requests the transmitting device 2 to send a synchronization signal.

[0077] When the transmitting device 2 receives a request to send a synchronization signal from the receiving device 3, it switches the connection of the input side of the changeover switch 22 from the connection with the normal signal transmission system to the connection with the synchronization data generation unit 21.

[0078] Then, a synchronization signal is transmitted from the transmitting device 2 to the receiving device 3 .

[0079] The receiving device 3 performs clock synchronization processing using the synchronization signal transmitted from the transmitting device 2, and when the synchronization detection unit 37 determines that the phases are synchronized, it transmits a synchronization completion notification signal to the transmitting device 2.

[0080] When the transmitting device 2 receives the synchronization completion notification signal transmitted from the receiving device 3, it switches the connection of the input side of the changeover switch 22 from the connection with the synchronization data generator 21 to the connection with the transmission system for normal signals.

[0081] Then, a normal signal is transmitted from the transmitting device 2 to the receiving device 3 .

[0082] According to the clock recovery method and wireless communication system 1 of the embodiment, clock timing synchronization processing is performed using a data pattern in which two consecutive symbols have the same symbol point. Since a signal with the same symbol point for two consecutive symbols is a signal that is less susceptible to differences in the roll-off rates of the roll-off filters, it is possible to improve the pull-in performance of clock timing synchronization.

[0083] According to the clock recovery method and wireless communication system 1 of the embodiment, the clock timing synchronization process is performed using the phase error stored before the line disconnection occurs, so that the clock synchronization process can be performed quickly when the line disconnection occurs.

[0084] According to the clock recovery method and wireless communication system 1 of the embodiment, a synchronization signal is transmitted when a predetermined time has elapsed since a line disconnection occurred, so that clock synchronization processing can be performed appropriately without taking unnecessary time when a line disconnection occurs.

[0085] The above describes an embodiment of the present invention, but the specific configuration is not limited to the above embodiment, and even if there are design changes within the scope of the present invention that do not deviate from the gist of the present invention, they are included in the present invention.

[0086] For example, in a data pattern in which two consecutive symbols have the same symbol point, the out-of-band characteristics are slightly increased as shown in FIG. 10 (in the example shown in FIG. 10, the power [dBm] is slightly increased particularly in the ranges of approximately −30 to −20 [MHz] and 20 to 30 [MHz]). Therefore, if the transmission spectrum mask is not satisfied as a wireless communication system, a filter may be added to the transmission system. Specifically, for example, as shown in FIG. 11, the modulation unit 25 of the transmitting side device 2 may be configured to include a roll-off filter 251, a low-pass filter 252, a changeover switch 253, and a quadrature modulator 254. The roll-off filter 251 performs band limiting processing on the signal output from the mapping unit 24 and outputs the signal. The low-pass filter 252 is configured to suppress the out-of-band characteristics of the signal output from the roll-off filter 251 to improve the spectrum mask (in other words, to satisfy the spectrum mask). Changeover switch 253 connects the output side of low-pass filter 252 to the input side of quadrature modulator 254 (the state shown in FIG. 11) during clock synchronization processing (i.e., when a synchronization signal is transmitted), and connects the output side of roll-off filter 251 to the input side of quadrature modulator 254 when clock synchronization is completed and a normal signal is to be transmitted. Quadrature modulator 254 quadrature-modulates the signal output from roll-off filter 251 or low-pass filter 252 and outputs the result. By configuring modulation section 25 of transmitting side device 2 in this manner, filtering is performed on the synchronization signal by low-pass filter 252, and therefore the spectrum mask is improved when transmitting a data pattern in which the same symbol point occurs in two consecutive symbols. [Explanation of symbols]

[0087] 1. Wireless communication systems 2. Sending device 21 Synchronization data generation unit 211 Signal Generator 212 S / P converter 22 Selector switch 23 Header Addition Section 24 Mapping section 25 Modulation section 251 Roll-off Filter 252 Low-pass filter 253 Switch 254 Quadrature Modulator 3. Receiving device 31 Roll-off filter 32 Phase error detection section 33 Low-pass filter 331 Multiplier 332 Adder 333 Delay Device 34 Numerically Controlled Oscillator 35 Multiplier 36 Demapping section 37 Synchronous detection section 38 memory 39 Changeover switch

Claims

1. The transmitting device transmits a data pattern in which two consecutive symbols have the same symbol point as a synchronization signal, a receiving device receives the synchronization signal and performs a process of synchronizing the timing of a clock by a zero-cross detection method using the synchronization signal; The frequency component of the synchronization signal is equal to or less than half the symbol frequency. A clock recovery method comprising:

2. If a line disconnection occurs after the clock timing synchronization is established, the receiving device performs a process of synchronizing the timing of the clock using the phase error stored before the line disconnection occurred; 2. The clock recovery method according to claim 1.

3. If clock timing synchronization cannot be established even after a predetermined time has elapsed since the line disconnection occurred, the receiving device requests the transmitting device to transmit the synchronization signal; 3. The clock recovery method according to claim 2.

4. The transmitting device performs filtering on the synchronization signal.

4. The clock recovery method according to claim 1, wherein the clock recovery method is a clock recovery method for recovering a clock signal from a clock signal.

5. Executing the clock recovery method according to any one of claims 1 to 4 A wireless communication system comprising:

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