Physical layer transceiver to reduce variation in packet latency

Abstract

A method of reducing the effects of variation in latency in data transfer between clock domains of a physical layer transceiver, the physical layer transceiver comprising physical coding sublayer circuitry having a first clock in a first clock domain and physical medium attachment circuitry having a second clock in a second clock domain, comprising: during initial training of the link, determining a transmit latency value in a transmission direction from the first clock domain to the second clock domain; during initial training of the link, separately from determining the transmit latency value, determining a receive latency value in a reception direction from the second clock domain to the first clock domain; and using the transmit latency value and the receive latency value to calculate latency in data transfer between the first clock domain and the second clock domain after the initial training until a subsequent training.

Description

[0001] Cross-references to related applications

[0002] This disclosure claims the benefit of co-pending, co-assigned U.S. Provisional Patent Application No. 63 / 164,351, filed March 22, 2021, which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to an Ethernet physical layer transceiver in which packet latency variation is reduced. More specifically, this disclosure relates to an Ethernet physical layer transceiver in which packet latency can be calibrated to a known value, thereby reducing latency variation and enhancing the ability to compute latency. Background Technology

[0004] The background description provided herein is intended to generally present the context of this disclosure. The work of the inventors, with respect to the work described in this background section and descriptions that may not conform to prior art at the time of submission, neither explicitly nor implicitly acknowledges any prior art as the subject matter of this disclosure.

[0005] An Ethernet physical layer transceiver (PHY) consists of a Physical Coding Sublayer (PCS) connected to the local “host” device and a Physical Media Access (PMA) layer connected to the Ethernet channel. These two parts of the PHY constitute two independent clock domains operating at different clock rates. For example, for 10Gb Ethernet (10GBASE-T), the PCS clock operates at 312.5MHz, while the PMA clock operates at 800MHz. Because these two clock rates are not multiples of each other, even if they are derived from a common clock source, their edges only overlap very occasionally. Furthermore, the interval between the edges of the two different clocks varies continuously between these instances. In one implementation, the PCS and PMA logic can operate as parallel data paths running at divided clock rates of 312.5MHz and 800MHz, respectively. For example, the PCS can be designed to operate with two parallel data paths, each with a clock rate of 156.25MHz.

[0006] Training an Ethernet link between two PHYs involves establishing the delay experienced by packets traversing the link, which is reflected in the difference between the timestamp placed on the packet when it is received by the receiving link partner PHY and the timestamp placed on the packet when it is transmitted by the originating link partner PHY. The delay (if known) can be calculated by adjusting the timestamps. However, since packets originate in the 312.5MHz PCS time domain of one PHY and eventually land in the 312.5MHz PCS time domain of another PHY, the delay can vary due to delay variations across time domain boundaries for the reasons discussed above. Because of this delay variation, it can be difficult to determine the required timestamp adjustment. Furthermore, even if the delay variation can be determined, it may change if one or both PHYs are reset. Therefore, it is difficult to calculate packet delay across time domain boundaries because the delay variation makes it difficult to know what the required delay correction is. Summary of the Invention

[0007] According to an implementation of the subject matter of this disclosure, a method for reducing the impact of latency variations in data transmission between clock domains of a physical layer transceiver, the physical layer transceiver including a physical coding sublayer circuit system having a first clock in a first clock domain and a physical medium connection circuit system having a second clock in a second clock domain, includes: determining a transmission latency value in the transmission direction from the first clock domain to the second clock domain during initial training of the link; determining a reception latency value in the reception direction from the second clock domain to the first clock domain separately from determining the transmission latency value during initial training of the link; and using the transmission latency value and the reception latency value to calculate the latency in data transmission between the first clock domain and the second clock domain after initial training until subsequent training.

[0008] In a first implementation of this method, determining the transmission delay value in the transmission direction may include: simultaneously resetting the first clock and the second clock, and starting to transmit data from the first clock domain to the second clock domain at a predetermined period of one of the first clock and the second clock.

[0009] According to a first aspect of the first implementation, transmitting data from the first clock domain to the second clock domain at a predetermined period of one of the first clock and the second clock may include: transmitting data from the first clock domain to the second clock domain at a predetermined period of the second clock.

[0010] In a second implementation of this method, determining the reception delay value in the reception direction may include resetting the first clock simultaneously with the detection of a received data frame.

[0011] According to the first aspect of the second implementation, detecting a received data frame may include the recovery of a frame start signal.

[0012] In a third implementation of this method, determining the reception delay value in the receiving direction may include: detecting the start of the received data frame, identifying the number of unit intervals of the first clock that have elapsed from the most recent simultaneous reset of the first clock and the second clock to the start of the received data frame, and retrieving the stored delay value corresponding to the number of unit intervals as the reception delay value.

[0013] According to the first aspect of the third implementation, the retrieval may include using the number as an index to retrieve the receive delay value from the lookup table.

[0014] A first instance of the first aspect may also include: establishing a lookup table during the calibration operation prior to detection.

[0015] In a first variant of this first instance, the calibration operation may include: separately measuring the reception delay when a data frame is received in each of the plurality of unit intervals of the first clock.

[0016] In a second variation of the first instance, the calibration operation may include: simulating the reception of data frames in each of the plurality of unit intervals of the first clock, and simulating the measurement of the reception delay in each of the plurality of unit intervals.

[0017] In a fourth implementation of this method, determining the transmission delay value in the transmission direction may include: establishing a synchronization pulse at the alignment of the first clock and the second clock, and aligning the transmission frame boundary with the synchronization pulse to fix the transmission delay value.

[0018] In a fifth implementation of this method, determining the reception delay value in the receiving direction may include: establishing a synchronization pulse at the alignment of the first clock and the second clock, and counting the number of time intervals from the synchronization pulse to the boundary of the received frame as the transmission delay value.

[0019] In a sixth implementation of this method, using transmission delay values ​​and reception delay values ​​to calculate the delay in data transmission between the first clock domain and the second clock domain may include adjusting the timestamps of data packets transmitted between the first clock domain and the second clock domain.

[0020] According to an implementation of the subject matter of this disclosure, a physical layer transceiver includes: a physical coding sublayer circuit system and a physical medium connection circuit system, the physical coding sublayer circuit system being configured to transmit data between a host device and the physical medium connection circuit system, and the physical medium connection circuit system being configured to transmit data between the physical coding sublayer circuit system and a channel medium; and a clock and control circuit system configured to provide a clock standard to the physical coding sublayer circuit system and the physical medium connection circuit system, the clock standard being converted into a first clock for a first clock domain of the physical coding sublayer circuit system and a clock for the physical medium connection circuit system. The second clock of the second clock domain of the physical medium connection circuit system, and the clock and control circuit system are further configured to reduce the impact of delay variations in data transmission between the first clock domain and the second clock domain by: determining a transmission delay value in the transmission direction from the first clock domain to the second clock domain during the initial training of the link; determining a reception delay value in the reception direction from the second clock domain to the first clock domain during the initial training of the link; and using the transmission delay value and the reception delay value to calculate the delay in data transmission between the first clock domain and the second clock domain after the initial training until subsequent training.

[0021] In a first implementation of such a physical layer transceiver, the clock and control circuitry can be configured to determine the transmission delay value in the transmission direction by simultaneously resetting a first clock and a second clock, and to begin transmitting data from the first clock domain to the second clock domain at a predetermined period of one of the first and second clocks.

[0022] According to a first aspect of the first implementation, the clock and control circuit system can be configured to: transmit data from the first clock domain to the second clock domain starting at a predetermined period of either the first clock or the second clock domain by transmitting data from the first clock domain to the second clock domain starting at a predetermined period of the second clock.

[0023] In this second implementation of the physical layer transceiver, the clock and control circuitry can be configured to determine the receive delay value in the receive direction by resetting the first clock simultaneously with the detection of a received data frame.

[0024] According to the first aspect of the second implementation, the clock and control circuit system may further include a clock data recovery circuit system configured to recover a frame start signal when a received data frame is detected.

[0025] In this third implementation of the physical layer transceiver, the clock and control circuitry system can be configured to determine the receive delay value in the receive direction by detecting the start of the received data frame, identifying the number of unit intervals of the first clock that have elapsed from the most recent simultaneous reset of the first clock and the second clock to the start of the received data frame, and retrieving the stored delay value corresponding to the number of unit intervals as the receive delay value.

[0026] According to the first aspect of the third implementation, the clock and control circuitry system can be configured to use the number as an index to retrieve the receive delay value from a lookup table.

[0027] According to the second aspect of this third implementation, the clock and control circuitry system can be configured to establish a lookup table during calibration operations.

[0028] In a first example of the second aspect, the clock and control circuitry system can be configured to establish a lookup table by measuring the reception delay when a data frame is received in each of a plurality of unit intervals of a first clock, and storing the measured reception delay for each of the plurality of unit intervals in the lookup table.

[0029] In a second example of the second aspect, the clock and control circuitry system can be configured to establish a lookup table by simulating the reception of data frames in each unit interval of a plurality of unit intervals of a first clock, simulating the measurement of the reception delay for each unit interval of the plurality of unit intervals, and storing the simulated measured reception delay for each unit interval of the plurality of unit intervals in the lookup table.

[0030] In a fourth implementation of such a physical layer transceiver, the clock and control circuitry can be configured to determine the transmission delay value in the transmission direction by establishing a synchronization pulse at the alignment of the first and second clocks and aligning the transmission frame boundary with the synchronization pulse to fix the transmission delay value.

[0031] In this fifth implementation of the physical layer transceiver, the clock and control circuitry can be configured to determine the receive delay value in the receive direction by establishing a synchronization pulse at the alignment of the first and second clocks and counting the number of time intervals from the synchronization pulse to the boundary of the receive frame as the transmission delay value.

[0032] In this sixth implementation of the physical layer transceiver, the clock and control circuitry can be configured to: adjust the timestamps of data packets transmitted between the first and second clock domains after initial training and before subsequent training by using transmission and reception delay values, and calculate the delay in data transmission between the first and second clock domains to reduce the impact of delay variations in data transmission between the first and second clock domains. Attached Figure Description

[0033] Further features, nature, and various advantages of this disclosure will become apparent upon consideration of the following detailed description in conjunction with the accompanying drawings, wherein like reference numerals refer to like parts throughout, and wherein:

[0034] Figure 1 This is a simplified block diagram of a physical layer transceiver implemented according to the subject matter of this disclosure;

[0035] Figure 2 The illustration shows how delay variations are introduced during the exit or transmission of data frames across clock domain boundaries;

[0036] Figure 3 The illustration shows how delay variations are introduced during the ingress or reception of data frames that cross clock domain boundaries;

[0037] Figure 4 This is a timing diagram illustrating a first implementation of the subject matter of this disclosure;

[0038] Figure 5 This is a timing diagram illustrating a second implementation of the subject matter of this disclosure; and

[0039] Figure 6 It is a flowchart illustrating a method for implementing the subject matter of this disclosure. Detailed Implementation

[0040] As noted above, training an Ethernet link between two PHYs involves establishing the latency experienced by packets traversing the link. This is reflected in the difference between the timestamp placed on the packet when it is received by the receiving link partner PHY and the timestamp placed on the packet when it is transmitted by the originating link partner PHY. However, since packets originate in the 312.5MHz PCS time domain of one PHY and ultimately fall into the 312.5MHz PCS time domain of the other PHY, the latency can vary due to latency variations across time domain boundaries for the reasons discussed above. Furthermore, even if the latency variation can be determined, and therefore the latency can be determined, the latency variation may change if one or both PHYs are reset. Due to the variation in packet latency, it is difficult to calculate packet latency.

[0041] According to the implementation of the subject matter of this disclosure, packet delay variation can be calculated by processing transmission delay and reception delay separately.

[0042] In the transmission direction, the PCS 312.5MHz clock and the PMA 800MHz clock are both under the control of the local PHY and locked together. There are several methods to generate the locked 312.5MHz and 800MHz clocks. For example, a higher frequency (e.g., 3.2GHz) master clock source can be used, and the generated clock output can be divided using a clock divider or state machine logic to provide an average clock frequency of 312.5MHz and 800MHz. In this case, the clock edge relationship between the 312.5MHz and 800MHz clocks repeats after a fixed number of clock cycles. Specifically, the two clocks are expected to align once every 256 cycles of the 800MHz clock. A synchronization pulse (“sync_pulse”) can be generated once every 256 cycles of the 800MHz clock. Therefore, if the position of the transmitted data frame boundary is established and aligned with this synchronization pulse, the contribution of the time domain boundary crossover to the transmission packet delay will remain unchanged—even during power-down / power-on cycles or hardware reset cycles—as long as the alignment of the sync_pulse and the transmitted data frame boundary is re-established. However, while the contribution to delay is constant, it may not be zero, but could be as high as 0.3125 ns due to the irregularity of the 312.5 MHz PCS clock. However, the contribution of local time-domain boundary crossings to the transmitted data delay is likely known, thus reducing delay variation.

[0043] Determining the latency in the receive direction is more complex because latency variations can be influenced by both the local PHY and the remote link partner PHY. For example, latency variations in the receive direction can include components such as the phase difference between the 800MHz clock of the local PHY and the 800MHz clock of the remote link partner PHY (which can be as high as 1.25ns in some implementations), as well as the effects of clock domain crossover in the remote link partner PHY and the local PHY (contributing up to 3.2ns of latency at each PHY for a single data path PCS with a 312.5MHz clock). For a single data path PCS with a 312.5MHz clock, the total latency variation can be as high as 3.2 + 3.2 + 1.25 + 0.3125 = 7.96ns. In other implementations with 2x data path PCS, the total latency variation can be as high as 6.4 + 6.4 + 1.25 + 0.3125 = 14.36ns.

[0044] According to the first implementation, on the transmission side, the hardware is reset or restarted at a point where the 312.5MHz PCS clock and the 800MHz PMA clock always have a constant fixed phase relationship (e.g., the aforementioned sync_pulse position), and since the LPDC frame always begins in the first cycle of the 800MHz PMA clock after the hardware is restarted, a constant fixed delay can be established at the time domain boundary crossover. On the receiving side, according to the first implementation, the 312.5MHz PCS clock generation logic is restarted when the start of a received LDPC frame is detected. This restart of the 312.5MHz PCS clock ensures that the PCS clock and the PMA clock have a constant fixed phase relationship. After this alignment, the clock domain crossover delay from the start of the LDPC frame in the PMA clock domain to the start of data in the PCS clock domain is then fixed on each reset of the link connection.

[0045] According to the second implementation, on the receiving side, for each unit interval of the PMA clock (e.g., 256 unit intervals of an 800MHz PMA clock, with an LDPC frame lasting 320ns), delay values ​​are collected via actual measurement or via simulation, and these delay values ​​are stored, for example, in a lookup table. When a Start-of-Frame (SOF) or "Rx blip" signal is detected for a received frame, the interval between "Rx blip" and the next sync_pulse is identified and used as an index to retrieve the stored delay value, which is used as the delay value from that point to the next clock reset event. This delay value can be used for compensation or calibrated by adjusting a fixed timestamp.

[0046] Therefore, since the latency variation is reduced or eliminated, the need to determine the latency each time a new frame arrives is reduced or eliminated, and the previously determined latency value can be used for latency compensation (e.g., using timestamp adjustment).

[0047] You can refer to Figures 1-6 To better understand the subject matter of this disclosure.

[0048] Figure 1 This is a simplified block diagram of a PHY 100 in which the subject matter of this disclosure can be implemented. The PHY 100 includes a Physical Coding Sublayer (PCS) circuit system module 101 communicating with a local “host” device (not shown) at 111, and a Physical Medium Connection Circuit System module 102 communicating with a wired channel medium (e.g., an Ethernet cable; not shown) at 112.

[0049] PCS circuit system module 101 includes at least a control circuit system 121, an encoding / decoding circuit system 131, and a protocol logic circuit system 141, which operate on data flowing bidirectionally between the host device and PMA circuit system module 102.

[0050] PMA circuit system module 102 includes a receive path 122, a transmit path 132, and a clock / control block 142. Clock / control block 142 includes at least a control circuit system 143 and a clock source 144. Clock source 144, for example, can be a phase-locked loop (PLL) that provides a master clock for the entire PHY 100. This master clock can be used directly or divided (e.g., to provide 800MHz and 312.5MHz clocks, as described above) in each of PCS circuit system module 101 and PMA circuit system module 102.

[0051] The transmission path 132 can be relatively straightforward, with filters such as a feedforward equalizer (FFE) 133 and a digital-to-analog converter 134 to drive the transmitted signal onto the channel medium.

[0052] The receive path 122 includes at least a sampler 123, an analog-to-digital converter 124, and an equalizer 125, the output of which is fed in parallel to a digital timing loop (DTL) unit 126 and a data decision unit 127, which may include filters, such as, for example, a decision feedback equalizer (DFE) in this particular implementation. The receive path 122 is clocked by an 800 MHz clock from a phase-locked loop (PLL) 144. The DTL unit 126 provides timing information back to the PLL 144 for clock data recovery and allows the sample hold to be locked.

[0053] Figure 2The diagram illustrates how delay variations are introduced during the exit or transmission of data in a low-density parity-check (LDPC) frame across clock domain boundaries 200 in transmission path 132. In the figures, the 312.5 MHz clock domain is identified as “CLK312”, and the 800 MHz clock domain is identified as “CLK800”. 64-bit data 201 (e.g., using 64B / 65B encoding 202 as described in the IEEE 802.3 standard) is encoded into 65-bit blocks. These continuous streams of 65-bit blocks are “framed” into 50 65-bit blocks 203, occupying 50 unit intervals of a 156.25 MHz clock (312.5 MHz clock divided by 2), extending over a total duration of 320 ns. Data is clocked out across boundary 200 via framer / encoder block 204, which includes a FIFO buffer and a barrel shifter (both shown), as well as auxiliary bit and parity bit insertion logic (both not shown). Framer / encoder 204 reconstructs LDPC frames from 50 65B blocks, occupying 64 unit intervals and extending over a total duration of 320ns, using a 200MHz clock (800MHz clock divided by 4). As data crosses boundary 200 via the FIFO buffer of framer / encoder 204, it is clocked in into the FIFO buffer according to a 312.5MHz clock, but clocked out from the FIFO buffer according to an 800MHz clock, with its edges having a varying relationship to the edges of the 312.5MHz clock, as noted above. The clock edge relationship is determined in framer / encoder 204, which also defines the start of frame (SOF) of the 50 65B blocks. As a result, unless corrected by an implementation of the subject matter according to the invention, depending on the relative positions of the edges of the two clocks, different data blocks will leave the FIFO of the framer / encoder 204 after spending different durations within the FIFO, resulting in delay variations and causing interruptions in the data.

[0054] Similarly, at the entry or receiving side of receiving path 122, such as Figure 3As shown, a 320ns LDPC frame 301 is formed from the incoming data stream, occupying 64 unit intervals over a 200MHz clock cycle (800MHz clock divided by 4), with SOF detection potentially being an Rx blip. This LDPC frame is timed to enter across boundary 200 via the FIFO buffer of the framebreaker / decoder 302 and reconstructed into 50 65-bit blocks 303, occupying 50 unit intervals over a 156MHz clock cycle (312.5MHz clock divided by 2), extending over a total duration of 320ns. The 65-bit data (e.g., using 64B / 65B decoding 304) is decoded into 64-bit data 305. When data crosses boundary 200 via the FIFO buffer of the framebreaker / decoder 302, it is timed to enter the FIFO buffer according to an 800MHz clock, but timed to exit the FIFO buffer according to a 312.5MHz clock, with its edges having a varying relationship to the edges of the 800MHz clock, as noted above. Similar to the exit path, LPDC frames are formed from the continuously incoming data stream, and the clock edge relationship between the two clocks is determined in the framebreaker / decoder 302. As a result, unless corrected according to an implementation of the subject matter of this disclosure, depending on the relative positions of the edges of the two clocks, different data blocks will spend different durations within the FIFO buffer of the framebreaker / decoder 302 before leaving the FIFO buffer, resulting in latency variations and causing interruptions in the data.

[0055] According to the implementation of the subject matter of this disclosure, by treating the contribution of delay variation in the transmission (egress) direction separately from the contribution of delay variation in the reception (ingress) direction, delay variation can be calculated each time the link is trained—for example, at power-on or after hardware reset.

[0056] In the transmission (egress) direction, both the 312.5MHz and 800MHz clocks are local to the transmission PHY. Therefore, for the 3.2GHz master clock, if both clocks are reset simultaneously, their edges will be aligned and will always realign after approximately 320ns (100 unit intervals for the 312.5MHz clock and 256 unit intervals for the 800MHz clock). Thus, the contribution to delay variation at the transmission end can be minimized by simultaneously resetting both clocks; however, in some implementations, irregularities in the 312.5MHz clock can lead to a delay variation of up to 0.3125ns from the transmission end. However, even if delay exists, the amount of delay is known and does not change.

[0057] The receiving (ingress) direction is more complex. The receiver PMA module and the remote transmitter PMA module are located in the same clock domain—that is, the channel's clock domain—so the two PMA clocks are aligned within a unit interval (i.e., within 1.25ns at 800MHz). However, the 312.5MHz clock at the remote transmitter PCS module and the 312.5MHz clock at the receiver PCS module cross the boundary between the two clock domains, which can introduce a delay of approximately 6.4ns. Specifically, for a PCS implementation with 2x data paths, the resulting delay variation could be as much as one unit interval of the aforementioned 156.25MHz clock (312.5MHz clock divided by 2), i.e., approximately 6.4ns for each boundary crossing, for a total possible delay variation of 12.8ns.

[0058] In the first implementation in the transmission direction, the framer / encoder 204 is reset or restarted at a constant fixed phase relationship point between the 312.5MHz PCS clock and the 800MHz PMA clock (or sync_pulse), and since the LDPC frame always begins in the first cycle of the 800MHz PMA clock after the clock start, a constant fixed delay is established at the time-domain boundary crossing of the first data of the 50 65B blocks to the SOF of the LDPC frame. In the reception direction, the detection of the start of the received LDPC frame is used as a trigger to reset the 312.5MHz PCS clock while keeping the 800MHz PMA clock running. The LDPC frame synchronization signal, or "Start of Frame (SOF)" or "blip signal," can be recovered from the received signal, for example, during link training, through the protocol logic circuitry system 141 in PCS 101. The delay contribution determined by the alignment of these two clocks with the blip signal remains unchanged. This reset operation can be repeated during subsequent reset events or power-off / power-on cycles to allow the delay contribution to be determined and fixed, eliminating delay variations.

[0059] In the second implementation in the receiving direction, the delay value is determined by measurement or simulation for each unit interval of the 800MHz PMA clock. Specifically, for each detected blip signal, the delay from the most recently aligned 312.5MHz PCS clock and 800MHz PMA clock is measured (by measuring the number of 800MHz PMA clock intervals between the "Rx blip" and the synchronization pulse). This determination is performed on the initial blip signal detection. During the duration of the LDPC frame, a delay value is determined for each unit interval of the 800MHz PMA clock, i.e., 256 unit intervals. These 256 delay values ​​are stored, for example, in a lookup table, and during runtime, when a blip signal is detected, the current unit interval among the 256 possibilities is identified, and the corresponding delay value is retrieved from the lookup table, thereby eliminating variations in delay by providing this delay variation information to the timestamp logic to adjust the timestamp value accordingly.

[0060] Figure 4 This is a timing diagram illustrating a first implementation of the combination in the transmission and reception directions. An 800MHz PMA clock 401 is aligned at 410 and 420 with a 312.5MHz PCS clock 402, which are aligned with corresponding LDPC frame blip signals 411 and 421 based on the received LDPC frames 412 and 422, respectively. On the transmission side, 50 65B coded data blocks 403 in the PCS clock domain are transmitted to the FIFO buffer of the framer / encoder 204 at the time of a fixed clock domain cross-delay (i.e., delay) measured before each clock alignment point, such that after the determined cross-delay 404, the resulting transmitted LDPC frame 422 begins at clock alignment point 420. On the receiving side, from that point onward, each received LDPC frame, via the FIFO buffer of the frame deframer / decoder 302, from the PMA clock domain to the PCS clock domain, begins by the blip signals 411, 421 and propagates such that each resulting group of 50 received 65B encoded data blocks begins at a time delayed by the determined cross-delay 405 from the corresponding clock alignment point 420.

[0061] Figure 5 This diagram illustrates the timing of the second implementation in the receiving direction. Based on the power-on of the PHY 100, the 800MHz PMA clock 501 is aligned with the 312.5MHz PCS clock 502 at points 510 and 520. This fixes the value of the output delay (not shown), which is similar to... Figure 4The output delay is 404. The determination of the value on the transmission side is similar to the first implementation (discussed above). On the receiving side, LDPC frames 530 and 540 are received, and the corresponding LDPC frame blip signals 511 and 521 are recovered based on the received LDPC frames 530 and 540, respectively. When the blip signals 511 and 521 are recovered, the corresponding period (n = 0, ..., 255) of the 256 cycles of the 800MHz PMA clock 501 is identified (in this case, it is the fourth period n = 3). (One way to calculate the value n is to count the number of clock intervals between the blip signals of 511 and 521 and the aforementioned sync_pulse.) The nth delay value is retrieved from the aforementioned lookup table, which has been previously filled by simulation or measurement, and the retrieved value is used as the receive delay adjustment in the timestamp logic before the next reset. The transmission and receive delay values ​​are determined only once during training and used before the next reset, and therefore there is no delay change.

[0062] Once the delay values ​​in each direction have been determined and are known to have little or no variation, they can be taken into account when transmitting data across clock domain boundaries (e.g., via control circuitry system 143). If the delays are known, then data misalignment based on clock misalignment on either side of the boundary, which may cause jitter or other artifacts, can be corrected (e.g., by adjusting the timestamps on the data packets).

[0063] The above implementation was described in conjunction with a 10Gbps link speed. However, other implementations are possible at other link speeds, and the various clock speed values ​​and latency values ​​scale linearly. Therefore, for a 5Gbps link, the PMA clock speed is 400MHz, the PCS clock speed is 156.25MHz, and the unit interval and latency duration are scaled accordingly. That is, the frame duration will be 640ns because the data volume is the same but all clocks run at half speed, which also means that the latency and any latency variations are doubled.

[0064] According to the method 600 for implementing the subject matter of this disclosure, Figure 6 The diagram is shown in the figure. Method 600 begins at 601, wherein, during the initial training of the link, in the transmission direction from the first clock domain to the second clock domain, a transmission delay value is determined for data transmission between the clock domains of a physical layer transceiver including a physical coding sublayer circuit system having a first clock in the first clock domain and a physical medium connection circuit system having a second clock in the second clock domain.

[0065] At position 602, during the initial training of the link, the receive delay value is determined in the receive direction from the second clock domain to the first clock domain.

[0066] At 603, when the new transmission and reception delay values ​​are determined, the transmission delay value and the reception delay value are used to calculate the delay in data transmission between the first clock domain and the second clock domain after the initial training and before subsequent training (e.g., by adjusting their timestamps when packets cross clock domain boundaries to calculate the determined reception delay value and / or transmission delay value). Then method 600 ends.

[0067] Therefore, it can be seen that by calibrating the packet delay to known values ​​in the transmission and reception directions respectively, a reduced packet delay variation in the Ethernet physical layer transceiver has been provided.

[0068] As used herein and in the appended claims, the construction “one of A and B” should mean “A or B”.

[0069] It should be noted that the above description only illustrates the principles of the present invention, and the present invention can be practiced in ways other than the described embodiments, which are presented for illustrative purposes rather than limiting, and the present invention is limited only by the following claims.

Claims

1. A method for reducing the impact of latency variations in data transmission between clock domains of a physical layer transceiver, the physical layer transceiver comprising a physical coding sublayer circuit system having a first clock in a first clock domain, and a physical medium connection circuit system having a second clock in a second clock domain, the method comprising: During the initial training of the link, the transmission delay value in the transmission direction from the first clock domain to the second clock domain is determined; During the initial training of the link, the receive delay value in the receive direction from the second clock domain to the first clock domain is determined separately from the determination of the transmission delay value; as well as Using the transmission delay value and the reception delay value, the latency in data transmission between the first clock domain and the second clock domain after the initial training and before subsequent training is calculated. Determining the transmission delay value in the transmission direction includes: simultaneously resetting the first clock and the second clock, and starting to transmit data from the first clock domain to the second clock domain at a predetermined period of one of the first clock and the second clock.

2. The method of claim 1, wherein beginning to transfer data from the first clock domain to the second clock domain at the predetermined period of one of the first clock and the second clock comprises: Data is transmitted from the first clock domain to the second clock domain at the predetermined period of the second clock.

3. The method of claim 1, wherein determining the receive latency value in the receive direction comprises: The first clock is reset while detecting received data frames.

4. The method of claim 3, wherein detecting the received data frame includes recovering the start-of-frame signal.

5. The method of claim 1, wherein determining the reception delay value in the receiving direction comprises: Detect the start of the received data frame; Identify the number of unit intervals of the first clock that have elapsed from the most recent simultaneous reset of the first clock and the second clock to the start of the received data frame; as well as The stored delay value corresponding to the number of unit intervals is retrieved as the receiving delay value.

6. The method of claim 5, wherein the retrieving comprises: The received delay value is retrieved from the lookup table using the number as an index.

7. The method of claim 6, further comprising: Prior to the detection, the lookup table is established during the calibration operation.

8. The method of claim 7, wherein the calibration operation comprises: The reception delay value is measured separately when a data frame is received in each of the multiple unit intervals of the first clock.

9. The method of claim 7, wherein the calibration operation comprises: Simulate the reception of data frames in each of the plurality of unit intervals of the first clock, and simulate the measurement of the reception delay value for each of the plurality of unit intervals.

10. The method of claim 1, wherein determining the transmission delay value in the transmission direction comprises: Establish a synchronization pulse at the alignment of the first clock and the second clock; as well as Align the transmission frame boundary with the synchronization pulse to fix the transmission delay value.

11. The method of claim 1, wherein determining the reception delay value in the receiving direction comprises: Establish a synchronization pulse at the alignment of the first clock and the second clock; as well as The number of time intervals from the synchronization pulse to the boundary of the received frame is used as the received delay value.

12. The method of claim 1, wherein using the transmit latency value and the receive latency value to calculate a latency in data transfers between the first clock domain and the second clock domain comprises: Adjust the timestamps of data packets transmitted between the first clock domain and the second clock domain.

13. A physical layer transceiver, comprising: A physical coding sublayer circuit system and a physical medium connection circuit system, wherein the physical coding sublayer circuit system is configured to transmit data between a host device and the physical medium connection circuit system, and the physical medium connection circuit system is configured to transmit data between the physical coding sublayer circuit system and the channel medium; as well as A clock and control circuitry system is configured to provide a clock standard to the physical coding sublayer circuitry system and the physical medium connection circuitry system. The clock standard is converted into a first clock for a first clock domain of the physical coding sublayer circuitry system and a second clock for a second clock domain of the physical medium connection circuitry system. The clock and control circuitry system is also configured to reduce the impact of latency variations in data transmission between the first clock domain and the second clock domain by: During the initial training of the link, the transmission delay value in the transmission direction from the first clock domain to the second clock domain is determined; During the initial training of the link, a reception delay value in the reception direction from the second clock domain to the first clock domain is determined; as well as Using the transmission delay value and the reception delay value, the latency in data transmission between the first clock domain and the second clock domain after the initial training and before subsequent training is calculated. The clock and control circuitry system is configured to determine the transmission delay value in the transmission direction by simultaneously resetting the first clock and the second clock, and to begin transmitting data from the first clock domain to the second clock domain at a predetermined period of one of the first clock and the second clock.

14. The physical layer transceiver of claim 13, wherein the clock and control circuitry is configured to: initiate data transmission from the first clock domain to the second clock domain at a predetermined period of one of the first clock and the second clock by initiating data transmission from the first clock domain to the second clock domain at a predetermined period of the second clock.

15. The physical layer transceiver of claim 13, wherein the clock and control circuitry is configured to determine the reception delay value in the reception direction by resetting the first clock while detecting a received data frame.

16. The physical layer transceiver of claim 15, wherein the clock and control circuitry further comprises a clock data recovery circuitry configured to recover a start-of-frame signal upon detection of the received data frame.

17. The physical layer transceiver of claim 13, wherein the clock and control circuitry is configured to determine the reception delay value in the receiving direction by: Detect the start of the received data frame; Identify the number of unit intervals of the first clock that have elapsed from the most recent simultaneous reset of the first clock and the second clock to the start of the received data frame; as well as The stored delay value corresponding to the number of unit intervals is retrieved as the receiving delay value.

18. The physical layer transceiver of claim 17, wherein the clock and control circuitry is configured to retrieve the receive delay value from a lookup table using the number as an index.

19. The physical layer transceiver of claim 18, wherein the clock and control circuitry is configured to establish the lookup table during a calibration operation.

20. The physical layer transceiver of claim 19, wherein the clock and control circuitry is configured to establish the lookup table in such a manner as follows: Measure the reception delay value when receiving a data frame in each unit interval of a plurality of unit intervals of the first clock; and The lookup table stores the measured reception delay value for each of the plurality of unit intervals.

21. The physical layer transceiver of claim 19, wherein the clock and control circuitry is configured to establish the lookup table in such a manner as follows: Simulate the reception of data frames in each of the multiple unit intervals of the first clock; Simulate the measurement of the received delay value for each of the plurality of unit intervals; as well as The lookup table stores the simulated, measured receive delay values ​​for each of the plurality of unit intervals.

22. The physical layer transceiver of claim 13, wherein the clock and control circuitry is configured to determine the transmission delay value in the transmission direction by: Establish a synchronization pulse at the alignment of the first clock and the second clock; and Align the transmission frame boundary with the synchronization pulse to fix the transmission delay value.

23. The physical layer transceiver of claim 13, wherein the clock and control circuitry is configured to determine the receive delay value in the receive direction by: Establish a synchronization pulse at the alignment of the first clock and the second clock; and The number of time intervals from the synchronization pulse to the boundary of the received frame is used as the received delay value.

24. The physical layer transceiver of claim 13, wherein the clock and control circuitry is configured to: adjust the timestamps of data packets transmitted between the first clock domain and the second clock domain after initial training and before subsequent training by using the transmission delay value and the reception delay value, and calculate the delay in data transmission between the first clock domain and the second clock domain to reduce the impact of delay variations in data transmission between the first clock domain and the second clock domain.

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