Wiring board, semiconductor device, and method of manufacturing wiring board

Abstract

To provide a wiring board capable of miniaturize pads, a semiconductor device, and a manufacturing method of the wiring board.SOLUTION: A wiring board includes: an insulation layer having a first surface; a first via hole penetrating the insulation layer; a first pad arranged in the first via hole and is exposed from the first surface; and a first wiring section which is connected to the first pad via a first via conductor arranged in the first via hole.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a wiring board, a semiconductor device, and a method for manufacturing a wiring board. [Background technology]

[0002] A wiring substrate on which a semiconductor element is flip-chip mounted is provided with a plurality of pads for flip-chip mounting. Conventionally, the pads for flip-chip mounting are formed by electrolytic plating. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2010-287742 [Patent Document 2] Japanese Patent Application Laid-Open No. 2016-178247 Summary of the Invention [Problem to be solved by the invention]

[0004] As semiconductor elements become more highly integrated, there is a demand for miniaturization of pads provided on wiring substrates.

[0005] An object of the present disclosure is to provide a wiring board, a semiconductor device, and a method for manufacturing a wiring board that allows pads to be miniaturized. [Means for solving the problem]

[0006] According to one aspect of the present disclosure, a first surface and a second surface opposite to the first surface. an insulating layer comprising: From the second surface to the first surface a first via hole penetrating the first surface; and a first pad provided in the first via hole and exposed from the first surface. a first wiring portion provided on the second surface; provided in the first via hole , connecting the first pad and the first wiring portion First via conductor and , a second pad including a third surface, a fourth surface opposite to the third surface, and a side surface between the third surface and the fourth surface, the fourth surface and the side surface being covered with the insulating layer, and the third surface being exposed from the first surface; the insulating layer penetrates from the second surface to the fourth surface, exposing a part of the fourth surface. 2nd Beer Hall and , a second wiring portion provided on the second surface; provided in the second via hole , connecting the second pad and the second wiring portion Second via conductor and , and The material of the portion of the first pad exposed from the first surface and the material of the portion of the second pad exposed from the first surface Three-sided A wiring substrate having different materials is provided. [Effects of the Invention]

[0007] According to the disclosed technology, pads can be miniaturized. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a cross-sectional view showing the structure of a wiring board according to a first embodiment. [Figure 2] 1A to 1C are cross-sectional views (part 1) illustrating the method for manufacturing a wiring board according to the first embodiment. [Figure 3] 5A and 5B are cross-sectional views (part 2) illustrating the method for manufacturing the wiring board according to the first embodiment. [Figure 4] 5A and 5B are cross-sectional views (part 3) illustrating the method for manufacturing the wiring board according to the first embodiment. [Figure 5] 10A and 10B are cross-sectional views (part 4) illustrating the method for manufacturing the wiring board according to the first embodiment. [Figure 6] 5 is a cross-sectional view (part 5) illustrating the method for manufacturing the wiring board according to the first embodiment. [Figure 7] FIG. 10 is a cross-sectional view showing a semiconductor device according to a second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, the embodiments will be described in detail with reference to the accompanying drawings. Note that in this specification and the drawings, components having substantially the same functional configurations may be denoted by the same reference numerals to avoid redundant description. In this disclosure, for convenience, the side of a wiring board on which a semiconductor element is mounted will be referred to as one side or lower side, and the opposite side will be referred to as the other side or upper side. Furthermore, the surface of a wiring board on which a semiconductor element is mounted will be referred to as one side or lower side, and the opposite side will be referred to as the other side or upper side. However, the wiring board and the semiconductor device can be used upside down or arranged at any angle. Furthermore, a planar view refers to a view of an object from the normal direction of one surface of the wiring board and the semiconductor device, and a planar shape refers to the shape of the object viewed from the normal direction of one surface of the wiring board and the semiconductor device.

[0010] (First embodiment) First, a first embodiment will be described. The first embodiment relates to a wiring board.

[0011] [Wiring board structure] First, the structure of the wiring board will be described. Fig. 1 is a cross-sectional view showing the structure of the wiring board according to the first embodiment.

[0012] As shown in FIG. 1, the wiring board 100 according to the first embodiment has a first insulating layer 10 having a first surface 10A on one side and a second surface 10B on the other side. The first surface 10A is the bottom surface, and the second surface 10B is the top surface. A plurality of first via holes 11 and a plurality of second via holes 12 are formed in the first insulating layer 10. For example, the first via holes 11 and the second via holes 12 have circular planar shapes. The first via holes 11 penetrate the first insulating layer 10 and have ends on the first surface 10A and the second surface 10B. The second via holes 12 do not penetrate the first insulating layer 10 and have ends on the top surface (the surface on the second surface 10B side) of a second pad 22 (described later) and on the second surface 10B. For example, the diameters of the first via holes 11 and the second via holes 12 are approximately 50 μm to 80 μm. For example, the second via holes 12 are formed around the first via holes 11 in a plan view.

[0013] The wiring substrate 100 has a plurality of first pads 21. One first pad 21 is provided inside each first via hole 11. The first pads 21 are exposed from the first surface 10A. The first pads 21 have a lower surface that is flush with the first surface 10A. The side surfaces of the first pads 21 are in contact with the inner wall surfaces of the first via holes 11, and the diameter of the first pads 21 is substantially equal to the diameter of the first via holes 11. For example, the diameter of the first pads 21 is approximately 50 μm to 80 μm. The first pads 21 include, for example, a gold film, a palladium film, and a nickel film that are laminated in this order from the first surface 10A side toward the second surface 10B side. In this case, the gold film is exposed from the first surface 10A. For example, the total thickness of the first pads 21 is approximately 3 μm to 5 μm.

[0014] The wiring substrate 100 has a plurality of second pads 22. The second pads 22 are exposed from the first surface 10A. The second pads 22 have lower surfaces that are flush with the first surface 10A. For example, in a plan view, the plurality of second pads 22 are formed around the plurality of first pads 21. The second via holes 12 are formed so as to reach the connection portions of the second pads 22. The diameter of the second pads 22 is larger than the diameter of the second via holes 12. The diameter of the second pads 22 is also larger than the diameter of the first pads 21. For example, the diameter of the second pads 22 is approximately 100 μm to 150 μm. The second pads 22 are, for example, electrolytic copper plating films. The second pads 22 are thicker than the first pads 21. For example, the thickness of the second pads 22 is approximately 5 μm to 15 μm.

[0015] The wiring substrate 100 has a first wiring layer 30 formed on a first insulating layer 10. The first wiring layer 30 includes a first wiring portion 31 connected to a first pad 21 through a first via conductor 31V in a first via hole 11, and a second wiring portion 32 connected to a second pad 22 through a second via conductor 32V in a second via hole 12. The entire upper surface of the first pad 21 contacts the first via conductor 31V. For example, the entire upper surface of the nickel film included in the first pad 21 contacts the first via conductor 31V. Meanwhile, a portion of the upper surface of the second pad 22 contacts the second via conductor 32V, and the remaining portion of the upper surface of the second pad 22 contacts the first insulating layer 10.

[0016] At the interface between the first pad 21 and the first via conductor 31V, the diameter of the first pad 21, the diameter of the first via conductor 31V, and the diameter of the first via hole 11 are all equal. At the interface between the second pad 22 and the second via conductor 32V, the diameter of the second via conductor 32V and the diameter of the second via hole 12 are all equal, and the diameter of the surface of the second via conductor 32V in contact with the second pad 22 is smaller than the diameter of the upper surface of the second pad 22.

[0017] A second insulating layer 40 is formed on the first insulating layer 10. A third via hole 43 is formed in the second insulating layer 40, reaching the connection portion of the first wiring layer 30, and a second wiring layer 50 is formed on the second insulating layer 40, connected to the first wiring layer 30 through a via conductor in the third via hole 43.

[0018] A solder resist layer 60 is formed on the lower surface of the first insulating layer 10, and a solder resist layer 70 is formed on the upper surface of the second insulating layer 40. A first opening 61 reaching the first pad 21 and a second opening 62 reaching the second pad 22 are formed in the solder resist layer 60, and a third opening 73 reaching the connection portion of the second wiring layer 50 is formed in the solder resist layer 70.

[0019] The wiring board 100 configured in this manner is used by flip-chip mounting a semiconductor element, for example, with the electrodes connected to the first pads 21 via bumps.

[0020] [Method of manufacturing wiring board] Next, a method for manufacturing the wiring board according to the first embodiment will be described. Figures 2 to 6 are cross-sectional views showing the method for manufacturing the wiring board according to the first embodiment.

[0021] First, as shown in FIG. 2(a), a support substrate 90 is prepared. The support substrate 90 includes, for example, a prepreg base 91, a carrier copper foil 92, and a copper foil 93. The carrier copper foil 92 is provided on the base 91, and the copper foil 93 is provided on the carrier copper foil 92 via a release layer (not shown). The base 91 is, for example, a woven or nonwoven fabric made of glass fiber, aramid fiber, or the like, which has been impregnated with a thermosetting epoxy resin or polyimide resin. For example, the thickness of the carrier copper foil 92 is approximately 10 μm to 50 μm, and the thickness of the copper foil 93 is approximately 1.5 μm to 5 μm.

[0022] As the support substrate 90, a large support substrate from which a plurality of wiring substrates 100 can be obtained is used. In other words, the support substrate 90 has a plurality of regions in which structures corresponding to the wiring substrates 100 are formed. Then, after members that will become a plurality of wiring substrates 100 are produced at once, the members are cut along cutting lines CL to separate the members into individual wiring substrates 100. For ease of explanation, the parts that will ultimately become the respective components of the wiring substrate 100 will be described using the reference numerals of the final components.

[0023] 2(b), a photosensitive plating resist layer 80 is formed on the entire upper surface of the copper foil 93. As the plating resist layer 80, for example, a dry film resist or the like can be used.

[0024] 2(c), the plating resist layer 80 is exposed and developed to form openings 81 in the plating resist layer 80 that expose the portions where the second pads 22 will be formed. The diameter of the openings 81 is approximately 100 μm to 150 μm.

[0025] 2(d), an electrolytic copper plating film is formed as a second pad 22 on the upper surface of the copper foil 93 exposed in the opening 81 by electrolytic plating using the copper foil 93 as a plating power supply path. The temperature of the electrolytic plating solution used to form the second pad 22 is, for example, about 40°C to 50°C. The plating resist layer 80 has sufficient resistance to the electrolytic plating solution at about 40°C to 50°C. For example, the thickness of the second pad 22 is about 5 μm to 15 μm. The diameter of the second pad 22 is equal to the diameter of the opening 81.

[0026] Next, as shown in FIG. 3(a), the plating resist layer 80 is removed.

[0027] Thereafter, as shown in FIG. 3(b), an uncured resin film is attached to the upper surface of the copper foil 93 so as to cover the second pads 22. The resin film is then cured by heat treatment to form the first insulating layer 10. The first insulating layer 10 has a first surface 10A (lower surface) and a second surface 10B (upper surface). The first insulating layer 10 is made of insulating resin such as epoxy resin or polyimide resin. The first insulating layer 10 may also be formed by applying a liquid resin.

[0028] 3(c), the first insulating layer 10 is processed with a laser to form a first via hole 11 in the first insulating layer 10, the first via hole 11 reaching the copper foil 93. For example, the diameter of the first via hole 11 is about 50 μm to 80 μm.

[0029] Next, as shown in FIG. 3(d), a first pad 21 is formed on the upper surface of the copper foil 93 exposed in the first via hole 11. To form the first pad 21, a gold film is formed on the copper foil 93, a palladium film is formed on the gold film, and a nickel film is formed on the palladium film. The temperature of the electroless plating solution used to form the first pad 21 is, for example, about 70°C to 90°C. Generally, a plating resist layer is likely to dissolve in an electroless plating solution at about 70°C to 90°C. However, in this embodiment, no plating resist layer is present during electroless plating. Therefore, in this embodiment, a decrease in yield due to dissolution of the plating resist layer can be avoided. For example, the total thickness of the first pad 21 is about 3 μm to 5 μm. The diameter of the first pad 21 is equal to the diameter of the first via hole 11.

[0030] 4(a), the first insulating layer 10 is processed with a laser to form a second via hole 12 in the first insulating layer 10, the second via hole 12 reaching the second pad 22. For example, the diameter of the second via hole 12 is about 50 μm to 80 μm.

[0031] 4(b), a first wiring layer 30 is formed on the first insulating layer 10. The first wiring layer 30 includes a first wiring portion 31 connected to the first pad 21 through a first via conductor 31V in the first via hole 11, and a second wiring portion 32 connected to the second pad 22 through a second via conductor 32V in the second via hole 12. The entire upper surface of the first pad 21 contacts the first wiring portion 31. Meanwhile, a portion of the upper surface of the second pad 22 contacts the second wiring portion 32.

[0032] The first wiring layer 30 can be formed by a semi-additive method. Here, a method for forming the first wiring layer 30 will be described in detail. First, a seed layer (not shown) made of copper or the like is formed on the upper surface of the first insulating layer 10, the inner surface of the first via hole 11, and the inner surface of the second via hole 12 by electroless plating or sputtering. Next, a plating resist layer (not shown) having openings where the first wiring layer 30 will be formed is formed on the seed layer. Next, a metal plating layer made of copper or the like is formed in the openings of the plating resist layer by electrolytic plating, using the seed layer as a plating power supply path. The plating resist layer is then removed. Next, the seed layer is removed by wet etching using the metal plating layer as a mask. In this manner, the first wiring layer 30 including the seed layer and the metal plating layer can be formed. For simplicity of illustration, the first wiring layer 30 is illustrated as if the seed layer and the metal plating layer were an integrated unit.

[0033] After the formation of the first wiring layer 30, as shown in Fig. 4(c), a second insulating layer 40 is formed on the first insulating layer 10 so as to cover the first wiring layer 30. The second insulating layer 40 can be formed in the same manner as the first insulating layer 10.

[0034] 5(a), the second insulating layer 40 is processed with a laser to form a third via hole 43 in the second insulating layer 40, the third via hole 43 reaching the connection portion of the first wiring layer 30. The third via hole 43 can be formed in the same manner as the first via hole 11.

[0035] 5(b), a second wiring layer 50 connected to the first wiring layer 30 through the via conductor in the third via hole 43 is formed on the second insulating layer 40. The second wiring layer 50 can be formed in the same manner as the first wiring layer 30.

[0036] Subsequently, as shown in FIG. 5(c), the copper foil 93 and the carrier copper foil 92 are separated from each other, and the carrier copper foil 92 and the base 91 are peeled off.

[0037] 6(a), the copper foil 93 is removed. The copper foil 93 can be removed by, for example, wet etching. As a result, the lower surface (first surface 10A) of the first insulating layer 10, the lower surfaces of the first pads 21, and the lower surfaces of the second pads 22 are exposed.

[0038] 6(b), a solder resist layer 60 is formed on the lower surface of the first insulating layer 10, and a solder resist layer 70 is formed on the upper surface of the second insulating layer 40. Next, a first opening 61 reaching the first pad 21 and a second opening 62 reaching the second pad 22 are formed in the solder resist layer 60, and a third opening 73 reaching the connection portion of the second wiring layer 50 is formed in the solder resist layer 70.

[0039] The solder resist layers 60 and 70 are formed from an insulating resin such as a photosensitive epoxy resin or acrylic resin. The solder resist layers 60 and 70 may be formed by attaching a resin film or applying a liquid resin. The first opening 61, the second opening 62, and the third opening 73 may be formed by exposure and development. The solder resist layers 60 and 70 may be formed from an insulating resin such as a non-photosensitive epoxy resin or polyimide resin. In this case, the first opening 61, the second opening 62, and the third opening 73 may be formed by laser processing or blasting.

[0040] Thereafter, as shown in Fig. 6(c), the structure shown in Fig. 6(b) is cut along cutting lines CL using a slicer or the like. As a result, structures corresponding to the wiring boards 100 are separated into individual pieces, and a plurality of wiring boards 100 according to the first embodiment are obtained. In this manner, the wiring boards 100 according to the first embodiment can be manufactured.

[0041] In the first embodiment, the first pad 21 can be provided in a self-aligned manner in the first via hole 11 formed by processing the first insulating layer 10 using a laser. If, after forming the first pad 21, a via hole is formed using a laser so as to reach the first pad 21, it is necessary to form the first pad 21 to a size that provides a margin to account for misalignment of the laser light. In contrast, in the present embodiment, such a margin is not necessary, and the first pad 21 can be formed finely with high precision.

[0042] Furthermore, the material of the portion of the first pad 21 exposed on the first surface 10A can be different from the material of the portion of the second pad 22 exposed on the first surface 10A. Therefore, these materials can be selected depending on the application of the first pad 21 and the second pad 22. For example, if the first pad 21 is used for flip-chip mounting of a semiconductor element and the second pad 22 is used for wire bonding, the material constituting the lower surface of the first pad 21 can be gold and the material constituting the lower surface of the second pad 22 can be copper. Furthermore, the lower surface of the second pad 22 may be subjected to an anti-oxidation treatment such as a water-soluble preflux (organic solderability preservative: OSP) treatment.

[0043] Furthermore, the first pads 21 can be formed by electroless plating without using a plating resist layer. When attempting to form a patterned electroless plated film using a plating resist layer, yield reduction and other issues occur due to the plating resist layer eluting into the plating solution. In contrast, in this embodiment, the first pads 21 are formed in the first via holes 11 formed in the first insulating layer 10, so that the first pads 21 can be formed finely and with high precision while avoiding yield reduction and other issues.

[0044] 3(d), when the plurality of first pads 21 are formed, the plurality of first pads 21 are at the same electrical potential via the copper foil 93. Therefore, the plurality of first pads 21 are formed at approximately the same speed, and excellent thickness uniformity can be obtained among the plurality of first pads 21.

[0045] The diameter of the first via hole 11 may be smaller than the diameter of the second via hole 12. Furthermore, the first via hole 11 and the second via hole 12 may have a tapered cross-sectional shape in which the diameter is smaller on the first surface 10A side than on the second surface 10B side. In this case, the diameter of the first via hole 11 is the diameter of the first via hole 11 on the first surface 10A, and the diameter of the second via hole 12 is the diameter of the end of the second via hole 12 on the first surface 10A side.

[0046] Furthermore, the planar shape of each pad and via hole does not have to be circular, and the diameter of a pad or via hole whose planar shape is not a perfect circle can be substituted with a circle-equivalent diameter.

[0047] Furthermore, in the above-described manufacturing method, a support substrate 90 having a carrier copper foil 92 and a copper foil 93 formed on only one side of the base 91 is used, and a wiring board 100 is formed on only one side, but a carrier copper foil 92 and a copper foil 93 may also be formed on the other side of the base 91, and a wiring board 100 may also be formed on the other side.

[0048] (Second embodiment) Next, a second embodiment will be described. The second embodiment relates to a semiconductor device. FIG. 7 is a cross-sectional view showing a semiconductor device according to the second embodiment. In the second embodiment, the wiring substrate 100 is arranged upside down compared to FIG. 1. Therefore, the second embodiment will be described with the upside down direction reversed from that of the first embodiment.

[0049] As shown in FIG. 7, the semiconductor device 200 according to the second embodiment includes the wiring substrate 100 according to the first embodiment, a laminated semiconductor element 210, bumps 220, bonding wires 230, and a sealing resin 240.

[0050] The laminated semiconductor element 210 has a first semiconductor element 211 and a second semiconductor element 212. The first semiconductor element 211 is connected to the first pads 21 via bumps 220. In other words, the first semiconductor element 211 is flip-chip mounted on the wiring substrate 100. The bumps 220 are, for example, solder bumps. Examples of materials for the solder bumps include lead-free solders such as tin-silver (SnAg)-based alloys, tin-zinc (SnZn)-based alloys, and tin-copper (SnCu)-based alloys, as well as leaded solders such as lead-tin (PbSn)-based alloys.

[0051] The second semiconductor element 212 is stacked on the first semiconductor element 211. Pads for external connection are formed on the upper surface of the second semiconductor element 212, and bonding wires 230 connect these pads to the second pads 22. Then, on the upper surface side of the solder resist layer 60, the second pads 22, the bumps 220, the stacked semiconductor element 210, and the bonding wires 230 are sealed with sealing resin 240.

[0052] The above describes in detail preferred embodiments, but the present invention is not limited to the above-described embodiments, and various modifications and substitutions can be made to the above-described embodiments without departing from the scope of the claims. [Explanation of symbols]

[0053] 10 First insulating layer 10A 1st side 10B 2nd side 11 Beer Hall No. 1 12 Second Beer Hall 21 First Pad 22 Second Pad 30 1st wiring layer 31 1st wiring section 31V 1st via conductor 32 2nd wiring section 32V Second via conductor 80 Plating resist layer 100 wiring board 200 Semiconductor device 220 Bump 230 Bonding Wire

Claims

1. an insulating layer having a first surface and a second surface opposite the first surface; a first via hole penetrating the insulating layer from the second surface to the first surface; a first pad provided in the first via hole and exposed from the first surface; a first wiring portion provided on the second surface; a first via conductor provided in the first via hole and connecting the first pad and the first wiring portion; a second pad including a third surface, a fourth surface opposite to the third surface, and a side surface between the third surface and the fourth surface, the fourth surface and the side surface being covered with the insulating layer, and the third surface being exposed from the first surface; a second via hole that penetrates the insulating layer from the second surface to the fourth surface and exposes a portion of the fourth surface; a second wiring portion provided on the second surface; a second via conductor provided in the second via hole and connecting the second pad and the second wiring portion; and A wiring board, wherein a material of a portion of the first pad exposed from the first surface is different from a material of the third surface of the second pad.

2. 2. The wiring board according to claim 1, wherein the diameter of the first pad, the diameter of the first via conductor, and the diameter of the first via hole are equal to each other at the interface between the first pad and the first via conductor.

3. 3. The wiring board according to claim 1, wherein the entire surface of the first pad on the side of the first wiring portion is in contact with the first via conductor.

4. a material of a portion of the first pad exposed from the first surface is gold; 4. The wiring board according to claim 1, wherein the material of the third surface of the second pad is copper.

5. 5. The wiring board according to claim 1, wherein the diameter of the second pad is larger than the diameter of the first pad.

6. 6. The wiring board according to claim 1, wherein the second pad is thicker than the first pad.

7. 7. The wiring board according to claim 1, wherein a diameter of the second via conductor and a diameter of the second via hole are equal to each other at an interface between the second pad and the second via conductor.

8. 8. The wiring board according to claim 1, wherein a portion of the fourth surface of the second pad contacts the second via conductor, and the remaining portion contacts the insulating layer.

9. 9. The wiring board according to claim 1, wherein the diameter of the first via hole is smaller than the diameter of the second via hole.

10. The wiring substrate according to any one of claims 1 to 9, a semiconductor element flip-chip mounted on the wiring substrate and connected to the first pad; A semiconductor device comprising:

11. forming a second pad on the support substrate by electroplating; forming an insulating layer on the support substrate to cover the second pad; forming a first via hole in the insulating layer that reaches the support substrate; forming a first pad on the support substrate exposed in the first via hole by electroless plating; forming a second via hole in the insulating layer that reaches the second pad; forming, on the insulating layer, a first wiring portion connected to the first pad through a first via conductor in the first via hole, and a second wiring portion connected to the second pad through a second via conductor in the second via hole; removing the support substrate; in that order, A method for manufacturing a wiring board, wherein a material constituting the surface of the first pad facing the support substrate is different from a material constituting the surface of the second pad facing the support substrate.

12. The method for manufacturing a wiring board according to claim 11, wherein the first wiring portion and the second wiring portion are formed simultaneously.

13. a material constituting the surface of the first pad facing the support substrate is gold; 13. The method for manufacturing a wiring board according to claim 11, wherein the material constituting the surface of the second pad facing the support substrate is copper.

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