Display device manufacturing method

Abstract

To suppress deterioration in reliability.SOLUTION: A manufacturing method of a display divice includes the steps of: forming a first lower electrode of a first sub-pixel, a second lower electrode of a second sub-pixel, a third lower electrode of a third sub-pixel, a first opening overlapped with the first lower electrode, a second opening overlapped with the second lower electrode, and a third opening overlapped with the third lower electrode; forming a first thin film including a first light emission layer; forming a first resist covering the first thin film of the first sub-pixel while exposing the first thin film of the second sub-pixel and the third sub-pixel; removing the first thin film of the second sub-pixel and the third sub-pixel by using the first resist as a mask; exposing the third lower electrode from the third opening while exposing the second lower electrode from the second opening; forming a second thin film including a second light emission layer; forming a second resist covering the second thin film of the second sub-pixel while exposing the second thin film of the first sub-pixel and the third sub-pixel; removing the second thin film of the first sub-pixel and the third sub-pixel by using the second resist as a mask; and exposing the third lower electrode from the third opening. An area of the first opening is larger than that of the second opening.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] An embodiment of the present invention relates to a method for manufacturing a display device. [Background technology]

[0002] In recent years, display devices using organic light-emitting diodes (OLEDs) as display elements have been put to practical use. These display elements include a pixel circuit including a thin-film transistor, a lower electrode connected to the pixel circuit, an organic layer covering the lower electrode, and an upper electrode covering the organic layer. In addition to the light-emitting layer, the organic layer includes functional layers such as a hole transport layer and an electron transport layer. In the process of manufacturing such display elements, a technique for suppressing deterioration in reliability is required. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2000-195677 [Patent Document 2] Japanese Patent Application Laid-Open No. 2004-207217 [Patent Document 3] Japanese Patent Application Laid-Open No. 2008-135325 [Patent Document 4] Japanese Patent Application Laid-Open No. 2009-32673 [Patent Document 5] Japanese Patent Application Laid-Open No. 2010-118191 [Patent Document 6] International Publication No. 2018 / 179308 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a method for manufacturing a display device that can suppress a decrease in reliability. [Means for solving the problem]

[0005] According to one embodiment, a method for manufacturing a display device includes the steps of: a first lower electrode of a first subpixel, a second lower electrode of a second subpixel, and a third lower electrode of a third subpixel; and a rib having a first opening overlapping the first lower electrode, a second opening overlapping the second lower electrode, and a third opening overlapping the third lower electrode; a processing substrate on which a rib is formed; a first thin film including a first light-emitting layer is formed across the first subpixel, the second subpixel, and the third subpixel; a first resist is formed to expose the first thin film of the second subpixel and the third subpixel and to cover the first thin film of the first subpixel; the first resist is used as a mask to remove the first thin film of the second subpixel and the third subpixel; the first thin film remains in the first subpixel; the second lower electrode is exposed from the second opening and the third lower electrode is exposed from the third opening; the first resist is removed; a second thin film including a second light-emitting layer is formed across the first subpixel, the second subpixel, and the third subpixel; a second resist is formed to expose the second thin film of the first subpixel and the third subpixel and to cover the second thin film of the second subpixel; the second thin film of the first subpixel and the third subpixel is removed using the second resist as a mask; the second thin film remains in the second subpixel; the third lower electrode is exposed from the third opening; and the second resist is removed; and the area of ​​the first opening is larger than the area of ​​the second opening.

[0006] According to one embodiment, a method for manufacturing a display device includes the steps of: a processing substrate on which a first lower electrode of a first subpixel, a second lower electrode of a second subpixel, and a third lower electrode of a third subpixel are formed, and on which a rib having a first opening overlapping the first lower electrode, a second opening overlapping the second lower electrode, and a third opening overlapping the third lower electrode is formed; a first thin film including a first light-emitting layer emitting light in a blue wavelength region is formed across the first subpixel, the second subpixel, and the third subpixel; a first resist is formed to expose the first thin film of the second subpixel and the third subpixel and to cover the first thin film of the first subpixel; the first resist is removed from the second subpixel and the third subpixel using the first resist as a mask, so that the first thin film remains in the first subpixel, the second lower electrode is exposed from the second opening, and the third lower electrode is exposed from the third opening; the first resist is removed; a second thin film including a second light-emitting layer that emits light in a green wavelength region; a second resist that exposes the second thin film of the first subpixel and the third subpixel and covers the second thin film of the second subpixel; a mask is used to remove the second thin film of the first subpixel and the third subpixel, leaving the second thin film in the second subpixel; a third lower electrode is exposed through the third opening and the second resist is removed; a third thin film including a third light-emitting layer that emits light in a red wavelength region is formed across the first subpixel, the second subpixel, and the third subpixel; a third resist that exposes the third thin film of the first subpixel and the second subpixel and covers the third thin film of the third subpixel; a mask is used to remove the third thin film of the first subpixel and the second subpixel, leaving the third thin film in the third subpixel; and a third resist is removed.

[0007] According to one embodiment, a method for manufacturing a display device includes the steps of: a processing substrate on which a first lower electrode of a first subpixel, a second lower electrode of a second subpixel, and a third lower electrode of a third subpixel are formed, and on which a rib having a first opening overlapping the first lower electrode, a second opening overlapping the second lower electrode, and a third opening overlapping the third lower electrode is formed; a first thin film including a first light-emitting layer emitting light in a blue wavelength region is formed across the first subpixel, the second subpixel, and the third subpixel; a first resist is formed to expose the first thin film of the second subpixel and the third subpixel and to cover the first thin film of the first subpixel; the first resist is removed from the second subpixel and the third subpixel using the first resist as a mask, so that the first thin film remains in the first subpixel, the second lower electrode is exposed from the second opening, and the third lower electrode is exposed from the third opening; the first resist is removed; a second thin film including a second light-emitting layer that emits light in a red wavelength region; a second resist that exposes the second thin film of the first subpixel and the third subpixel and covers the second thin film of the second subpixel; the second thin film of the first subpixel and the third subpixel is removed using the second resist as a mask, leaving the second thin film in the second subpixel; the third lower electrode is exposed through the third opening and the second resist is removed; a third thin film including a third light-emitting layer that emits light in a green wavelength region is formed across the first subpixel, the second subpixel, and the third subpixel; a third resist that exposes the third thin film of the first subpixel and the second subpixel and covers the third thin film of the third subpixel; the third resist is removed using the third resist as a mask, leaving the third thin film in the third subpixel; and the third resist is removed. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a diagram showing an example of the configuration of a display device DSP. [Figure 2] FIG. 2 is a diagram showing an example of the layout of the subpixels SP1, SP2, and SP3. [Figure 3] FIG. 3 is a schematic cross-sectional view of the display device DSP taken along the line III-III in FIG. [Figure 4] FIG. 4 is a diagram showing an example of the configuration of the display elements 201 to 203. [Figure 5] FIG. 5 is a flow chart for explaining an example of a method for manufacturing the display device DSP. [Figure 6] FIG. 6 is a flow diagram illustrating an example of a thin film formation process. [Figure 7] FIG. 7 is a flow diagram illustrating an example of the thin film removing step. [Figure 8] FIG. 8 is a diagram for explaining a manufacturing method of the display device DSP. [Figure 9] FIG. 9 is a diagram for explaining a manufacturing method of the display device DSP. [Figure 10] FIG. 10 is a diagram for explaining a manufacturing method of the display device DSP. [Figure 11] FIG. 11 is a diagram for explaining a manufacturing method of the display device DSP. [Figure 12] FIG. 12 is a diagram for explaining a manufacturing method of the display device DSP. [Figure 13] FIG. 13 is a diagram for explaining a manufacturing method of the display device DSP. [Figure 14] FIG. 14 is a diagram for explaining a manufacturing method of the display device DSP. [Figure 15] FIG. 15 is a diagram for explaining a manufacturing method of the display device DSP. DETAILED DESCRIPTION OF THE INVENTION

[0009] An embodiment will be described with reference to the drawings. The disclosure is merely an example, and appropriate modifications that a person skilled in the art can easily make while maintaining the gist of the invention are naturally included within the scope of the present invention. Furthermore, the drawings may be schematic in terms of the width, thickness, shape, etc. of each part compared to the actual embodiment for the sake of clarity, but these are merely examples and are not intended to limit the interpretation of the present invention. Furthermore, in this specification and each drawing, components that perform the same or similar functions as those described above with reference to the previous drawings are designated by the same reference numerals, and redundant detailed descriptions may be omitted as appropriate.

[0010] In the drawings, mutually orthogonal X-, Y-, and Z-axes are shown as necessary to facilitate understanding. The direction along the X-axis is referred to as the first direction, the direction along the Y-axis is referred to as the second direction, and the direction along the Z-axis is referred to as the third direction. Viewing various elements parallel to the third direction Z is referred to as a planar view.

[0011] The display device according to this embodiment is an organic electroluminescence display device having organic light-emitting diodes (OLEDs) as display elements, and can be installed in televisions, personal computers, in-vehicle devices, tablet terminals, smartphones, mobile phone terminals, and the like.

[0012] FIG. 1 is a diagram showing an example of the configuration of a display device DSP. The display device DSP has a display area DA for displaying an image and a peripheral area SA around the display area DA, both of which are disposed on an insulating substrate 10. The substrate 10 may be made of glass or a flexible resin film.

[0013] In this embodiment, the shape of the substrate 10 in plan view is rectangular. However, the shape of the substrate 10 in plan view is not limited to rectangular, and may be other shapes such as square, circle, or ellipse.

[0014] The display area DA includes a plurality of pixels PX arranged in a matrix in the first direction X and the second direction Y. Each pixel PX includes a plurality of subpixels SP. In one example, the pixel PX includes a first color subpixel SP1, a second color subpixel SP2, and a third color subpixel SP3. The first color, second color, and third color are different from each other. Note that the pixel PX may include subpixels SP of another color, such as white, in addition to the subpixels SP1, SP2, and SP3, or instead of any of the subpixels SP1, SP2, and SP3.

[0015] The subpixel SP includes a pixel circuit 1 and a display element 20 driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a drive transistor 3, and a capacitor 4. The pixel switch 2 and the drive transistor 3 are switching elements formed of, for example, thin film transistors.

[0016] The gate electrode of the pixel switch 2 is connected to the scanning line GL. One of the source electrode and drain electrode of the pixel switch 2 is connected to the signal line SL, and the other is connected to the gate electrode of the drive transistor 3 and the capacitor 4. In the drive transistor 3, one of the source electrode and drain electrode is connected to the power line PL and the capacitor 4, and the other is connected to the anode of the display element 20.

[0017] The configuration of the pixel circuit 1 is not limited to the example shown in the drawing. For example, the pixel circuit 1 may include more thin film transistors and capacitors.

[0018] The display element 20 is an organic light-emitting diode (OLED) as a light-emitting element, and may be referred to as an organic EL element.

[0019] FIG. 2 is a diagram showing an example of the layout of the subpixels SP1, SP2, and SP3. 2, the subpixels SP2 and SP3 are aligned in the second direction Y. Furthermore, the subpixels SP2 and SP3 are aligned in the first direction X with the subpixel SP1, respectively.

[0020] When the subpixels SP1, SP2, and SP3 are laid out in this manner, the display area DA is formed with columns in which the subpixels SP2 and SP3 are alternately arranged in the second direction Y, and columns in which multiple subpixels SP1 are repeatedly arranged in the second direction Y. These columns are arranged alternately in the first direction X.

[0021] The layout of the subpixels SP1, SP2, and SP3 is not limited to the example in Fig. 2. As another example, the subpixels SP1, SP2, and SP3 in each pixel PX may be arranged in order in the first direction X.

[0022] The display area DA is provided with ribs 5 and partition walls 6. The ribs 5 have openings AP1, AP2, and AP3 in the subpixels SP1, SP2, and SP3, respectively.

[0023] The partitions 6 overlap the ribs 5 in a plan view. The partitions 6 have a plurality of first partitions 6x extending in the first direction X and a plurality of second partitions 6y extending in the second direction Y. The first partitions 6x are respectively arranged between the openings AP2 and AP3 adjacent to each other in the second direction Y and between two openings AP1 adjacent to each other in the second direction Y. The second partitions 6y are respectively arranged between the openings AP1 and AP2 adjacent to each other in the first direction X and between the openings AP1 and AP3 adjacent to each other in the first direction X.

[0024] 2, the first partition 6x and the second partition 6y are connected to each other. As a result, the partition 6 as a whole is formed in a lattice shape surrounding the openings AP1, AP2, and AP3. It can also be said that the partition 6 has openings in the subpixels SP1, SP2, and SP3, similar to the rib 5.

[0025] The subpixels SP1, SP2, and SP3 include display elements 201, 202, and 203 as the display element 20, respectively. Subpixel SP1 includes a lower electrode LE1, an upper electrode UE1, and an organic layer OR1 that overlap with aperture AP1. Subpixel SP2 includes a lower electrode LE2, an upper electrode UE2, and an organic layer OR2 that overlap with aperture AP2. Subpixel SP3 includes a lower electrode LE3, an upper electrode UE3, and an organic layer OR3 that overlap with aperture AP3.

[0026] In the example of FIG. 2, the outlines of the lower electrodes LE1, LE2, and LE3 are indicated by dotted lines, and the outlines of the organic layers OR1, OR2, and OR3 and the upper electrodes UE1, UE2, and UE3 are indicated by dashed-dotted lines. The peripheral edges of the lower electrodes LE1, LE2, and LE3 overlap the ribs 5. The outline of the upper electrode UE1 roughly matches the outline of the organic layer OR1, and the peripheral edges of the upper electrode UE1 and the organic layer OR1 overlap the partition walls 6. The outline of the upper electrode UE2 roughly matches the outline of the organic layer OR2, and the peripheral edges of the upper electrode UE2 and the organic layer OR2 overlap the partition walls 6. The outline of the upper electrode UE3 roughly matches the outline of the organic layer OR3, and the peripheral edges of the upper electrode UE3 and the organic layer OR3 overlap the partition walls 6.

[0027] The lower electrode LE1, the upper electrode UE1, and the organic layer OR1 constitute the display element 201 of the subpixel SP1. The lower electrode LE2, the upper electrode UE2, and the organic layer OR2 constitute the display element 202 of the subpixel SP2. The lower electrode LE3, the upper electrode UE3, and the organic layer OR3 constitute the display element 203 of the subpixel SP3.

[0028] The lower electrodes LE1, LE2, and LE3 correspond to, for example, the anodes of the display elements, and the upper electrodes UE1, UE2, and UE3 correspond to the cathodes of the display elements or a common electrode.

[0029] The lower electrode LE1 is connected to the pixel circuit 1 of the subpixel SP1 (see FIG. 1) through a contact hole CH1. The lower electrode LE2 is connected to the pixel circuit 1 of the subpixel SP2 through a contact hole CH2. The lower electrode LE3 is connected to the pixel circuit 1 of the subpixel SP3 through a contact hole CH3.

[0030] 2, the area of ​​opening AP1 is larger than the area of ​​opening AP2, which is larger than the area of ​​opening AP3. In other words, the area of ​​the lower electrode LE1 exposed from opening AP1 is larger than the area of ​​the lower electrode LE2 exposed from opening AP2, and the area of ​​the lower electrode LE2 exposed from opening AP2 is larger than the area of ​​the lower electrode LE3 exposed from opening AP3.

[0031] The relationship between the aperture area and the color of the sub-pixel is as follows. Subpixels with a large aperture area are assigned to pixels with a relatively short life span or low luminous efficiency. Subpixels with a large aperture area can also be said to be pixels that are sensitive to process variations. For this reason, it is desirable for subpixels with a large aperture area to be formed in an environment with few contaminants. In other words, if a pixel PX includes three subpixels with different aperture areas, it is desirable to form the subpixel with the largest aperture area first and the subpixel with the smallest aperture area last.

[0032] For example, the display element 201 of the subpixel SP1 is configured to emit light in the blue wavelength range, the display element 202 of the subpixel SP2 is configured to emit light in the green wavelength range, and the display element 203 of the subpixel SP3 is configured to emit light in the red wavelength range. Alternatively, the display element 201 of subpixel SP1 may be configured to emit light in the blue wavelength range, the display element 202 of subpixel SP2 may be configured to emit light in the red wavelength range, and the display element 203 of subpixel SP3 may be configured to emit light in the green wavelength range.

[0033] FIG. 3 is a schematic cross-sectional view of the display device DSP taken along the line III-III in FIG. A circuit layer 11 is disposed on the substrate 10. The circuit layer 11 includes various circuits and wirings such as the pixel circuits 1, scanning lines GL, signal lines SL, and power supply lines PL shown in FIG. 1. The circuit layer 11 is covered with an insulating layer 12. The insulating layer 12 functions as a planarizing film that flattens unevenness caused by the circuit layer 11.

[0034] The lower electrodes LE1, LE2, and LE3 are disposed on the insulating layer 12. The rib 5 is disposed on the insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The ends of the lower electrodes LE1, LE2, and LE3 are covered by the rib 5. In other words, the ends of the lower electrodes LE1, LE2, and LE3 are disposed between the insulating layer 12 and the rib 5. Between adjacent lower electrodes LE1, LE2, and LE3, the insulating layer 12 is covered by the rib 5.

[0035] The partition 6 includes a lower portion (stem) 61 disposed on the rib 5 and an upper portion (cap) 62 disposed on the lower portion 61. The lower portion 61 of the partition 6 shown on the right side of the figure is located between the openings AP1 and AP2. The lower portion 61 of the partition 6 shown on the left side of the figure is located between the openings AP2 and AP3. The upper portion 62 has a width greater than that of the lower portion 61. As a result, both ends of the upper portion 62 protrude beyond the side surfaces of the lower portion 61 in FIG. 3. Such a shape of the partition 6 can also be said to be overhanging. The portion of the upper portion 62 protruding beyond the lower portion 61 may be simply referred to as the protruding portion.

[0036] 2 includes a first portion OR1a and a second portion OR1b spaced apart from each other, as shown in FIG. 3. The first portion OR1a contacts the lower electrode LE1 through the opening AP1, covers the lower electrode LE1, and overlaps a part of the rib 5. The second portion OR1b is disposed on the upper portion 62. 2 includes a first portion UE1a and a second portion UE1b spaced apart from each other, as shown in FIG. 3. The first portion UE1a faces the lower electrode LE1 and is disposed on the first portion OR1a. The first portion UE1a contacts a side surface of the lower portion 61. The second portion UE1b is located above the partition wall 6 and is disposed on the second portion OR1b. The first portion OR1a and the first portion UE1a are located below the upper portion 62.

[0037] 2 includes a first portion OR2a and a second portion OR2b that are spaced apart from each other, as shown in Fig. 3. The first portion OR2a contacts the lower electrode LE2 through the opening AP2, covers the lower electrode LE2, and overlaps a part of the rib 5. The second portion OR2b is disposed on the upper portion 62. 2 includes a first portion UE2a and a second portion UE2b spaced apart from each other, as shown in FIG. 3. The first portion UE2a faces the lower electrode LE2 and is disposed on the first portion OR2a. The first portion UE2a contacts a side surface of the lower portion 61. The second portion UE2b is located above the partition wall 6 and is disposed on the second portion OR2b. The first portion OR2a and the first portion UE2a are located below the upper portion 62.

[0038] 2 includes a first portion OR3a and a second portion OR3b spaced apart from each other, as shown in FIG. 3. The first portion OR3a contacts the lower electrode LE3 through the opening AP3, covers the lower electrode LE3, and overlaps a part of the rib 5. The second portion OR3b is disposed on the upper portion 62. 2 includes a first portion UE3a and a second portion UE3b spaced apart from each other, as shown in FIG. 3. The first portion UE3a faces the lower electrode LE3 and is disposed on the first portion OR3a. The first portion UE3a contacts a side surface of the lower portion 61. The second portion UE3b is located above the partition wall 6 and is disposed on the second portion OR3b. The first portion OR3a and the first portion UE3a are located below the upper portion 62.

[0039] In the example shown in FIG. 3, the subpixels SP1, SP2, and SP3 include cap layers (optical adjustment layers) CP1, CP2, and CP3 for adjusting the optical properties of the light emitted from the light-emitting layers of the organic layers OR1, OR2, and OR3.

[0040] The cap layer CP1 includes a first portion CP1a and a second portion CP1b spaced apart from each other. The first portion CP1a is located in the opening AP1, below the upper portion 62, and above the first portion UE1a. The second portion CP1b is located above the partition wall 6 and above the second portion UE1b.

[0041] The cap layer CP2 includes a first portion CP2a and a second portion CP2b spaced apart from each other. The first portion CP2a is located in the opening AP2, below the upper portion 62, and above the first portion UE2a. The second portion CP2b is located above the partition wall 6 and above the second portion UE2b.

[0042] The cap layer CP3 includes a first portion CP3a and a second portion CP3b spaced apart from each other. The first portion CP3a is located in the opening AP3, below the upper portion 62, and above the first portion UE3a. The second portion CP3b is located above the partition wall 6 and above the second portion UE3b.

[0043] Sealing layers SE1, SE2, and SE3 are disposed in the subpixels SP1, SP2, and SP3, respectively.

[0044] The sealing layer SE1 is in contact with the first portion CP1a, the lower portion 61 and upper portion 62 of the partition wall 6, and the second portion CP1b, and continuously covers each component of the subpixel SP1. Note that the sealing layer SE1 may have a gap below the upper portion 62 of the partition wall 6 (below the protrusion 621), but this is not shown here.

[0045] The sealing layer SE2 is in contact with the first portion CP2a, the lower portion 61 and upper portion 62 of the partition wall 6, and the second portion CP2b, and continuously covers each component of the subpixel SP2. Note that the sealing layer SE2 may have a gap below the upper portion 62 of the partition wall 6 (below the protrusion 622), but this is not shown here.

[0046] The sealing layer SE3 is in contact with the first portion CP3a, the lower portion 61 and upper portion 62 of the partition wall 6, and the second portion CP3b, and continuously covers each component of the subpixel SP3. Note that the sealing layer SE3 may have a gap below the upper portion 62 of the partition wall 6 (below the protrusion 623), but this is not shown here.

[0047] The sealing layers SE1, SE2, and SE3 are covered with a protective layer 13.

[0048] 3, on the partition wall 6 between the subpixels SP1 and SP2, the second portion OR1b of the organic layer OR1 is spaced apart from the second portion OR2b of the organic layer OR2, the second portion UE1b of the upper electrode UE1 is spaced apart from the second portion UE2b of the upper electrode UE2, the second portion CP1b of the cap layer CP1 is spaced apart from the second portion CP2b of the cap layer CP2, and the sealing layer SE1 is spaced apart from the sealing layer SE2. The protective layer 13 is disposed between the second portions OR1b and OR2b, between the second portions UE1b and UE2b, between the second portions CP1b and CP2b, and between the sealing layer SE1 and SE2.

[0049] Furthermore, on the partition wall 6 between the subpixels SP2 and SP3, the second portion OR2b of the organic layer OR2 is spaced apart from the second portion OR3b of the organic layer OR3, the second portion UE2b of the upper electrode UE2 is spaced apart from the second portion UE3b of the upper electrode UE3, the second portion CP2b of the cap layer CP2 is spaced apart from the second portion CP3b of the cap layer CP3, and the sealing layer SE2 is spaced apart from the sealing layer SE3. The protective layer 13 is disposed between the second portions OR2b and OR3b, between the second portions UE2b and UE3b, between the second portions CP2b and CP3b, and between the sealing layer SE2 and SE3.

[0050] The insulating layer 12 is an organic insulating layer, and the rib 5 and the sealing layers SE1, SE2, and SE3 are inorganic insulating layers.

[0051] The sealing layers SE1, SE2, and SE3 are formed of, for example, the same inorganic insulating material. The rib 5 is made of silicon nitride (SiNx), which is an example of an inorganic insulating material. The rib 5 may be formed as a single layer of other inorganic insulating materials, such as silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3). The rib 5 may also be formed as a laminated body of a combination of at least two of a silicon nitride layer, a silicon oxide layer, a silicon oxynitride layer, and an aluminum oxide layer. The sealing layers SE1, SE2, and SE3 are formed of silicon nitride (SiNx), an example of an inorganic insulating material. The sealing layers SE1, SE2, and SE3 may be formed as a single layer of other inorganic insulating materials, such as silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3). The sealing layers SE1, SE2, and SE3 may also be formed as a laminated body combining at least two of a silicon nitride layer, a silicon oxide layer, a silicon oxynitride layer, and an aluminum oxide layer. Therefore, the sealing layers SE1, SE2, and SE3 may be formed of the same material as the rib 5.

[0052] The lower portion 61 of the partition wall 6 is made of a conductive material and is electrically connected to the first portions UE1a, UE2a, UE3a of the upper electrodes. Both the lower portion 61 and the upper portion 62 of the partition wall 6 may be conductive.

[0053] The thickness of the rib 5 is sufficiently smaller than the thickness of the partition wall 6 and the insulating layer 12. In one example, the thickness of the rib 5 is not less than 200 nm and not more than 400 nm. The thickness of the sealing layer SE1, the thickness of the sealing layer SE2, and the thickness of the sealing layer SE3 are approximately equal to each other. The thickness of the lower portion 61 of the partition wall 6 (the thickness from the upper surface of the rib 5 to the lower surface of the upper portion 62 ) is greater than the thickness of the rib 5 .

[0054] The lower electrodes LE1, LE2, and LE3 may be formed of a transparent conductive material such as ITO, or may have a laminated structure of a metal material such as silver (Ag) and a transparent conductive material. The upper electrodes UE1, UE2, and UE3 are formed of a metal material such as an alloy of magnesium and silver (MgAg). The upper electrodes UE1, UE2, and UE3 may be formed of a transparent conductive material such as ITO.

[0055] When the potential of the lower electrodes LE1, LE2, LE3 is relatively higher than the potential of the upper electrodes UE1, UE2, UE3, the lower electrodes LE1, LE2, LE3 correspond to anodes and the upper electrodes UE1, UE2, UE3 correspond to cathodes. Also, when the potential of the upper electrodes UE1, UE2, UE3 is relatively higher than the potential of the lower electrodes LE1, LE2, LE3, the upper electrodes UE1, UE2, UE3 correspond to anodes and the lower electrodes LE1, LE2, LE3 correspond to cathodes.

[0056] The organic layers OR1, OR2, and OR3 each include a plurality of functional layers. The first portion OR1a and the second portion OR1b of the organic layer OR1 each include an emitting layer EM1 formed of the same material. The first portion OR2a and the second portion OR2b of the organic layer OR2 each include an emitting layer EM2 formed of the same material. The emitting layer EM2 is formed of a material different from that of the emitting layer EM1. The first portion OR3a and the second portion OR3b of the organic layer OR3 each include an emitting layer EM3 formed of the same material. The emitting layer EM3 is formed of a material different from that of the emitting layers EM1 and EM2.

[0057] The material forming the light emitting layer EM1, the material forming the light emitting layer EM2, and the material forming the light emitting layer EM3 are materials that emit light in different wavelength ranges. In one example, the light-emitting layer EM1 is formed of a material that emits light in the blue wavelength range, the light-emitting layer EM2 is formed of a material that emits light in the green wavelength range, and the light-emitting layer EM3 is formed of a material that emits light in the red wavelength range. Alternatively, the light-emitting layer EM1 is formed of a material that emits light in the blue wavelength range, the light-emitting layer EM2 is formed of a material that emits light in the red wavelength range, and the light-emitting layer EM3 is formed of a material that emits light in the green wavelength range.

[0058] The cap layers CP1, CP2, and CP3 are formed, for example, by a multilayer structure of transparent thin films. The multilayer structure may include thin films formed from inorganic materials and thin films formed from organic materials. These thin films have different refractive indices. The material of the thin films constituting the multilayer structure is different from the material of the upper electrodes UE1, UE2, and UE3 and also different from the material of the sealing layers SE1, SE2, and SE3. The cap layers CP1, CP2, and CP3 may be omitted.

[0059] The protective layer 13 is a transparent organic insulating layer. The sealing layer 14 is a transparent inorganic insulating layer and is disposed on the protective layer 13. The sealing layer 14 is made of, for example, silicon nitride (SiNx). The overcoat layer 15 is a transparent organic insulating layer and is disposed on the sealing layer 14.

[0060] A common voltage is supplied to the partition 6. This common voltage is supplied to the first portions UE1a, UE2a, and UE3a of the upper electrodes in contact with the side surfaces of the lower portion 61. A pixel voltage is supplied to the lower electrodes LE1, LE2, and LE3 through the pixel circuits 1 included in the subpixels SP1, SP2, and SP3, respectively.

[0061] When a potential difference is generated between the lower electrode LE1 and the upper electrode UE1, the light-emitting layer EM1 in the first portion OR1a of the organic layer OR1 emits light in a first wavelength region. When a potential difference is generated between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer EM2 in the first portion OR2a of the organic layer OR2 emits light in a second wavelength region. When a potential difference is generated between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer EM3 in the first portion OR3a of the organic layer OR3 emits light in a third wavelength region.

[0062] 4 is a diagram showing an example of the configuration of the display elements 201 to 203. Here, an example will be described in which the lower electrode corresponds to the anode and the upper electrode corresponds to the cathode. The display element 201 includes an organic layer OR1 between a lower electrode LE1 and an upper electrode UE1.

[0063] In the organic layer OR1, the hole injection layer HIL, the hole transport layer HTL, and the electron blocking layer EBL are located between the lower electrode LE1 and the light emitting layer EM1. The hole injection layer HIL is disposed on the lower electrode LE1, the hole transport layer HTL is disposed on the hole injection layer HIL, the electron blocking layer EBL is disposed on the hole transport layer HTL, and the light emitting layer EM1 is disposed on the electron blocking layer EBL. In the organic layer OR1, the hole blocking layer HBL, the electron transport layer ETL, and the electron injection layer EIL are located between the emitting layer EM1 and the upper electrode UE1. The hole blocking layer HBL is disposed on the emitting layer EM1, the electron transport layer ETL is disposed on the hole blocking layer HBL, the electron injection layer EIL is disposed on the electron transport layer ETL, and the upper electrode UE1 is disposed on the electron injection layer EIL. In addition to the above-mentioned functional layers, the organic layer OR1 may include other functional layers such as a carrier generation layer as needed, or at least one of the above-mentioned functional layers may be omitted.

[0064] The cap layer CP1 includes a transparent layer TL and an inorganic layer IL. The transparent layer TL is disposed on the upper electrode UE1. The inorganic layer IL is disposed on the transparent layer TL. The sealing layer SE1 is disposed on the inorganic layer IL. The transparent layer TL is an organic layer made of, for example, an organic material, and is a high-refractive index layer having a refractive index higher than that of the upper electrode UE1. The inorganic layer IL is a transparent thin film made of, for example, lithium fluoride (LiF), and is a low-refractive index layer having a refractive index lower than that of the transparent layer TL. 4, the cap layer CP1 is a laminate of two layers, a transparent layer TL and an inorganic layer IL, but may be a laminate of three or more layers. In the cap layer CP1, the inorganic layer IL is located at the top and is covered with a sealing layer SE1.

[0065] The display element 202 is configured similarly to the display element 201, except that the organic layer OR2 between the lower electrode LE2 and the upper electrode UE2 includes an emitting layer EM2 instead of the emitting layer EM1. The transparent layer TL of the cap layer CP2 is disposed on the upper electrode UE2, and the inorganic layer IL of the cap layer CP2 is covered with the sealing layer SE2.

[0066] The display element 203 is configured similarly to the display element 201, except that the organic layer OR3 between the lower electrode LE3 and the upper electrode UE3 includes an emitting layer EM3 instead of the emitting layer EM1. The transparent layer TL of the cap layer CP3 is disposed on the upper electrode UE3, and the inorganic layer IL of the cap layer CP3 is covered with the sealing layer SE3.

[0067] 4, functional layers such as the hole injection layer HIL, hole transport layer HTL, electron blocking layer EBL, hole blocking layer HBL, electron transport layer ETL, and electron injection layer EIL are provided in common to the display elements 201 to 203, but are spaced apart from each other for each of the display elements 201 to 203 and are formed individually for each of the display elements 201 to 203. The thickness of each of the functional layers may differ for each of the display elements 201 to 203. Furthermore, when focusing on one of the multiple functional layers described above, it is possible that the functional layer of one of the display elements 201 to 203 is formed from a material different from the functional layers of the other two display elements, or that all of the functional layers of the display elements 201 to 203 are formed from materials different from each other. Furthermore, the layer configuration of one of the display elements 201 to 203 may be different from the layer configurations of the other two display elements, or all of the layer configurations of the display elements 201 to 203 may be different from each other. For example, when focusing on one functional layer, one of the display elements 201 to 203 may not include this functional layer, or only one of the display elements 201 to 203 may include this functional layer. Furthermore, when focusing on one functional layer, it may be the case that this functional layer is multi-layered in one of the display elements 201 to 203.

[0068] The transparent layer TL and the inorganic layer IL are provided in common to the display elements 201 to 203, but are spaced apart from each other for each of the display elements 201 to 203, and are formed individually for each of the display elements 201 to 203. The thicknesses of the transparent layer TL and the inorganic layer IL may differ for each of the cap layers CP1 to CP3. In addition, the transparent layer TL of one of the cap layers CP1 to CP3 may be formed of a different material from the transparent layers TL of the other two cap layers, or all of the transparent layers TL of the cap layers CP1 to CP3 may be formed of different materials from each other. In addition, the inorganic layer IL of one of the cap layers CP1 to CP3 may be formed from a material different from the inorganic layers IL of the other two cap layers, or all of the inorganic layers IL of the cap layers CP1 to CP3 may be formed from materials different from each other. Furthermore, the layer structure of one of the cap layers CP1 to CP3 may be different from the layer structure of the other two cap layers, or all of the cap layers CP1 to CP3 may have different layer structures.

[0069] Next, an example of a method for manufacturing the display device DSP will be described.

[0070] FIG. 5 is a flow chart for explaining an example of a method for manufacturing the display device DSP. The manufacturing method shown here broadly includes the steps of preparing a processing substrate SUB having subpixels SP1, SP2, and SP3 (step ST1), forming a display element 201 for subpixel SP1 (step ST2), forming a display element 202 for subpixel SP2 (step ST3), and forming a display element 203 for subpixel SP3 (step ST4).

[0071] In step ST1, first, a processing substrate SUB is prepared on a substrate 10, on which a lower electrode LE1 for subpixel SP1, a lower electrode LE2 for subpixel SP2, a lower electrode LE3 for subpixel SP3, a rib 5, and a partition wall 6 are formed. As shown in Fig. 3, a circuit layer 11 and an insulating layer 12 are also formed between the substrate 10 and the lower electrodes LE1, LE2, and LE3. Details will be described later.

[0072] In step ST2, first, a first thin film 31 including an emitting layer EM1 is formed on a processing substrate SUB (step ST21). Then, a first resist 41 patterned into a predetermined shape is formed on the first thin film 31 (step ST22). Then, a portion of the first thin film 31 is removed by etching using the first resist 41 as a mask (step ST23). Then, the first resist 41 is removed (step ST24). This forms a subpixel SP1. The subpixel SP1 includes a display element 201 having a first thin film 31 of a predetermined shape.

[0073] In step ST3, first, a second thin film 32 including an emitting layer EM2 is formed on a processing substrate SUB (step ST31). Then, a second resist 42 patterned into a predetermined shape is formed on the second thin film 32 (step ST32). Then, a portion of the second thin film 32 is removed by etching using the second resist 42 as a mask (step ST33). Then, the second resist 42 is removed (step ST34). This forms a subpixel SP2. The subpixel SP2 includes a display element 202 having a second thin film 32 of a predetermined shape.

[0074] In step ST4, first, a third thin film 33 including an emitting layer EM3 is formed on a processing substrate SUB (step ST41). Then, a third resist 43 patterned into a predetermined shape is formed on the third thin film 33 (step ST42). Then, a portion of the third thin film 33 is removed by etching using the third resist 43 as a mask (step ST43). Then, the third resist 43 is removed (step ST44). This forms a subpixel SP3. The subpixel SP3 includes a display element 203 having a third thin film 33 of a predetermined shape.

[0075] 6 is a flow diagram illustrating an example of a thin film forming process. The thin film forming process described here corresponds to the above-described process of forming the first thin film 31 (step ST21), the process of forming the second thin film 32 (step ST31), and the process of forming the third thin film 33 (step ST41). The process of forming the first thin film 31 will be described below. Note that the first thin film 31 includes, for example, the organic layer OR1, the upper electrode UE1, the cap layer CP1, and the sealing layer SE1 shown in FIG.

[0076] First, a material for forming the hole injection layer HIL is deposited on the processing substrate SUB (step ST211), thereby forming the hole injection layer HIL in contact with the lower electrode LE1.

[0077] Thereafter, a material for forming the hole transport layer HTL is deposited on the hole injection layer HIL (step ST212), thereby forming the hole transport layer HTL in contact with the hole injection layer HIL.

[0078] Thereafter, a material for forming the electron blocking layer EBL is deposited on the hole transport layer HTL (step ST213), thereby forming the electron blocking layer EBL in contact with the hole transport layer HTL.

[0079] Thereafter, a material for forming the emitting layer EM1 is deposited on the electron blocking layer EBL (step ST214), thereby forming the emitting layer EM1 in contact with the electron blocking layer EBL.

[0080] Thereafter, a material for forming the hole-blocking layer HBL is deposited on the emitting layer EM1 (step ST215), thereby forming the hole-blocking layer HBL in contact with the emitting layer EM1.

[0081] Thereafter, a material for forming the electron transport layer ETL is deposited on the hole blocking layer HBL (step ST216), thereby forming the electron transport layer ETL in contact with the hole blocking layer HBL.

[0082] Thereafter, a material for forming the electron injection layer EIL is deposited on the electron transport layer ETL (step ST217), thereby forming the electron injection layer EIL in contact with the electron transport layer ETL.

[0083] The organic layer OR1 is formed through a series of steps from step ST211 to step ST217. Note that at least one of steps ST211 to ST213 and at least one of steps ST215 to ST217 may be omitted as necessary. Furthermore, in addition to steps ST211 to ST217, a step for forming a functional layer may be added.

[0084] Thereafter, a material for forming the upper electrode UE1 is deposited on the electron injection layer EIL (step ST218), thereby forming the upper electrode UE1 in contact with the electron injection layer EIL and the partition wall 6.

[0085] Thereafter, a material for forming the transparent layer TL of the cap layer CP1 is deposited on the upper electrode UE1 (step ST219), thereby forming the transparent layer TL in contact with the upper electrode UE1.

[0086] Thereafter, a material for forming the inorganic layer IL of the cap layer CP1 is deposited on the transparent layer TL (step ST220), thereby forming the inorganic layer IL in contact with the transparent layer TL. In the above steps ST221 to ST220, the material is deposited by evaporation, for example, but other methods may also be used. For example, the material may be deposited by sputtering in step ST218.

[0087] Thereafter, a material for forming the sealing layer SE1 is deposited on the inorganic layer IL through a CVD (Chemical Vapor Deposition) process (step ST221), thereby forming the sealing layer SE1 that covers the upper electrode UE1, the cap layer CP1, and the partition wall 6.

[0088] The second thin film 32 includes, for example, the organic layer OR2, the upper electrode UE2, the cap layer CP2, and the sealing layer SE2 shown in FIG. In this case, the process of forming the second thin film 32 is the same as the process of forming the first thin film 31, except that in step ST214 above, the light-emitting layer EM2 is formed instead of the light-emitting layer EM1, and therefore the explanation will be omitted.

[0089] The third thin film 33 includes, for example, the organic layer OR3, the upper electrode UE3, the cap layer CP3, and the sealing layer SE3 shown in FIG. In this case, the process of forming the third thin film 33 is the same as the process of forming the first thin film 31, except that in step ST214 above, the light-emitting layer EM3 is formed instead of the light-emitting layer EM1, and therefore the explanation will be omitted.

[0090] 7 is a flow diagram illustrating an example of the thin film removing step. The thin film removing step described here corresponds to the step of removing the first thin film 31 (step ST23), the step of removing the second thin film 32 (step ST33), and the step of removing the third thin film 33 (step ST43). The step of removing the first thin film 31 will be described below.

[0091] First, using the first resist 41 formed in step ST22 as a mask, dry etching is performed to remove the sealing layer SE1 exposed from the first resist 41 (step ST231). Thereafter, using the first resist 41 as a mask, wet etching is performed to remove the inorganic layer IL exposed from the sealing layer SE1 (step ST232). Thereafter, using the first resist 41 as a mask, dry etching is performed to remove the transparent layer TL exposed from the inorganic layer IL (step ST233). Thereafter, using the first resist 41 as a mask, wet etching is performed to remove the upper electrode UE1 exposed from the transparent layer TL (step ST234). Thereafter, using the first resist 41 as a mask, dry etching is performed to remove the organic layer OR1 exposed from the upper electrode UE1 (step ST235).

[0092] The process of removing the second thin film 32 is substantially the same as steps ST231 to ST235 described above, and will be briefly described below. First, the second resist 42 formed in step ST32 is used as a mask to remove the sealing layer SE2 exposed from the second resist 42. Thereafter, the inorganic layer IL exposed from the sealing layer SE2 is removed, the transparent layer TL exposed from the inorganic layer IL is removed, and the upper electrode UE2 exposed from the transparent layer TL is removed. Thereafter, the organic layer OR2 exposed from the upper electrode UE2 is removed.

[0093] The process of removing the third thin film 33 is substantially the same as steps ST231 to ST235 described above, and will be briefly described below. First, the third resist 43 formed in step ST42 is used as a mask to remove the sealing layer SE3 exposed from the third resist 43. Thereafter, the inorganic layer IL exposed from the sealing layer SE3 is removed, the transparent layer TL exposed from the inorganic layer IL is removed, and the upper electrode UE3 exposed from the transparent layer TL is removed. Thereafter, the organic layer OR3 exposed from the upper electrode UE3 is removed.

[0094] Steps ST1 and ST4 will be described below with reference to FIGS.

[0095] First, in step ST1, a process substrate SUB is prepared as shown in the upper part of FIG. 8 . The process of preparing the process substrate SUB includes the steps of forming a circuit layer 11 on a substrate 10, forming an insulating layer 12 on the circuit layer 11, forming a lower electrode LE1 for subpixel SP1, a lower electrode LE2 for subpixel SP2, and a lower electrode LE3 for subpixel SP3 on the insulating layer 12, forming a rib 5 having openings AP1, AP2, and AP3 overlapping with the lower electrodes LE1, LE2, and LE3, respectively, and forming a partition wall 6 including a lower portion 61 disposed on the rib 5 and an upper portion 62 disposed on the lower portion 61 and protruding from a side surface of the lower portion 61. As described above, the area of ​​opening AP1 is larger than the area of ​​opening AP, and the area of ​​opening AP2 is larger than the area of ​​opening AP3. Note that the cross sections shown in FIGS. 8 to 15 correspond to cross sections taken along line III-III in FIG. 2, for example, and the relative sizes of the areas of the openings are not reflected in the figures. 9 to 15, the substrate 10 and the circuit layer 11 below the insulating layer 12 are omitted from the illustration.

[0096] 8, the first thin film 31 is formed across the subpixels SP1, SP2, and SP3. The process of forming the first thin film 31 includes the steps of forming, on the processing substrate SUB, an organic layer OR1 including an emitting layer EM1 that emits light in the blue wavelength region, forming an upper electrode UE1 on the organic layer OR1, forming a cap layer CP1 on the upper electrode UE1, and forming a sealing layer SE1 on the cap layer CP1.

[0097] The organic layer OR1 is formed on each of the lower electrodes LE1, LE2, and LE3, and also on the partition wall 6. Of the organic layer OR1, the portion formed on the upper portion 62 is separated from the portions formed on the lower electrodes.

[0098] The upper electrode UE1 is formed on the organic layer OR1 directly above the lower electrodes LE1, LE2, and LE3, and is in contact with the lower portion 61 of the partition wall 6. The upper electrode UE1 is also formed on the organic layer OR1 directly above the upper portion 62. The portion of the upper electrode UE1 formed directly above the upper portion 62 is spaced apart from the portions formed directly above each lower electrode.

[0099] The cap layer CP1 is formed on the upper electrode UE1 directly above the lower electrodes LE1, LE2, and LE3, and is also formed on the upper electrode UE1 directly above the upper portion 62. The portion of the cap layer CP1 formed directly above the upper portion 62 is spaced apart from the portions formed directly above each lower electrode.

[0100] The sealing layer SE1 is formed so as to cover the cap layer CP1 and the partition wall 6. That is, the sealing layer SE1 is formed on the cap layer CP1 directly above the lower electrodes LE1, LE2, and LE3, and is also formed on the cap layer CP1 directly above the upper portion 62. In the sealing layer SE1, the portion formed directly above the upper portion 62 is connected to the portions formed directly above each lower electrode.

[0101] Next, in step ST22, as shown in FIG. 9, a first resist 41 is formed on the sealing layer SE1. First, as shown in the upper part of FIG. 9, the first resist 41 is applied over the entire surface of the sealing layer SE1. Then, as shown in the lower part of FIG. 9, the first resist 41 is patterned. The first resist 41 covers the first thin film 31 of the subpixel SP1 and exposes the first thin films 31 of the subpixels SP2 and SP3. That is, the first resist 41 is disposed directly above the lower electrode LE1. The first resist 41 also extends above the partition wall 6 from the subpixel SP1. On the partition wall 6 between the subpixels SP1 and SP2, the first resist 41 is disposed on the subpixel SP1 side (the right side of the figure) and exposes the sealing layer SE1 on the subpixel SP2 side (the left side of the figure). The first resist 41 also exposes the sealing layer SE1 in the subpixels SP2 and SP3.

[0102] 10, etching is performed using the first resist 41 as a mask to remove the first thin film 31 in the subpixels SP2 and SP3 that is exposed through the first resist 41, leaving the first thin film 31 in the subpixel SP1. That is, the sealing layer SE1, cap layer CP1, upper electrode UE1, and organic layer OR1 are removed from the subpixels SP2 and SP3. As a result, the lower electrode LE2 is exposed through the opening AP2 in the subpixel SP2, and the rib 5 surrounding the lower electrode LE2 is also exposed. Furthermore, the lower electrode LE3 is exposed through the opening AP3 in the subpixel SP3, and the rib 5 surrounding the lower electrode LE3 is also exposed. Furthermore, part of the sealing layer SE1, part of the cap layer CP1, part of the upper electrode UE1, and part of the organic layer OR1 are removed from the partition wall 6 between the subpixels SP1 and SP2, thereby exposing the subpixel SP2 side of the partition wall 6. In addition, the partition wall 6 between the subpixels SP2 and SP3 is exposed.

[0103] Next, in step ST24, as shown in the lower part of FIG. 10, the first resist 41 is removed, thereby exposing the sealing layer SE1 of the subpixel SP1. Through steps ST21 to ST24, a display element 201 is formed in the subpixel SP1. The display element 201 is composed of a lower electrode LE1, an organic layer OR1 including an emitting layer EM1, an upper electrode UE1, and a cap layer CP1. The display element 201 is also covered with the sealing layer SE1.

[0104] A laminate of an organic layer OR1 including an emitting layer EM1, an upper electrode UE1, a cap layer CP1, and a sealing layer SE1 is formed on the partition wall 6 between the subpixels SP1 and SP2. The portion of the partition wall 6 on the side of the subpixel SP1 is covered with the sealing layer SE1.

[0105] 11, the second thin film 32 is formed across the subpixels SP1, SP2, and SP3. The second thin film 32 covers the first thin film 31 in the subpixel SP1. The process of forming the second thin film 32 includes the steps of forming, on the processing substrate SUB, an organic layer OR2 including an emitting layer EM2 that emits light in the green wavelength range, forming an upper electrode UE2 on the organic layer OR2, forming a cap layer CP2 on the upper electrode UE2, and forming a sealing layer SE2 on the cap layer CP2.

[0106] The organic layer OR2 is formed on the lower electrode LE2 and the lower electrode LE3, and is also formed on the sealing layer SE1 of the subpixel SP1. The organic layer OR2 is also formed on the partition wall 6. A portion of the organic layer OR2 formed on the partition wall 6 between the subpixels SP1 and SP2 is spaced apart from a portion formed directly above the lower electrode LE2. A portion of the organic layer OR2 formed on the partition wall 6 between the subpixels SP2 and SP3 is spaced apart from a portion formed directly above the lower electrode LE2 and a portion formed directly above the lower electrode LE3.

[0107] The upper electrode UE2 is formed on the organic layer OR2. The upper electrode UE2 formed directly on the lower electrodes LE2 and LE3 is in contact with the lower portion 61 of the partition wall 6. The upper electrode UE2 is also formed on the organic layer OR2 directly above the upper portion 62.

[0108] The cap layer CP2 is formed directly above the lower electrodes LE1, LE2, and LE3, and directly above the partition wall 6 on the upper electrode UE2.

[0109] The sealing layer SE2 is formed so as to cover the cap layer CP2 and the partition wall 6. That is, the sealing layer SE2 is formed on the cap layer CP2 directly above the lower electrode LE1, the lower electrode LE2, and the lower electrode LE3, and is also formed on the cap layer CP2 directly above the upper portion 62.

[0110] Subsequently, in step ST32, a second resist 42 is formed on the sealing layer SE2. First, as shown in the lower part of FIG. 11, the second resist 42 is applied over the entire surface of the sealing layer SE2. Then, as shown in the upper part of FIG. 12, the second resist 42 is patterned. The second resist 42 covers the second thin film 32 of the subpixel SP2 and exposes the second thin films 32 of the subpixels SP1 and SP3. In other words, the second resist 42 is disposed directly above the lower electrode LE2. The second resist 42 also extends from the subpixel SP2 above the partition wall 6. The second resist 42 also exposes the sealing layer SE2 in the subpixels SP1 and SP3.

[0111] 12, in step ST33, etching is performed using the second resist 42 as a mask to remove the second thin film 32 in the subpixels SP1 and SP3 that is exposed through the second resist 42, leaving the second thin film 32 in the subpixel SP2. That is, the sealing layer SE2, cap layer CP2, upper electrode UE2, and organic layer OR2 in the subpixels SP1 and SP3 are removed. As a result, the sealing layer SE1 in the subpixel SP1 is exposed, and the lower electrode LE3 is exposed from the opening AP3 in the subpixel SP3, and the rib 5 surrounding the lower electrode LE3 is also exposed.

[0112] Furthermore, a part of the sealing layer SE2, a part of the cap layer CP2, a part of the upper electrode UE2, and a part of the organic layer OR2 are removed from the partition wall 6 between the subpixels SP1 and SP2. The first thin film 31 and the second thin film 32 are separated from each other on the partition wall 6. That is, the sealing layer SE2, the cap layer CP2, the upper electrode UE2, and the organic layer OR2 remaining on the partition wall 6 are separated from the sealing layer SE1, the cap layer CP1, the upper electrode UE1, and the organic layer OR1 remaining on the partition wall 6. Furthermore, part of the sealing layer SE2, part of the cap layer CP2, part of the upper electrode UE2, and part of the organic layer OR2 are removed from the partition wall 6 between the subpixels SP2 and SP3, thereby exposing the subpixel SP3 side of the partition wall 6.

[0113] Next, in step ST34, as shown in the upper part of FIG. 13, the second resist 42 is removed, thereby exposing the sealing layer SE2 of the subpixel SP2. Through steps ST31 to ST34, the display element 202 is formed in the subpixel SP2. The display element 202 is composed of a lower electrode LE2, an organic layer OR2 including an emitting layer EM2, an upper electrode UE2, and a cap layer CP2. The display element 202 is also covered with the sealing layer SE2.

[0114] A laminate of an organic layer OR2 including an emitting layer EM2, an upper electrode UE2, a cap layer CP2, and a sealing layer SE2 is formed on the partition wall 6 between the subpixels SP1 and SP2 and on the partition wall 6 between the subpixels SP2 and SP3. The portion of the partition wall 6 on the side of the subpixel SP2 is covered with the sealing layer SE2.

[0115] 13, the third thin film 33 is formed over the subpixels SP1, SP2, and SP3. The third thin film 33 covers the first thin film 31 in the subpixel SP1 and the second thin film 32 in the subpixel SP2. The process of forming the third thin film 33 includes the steps of forming, on the process substrate SUB, an organic layer OR3 including an emission layer EM3 that emits light in the red wavelength region, forming an upper electrode UE3 on the organic layer OR3, forming a cap layer CP3 on the upper electrode UE3, and forming a sealing layer SE3 on the cap layer CP3.

[0116] The organic layer OR3 is formed on the lower electrode LE3, and is also formed on the sealing layer SE1 of the subpixel SP1 and on the sealing layer SE2 of the subpixel SP2. The organic layer OR3 is also formed on the partition wall 6. On the partition wall 6 between the subpixels SP1 and SP2, the organic layer OR3 covers the first thin film 31 and the second thin film 32. The portion of the organic layer OR3 formed on the partition wall 6 between the subpixels SP2 and SP3 is separated from the portion formed on the lower electrode LE3.

[0117] The upper electrode UE3 is formed on the organic layer OR3. The organic layer OR3 formed directly on the lower electrode LE3 is in contact with the lower part 61 of the partition wall 6. The upper electrode UE3 is also formed on the organic layer OR3 directly above the upper part 62.

[0118] The cap layer CP3 is formed directly above the lower electrodes LE1, LE2, and LE3, and directly above the partition wall 6 on the upper electrode UE3.

[0119] The sealing layer SE3 is formed so as to cover the cap layer CP3 and the partition wall 6. That is, the sealing layer SE3 is formed on the cap layer CP3 directly above the lower electrode LE1, the lower electrode LE2, and the lower electrode LE3, and is also formed on the cap layer CP3 directly above the upper portion 62.

[0120] Next, in step ST42, a third resist 43 is formed on the sealing layer SE3. First, as shown in the upper part of FIG. 14, the third resist 43 is applied over the entire surface of the sealing layer SE3. Then, as shown in the lower part of FIG. 14, the third resist 43 is patterned. The third resist 43 covers the third thin film 33 in the subpixel SP3 and exposes the third thin films 33 in the subpixels SP1 and SP2. In other words, the third resist 43 is disposed directly above the lower electrode LE3. The third resist 43 also extends from the subpixel SP3 above the partition wall 6. The third resist 43 also exposes the sealing layer SE3 in the subpixels SP1 and SP2.

[0121] 15, in step ST43, etching is performed using the third resist 43 as a mask to remove the third thin film 33 in the subpixels SP1 and SP2 that is exposed from the third resist 43, leaving the third thin film 33 in the subpixel SP3. That is, the sealing layer SE3, cap layer CP3, upper electrode UE3, and organic layer OR3 in the subpixels SP1 and SP2 are removed. As a result, the sealing layer SE1 in the subpixel SP1 and the sealing layer SE2 in the subpixel SP2 are exposed.

[0122] Furthermore, the sealing layer SE3, the cap layer CP3, the upper electrode UE3, and the organic layer OR3 are removed from the partition wall 6 between the subpixels SP1 and SP2. Furthermore, a part of the sealing layer SE3, a part of the cap layer CP3, a part of the upper electrode UE3, and a part of the organic layer OR3 are removed from the partition wall 6 between the subpixels SP2 and SP3. On the partition wall 6, the second thin film 32 and the third thin film 33 are separated.

[0123] Next, in step ST44, as shown in the lower part of FIG. 15, the third resist 43 is removed, thereby exposing the sealing layer SE3 of the subpixel SP3. Through steps ST41 to ST44, the display element 203 is formed in the subpixel SP3. The display element 203 is composed of a lower electrode LE3, an organic layer OR3 including an emitting layer EM3, an upper electrode UE3, and a cap layer CP3. The display element 203 is also covered with the sealing layer SE3. On the partition wall 6 between the subpixels SP2 and SP3, a laminate of an organic layer OR3 including an emitting layer EM3, an upper electrode UE3, a cap layer CP3, and a sealing layer SE3 is formed.

[0124] Through the above steps, a display element 201 is formed in the subpixel SP1, a display element 202 is formed in the subpixel SP2, and a display element 203 is formed in the subpixel SP3.

[0125] Among the above processes, in the process of forming the second thin film 32 in step ST31, the light-emitting layer EM2 may be formed from a material that emits light in the red wavelength region, and in the process of forming the third thin film 33 in step ST41, the light-emitting layer EM3 may be formed from a material that emits light in the green wavelength region.

[0126] In the above example, the subpixel SP1 corresponds to the first subpixel, the opening AP1 corresponds to the first opening, the lower electrode LE1 corresponds to the first lower electrode, the organic layer OR1 corresponds to the first organic layer, the emitting layer EM1 corresponds to the first emitting layer, the upper electrode UE1 corresponds to the first upper electrode, the cap layer CP1 corresponds to the first cap layer, and the sealing layer SE1 corresponds to the first sealing layer. Furthermore, the subpixel SP2 corresponds to the second subpixel, the opening AP2 corresponds to the second opening, the lower electrode LE2 corresponds to the second lower electrode, the organic layer OR2 corresponds to the second organic layer, the emitting layer EM2 corresponds to the second emitting layer, the upper electrode UE2 corresponds to the second upper electrode, the cap layer CP2 corresponds to the second cap layer, and the sealing layer SE2 corresponds to the second sealing layer. Furthermore, the subpixel SP3 corresponds to the third subpixel, the opening AP3 corresponds to the third opening, the lower electrode LE3 corresponds to the third lower electrode, the organic layer OR3 corresponds to the third organic layer, the emitting layer EM3 corresponds to the third emitting layer, the upper electrode UE3 corresponds to the third upper electrode, the cap layer CP3 corresponds to the third cap layer, and the sealing layer SE3 corresponds to the third sealing layer.

[0127] According to this embodiment, the subpixel SP1, which has the largest aperture area, is formed first in the pixel PX. This allows the organic layer OR1, which contains sensitive materials, to be formed on the lower electrode LE1, which has the least damage from etching and a good surface condition. The organic layer OR1 is then protected by the upper electrode UE1, cap layer CP1, and sealing layer SE1. Therefore, the organic layer OR1 is not damaged in the subsequent etching process, and the organic layer OR1 can be maintained in a high-quality state. In addition, in the pixel PX, the subpixel SP3, which has the smallest aperture area, is formed last. As a result, the organic layer OR3, which contains a material that is less susceptible to process variations, is formed on the lower electrode LE3, which is most damaged by etching during the manufacturing process.

[0128] Therefore, any of the organic layers OR1, OR2, and OR3 is prevented from deteriorating significantly early due to adverse effects during the manufacturing process, resulting in problems such as reduced brightness, shortened lifespan, and fluctuations in chromaticity.

[0129] As described above, according to this embodiment, it is possible to provide a manufacturing method for a display device that can suppress a decrease in reliability and improve manufacturing yield.

[0130] All display device manufacturing methods that can be implemented by a person skilled in the art by making appropriate design modifications based on the display device manufacturing method described above as an embodiment of the present invention also fall within the scope of the present invention as long as they include the gist of the present invention.

[0131] Within the scope of the concept of the present invention, a person skilled in the art may conceive of various modifications, and these modifications are also understood to fall within the scope of the present invention. For example, even if a person skilled in the art appropriately adds or deletes components or modifies the design of the above-described embodiment, or adds or omits steps or modifies conditions, these modifications are also included within the scope of the present invention as long as they maintain the gist of the present invention.

[0132] Furthermore, with regard to other effects brought about by the aspects described in the above embodiments, those that are clear from the description in this specification or that can be appropriately thought of by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0133] DSP…display device 10...Substrate 12...Insulating layer 5...Rib AP1, AP2, AP3...Opening 6...Bulkhead 61...Lower 62...Upper PX...pixel SP1, SP2, SP3...subpixel 20, 201, 202, 203...Display element (organic EL element) LE, LE1, LE2, LE3...lower electrode (anode) UE, UE1, UE2, UE3...Upper electrode (cathode) OR,OR1,OR2,OR3…Organic layer CP, CP1, CP2, CP3...cap layer SE, SE1, SE2, SE3…Sealing layer 31...First thin film 32...Second thin film 33...Third thin film 41...First resist 42...Second resist 43...Third resist

Claims

1. preparing a processing substrate on which a first lower electrode of a first subpixel, a second lower electrode of a second subpixel, and a third lower electrode of a third subpixel are formed, and on which a rib is formed, the rib having a first opening overlapping the first lower electrode, a second opening overlapping the second lower electrode, and a third opening overlapping the third lower electrode; forming a first thin film including a first light-emitting layer across the first subpixel, the second subpixel, and the third subpixel; forming a first resist that exposes the first thin film of the second subpixel and the third subpixel and covers the first thin film of the first subpixel; removing the first thin film of the second subpixel and the third subpixel using the first resist as a mask, so that the first thin film remains in the first subpixel, and the second lower electrode is exposed from the second opening and the third lower electrode is exposed from the third opening; removing the first resist; forming a second thin film including a second light-emitting layer across the first subpixel, the second subpixel, and the third subpixel; forming a second resist that exposes the second thin film of the first subpixel and the third subpixel and covers the second thin film of the second subpixel; removing the second thin film of the first subpixel and the third subpixel using the second resist as a mask, so that the second thin film remains in the second subpixel and the third lower electrode is exposed through the third opening; removing the second resist; A method for manufacturing a display device, wherein an area of ​​the first opening is larger than an area of ​​the second opening.

2. After removing the second resist, forming a third thin film including a third light-emitting layer across the first subpixel, the second subpixel, and the third subpixel; forming a third resist that exposes the third thin film of the first subpixel and the second subpixel and covers the third thin film of the third subpixel; removing the third thin film from the first subpixel and the second subpixel using the third resist as a mask, so that the third thin film remains in the third subpixel; removing the third resist; The method for manufacturing a display device according to claim 1 , wherein an area of ​​the second opening is larger than an area of ​​the third opening.

3. The method for manufacturing a display device according to claim 1 , wherein the first light-emitting layer is formed of a material that emits light in a blue wavelength range.

4. the first light-emitting layer is formed of a material that emits light in a blue wavelength region, the second light-emitting layer is formed of a material that emits light in a green wavelength range, The method for manufacturing a display device according to claim 2 , wherein the third light-emitting layer is formed of a material that emits light in a red wavelength region.

5. the first light-emitting layer is formed of a material that emits light in a blue wavelength region, the second light-emitting layer is formed of a material that emits light in a red wavelength region, The method for manufacturing a display device according to claim 2 , wherein the third light-emitting layer is formed of a material that emits light in a green wavelength range.

6. The step of preparing the processing substrate further includes: The method of claim 2 , further comprising forming a partition wall including a lower portion located on the rib and an upper portion located on the lower portion and protruding from a side surface of the lower portion.

7. The method for manufacturing a display device according to claim 6 , wherein the lower portion of the partition wall is formed of a conductive material.

8. In the step of forming the first thin film, forming a first organic layer including the first light-emitting layer on each of the first lower electrode, the second lower electrode, and the third lower electrode; forming a first upper electrode on the first organic layer so as to be in contact with the lower portion of the partition wall; forming a first cap layer on the first upper electrode; The method for manufacturing a display device according to claim 7 , further comprising forming a first sealing layer on the first cap layer.

9. In the step of forming the second thin film, forming a second organic layer including the second light-emitting layer on the second lower electrode, the third lower electrode, and the first sealing layer of the first subpixel; forming a second upper electrode on the second organic layer so as to be in contact with the lower portion of the partition wall; forming a second cap layer on the second upper electrode; The method for manufacturing a display device according to claim 8 , further comprising forming a second sealing layer on the second cap layer.

10. In the step of forming the third thin film, forming a third organic layer including the third light-emitting layer on the third lower electrode, on the first sealing layer of the first subpixel, and on the second sealing layer of the second subpixel; forming a third upper electrode on the third organic layer so as to be in contact with the lower portion of the partition wall; forming a third cap layer on the third upper electrode; The method for manufacturing a display device according to claim 9 , further comprising forming a third sealing layer on the third cap layer.

11. The method for manufacturing a display device according to claim 10 , wherein the first sealing layer, the second sealing layer, and the third sealing layer are formed of the same inorganic insulating material.

12. The method for manufacturing a display device according to claim 10 , wherein the rib, the first sealing layer, the second sealing layer, and the third sealing layer are made of silicon nitride.

13. preparing a processing substrate on which a first lower electrode of a first subpixel, a second lower electrode of a second subpixel, and a third lower electrode of a third subpixel are formed, and on which a rib is formed, the rib having a first opening overlapping the first lower electrode, a second opening overlapping the second lower electrode, and a third opening overlapping the third lower electrode; forming a first thin film including a first light-emitting layer that emits light in a blue wavelength range across the first subpixel, the second subpixel, and the third subpixel; forming a first resist that exposes the first thin film of the second subpixel and the third subpixel and covers the first thin film of the first subpixel; removing the first thin film of the second subpixel and the third subpixel using the first resist as a mask, so that the first thin film remains in the first subpixel, and the second lower electrode is exposed from the second opening and the third lower electrode is exposed from the third opening; removing the first resist; forming a second thin film including a second light-emitting layer that emits light in a green wavelength range across the first subpixel, the second subpixel, and the third subpixel; forming a second resist that exposes the second thin film of the first subpixel and the third subpixel and covers the second thin film of the second subpixel; removing the second thin film of the first subpixel and the third subpixel using the second resist as a mask, so that the second thin film remains in the second subpixel and the third lower electrode is exposed through the third opening; removing the second resist; forming a third thin film including a third light-emitting layer that emits light in a red wavelength range across the first subpixel, the second subpixel, and the third subpixel; forming a third resist that exposes the third thin film of the first subpixel and the second subpixel and covers the third thin film of the third subpixel; removing the third thin film from the first subpixel and the second subpixel using the third resist as a mask, so that the third thin film remains in the third subpixel; The method for manufacturing a display device further comprises removing the third resist.

14. preparing a processing substrate on which a first lower electrode of a first subpixel, a second lower electrode of a second subpixel, and a third lower electrode of a third subpixel are formed, and on which a rib is formed, the rib having a first opening overlapping the first lower electrode, a second opening overlapping the second lower electrode, and a third opening overlapping the third lower electrode; forming a first thin film including a first light-emitting layer that emits light in a blue wavelength range across the first subpixel, the second subpixel, and the third subpixel; forming a first resist that exposes the first thin film of the second subpixel and the third subpixel and covers the first thin film of the first subpixel; removing the first thin film of the second subpixel and the third subpixel using the first resist as a mask, so that the first thin film remains in the first subpixel, and the second lower electrode is exposed from the second opening and the third lower electrode is exposed from the third opening; removing the first resist; forming a second thin film including a second light-emitting layer that emits light in a red wavelength range across the first subpixel, the second subpixel, and the third subpixel; forming a second resist that exposes the second thin film of the first subpixel and the third subpixel and covers the second thin film of the second subpixel; removing the second thin film of the first subpixel and the third subpixel using the second resist as a mask, so that the second thin film remains in the second subpixel and the third lower electrode is exposed through the third opening; removing the second resist; forming a third thin film including a third light-emitting layer that emits light in a green wavelength range across the first subpixel, the second subpixel, and the third subpixel; forming a third resist that exposes the third thin film of the first subpixel and the second subpixel and covers the third thin film of the third subpixel; removing the third thin film from the first subpixel and the second subpixel using the third resist as a mask, so that the third thin film remains in the third subpixel; The method for manufacturing a display device further comprises removing the third resist.

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