Integration of power and optics with cold plates for delivery to electronic and photonic integrated circuits.

Abstract

In one embodiment, the apparatus includes an upper cold plate and a lower cold plate, at least one of the upper cold plate or the lower cold plate having an electrical or optical path extending therethrough, a substrate and die package interposed between the upper cold plate or the lower cold plate, and a connector coupled to one of the upper cold plate or the lower cold plate for transmitting power or an optical signal to the substrate and die package through the electrical or optical path.

Description

[Technical Field]

[0001] The present disclosure relates generally to power and optical integration, and more particularly to power and optical signal distribution in electronics and photonics packages. [Background technology]

[0002] As ASIC (application-specific integrated circuit) process nodes advance and device power continues to increase, delivering the required power becomes more challenging. Higher power distribution also presents additional thermal challenges. When ASICs or other electronic integrated circuits are packaged with cold plates, additional difficulties arise in delivering power to the electronic integrated circuit and optical signals to the photonic integrated circuit. [Brief explanation of the drawings]

[0003] [Figure 1] FIG. 1 is a block diagram illustrating one embodiment of power distribution and optical signal transmission through a point-of-load (POL) module. [Figure 2] FIG. 1 is a schematic perspective view of a POL module, a cold plate with a power delivery block having power vias for delivery of power from the POL module, and an optical path for transmission of an optical signal through the cold plate, according to one embodiment. [Figure 3] FIG. 1 is a cross-sectional schematic diagram of a POL module and a substrate and die package interposed between two cold plates, according to one embodiment. [Figures 4A-4D] 1A-1C are cross-sectional schematic diagrams illustrating a manufacturing process for creating an optical path through a cold plate according to one embodiment. [Figure 5] FIG. 1 is a schematic diagram illustrating the attachment of an optical path to a substrate and die package according to one embodiment. [Figure 6] 1 is a schematic perspective view illustrating a connector optically coupled to an optical path and electrically coupled to a POL module according to one embodiment. FIG. [Figure 7]FIG. 7 is a perspective view that schematically illustrates details of the connector shown in FIG. 6 aligned with a cable and connector assembly, according to one embodiment. [Figure 8A] FIG. 1 is an exploded perspective view of an optical and electrical connector and cable and connector assembly according to one embodiment. [Figure 8B] 8B is a perspective view of a cable and connector assembly coupled to the optical and electrical connector of FIG. 8A. [Figure 9] 1 is a flowchart illustrating an overview of a process for distributing power and electronics through multiple cold plates, according to one embodiment. [Figure 10] 1 is a schematic perspective view of a substrate and die package interposed between a cold plate having a POL module and an optical connector mounted on the cold plate, according to one embodiment. FIG. [Figure 11] FIG. 11 is a partial exploded view of the assembly shown in FIG. 10 showing details of the substrate and die packaging and the lower cold plate. [Figure 12] FIG. 11 is an exploded view of a portion of the assembly shown in FIG. 10 showing details of the substrate and die packaging and the top cold plate. [Figure 13] FIG. 2 is a side view of a substrate and die package and a cold plate according to one embodiment. [Figure 14] FIG. 14 is a cross-sectional view of the assembly shown in FIG. 13.

[0004] Corresponding reference characters indicate corresponding parts throughout the several views of the drawings. DETAILED DESCRIPTION OF THE INVENTION

[0005] overview Aspects of the invention are set out in the independent claims and preferred features are set out in the dependent claims. Features of one aspect may be applied to any aspect alone or in combination with other aspects.

[0006] In one embodiment, the apparatus generally includes an upper cold plate and a lower cold plate, at least one of the upper cold plate or the lower cold plate having an electrical or optical path extending therethrough, a substrate and die package interposed between the upper and lower cold plates, and a connector coupled to one of the upper or lower cold plate for transmitting power or an optical signal to the substrate and die package through the electrical or optical path.

[0007] In another embodiment, an apparatus generally comprises: a first cold plate including an electrical path extending therethrough; a second cold plate including an optical path extending therethrough; a substrate and die package including at least one electronic integrated circuit and at least one photonic integrated circuit, the substrate and die package being interposed between the first and second cold plates; an electrical connector coupled to the first cold plate for transmitting power or an electrical signal through the electrical path; and an optical connector coupled to the second cold plate for transmitting an optical signal through the optical path.

[0008] In yet another embodiment, a method generally includes creating electrical and optical paths through cold plates, positioning the cold plates on opposite sides of a substrate and die package, and transmitting electrical power through the electrical paths and optical signals through the optical paths, wherein electrical power is transmitted from a power connector coupled to one of the cold plates and optical signals are transmitted from or received at an optical connector coupled to one of the cold plates.

[0009] In a further embodiment, an apparatus generally comprises: a cold plate including a first side and a second side; a photonic integrated circuit connected to a substrate positioned on the second side of the cold plate; and an optical path extending through the cold plate and optically coupled to the photonic integrated circuit for transmitting an optical signal between the photonic integrated circuit and the first side of the cold plate.

[0010] In another embodiment, an apparatus generally comprises a connector for receiving or transmitting an optical signal, an optical path coupled to the connector and the photonic integrated circuit, and a cold plate interposed between the connector and the photonic integrated circuit, the optical path extending through the cold plate.

[0011] In yet another embodiment, a method generally includes attaching a substrate to a cold plate, the substrate comprising at least one photonic die connected thereto, and creating an optical path through the cold plate and the substrate, wherein an optical signal is transmitted to or from the photonic die through the optical path in the cold plate and the substrate.

[0012] A further understanding of the features and advantages of the embodiments described herein may be realized by reference to the remaining portions of the specification and the attached drawings.

[0013] Illustrative Embodiments The following description is presented to enable those skilled in the art to make and use the embodiments. Descriptions of specific embodiments and applications are provided by way of example only, and various modifications will be readily apparent to those skilled in the art. The general principles described herein may be applied to other applications without departing from the scope of the embodiments. Thus, the embodiments should not be limited to those shown, but should be accorded the widest scope consistent with the principles and features described herein. For clarity, details relating to technical materials known in the technical fields relevant to the embodiments have not been described in detail.

[0014] Power distribution systems can be configured to deliver power from a point-of-load (POL) to an ASIC (application-specific integrated circuit) or other integrated circuit. Increased power requirements may necessitate additional thermal considerations. Optical applications within a package may present additional challenges, including integrating optics and delivering optical signals without impacting the cooling system.

[0015] One or more embodiments described herein provide for the integration of power and optics for delivery to electronic and photonic integrated circuits (ICs) (die, ASIC, chip) through one or more cold plates. As described in detail below, one or more electrical and optical paths are formed within the cold plate to allow power to pass from POLs to electronic components coupled to the substrate and to allow optical signals to pass through the cold plate to the photonic elements. The cold plate may comprise, for example, a power delivery block (e.g., a PCB (printed circuit board)) having one or more power vias for transferring power through the cold plate and one or more openings for defining the optical path. The optical path may comprise one or more optical elements (e.g., waveguides, mirrors, or other optics) for transmitting optical signals through the cold plate and directing the optical signals to or from the photonic integrated circuit. As described in detail below, the optical path may be coupled to a connector positioned on the cold plate for receiving or transmitting optical signals. The connector may also be configured to receive power (eg, multi-phase pulsed power) that may be delivered to the POL for distribution through the cold plate.

[0016] The embodiments described herein operate in the context of a data communications network including multiple network devices. The network may include any number of network devices communicating through any number of nodes (e.g., routers, switches, gateways, controllers, edge devices, access devices, aggregation devices, core nodes, intermediate nodes, power supplies, power devices, or other network devices) that facilitate the passage of data within the network. One or more of the network devices may comprise one or more power and optics distribution systems described herein. The network devices may further include any combination of memory, processors, power supply units, and network interfaces.

[0017] Referring now to the drawings, and initially to Figure 1, there is shown a block diagram illustrating one example of power distribution through a POL power supply located on board 10, according to one embodiment. As will be described in detail below, optics 11 are integrated with the power system, and an optical path is created to transmit optical signals through the cold plate and substrate to or from a photonic chip 13 (photonic die, photonic integrated circuit, integrated optical circuit, optical engine) that integrates multiple photonic functions.

[0018] Power is delivered to multiple POLs (POL modules (circuits), power supply components) 14a, 14c, 14d, and 14e in element 12. In one embodiment, pulsed power at a voltage greater than 100V (e.g., 108V, 380V) or any other suitable voltage is delivered to fixed POL 14a. Power supply 12 may also deliver pulsed power to POLs 14c, 14d, and 14e (e.g., fixed POLs). In another embodiment, power supply 12 delivers 54VDC (or any other suitable voltage (e.g., intermediate bus voltage level selected based on overall system efficiency, routability, and cost)) to POL modules 14c, 14d, and 14e. The fixed POL 14a transfers power (e.g., 54 VDC or other voltage) to the regulated POL (POL converter, POL regulator) 14b, which distributes the power to the ASIC 16 (e.g., an integrated circuit, die, chip, multi-chip module, etc.). As described below, the fixed POL 14a may be connected to the regulated POL 14b through a busbar interconnect or any other suitable electrical connection. The regulated POL 14b may provide, for example, 150 amps or more of output. Each power connection may also include 10 Mbps (or any other data rate) communication. In the embodiment shown in FIG. 1, power is delivered from the regulated POL module 14b to the ASIC 16 via a voltage rail. Power may be provided to the ASIC 16 in a multi-drop configuration, for example.

[0019] It should be understood that, as used herein, the term "POL module" may refer to various types of POL configurations, including, for example, individual POLs and modules, or power delivery block-based voltage regulator designs. It may also be understood that the POLs may be single-phase or multi-phase POLs that may work together to deliver one or more outputs.

[0020] The system components (POL modules, cold plates, electronic and photonic packages (substrate and die packages)) are connected to board 10. Board 10 may comprise a printed circuit board, or the components may be mounted directly to a sheet metal module, wiring card, or any other suitable support member. For example, the wiring card circuit board may be removed and the electronic packages interconnected through fiber and copper connections at the ASIC edge.

[0021] As mentioned above, pulsed power may be supplied to one or more of the POL modules. As used herein, the term “pulsed power” (also referred to as “pulsed power”) refers to power delivered in multiple voltage pulses (a series of voltage pulses) 18a, where the voltage varies between a very small voltage (e.g., close to 0 V, 3 V) during pulse-off time 19a and a larger voltage (e.g., ≥ 12 V) during pulse-on time 19b. High-voltage pulsed power (high-voltage pulses) (e.g., > 56 V, ≥ 60 V, ≥ 300 V, ∼ 108 VDC, ∼ 380 VDC) may be transmitted from a power source equipment (PSE) to a powered device (PD) for use in powering the powered device, while low-voltage pulsed power (low-voltage pulses) (e.g., about 12 V, about 24 V, ≤ 30 V, ≤ 56 V) may be used at short intervals for startup (e.g., initialization, synchronization, charging a local energy store, powering up a controller, testing, or any combination thereof). For example, as described in U.S. Patent Application No. 16 / 671,508, filed November 1, 2019, entitled "Initialization and Synchronization for Pulse Power in a Network System," which is incorporated herein by reference in its entirety, high-voltage pulsed power may be transmitted from a power supply to a powered device for use in powering the powered device. Pulse transmission may occur via, for example, cables, transmission lines, bus bars, backplanes, PCBs (printed circuit boards), and power distribution systems.

[0022] In one or more embodiments, pulsed power may be delivered in multiple phases (18b, 18c in FIG. 1 ), with pulses offset from one another between phases to provide continuous power. As described in U.S. patent application Ser. No. 16 / 380,954, filed April 10, 2019 ("Multiple Phase Pulse Power in a Network Communications System"), which is incorporated herein by reference in its entirety, one or more embodiments may use multi-phase pulsed power to achieve fewer losses by using continuous, uninterrupted power with overlapping phase pulses to power devices.

[0023] It should be understood that the voltage, power, and current levels described herein are provided by way of example only, and that power may be delivered at different levels (volts, amperes, watts) than those described herein without departing from the scope of the embodiments. Power may be received as ESP (Enhanced Safety Power) (FMP (Fault Management Power)) (e.g., pulsed power, multi-phase pulsed power, pulsed power with fault detection and safety protection), PoE (Power over Ethernet), or in accordance with current or future standards.

[0024] As used herein, the term ESP (or FMP) refers to high-power (e.g., >100 watts (W)), high-voltage (e.g., ≥56 volts (V)) operation with pulsed power delivered to one or more wires or wire pairs within a cable (e.g., an Ethernet cable). In one or more embodiments, ESP includes fault detection (e.g., fault detection during initialization and between high-voltage pulses) and pulse synchronization. As shown in FIG. 1, pulsed power or multiphase pulsed power can be received at a fixed POL module 14a. As described below with respect to FIG. 6, pulsed power can be received at a connector mounted on the cold plate and transmitted to the fixed POL module through an interconnect.

[0025] FIG. 2 is a schematic perspective view illustrating the connection between fixed POL 20 and regulating POL 22, the distribution of power through cold plate 25, and the transport of optical data through the cold plate and substrate and die package 21, according to one embodiment. Fixed POL module 20 may provide input power to regulating POL module 22 via electrical connection 24, including, for example, a bus bar, wire, or other interconnect. For simplicity, only one POL module 22 is shown connected to cold plate 25, but any number of POL modules may be connected to the cold plate. Each POL may provide a single voltage rail or multiple voltage rails, as shown in FIG. 1. In the example shown in FIG. 2, optical path 23 extends through cold plate 25 and the substrate for transmitting optical signals through the cold plate.

[0026] In one or more embodiments, the device comprises a cold plate 25 including a first side 27a (top surface as viewed in FIG. 2) and a second side 27b (bottom surface) opposite the first side, a photonic integrated circuit (chip) 29 connected to a substrate (e.g., a printed circuit board, an interposer, a printed circuit board and an interposer) positioned on the second side of the cold plate, and an optical path 23 for transmitting an optical signal between the first side of the cold plate and the photonic integrated circuit, extending through the cold plate 25 and the substrate (extending into the substrate and die package 21) and optically coupled to the photonic integrated circuit.

[0027] As used herein, the term "substrate and die package" may refer to one or more electronic or photonic integrated circuits coupled to one or more substrates (printed circuit boards, electrical boards, ceramic substrates). One or more of the electronic or photonic integrated circuits may be attached to one or more sides of the substrate. For example, as described below with respect to FIGS. 13 and 14, an optical engine or SerDes (serializer / deserializer) may be implemented on both sides of the substrate. As used herein, the term "integrated circuit" may refer to an electronic integrated circuit, a photonic integrated circuit, an ASIC, an optical engine, a die, a silicon die, a chip, a chiplet, a SerDes circuit (chip), etc.

[0028] The optical path 23 is created to allow light (indicated by arrows in the optical path) to pass through the cold plate 25 and substrate to reach the optical engine (photonic integrated circuit, chip, die) 29. In the example shown in FIG. 2 , the photonic chip 29 is located below the substrate in the substrate-and-die package (described below with respect to FIG. 3 ). In another example, as illustrated in the alternative view shown in dashed lines in FIG. 2 , the photonic chip 29 may be located above the substrate (adjacent to the cold plate) where the optical path 23 does not need to extend through the substrate of the substrate-and-die package 21. The optical path 23 may comprise one or more waveguides or openings, for example, to receive optical fibers. In one or more embodiments, the optical path 23 may be configured for, for example, optical, laser-written waveguides in glass, free-space optics, or optical fibers. Cutouts may be made in the cold plate and substrate, and passages 23 may be inserted therein to link the POL module 22 and bus bar 24 to the photonic chip 29. In one example, the optics are integrated with power delivery via busbar 24. Optical path 23 may be aligned and optically coupled to photonics die 29 and module 22 as shown in FIG. 2, or may be interconnected with a connector having interlocking features as described below with respect to FIGS. 6 and 8A. Optical path 23 may be attached to chip 29 using an active or passive alignment process and an adhesive such as index-matching epoxy as described below with respect to FIG. 5. Optical path 23 may also be coupled to the edge, top, or bottom of die 29 as described below with respect to FIGS. 4A-4D. Various coupling approaches may be used, including, for example, edge coupling, vertical coupling, etc.

[0029] In one or more embodiments, the optical path 23 may be part of a dedicated cutout separate from the electronics, as shown in FIG. 2. In one or more embodiments, the optical path and the electrical path may be defined along the same cutout in the cold plate 25. For example, a piece of glass may be laser patterned with waveguides and plated with metal vias to form a combined optical and electrical path. Also, two or more optical paths 23 may be formed in the cold plate 25 and substrate to communicate with one or more photonic dies 29.

[0030] In one or more embodiments, the optical path 23 may be constructed from an optical bulk material (e.g., SiO2 or other suitable material) in which multiple waveguides and mirrors are defined, as described in U.S. Patent Application No. 16 / 546,084, filed August 20, 2019 ("Periscope Optical Assembly"), which is incorporated herein by reference in its entirety. The optical path 23 may include an optical path structure (e.g., a periscope optical assembly) including, for example, one or more waveguides, mirrors, lenses, optical gratings, filters, or any combination thereof. The optical system may be defined by various processes in the bulk material based on the refractive index and angle of light passing from one region to another. For example, a waveguide may be defined to confine light to a predetermined path within the bulk material, while the optical system (e.g., a mirror) may redirect light received in one direction to a second direction. Other optical systems may have other effects on the light carried in the bulk material, such as lenses that focus / converge or diffuse / diverge incident light, optical gratings that split and diffract light into several beams, and filters that filter out, block, attenuate, or polarize specific wavelengths of light. Laser patterning may be used to define the path of the waveguide, and physical or chemical etching processes may be used to form the mirrors. The mirrors may be defined, for example, as three-dimensional reflective structures within the bulk material, or they may be defined via reflective surface treatments. It may also be noted that the optical path 23 may be formed from one piece or multiple pieces combined together, as described below with respect to Figures 4A-4D. These are merely examples, and it should be understood that other processes may be used to define the optical system within the optical path 23, or other optical components may be used, without departing from the scope of the embodiments.

[0031] An example of a manufacturing process for creating the optical path 23 in the cold plate and substrate is described below with respect to Figures 4A-4D.

[0032] In addition to providing an optical path 23 through the cold plate 25 as described above, one or more electrical pathways 28 may be created within the cold plate. As shown in the example of FIG. 2, the cold plate 25 includes multiple power delivery blocks 26, each including multiple power vias (electrical pathways) 28 for transmitting power through the cold plate from the POL module 22 to the electronics package 21 (substrate and die package) (described below with respect to FIG. 3). Power is transmitted from a first side of the cold plate 25 (e.g., top surface 27a as shown in FIG. 2) to a second side of the cold plate opposite and generally parallel to the first side (e.g., bottom surface 27b as shown in FIG. 2). In one or more embodiments, the power delivery blocks 26 include small (miniature) power printed circuit boards. Depending on the application, other components may also be inserted into the cold plate 25, or strategically placed cutouts may be used.

[0033] The power delivery block 26 includes a plurality of through-holes (vias) 28 that extend through the entire thickness of the power delivery block (as shown in phantom in FIG. 2 ) and are plated along their interior surfaces. The through-holes may be created, for example, using a drilling process and plated with a metallic material (e.g., copper or any conductive or metallic layer). The plating may effectively coat the cylinder of the hole and create an electrical path 28 through the cold plate 25.

[0034] As used herein, the term "power delivery block" may refer to any block of thermally and electrically conductive material in which electrical paths (e.g., power vias) can be formed to enable the passage of power directly through the cold plate 25. The term "printed circuit board" is used herein as one example of a substrate for the power delivery block 26, although in other implementations, the PCB can be replaced with other substrates (e.g., ceramic circuit boards) or other elements. Non-printed circuit boards may also be used for the power delivery block 26. For example, a piece of glass may be laser patterned with waveguides and plated with metal vias to form combined optical and electrical paths. Also, as noted above, other components may be inserted into the cold plate 25 in addition to or instead of the PCB.

[0035] The cold plate 25 may include, for example, liquid, gas, or multiphase (multi-phase cold plate) based cooling. The through power vias 28 may deliver, for example, 10 amps per tube and may be cooled by the cold plate 25. In one or more embodiments, the cold plate 25 is formed with one or more openings for inserting one or more power delivery blocks 26, which may be press-fit into the cold plate 25, for example. An epoxy or adhesive filler may be used to press the power delivery blocks 26 into place within the cold plate 25. Epoxy may be used to account for the tolerance between the power delivery blocks 26 and the cold plate openings. If the cold plate 25 utilizes cooling tubes or reservoirs, these are routed or positioned around the power delivery blocks and optical path openings. The cold plate 25 keeps the temperature rise of the power vias 28 low, thereby maximizing current transfer from the POL 22 to the substrate and die package. In one embodiment, the cold plate 25 is configured with multiple internal zones to maintain an optical temperature below 75 degrees Celsius. The cold plates and temperatures described herein are merely examples, and other designs may be used to maintain cooling at different temperatures.

[0036] In one or more embodiments, the power block, power vias, and cold plate may be configured as described in U.S. Patent Application No. 16 / 743,371, filed January 15, 2020, entitled "Power Distribution from Point-of-Load With Cooling," which is incorporated herein by reference in its entirety.

[0037] Power delivery block 26 and vias 28 formed therein extend through cold plate 25 to provide power to attached substrate and die package 21. For simplicity, only a portion of power delivery block 26 and vias 28 are shown in phantom extending through cold plate 25. Also, while substrate and die package 21 is shown as a single block structure, it will be understood that the package may comprise one or more substrates having any number of components attached thereto (e.g., electronic integrated circuits, ASICs, photonic integrated circuits, optical engines, dies, chips, chiplets, FAUs (fiber attachment (array) units), CAUs (copper attachment (array) units)), as described below with respect to FIG. 3 .

[0038] In one or more embodiments, an additional cold plate 31 may be used, with the substrate and die package 21 interposed between the two cold plates 25, 31 to provide additional cooling. It may be appreciated that the use of a second cold plate 31 is optional based on power and cooling requirements. It should also be understood that the cold plates 25, 31 may include any number of individual cold plates. For example, a cold plate may comprise two or more smaller cold plates, with one or more of a power delivery block, electrical path, or optical path interposed therebetween.

[0039] In addition to passing power through the power delivery block 26, communications (e.g., control plane communications) may also pass through the power delivery block. Thus, electrical paths may transmit power or electrical signals therethrough. In one or more embodiments, regulation POL and ASIC control communications to the system FPGA (Field Programmable Gate Array) may pass through the cold plate 25 or ribbon cable. In one or more embodiments, communications may pass through communication vias (not shown) formed in the power delivery block, which may include both power and communication vias, or only communication vias. In one example, low-speed communications may pass through the POL (e.g., in the 200 Mbps range). The cold plate 25 may include any combination of power vias, communication vias, or power delivery blocks with optical paths. Control plane communications may also be provided through a separate communications element (e.g., via ribbon cable or other means) that may be used to route control communications in and out of the package. In one or more embodiments, full-speed PCIe (Peripheral Component Interconnect Express) or faster may be used. The cold plate 25 may be connected to any number or combination of POL modules 22 and communication modules.

[0040] It will be appreciated that the configuration shown in FIG. 2 is merely an example and that the cold plate may include any number, combination, or arrangement of power blocks 26, optical paths 23, and communication paths.

[0041] Note that terms such as lower, upper, bottom, top, lower, upper, horizontal, and vertical that may be used herein are relative terms that depend on the orientation of the package and components and should not be construed as limiting. These terms describe reference points and do not limit the embodiments to any particular orientation or configuration. For example, the assembly shown in FIG. 2 could be rotated 180 degrees (flipped vertically) with the POL module 22 mounted on the outer surface of the lower cold plate. Also, as described in more detail below with respect to FIGS. 10-14, power and optical signals could be transmitted through both cold plates, in which case the module 22 would be mounted on the outer surface (the surface not adjacent to the substrate and die package 21) with electrical paths 28 and optical paths 23 on both cold plates 25, 31.

[0042] Referring now to FIG. 3 , a cross-sectional schematic diagram illustrates an apparatus comprising a substrate 41 having a first surface 41 a and a second surface 41 b opposite the first surface; an integrated circuit (one or more dies (chips)) 33 mounted on the first surface of the substrate; a cold plate 35 mounted on the second surface of the substrate and having electrical pathways (e.g., power vias) 38 extending therethrough for transmitting power from a power supply component (e.g., a POL module) 32 to the electronic integrated circuit 33; and an optical pathway 48 for transmitting one or more optical signals to or from a photonic integrated circuit (photonic chip, optical engine) 39. As used herein, the term “substrate” may refer to an electrical substrate, a ceramic substrate, or an element formed from any other suitable material. As described below, the substrate may also comprise an interposer (e.g., a glass element laser patterned with waveguides and plated with metal vias to form combined optical and electrical pathways).

[0043] A bus bar 34 is shown connected to the multi-zone POL 30 (e.g., having DC power to rail voltages), and the POL module 32 is mounted to a cold plate 35 and configured to distribute power from the POL module to an electronics and optical package comprising a substrate 41 and an integrated circuit 33 (ASIC, NPU (Network Processing Unit), die, chip) and two optical engines (photonic integrated circuits) 39 (SerDes (Serializer / Deserializer) chiplets) mounted to the substrate 41. The electronics and optical package (also referred to herein as a substrate and die package) may comprise one or more integrated circuits, ASICs, NPUs, MCMs, dies, chips, chiplets, processors, electronic components, or photonic components mounted to one or more substrates. In the example of FIG. 3 , the substrate and die package includes the substrate 41, the NPU 33, the optical engine 39, and the FAU / CAU 40. It should be understood that this is just one example, and that the substrate and die package may include any number of components in any configuration. The FAU / CAU 40 may be attached to the underside of the optical engine 39 (as shown in FIG. 3 ), or may be located on or above the top of the optical engine 39, or may be removed if the optics and power are transmitted by other means. In the example of FIG. 3 , the second cold plate 37 is thermally coupled to the NPU 33 through a thermal conductor (interposer) 49. The thermal conductor (or multiple thermal conductors) may be disposed across multiple dies. One or more embodiments may also include an optional lid between the multi-chip module and the cold plate 37.

[0044] In the example shown in Figure 3, two optical paths 48 extend through the cold plate 35 and the substrate 41 and are optically coupled to one side of the photonic chip 39. As described below with respect to Figures 4A-4D, the optical paths 48 may also be coupled to the photonic chip 39 along the bottom edge of the chip. As described above with respect to Figure 2, the optical signal may be transmitted along with power in the POL module 32.

[0045] As previously mentioned, the cold plate 35 includes one or more power delivery blocks 36 (e.g., PWR PCBs) inserted into the cold plate and having one or more electrical paths (power vias) 38 formed therein. In one or more embodiments, the power delivery blocks 36 are formed separately from the cold plate 35 and inserted into openings 46 formed in the cold plate to receive the blocks. As discussed above, an epoxy or adhesive filler may be used to press and position the power delivery blocks 36 within the openings 46 in the cold plate 35.

[0046] The substrate 41 may have traces 43 and pads 45 embedded within or deposited on the substrate for connecting with the power vias 38 and dies 33, 39. Etching, deposition, bonding, or other processes may be used to form the traces and pads. The substrate 41 may be bonded to the cold plate 35 using a solder process, as is well known to those skilled in the art.

[0047] 3 are merely examples, and it should be understood that other types or numbers of components having different sizes and configurations, or additional components, may be used without departing from the scope of the embodiments. For example, one or more integrated circuits may be located on the top surface (opposite the substrate 41) of the cold plate 35. In one or more embodiments, the cold plate 35 may include only an optical path 48, with power provided to the electronic integrated circuit (NPU) 33 via a separate path.

[0048] Also, as noted above, terms such as lower, upper, bottom, top, below, and above are relative terms that depend on the orientation of the package. Thus, cold plate 35 may be a "lower cold plate," with optical and electrical paths extending upward through the cold plate to the substrate and die package. As described below, optical and electrical paths may be in both cold plates for distributing power and optical signals from both sides of the substrate and die package. As described below, optical engine 39 may also be positioned on the top surface of substrate 41.

[0049] 4A-4D, a manufacturing process for an optical path is shown, according to one embodiment. In this example, an interposer (e.g., a glass interposer) 51 is positioned between a substrate 41 and a photonic integrated circuit 39. The glass interposer 51 may include any number of optical or electrical connections between the substrate 41 and the photonic integrated circuit 39. The connections may include, for example, one or more power connections (e.g., conductive vias) 44, one or more high-speed signal connections, or any combination thereof. The interposer 51 may be formed from an optically transparent material, such as silicate glass, quartz, or any other suitable material. The interposer 51 may be coupled to the substrate 41 through any suitable surface mount technology. Solder balls may be attached to the interposer 51 and coupled to the circuitry of the substrate 41, for example, in a ball grid array. The photonic chip 39 is attached to the interposer 51 through any suitable means (e.g., bonding). In one or more embodiments, the photonic integrated circuit 39 may be coupled to an interposer 51, for example, as described in U.S. Pat. No. 10,393,959, issued August 27, 2019 ("Photonic Integrated Circuit Bonded with Interposer"). In the example shown in FIGS. 4A-4D, an electronic integrated circuit 53 is also shown coupled to the photonic integrated circuit 39.

[0050] It is understood that the term "substrate" as used herein with respect to Figures 4A-4D can refer to multiple elements (eg, printed circuit board 41 and interposer 51) or a single element or board.

[0051] Referring initially to FIG. 4A , a cross-sectional view illustrating a first opening 50 through the cold plate 35 and substrate 41 is shown. As described below with respect to FIG. 4B , the opening 50 is used to insert an optical path structure for communicating with the photonic chip 39 along the edge of the chip. A second opening 52 is shown extending through the cold plate 35, substrate 41, and interposer 51 to receive an optical path structure for communicating with the photonic chip 39 through the top surface of the chip. For simplicity, a schematic view with a cross-section through the openings 50, 52 is shown, and material behind the openings is not shown. In one or more embodiments, vertical or edge coupling may be used to attach the optical system to the photonic die 39. While two different optical path arrangements are shown in FIGS. 4A-4D for illustrative purposes, it is understood that only one of the paths may be used to provide an optical path through the cold plate 35 and substrate 41. In one or more embodiments, the interposer 51 may be shortened so that the opening 52 passes through the cold plate 35 and the substrate 41 and along one side of the interposer 51. Also, in one or more embodiments, an optical path may extend through the cold plate 35 and along the outer edge of the substrate 41 and interposer 51 and couple to the underside of the photonic die 39 through the use of optics that redirect light towards the underside of the die.

[0052] The optical engine (photonic integrated circuit, photonic die, photonic chip) 39 is first attached to the interposer 51 and substrate 41, and then attached to the cold plate 35. Cutouts 50, 52 may then be formed in the cold plate 35, substrate 41, and interposer 51 to accommodate the optical path. In one or more embodiments, a sleeve (not shown) may be inserted into the opening, which may be formed using any suitable process.

[0053] As shown in FIG. 4B , optical paths (optical path structures) 48 a, 48 b are positioned within openings 52, 50 and attached to the photonic die 39 to optically couple the photonic die to the optical paths. The optical paths 48 a, 48 b may be attached using active alignment, precision passive alignment, UV / thermal curing epoxy, or any other suitable process. Further details of attachment methods are described below with respect to FIG. 5 . Depending on where the optical connection is located on the die 39 (e.g., on the side or top as viewed in FIGS. 4A-4D ) and whether the light enters from the top or side of the die, the optical paths may attach to the die's surface (as shown for optical path 48 a) or one of its edges (as shown for optical path 48 b). The optical paths 48 a, 48 b each include a waveguide 55 a, 55 b defined to confine the light to a predetermined path. Optical path 48b includes a mirror (optical system) 56b for redirecting light received in one direction into a second direction. As noted above, each optical path 48a, 48b may include other optical components, such as lenses for focusing / converging or diffusing / diverging incident light, optical gratings for splitting and diffracting light into several beams, or filters for removing, blocking, attenuating, or polarizing light of specific wavelengths.

[0054] As shown in FIG. 4C, to simplify manufacturing, optical paths 48a, 48b may be plugged into or connected to another optical path (e.g., a periscope / routing structure) 57 to combine all of the optical signals. Optical path structure 57 includes a waveguide 55c and mirrors 56c, 56d to redirect light from optical paths 48a, 48b to optical connector 54 (FIG. 4D). Strain relief epoxy or filler may be used to further support the optical path structure. Index-matching epoxy may also be used within the optical paths to improve coupling at the connections between the optical paths.

[0055] 4D illustrates the completed assembly with POL module 32, optical connector 54, and the remaining mechanical components attached to complete the package. Optical path 57 may include an additional mirror (not shown) that redirects the light to connector 54.

[0056] As described above, the optical path may also extend through a lower cold plate positioned adjacent to the photonic chip 39, in which case the optical path may be coupled directly to the photonic chip without passing through the substrate 41 or interposer 51.

[0057] It is understood that the optical paths shown and described herein are merely examples, and that structures may be configured or fabricated differently than described or shown without departing from the scope of the embodiments. As noted above, multiple optical paths may be attached or plugged together to create an optical path between the top surface of the cold plate and the photonic die. Optical paths may be formed from a variety of materials (e.g., glass, heat-resistant polymers, etc.) using a variety of processes. In one example, laser patterning of glass may be used to write waveguides and precisely write and etch mechanical features such as plugs for interlock slots (described below with respect to FIG. 5). Laser patterning may also be used to pattern other glasses, such as Gorilla Glass (chemically strengthened glass) or flexible glass. As noted above, mirrors, lenses, or other optical elements may also be patterned into the optical path. Plated metal electrical vias may be created within the laser-patterned structure to allow electrical signals to be routed within the same structure as the optical signals.

[0058] FIG. 5 illustrates an example of an optical path 59 having an etched mirror 61 and opening 63 a for use in aligning the optical path with an interposer and photonic chip assembly 62. The optical path 59 includes a waveguide 60, a mirror 61, and openings 63 a for receiving alignment pins 63 b for attachment to the interposer and photonic chip assembly 62. Index-matching epoxy 64 may be used to hold the plug in place and ensure coupling between the plug 63 b and the optical path (e.g., periscope) 59. Also, more than one alignment pin may be used. As described above, active alignment may be used to attach the optical path 59, with alignment pins 63 b used to couple the optical path to an interposer or another optical path. In embodiments where edge coupling may not be used, the optical path may be attached by normal or evanescent coupling.

[0059] In one or more embodiments, optical signals and pulsed power may be received from connectors inserted into connector cages coupled to the optical paths, as shown in FIG. 6. As described above with respect to FIG. 2, fixed POL module 20 is coupled to regulating POL module 22 via power bridge 24. A high-power (ESP, pulsed power) bridge 66 connects fixed POL 20 to connectors (connector cages) 67 positioned on a first (top) side of cold plate 65. Optical signals are received at optical interface 74a, and electrical power (e.g., multiphase pulsed power) is received at electrical interfaces 74b, 74c. One or more optical signals are transmitted to or from photonic chip 29 via optical paths 68 that pass through cold plate 65 and substrate 71, as described above with respect to FIG. 2. Optical paths 68 optically couple optical interface 74a and photonic chip 29. The multiphase pulsed power is transmitted from electrical interfaces 74b, 74c through high power bridge 66 to fixed POL 20 and used to power regulation POL 22 via power bridge 24. In one example, the multiphase pulsed power may be transmitted from electrical interfaces 74b, 74c to high power bridge 66 via an electrical path integrally formed with optical path 68 or by other means through connector (connector and connector cage) 67. As described above with respect to FIG. 1 , the multiphase pulsed power may be modified before being transmitted from fixed POL module 20 to regulation POL module 22.

[0060] As noted above, cold plate 65 may be the "lower cold plate," with optical and electrical paths extending upward through the cold plate to the substrate and die package. Optical and electrical paths may also be located in both cold plates for distributing power and optical signals from both sides of the substrate and die package.

[0061] FIG. 7 illustrates details of an optical and electrical connector, according to one embodiment. As described above, connector 77 is coupled to optical path 68. Connector 77 includes optical interface 75 and electrical interface 76. In one or more embodiments, optical interface 75 can be configured to mate with an MPO (multi-fiber push-on) type connector 79, as described below with respect to FIGS. 8A and 8B. In one example, optical interface 75 includes a photonic element (e.g., a photonic die). In the example shown in FIG. 7, electrical interface 76 is configured to receive three-phase pulsed power (P1, P2, P3). A hybrid cable 78 including one or more optical fibers and electrical wires (e.g., two optical fibers and three pairs of copper wires) is coupled to cable connector 79 for mating with connector 77 mounted on the cold plate.

[0062] It will be understood that the interface configuration shown in FIG. 7 is merely an example, and that connector 77 may be configured to couple with any number of optical fibers or electrical wires (wire pairs) to receive pulsed power of any number of phases, and to receive or transmit any number of optical signals.

[0063] In one or more embodiments, the optical portion of the connector assembly may be configured as shown and described in U.S. Patent Application No. 16 / 544,699, filed August 19, 2019, entitled "Connection Features for Electronic and Optical Packaging," which is incorporated herein by reference in its entirety. The connector may be modified to include a power input (e.g., multiphase pulsed power as described above with respect to FIG. 7).

[0064] 8A and 8B illustrate an example of a clamp assembly configured for use with an MPO connector. It is understood that the MPO is merely an example and the clamp assembly can be used with other types of optical connectors (e.g., LC connectors). As described below, the clamp structure of the connector assembly can be used to provide electrical contact between the optical and electrical cables and the photonics package. While optical signals are transmitted via optical fiber, the clamp provides contact for electrical signals. The clamp and electrical connection can be integrated into the photonics die by using the clamp to provide electrical contact.

[0065] FIG. 8A illustrates an exploded view of a connector assembly according to one embodiment. The connector assembly includes an optical and electrical connector, generally designated 80, mounted on a cold plate as described above with respect to FIG. 6, and a cable connector 86 used to couple a hybrid cable to a package. The optical and electrical connector 80 comprises a frame 81, a photonic element (e.g., a photonic integrated circuit) 82 mounted within the frame, an optical adapter 84, and a fastener (clamp) 83a. The photonic element 82 optically interfaces with the optical adapter 84 to convey an optical signal from the cable connector 86 to the photonic element 82 via optical fiber. The photonic element 82 may include one or more waveguides connected to optical components integrated within the photonic element. The frame 81 includes an opening 85 for receiving an attachment finger 83b (peg) of the fastener 83a. The opening 85 provides a mechanical connection point for the fastener 83a, which includes a mechanical attachment portion 83b. As mentioned above, fastener (clamp) 83 a may provide an electrical connection between cable connector 86 and optical and electrical connector 80 coupled to one or more wire pairs 89 .

[0066] The cable connector 86 provides an optical connection between the optical fiber 88 and the optical features on the photonic element 82, and an electrical connection between the electrical wires 89 in the cable and the electrical interface on the connector 80. The cable connector 86 may include alignment pins 87 that may assist in mechanical alignment of the optical connector with the frame 81 and the photonic element 82. As described above, the cable connector 86 may include an MPO connector modified to provide an electrical connection between the electrical wires 89 in the hybrid cable and the connector 80. The electrical wires 89 received in the hybrid cable comprising the optical fiber 88 and the electrical wires may be coupled to the cable connector at various locations. For example, as shown in FIG. 8A , the electrical wires 89 may enter the cable connector 86 along with the optical fiber 88, or may be received at one or more edge portions of the cable connector.

[0067] The assembled optical and electrical connector 80 and cable connector 86 are shown in Figure 8B. In this example, an electrical wire 89 is shown offset from the optical fiber 88, with an electrical connection formed between the electrical wire and fastener 83a. As noted above, the MPO connector can be modified to receive the electrical wire, or the electrical wire can be coupled independently of the connector 80 (e.g., electrically coupled to a clamp assembly).

[0068] It will be understood that the connector assemblies shown in Figures 8A and 8B are merely examples, and that other types of optical and electrical connectors may be used without departing from the scope of the embodiments.

[0069] FIG. 9 is a flowchart illustrating an overview of a process for implementing a power and optical signal distribution system through multiple cold plates, according to one embodiment. In step 90, optical and electrical pathways are created through the cold plate. As described above, the pathways extend from one surface (e.g., top) to the opposite surface (e.g., bottom) of the cold plate to electrically couple a power connector to an electronic integrated circuit (die, chip, ASIC, SerDes) or optically couple an optical connector to a photonic integrated circuit (die, optical engine, photonic chip). Creating the electrical pathways may include inserting a power delivery block containing the electrical pathways into the cold plate. Creating the optical pathways may include inserting a waveguide for transmitting light through the cold plate. As described above, one or more optical pathway structures (e.g., periscope optical assemblies) may be inserted into openings formed in the cold plate and attached to one or more other optical structures to form optical pathways between the photonic die and optical connectors positioned outside the cold plate ( FIGS. 4C and 4D ).

[0070] Cold plates are positioned on opposite sides of the substrate and die package (step 92). Optical signals and power are then transmitted through the cold plates from one or more electrical or optical connectors to one or more electronic or photonic integrated circuits (step 94).

[0071] It should be understood that the process shown in FIG. 9 and described above is merely an example, and that steps may be added, modified, combined, or rearranged without departing from the scope of the embodiments.

[0072] FIG. 10 is a perspective view of an assembly, generally designated 100, comprising a substrate and die package (electrical die 102, optical engine 104, and SerDes (not shown in FIG. 10) coupled to substrate 108) interposed between cold plates 110, 112. Electrical connectors (POL modules) 114 and optical connectors 116 are mounted on the outer surfaces of cold plates 110, 112. As described in detail above, each cold plate comprises multiple electrical and optical paths (shown in FIGS. 11 and 12).

[0073] In one or more embodiments, the apparatus 100 includes an upper cold plate 100 and a lower cold plate 112, at least one of which has an electrical or optical path extending therethrough, a substrate and die package (substrate 108, die 102, optical engine 104) interposed between the upper and lower cold plates, and a connector 114, 116 coupled to one of the upper or lower cold plates for transmitting power or optical signals to the substrate and die package through the electrical or optical path.

[0074] In one or more embodiments, the apparatus 100 comprises a first cold plate (110 or 112) including an electrical path extending therethrough; a second cold plate including an optical path 122 extending therethrough; a substrate and die package including at least one electronic integrated circuit (die 102) and at least one photonic integrated circuit (optical engine 104), the substrate and die package being interposed between the two cold plates; an electrical connector (POL module) 114 coupled to the first cold plate for transmitting power or an electrical signal through the electrical path; and an optical connector 116 coupled to the second cold plate for transmitting an optical signal through the optical path.

[0075] FIG. 11 is a partial exploded view illustrating details of components positioned below the upper cold plate 110. The substrate 108 includes multiple power / ground mounting pads 121. Power / ground posts 124 are shown for attachment to the lower cold plate pass-through. Optical paths (waveguides) 126 extend through the substrate 108 for passing optical signals to the substrate, as described above. Silicon die bumps 128 are shown on the top surface of the die 102. In this example, the substrate and die package includes an optical engine 104 and a SerDes chip 106. The optical engine 104 is positioned to receive or transmit optical signals from or to optical connectors 116 mounted on the outer surfaces of the cold plates 110, 112 (top surface of the upper cold plate 110, bottom surface of the lower cold plate 112). Each cold plate 110, 112 includes electrical paths 118 within a power block 120 and optical paths 122 within an optical block 129. As described above, electrical pathways 118 may transmit power or electrical signals (e.g., communications) therethrough. Thermal pads 130 are positioned on the inner surface of lower cold plate 112 for thermal contact with die 102, as described above.

[0076] 11, the electrical connector 114 includes two IBV (Intermediate Bus Voltage) or FMP (Fault Management Power) power connections 125 electrically coupled to pads 127 for output power and ground for direct attachment to the cold plate. It will be understood that this is just one example and that the electrical connector may include any number of power and ground connection points.

[0077] 12 is an exploded view of the POL module 114, the top cold plate 110, the substrate 108, the die 102, the optical engine 104, and one of the SerDes chips 106. The electrical connector 114 includes power connection points 125, 127, as described above with respect to FIG.

[0078] In the example shown in FIGS. 10-12 , each cold plate 110, 112 includes multiple electrical and optical paths for coupling with the electrical connector 114 and optical connector 116. In another example, only one of the cold plates may include optical or electrical paths. In yet another example, one of the cold plates may include only electrical paths and the other cold plate may include only optical paths. The cold plates may include any number of optical paths for transmitting optical signals and electrical paths for transmitting power or electrical signals (e.g., communications). Any number of electrical or optical connectors may be coupled (e.g., mounted) to one or both cold plates for electrical or optical connection with the electrical or optical paths. Also, although two separate cold plates are shown and described herein, the two cold plates may be physically connected (e.g., rotatably or movably connected) or thermally coupled to one another.

[0079] FIG. 13 is a side view of assembly 130 including a substrate and die package (substrate 138, die (NPU, ASIC, electronic integrated circuit) 140, optical engine 142, and SerDes 149 (shown in FIG. 14)) interposed between cold plates 134, 136, according to one embodiment. In this example, POL module 132 and optical connector 133 are mounted on the outer surfaces of upper cold plate 134 and lower cold plate 136. Electrical paths (power blocks) 139a and 139b extend through cold plates 134 and 136, respectively, to transmit power from POL module 132 to substrate 138. For simplicity, individual electrical paths within the power blocks are not shown. Electrical path 139c transmits power directly from one of POL modules 132 to electronic integrated circuit (die, chip) 140. In this example, optical engines 142 are mounted on either side of substrate 138 and are directly coupled to optical connectors 133 through optical paths 144. Thermal pads 143a thermally couple the upper cold plate 134 to substrate 138. Thermal pads 143b thermally couple the lower cold plate 136 and die 140. In this example, power blocks containing electrical paths extend beyond the inner surfaces of the cold plates 134, 136 to make contact with substrate 138 or die 140.

[0080] Figure 14 is a cross-sectional view showing an electrical chip (e.g., SerDes) 145 positioned behind the optical engine 142 shown in Figure 13. In this example, an electrical connector 150 provides power to the SerDes chip 145 through electrical wires 152. The electrical wires 152 pass through power vias as described above.

[0081] 13 and 14 are merely examples, and it is understood that modifications may be made without departing from the scope of the embodiments. For example, the substrate and die package may include any number of electrical or optical components in any arrangement. Also, any number of POL modules, optical connectors, electrical connectors, or optical / electrical connectors may be used to transfer electrical power, optical signals, or electrical and electrical signals through the cold plate.

[0082] In summary, in one embodiment, an apparatus includes a cold plate including a first side and a second side, a photonic integrated circuit connected to a substrate positioned on the second side of the cold plate, and an optical path extending through the cold plate and optically coupled to the photonic integrated circuit for transmitting an optical signal between the photonic integrated circuit and the first side of the cold plate.

[0083] In another embodiment, an apparatus includes an upper cold plate and a lower cold plate, at least one of the upper cold plate or the lower cold plate having an electrical or optical path extending therethrough, a substrate and die package interposed between the upper cold plate or the lower cold plate, and a connector coupled to one of the upper cold plate or the lower cold plate for transmitting power or an optical signal to the substrate and die package through the electrical or optical path.

[0084] While the present apparatus and method have been described in accordance with illustrated embodiments, those skilled in the art will readily recognize that modifications may be made thereto without departing from the scope of the embodiments. Accordingly, it is intended that all matter contained in the above description and shown in the accompanying drawings shall be interpreted as illustrative and not in a limiting sense.

Claims

1. 1. An apparatus comprising: a cold plate including a first side and a second side; a photonic integrated circuit connected to a substrate positioned on the second side of the cold plate; an optical path extending through the cold plate and optically coupled to the photonic integrated circuit for transmitting optical signals between the photonic integrated circuit and the first side of the cold plate; a power delivery block inserted within the opening in the cold plate, the power delivery block comprising a plurality of electrical paths including power vias and communication vias.

2. 10. The apparatus of claim 1, wherein the optical path comprises a waveguide for transmitting light through the cold plate and optics for directing light to or from the photonic integrated circuit.

3. The apparatus of claim 2 , further comprising additional optics for directing light from the waveguide to a connector positioned on the first side of the cold plate.

4. 4. The apparatus of claim 2 or 3, wherein the optical system includes a mirror, and one or more of the waveguide and the mirror are defined by laser patterning.

5. The apparatus of any one of claims 1 to 4, wherein the optical path comprises an optical structure actively aligned to the photonic integrated circuit.

6. 6. The apparatus of claim 1, wherein the optical path comprises an optical structure coupled to one or more alignment pins for aligning the optical structure with the photonic integrated circuit.

7. The apparatus of any one of claims 1 to 6, wherein the substrate comprises a printed circuit board and a glass interposer, and the optical path extends through the substrate.

8. The apparatus of any one of claims 1 to 7, wherein the optical path comprises at least one optical fiber.

9. The apparatus of any one of claims 1 to 8, further comprising a connector positioned on the first side of the cold plate and coupled to the optical path.

10. 10. The device of claim 9, wherein the connector includes an optical interface and an electrical interface for connection to a cable including at least one optical fiber and at least one electrical wire.

11. The apparatus of claim 10 , wherein the connector is configured to receive multiphase pulsed power from the cable via multiple wires.

12. The apparatus of any one of claims 1 to 11, wherein the electrical pathways include an electrical pathway for transmitting power through the cold plate to an electronic integrated circuit mounted on the substrate.

13. a connector optically coupled to the optical path; a first power bridge interconnecting the connector to a fixed point-of-load (POL) module; 13. The apparatus of claim 12, further comprising: a second power bridge interconnecting the fixed POL module to a regulating POL module positioned on the first side of the cold plate for transmitting power to the electrical path.

14. The apparatus of claim 13 , wherein the first power bridge is operable to transmit multi-phase pulsed power from the connector to the fixed POL module.

15. 1. An apparatus comprising: a connector for receiving or transmitting an optical signal; an optical path coupled to the connector and the photonic integrated circuit; a cold plate interposed between the connector and the photonic integrated circuit, the optical path extending through the cold plate; a power delivery block inserted into the opening in the cold plate, the power delivery block comprising a plurality of electrical paths including power vias and communication vias.

16. 16. The apparatus of claim 15, wherein the connector is further configured to receive electrical power, the electrical path including an electrical path for transmitting the power through the cold plate to an electronic integrated circuit, the electronic integrated circuit and the photonic integrated circuit being mounted on a substrate attached to the cold plate.

17. 17. The apparatus of claim 15 or 16, wherein the optical path comprises a waveguide for transmitting light through the cold plate and optics for directing light to or from the photonic integrated circuit.

18. 20. The apparatus of claim 17, further comprising additional optics for directing light from the waveguide to the connector.

19. The apparatus of any one of claims 15 to 18, wherein the connector comprises a clamping assembly for attaching a cable to the connector and providing an electrical path to the connector.

20. 20. The apparatus of any one of claims 15 to 19, wherein the connector is configured to make an optical connection with at least one optical fiber in a hybrid cable and to receive multiphase pulsed power from the hybrid cable.

21. 1. A method comprising: attaching a substrate to a cold plate, the substrate having at least one photonic die connected thereto; creating an optical path through the cold plate and the substrate; inserting a power delivery block into the opening in the cold plate, the power delivery block including a plurality of electrical paths including power vias and communication vias extending through the cold plate; A method wherein an optical signal is transmitted to or from the photonic die through the optical path in the cold plate and the substrate.

22. 22. The method of claim 21, further comprising attaching a connector to the cold plate and optically coupling the connector to the optical path.

23. 23. The method of claim 21 or 22, wherein the substrate comprises a printed circuit board and a glass interposer.

24. 24. The method of any one of claims 21 to 23, wherein creating the optical path comprises creating other openings in the cold plate and the substrate, and inserting waveguides for transmitting light through the cold plate and the substrate, and optics for directing light to or from the photonic die.

25. 25. The method of claim 24, further comprising connecting the optical path to another optical path mounted on the cold plate to direct the optical signal to a connector positioned on the cold plate.

26. 1. An apparatus comprising: an upper cold plate and a lower cold plate, at least one of the upper cold plate or the lower cold plate including an electrical or optical path extending therethrough; a power delivery block inserted into an opening in at least one of the upper cold plate or the lower cold plate, the power delivery block including a plurality of the electrical paths including power vias and communication vias; a substrate and die package interposed between the upper and lower cold plates; a connector coupled to one of the upper cold plate or the lower cold plate for transmitting power or optical signals through the electrical or optical path to the substrate and die package; each of the upper cold plate and the lower cold plate includes the electrical path or the optical path; The connector a first connector coupled to the upper cold plate for transmitting at least one of electrical power through the electrical path and optical signals through the optical path to the substrate and die package; a second connector coupled to the lower cold plate for transmitting at least one of electrical power through the electrical path and optical signals through the optical path to the substrate and die package.

27. 27. The apparatus of claim 26, wherein the connector comprises an optical connector and the substrate and die package comprises a photonic integrated circuit.

28. 28. The apparatus of claim 26 or 27, wherein the connector comprises a point-of-load (POL) module and the substrate and die package comprises an optical integrated circuit.

29. 29. The apparatus of claim 26, wherein at least one of the upper cold plate or the lower cold plate comprises a power delivery block inserted within the cold plate, and the electrical path comprises a power via formed in the power delivery block.

30. 30. The apparatus of any one of claims 26 to 29, wherein the substrate and die package comprises an optical engine, and the optical path comprises a waveguide for transmitting light through the cold plate to or from the optical engine.

31. 31. The apparatus of claim 26, wherein the electrical or optical path comprises an upper path extending through the upper cold plate and a substrate of the substrate-and-die package, and a lower path extending through the lower cold plate for direct contact with a die of the substrate-and-die package.

32. 32. The apparatus of any one of claims 26 to 31, wherein the electrical or optical paths comprise at least one path extending through the upper cold plate and at least one path extending through the lower cold plate.

33. 33. The apparatus of any one of claims 26 to 32, wherein the substrate and die package comprises at least one electronic integrated circuit and at least one photonic integrated circuit, and the electrical or optical pathways comprise at least one electrical pathway and at least one optical pathway.

34. 1. An apparatus comprising: a first cold plate including an electrical pathway extending therethrough; a second cold plate including an optical path extending therethrough; a substrate and die package including at least one electronic integrated circuit and at least one photonic integrated circuit, the substrate and die package being interposed between the first cold plate and the second cold plate; an electrical connector coupled to the first cold plate for transmitting power or an electrical signal through the electrical path; an optical connector coupled to the second cold plate for transmitting an optical signal through the optical path; a power delivery block inserted into the opening in the first cold plate, the power delivery block comprising a plurality of the electrical paths including power vias and communication vias.

35. 35. The apparatus of claim 34, wherein the electrical connector comprises a point-of-load (POL) module.

36. 36. The apparatus of claim 34 or 35, wherein the electrical pathway comprises a power via formed in the power delivery block.

37. 37. Apparatus according to any one of claims 34 to 36, wherein the optical path comprises a waveguide for transmitting light through the second cold plate to or from the photonic integrated circuit.

38. 38. The apparatus of any one of claims 34 to 37, wherein the optical path in the second cold plate is directly optically coupled to the photonic integrated circuit, and the electrical path extends to the substrate and a substrate of a die package.

39. 39. The apparatus of any one of claims 34 to 38, wherein the electronic integrated circuit comprises an ASIC (Application Specific Integrated Circuit), the photonic integrated circuit comprises an optical engine, and the substrate comprises a printed circuit board on which the ASIC and the optical engine are mounted.

40. 40. The apparatus of any one of claims 34 to 39, wherein the electrical pathway comprises a passage through which an electrical wire passes.

41. The apparatus of any one of claims 34 to 40, wherein each of the first cold plate and the second cold plate comprises a plurality of electrical paths and a plurality of optical paths.

42. 1. A method comprising: creating an electrical path and an optical path through the cold plate; positioning the cold plates on opposite sides of a substrate and die package; transmitting electrical power through the electrical path and an optical signal through the optical path; power is transmitted from a power connector coupled to a first one of the cold plates, and an optical signal is transmitted from or received at an optical connector coupled to a second one of the cold plates; The method, wherein the first cold plate comprises a power delivery block inserted into an opening in the first cold plate, the power delivery block comprising a plurality of the electrical paths including power vias and communication vias.

43. 43. The method of claim 42, wherein creating the electrical path comprises inserting the power delivery block into the opening in the first cold plate, the electrical path comprising power vias formed in the power delivery block.

44. 44. The method of claim 42 or 43, wherein creating the optical path comprises inserting a waveguide for transmitting light through one of the cold plates.

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