AD conversion device, semiconductor integrated circuit device, and AD conversion device design method

Abstract

This AD conversion device comprises a plurality of AD conversion circuit units that perform analog-digital conversion in a time-interleaved manner, and a multiplexer circuit that generates a digital signal from the output signals of the plurality of AD conversion circuit units. The multiplexer circuit is a circuit wherein by means of a plurality of logic circuits and a plurality of intermediate connection wirings, said logic circuits and intermediate connection wirings being dispersedly disposed among the plurality of AD conversion circuit units, the plurality of logic circuits are connected in a tournament-bracket form, and in each of the AD conversion circuit units, an output circuit and a first element circuit portion including one of the logic circuits are disposed along an outer periphery portion, and one of the intermediate connection wirings is disposed so as to cross in a first direction. The plurality of AD conversion circuit units are disposed along the first direction such that, with two neighboring AD conversion circuit units being designated as a set, the output circuits and first element circuit portions of the AD conversion circuit units of each set face each other.

Description

[Technical Field]

[0001] The present invention relates to an AD conversion device, a semiconductor integrated circuit device, and a method for designing an AD conversion device. [Background technology]

[0002] A time-interleaved AD conversion device using multiple analog-to-digital (AD conversion) circuit units that convert analog signals to digital signals has a data bus circuit that combines the outputs of the multiple AD conversion circuit units using a multiplexer circuit and outputs them. When multiple AD conversion circuit units are arranged in one direction (vertically stacked), skew occurs in the data bus circuit depending on the arrangement positions of the AD conversion circuit units.

[0003] A data bus circuit using four AD conversion circuit units is configured, for example, as shown in FIG. 12A. A function as a multiplexer circuit is realized by non-conjunction operation circuits (NAND circuits) 1201 and 1202 and a non-OR operation circuit (NOR circuit) 1203. An output signal ADC1 from the first AD conversion circuit unit and an output signal ADC2 from the second AD conversion circuit unit are input to the NAND circuit 1201, and an output signal ADC3 from the third AD conversion circuit unit and an output signal ADC4 from the fourth AD conversion circuit unit are input to the NAND circuit 1202. An output signal NANDA from the NAND circuit 1201 and an output signal NANDB from the NAND circuit 1202 are input to the NOR circuit 1203. An output signal NOR from the NOR circuit 1203 is input to a flip-flop circuit 1204.

[0004] 12B, it is assumed that the conversion result from the first AD conversion circuit unit is input to the data bus circuit shown in Fig. 12A during a first period from time T101 to time T102, and the conversion result from the second AD conversion circuit unit is input during a second period from time T102 to time T103. It is also assumed that the conversion result from the third AD conversion circuit unit is input during a third period from time T103 to time T104, and the conversion result from the fourth AD conversion circuit unit is input during a fourth period from time T104 to time T105. It is also assumed that the outputs ADC1 to ADC4 from each AD conversion circuit unit are fixed to a high level when not in the corresponding period.

[0005] If no skew occurs between the output signals of the AD conversion circuit units in the data bus circuit and no difference in transmission delay occurs before the signals reach the NAND circuits 1201 and 1202, the AD-converted digital signals are transmitted as indicated by the signals NANDA, NANDB, and NOR in Fig. 12B. In this case, as indicated by the signal FF, the flip-flop circuit 1204 holds signals of the correct levels (L, H, L, H) corresponding to the levels (L, H, L, H) of the output signals of ADC1 to ADC4. On the other hand, if skew occurs between the output signals of the AD conversion circuit units, a difference occurs in transmission delay before the signals reach the NAND circuits 1201 and 1202. For example, skew occurs as indicated by the signals NANDB(SKEW) and NOR(SKEW) in Fig. 12B, and the AD-converted digital signals may be transmitted erroneously. In this case, as indicated by signal FF, a signal of an incorrect level (L, H, H, L) that does not correspond to the levels (L, H, L, H) of the output signals of ADC1 to ADC4 is held in flip-flop circuit 1204. In order to prevent skew from occurring and digital signals from being erroneously transmitted, Patent Document 1 discloses a technique for adjusting the skew by providing a variable delay circuit for the output of an AD conversion circuit unit. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] U.S. Patent No. 7,250,885 Summary of the Invention [Problem to be solved by the invention]

[0007] An object of the present invention is to provide an AD conversion device that can suppress skew that occurs between output signals of multiple AD conversion circuit units that perform AD conversion using a time interleaving method without adding any circuits. [Means for solving the problem]

[0008] One aspect of the AD conversion device is Each one Time-interleaved analog-to-digital conversion an AD conversion circuit; and an output circuit that outputs the result of the AD conversion by the AD conversion circuit as an output signal. The multiplexer circuit generates a digital signal from the output signals of the plurality of AD conversion circuit units. , complex Number logic circuit but Multiple intermediate connection cables On the line Yes Teto The circuit is connected in a concertina configuration. An AD conversion device , In the circuit layout of the AD conversion device, a plurality of logic circuits and a plurality of intermediate connection wires are distributed among a plurality of AD conversion circuit units, Each of the AD conversion circuit units In a first element circuit unit including an output circuit and a logic circuit; perpendicular to the first direction outer periphery One side of The AD conversion circuit units are arranged along the first direction, with the intermediate connecting wiring arranged to cross the first direction. The plurality of AD conversion circuit units are arranged in pairs of two adjacent AD conversion circuit units, and are arranged along the first direction such that the output circuits and first element circuit portions of the AD conversion circuit units in each pair face each other. [Effects of the Invention]

[0009] The disclosed AD conversion device can suppress skew occurring between output signals of a plurality of AD conversion circuit units that perform AD conversion by a time interleaving method, without adding any circuitry. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a diagram showing an example of the configuration of an AD conversion device according to this embodiment. [Figure 2A] FIG. 2A is a diagram illustrating an example of the configuration of a data bus circuit. [Figure 2B] FIG. 2B is a timing chart illustrating the operation of the data bus circuit. [Figure 3] FIG. 3 is a diagram illustrating the first AD conversion circuit unit. [Figure 4A] FIG. 4A is a diagram illustrating an example of the arrangement of the first AD conversion circuit unit. [Figure 4B] FIG. 4B is a diagram illustrating an example of the arrangement of the first AD conversion circuit unit. [Figure 5] FIG. 5 is a diagram illustrating a reference example of an AD conversion device. [Figure 6] FIG. 6 is a diagram illustrating a first example of an AD conversion device. [Figure 7] FIG. 7 is a diagram illustrating the second AD conversion circuit unit. [Figure 8] FIG. 8 is a diagram illustrating a second example of an AD conversion device. [Figure 9] FIG. 9 is a diagram for explaining a method for designing an AD conversion device according to this embodiment. [Figure 10A] FIG. 10A is a diagram illustrating an example of the layout of logic circuits included in a multiplexer circuit. [Figure 10B] FIG. 10B is a diagram illustrating an example of the layout of logic circuits included in a multiplexer circuit. [Figure 10C] FIG. 10C is a diagram illustrating an example of the layout of logic circuits included in a multiplexer circuit. [Figure 10D] FIG. 10D is a diagram illustrating an example of the layout of logic circuits included in a multiplexer circuit. [Figure 10E] FIG. 10E is a diagram illustrating an example of the layout of logic circuits included in a multiplexer circuit. [Figure 10F] FIG. 10F is a diagram illustrating an example of the layout of logic circuits included in a multiplexer circuit. [Figure 11] FIG. 11 is a diagram showing an example of the configuration of a semiconductor integrated circuit device according to this embodiment. [Figure 12A] FIG. 12A is a diagram illustrating an example of a data bus circuit. [Figure 12B] FIG. 12B is a timing chart illustrating the operation of the data bus circuit shown in FIG. 12A. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

[0012] 1 is a diagram showing an example of the configuration of an analog-to-digital conversion (AD conversion) device according to this embodiment. The AD conversion device according to this embodiment includes a plurality of AD conversion circuit units 10-i, a multiplexer circuit 20, and a control circuit 30. Note that i is a subscript, and is an integer from 1 to n (n is arbitrary).

[0013] Each of the AD conversion circuit units 10-i has an AD conversion circuit and performs analog-to-digital conversion (AD conversion) on an input analog signal to convert it into a digital signal. The multiple AD conversion circuit units 10-i included in the AD conversion device perform AD conversion in a time-interleaved format. The number of AD conversion circuit units 10-i and the number of bits involved in AD conversion are determined according to the specifications required of the AD conversion device, and are not particularly limited. The AD conversion processing method in the AD conversion circuit units 10-i is not particularly limited, and any AD conversion processing method can be applied.

[0014] The multiplexer circuit 20 combines output signals from the plurality of AD conversion circuit units 10-i to generate a digital signal to be output. The multiplexer circuit 20 generates a digital signal by selectively outputting output signals from the plurality of AD conversion circuit units 10-i that are AD converted using a time interleaving method. Note that a multiplexer circuit 20 is provided for each bit of the output signal from the AD conversion circuit unit 10-i. The multiplexer circuit 20 has a plurality of logic circuits, which are connected in a tournament configuration by a plurality of intermediate interconnections. In this embodiment, as an example, a circuit is used in which the plurality of logic circuits are non-conjunction circuits (NAND circuits) and non-or circuits (NOR circuits) connected in a tournament configuration.

[0015] The control circuit 30 outputs the digital signal generated by the multiplexer circuit 20 to a digital signal processing circuit or the like.

[0016] FIG. 2A is a diagram showing an example of the configuration of a data bus circuit. The data bus circuit includes the multiplexer circuit 20 shown in FIG. 1, integrates the outputs of multiple AD conversion circuit units 10-i, and outputs the resulting digital signal. The data bus circuit has an inverter 200, NAND circuits 210, 231, 232, 233, 234, 235, and 238, flip-flop circuits 220, 240, and 250, and NOR circuits 236 and 237. Note that FIG. 2A shows an example of the configuration when AD conversion is performed by a time interleaving method using ten AD conversion circuit units 10-i. The data bus circuit shown in FIG. 2A is configured using, for example, standard cells.

[0017] The inverter 200 receives an output signal SIN from a corresponding one of the ten AD conversion circuit units 10-i. The NAND circuit 210 receives an output signal (an inverted signal of the signal SIN) from the inverter 200 and an enable signal EN. The output signal from the NAND circuit 210 is input to a flip-flop circuit 220. The enable signal EN is a control signal for outputting the output signal SIN as the output signal of the NAND circuit 210 during a period in which the output signal SIN from the corresponding AD conversion circuit unit 10-i is enabled, and fixing the output signal of the NAND circuit 210 to a high level during a period in which the output signal SIN from the corresponding AD conversion circuit unit 10-i is disabled, in time-interleaved AD conversion. The flip-flop circuit 220 receives the output signal from the NAND circuit 210 in response to a clock signal CLK and outputs it as an output signal S11.

[0018] In addition, the inverter Ta2 00, a NAND circuit 210, and a flip-flop circuit 220 are provided for each AD conversion circuit unit 10-i. Ta2 00, NAND There are provided ten pairs of circuits 210 and flip-flop circuits 220.

[0019] A multiplexer circuit 230 is configured by NAND circuits 231, 232, 233, 234, 235, and 238 and NOR circuits 236 and 237. The multiplexer circuit 230 corresponds to the multiplexer circuit 20 shown in Fig. 1. The NAND circuits 231, 232, 233, 234, and 235 are in the first stage, the NOR circuits 236 and 237 are in the second stage, and the NAND circuit 238 is in the third stage, and are connected in a tournament configuration.

[0020] The NAND circuit 231 receives an output signal of the flip-flop circuit 220 corresponding to the first AD conversion circuit unit 10-1 and an output signal of the flip-flop circuit 220 corresponding to the second AD conversion circuit unit 10-2. The NAND circuit 232 receives an output signal of the flip-flop circuit 220 corresponding to the third AD conversion circuit unit 10-3 and an output signal of the flip-flop circuit 220 corresponding to the fourth AD conversion circuit unit 10-4, and the NAND circuit 233 receives an output signal of the flip-flop circuit 220 corresponding to the fifth AD conversion circuit unit 10-5 and an output signal of the flip-flop circuit 220 corresponding to the sixth AD conversion circuit unit 10-6. Similarly, the output signal of the flip-flop circuit 220 corresponding to the seventh AD conversion circuit unit 10-7 and the output signal of the flip-flop circuit 220 corresponding to the eighth AD conversion circuit unit 10-8 are input to the NAND circuit 234, and the output signal of the flip-flop circuit 220 corresponding to the ninth AD conversion circuit unit 10-9 and the output signal of the flip-flop circuit 220 corresponding to the tenth AD conversion circuit unit 10-10 are input to the NAND circuit 235.

[0021] The output signals of the NAND circuits 231, 232, and 233 are input to the NOR circuit 236, and the output signals of the NAND circuits 234 and 235 are input to the NOR circuit 237. The output signals of the NOR circuits 236 and 237 are input to the NAND circuit 238. The output signal S12 of the NAND circuit 238 is input to the flip-flop circuit 240.

[0022] As described above, by controlling using the enable signal EN, one AD conversion circuit unit 10-i out of the ten AD conversion circuit units 10-i is exclusively enabled, and the output signals of the flip-flop circuits 220 corresponding to the other AD conversion circuit units 10-i are fixed to a high level. Therefore, the multiplexer circuit 230 outputs the output signal of the flip-flop circuit 220 corresponding to the enabled AD conversion circuit unit 10-i, i.e., the output signal of the enabled AD conversion circuit unit 10-i, as the output signal S12.

[0023] The flip-flop circuit 240 receives the output signal S12 of the multiplexer circuit 230 (the output signal of the NAND circuit 238) in response to the clock signal CLK and outputs it as an output signal S13. The flip-flop circuit 250 receives the output signal S13 of the flip-flop circuit 240 in response to the clock signal CLK and outputs it as an output signal SOUT.

[0024] 2B is a timing chart illustrating the operation of the data bus circuit shown in FIG. 2A. At time T11, the enable signal EN goes high, and at time T12, an output signal S11 (low) corresponding to the output signal SIN (low here) of the corresponding AD conversion circuit unit 10-i is output. This output signal S11 is then output as the output signal S12 (high) via the multiplexer circuit 230. Thereafter, at times T13 and T14, the output signal S11 is sequentially transmitted by the flip-flops 240 and 250 and output as the output signal SOUT (high). Although not shown, the enable signals EN corresponding to the AD conversion circuit units 10-i sequentially go high, and the output signal SIN of the corresponding AD conversion circuit unit 10-i is output as the output signal S12 via the multiplexer circuit 230, and finally output as the output signal SOUT.

[0025] FIG. 3 is a diagram illustrating the first AD conversion circuit unit 300. FIG. 3 shows a schematic circuit layout of the first AD conversion circuit unit. In FIG. 3, reference numeral 301 denotes a control circuit that controls the AD conversion circuit included in the first AD conversion circuit unit 300 and outputs the AD conversion result. Reference numeral 302 denotes a driver circuit that receives and outputs the output (AD conversion result) of the control circuit 301. Reference numerals 303 and 304 denote element circuit sections that include logic circuits such as NAND circuits and NOR circuits, which are element circuits that constitute a multiplexer circuit. In the first AD conversion circuit unit 300, the driver circuit 302 and the element circuit sections 303 and 304 are arranged along the periphery. The driver circuit 302 is an output circuit that receives the output of the control circuit 301 via wiring within the first AD conversion circuit unit 300 and outputs the output via the NAND circuits and NOR circuits arranged in the element circuit sections 303 and 304 on the left and right sides. Note that the remaining parts of the first AD conversion circuit unit 300 are circuit sections that perform AD conversion operations. Further, reference numerals 305, 306, and 307 denote intermediate connection wirings that connect the first AD conversion circuit units 300 together, and are arranged to traverse the first AD conversion circuit units 300. center and at both ends. In this example, the intermediate connecting wires 305 and 306 are data wirings for half the number of bits involved in AD conversion, and the intermediate connecting wire 307 is data wiring for the same number of bits involved in AD conversion. In this embodiment, the element circuit sections 303 and 304 and the intermediate connecting wires 305, 306, and 307 allow the element circuits (logic circuits) and intermediate connecting wires that make up the multiplexer circuit to be distributed and arranged in the first AD conversion circuit unit 300.

[0026] In this embodiment, when an AD conversion device is configured using first AD conversion circuit units 300, two first AD conversion circuit units 300 are arranged so that the output circuits (driver circuits 302) and element circuits 303 and 304 of the first AD conversion circuit units 300 face each other, as shown in Fig. 4A. By arranging them in this manner, compared to the arrangement shown in Fig. 4B, intermediate connection wiring for transmitting the AD conversion result from one first AD conversion circuit unit 300 to the other first AD conversion circuit unit 300 is not required, and skew occurring between the output signals of the first AD conversion circuit units 300 can be suppressed.

[0027] For example, when 10 first AD conversion circuit units 300-1 to 300-10 are arranged in one direction (arranged vertically), if a set of first AD conversion circuit units 300 as shown in FIG. 4B is arranged in one direction (the direction in which the intermediate connection wirings 305, 306, and 307 extend), as shown in FIG. 5, the difference between the longest path and the shortest path until transmission to the relay flip-flop 310 becomes large, and skew occurs due to this difference in transmission delay.

[0028] Fig. 5 is a diagram illustrating a reference example of an AD conversion device. In the configuration shown in Fig. 5, output signals from the first AD conversion circuit units 300-1, 300-2, and 300-3 are input to a NAND circuit 501, and output signals from the first AD conversion circuit units 300-4 and 300-5 are input to a NAND circuit 502. Output signals from the first AD conversion circuit units 300-6 and 300-7 are input to a NAND circuit 503, and output signals from the first AD conversion circuit units 300-8, 300-9, and 300-10 are input to a NAND circuit 504. Output signals from the NAND circuits 501, 502, and 503 are input to a NOR circuit 505, and an output signal from the NAND circuit 504 is input to a NOR circuit 506. Furthermore, the output signals of the NOR circuits 505 and 506 are input to the NAND circuit 507 , and the output signal of the NAND circuit 507 is input to the relay flip-flop 310 .

[0029] Here, the output signal of the first AD conversion circuit unit 300-1 is input to the NAND circuit 501 via the intermediate connecting wires 305 and 306 of the first AD conversion circuit units 300-1 and 300-2, and the output signal of the first AD conversion circuit unit 300-10 is input to the NAND circuit 504 via the intermediate connecting wires 305 and 306 of the first AD conversion circuit units 300-9 and 300-10. In addition, the output signal of the NAND circuit 501 is input to the NOR circuit 505 via the intermediate connecting wires 305 and 306 of the first AD conversion circuit units 300-3 and 300-4, and the output signal of the NAND circuit 503 is input to the NOR circuit 505 via the intermediate connecting wires 305 and 306 of the first AD conversion circuit units 300-5 and 300-6. The output signal of the NOR circuit 505 is input to the NAND circuit 507 via the intermediate connection wiring 307 of the first AD conversion circuit units 300-5 and 300-6, and the output signal of the NOR circuit 506 is input to the NAND circuit 507 via the intermediate connection wiring 305 and 306 of the first AD conversion circuit units 300-7 and 300-8. The output signal of the NAND circuit 507 is input to the relay flip-flop 310 via the intermediate connection wiring 307 of the first AD conversion circuit units 300-7, 300-8, 300-9, and 300-10.

[0030] When comparing the first AD conversion circuit unit 300-1, which has the longest transmission path for the AD conversion results, with the first AD conversion circuit units 300-4, 300-5, 300-8, and 300-9, which have the shortest transmission paths for the AD conversion results, there is a difference in wiring length equivalent to four first AD conversion circuit units, and this difference in transmission delay results in skew.

[0031] In contrast, as shown in Fig. 6, if a set of first AD conversion circuit units 300 such as those shown in Fig. 4A are arranged in one direction (the direction in which the intermediate connection wirings 305, 306, and 307 extend), the difference between the longest path and the shortest path until transmission to the relay flip-flop 310 becomes smaller than that shown in Fig. 5, and the skew that occurs can be suppressed. Fig. 6 is a diagram illustrating a first example of an AD conversion device.

[0032] 6, the output signals of the first AD conversion circuit units 300-1 and 300-2 are input to a NAND circuit 601, and the output signals of the first AD conversion circuit units 300-3 and 300-4 are input to a NAND circuit 602. The output signals of the first AD conversion circuit units 300-5 and 300-6 are input to a NAND circuit 603, and the output signals of the first AD conversion circuit units 300-7 and 300-8 are input to a NAND circuit 604. The output signals of the first AD conversion circuit units 300-9 and 300-10 are input to a NAND circuit 605. The output signals of the NAND circuits 601, 602, and 603 are input to a NOR circuit 606, and the output signals of the NAND circuits 604 and 605 are input to a NOR circuit 607. The output signals of the NOR circuits 606 and 607 are input to the NAND circuit 608 , and the output signal of the NAND circuit 608 is input to the relay flip-flop 310 .

[0033] A NAND circuit 601 is arranged in the element circuit sections 303 and 304 between the first AD conversion circuit units 300-1 and 300-2, and a NAND circuit 602 is arranged in the element circuit sections 303 and 304 between the first AD conversion circuit units 300-3 and 300-4. A NAND circuit 603 is arranged in the element circuit sections 303 and 304 between the first AD conversion circuit units 300-5 and 300-6, and a NAND circuit 604 is arranged in the element circuit sections 303 and 304 between the first AD conversion circuit units 300-7 and 300-8. A NAND circuit 605 is arranged in the element circuit sections 303 and 304 between the first AD conversion circuit units 300-9 and 300-10.

[0034] The NOR circuit 606 is arranged in the element circuit sections 303 and 304 between the first AD conversion circuit units 300-3 and 300-4, and the NOR circuit 607 is arranged in the element circuit sections 303 and 304 between the first AD conversion circuit units 300-7 and 300-8. The NAND circuit 608 is arranged in the element circuit sections 303 and 304 between the first AD conversion circuit units 300-5 and 300-6.

[0035] Here, the output signal of the NAND circuit 601 is input to the NOR circuit 606 via the intermediate interconnections 305 and 306 of the first AD conversion circuit units 300-2 and 300-3, and the output signal of the NAND circuit 603 is input to the NOR circuit 606 via the intermediate interconnections 305 and 306 of the first AD conversion circuit units 300-4 and 300-5. In addition, the output signal of the NAND circuit 605 is input to the NOR circuit 607 via the intermediate interconnections 305 and 306 of the first AD conversion circuit units 300-8 and 300-9. The output signal of the NOR circuit 606 is input to the NAND circuit 608 via the intermediate connection wiring 307 of the first AD conversion circuit units 300-4 and 300-5, and the output signal of the NOR circuit 607 is input to the NAND circuit 608 via the intermediate connection wiring 305 and 306 of the first AD conversion circuit units 300-6 and 300-7. The output signal of the NAND circuit 608 is input to the relay flip-flop 310 via the intermediate connection wiring 307 of the first AD conversion circuit units 300-6, 300-7, 300-8, 300-9, and 300-10.

[0036] Therefore, when comparing the first AD conversion circuit units 300-1, 300-2, 300-5, 300-6, 300-9, and 300-10, which have the longest transmission paths for the AD conversion results, with the first AD conversion circuit units 300-3, 300-4, 300-7, and 300-8, which have the shortest transmission paths for the AD conversion results, the difference in wiring length is equivalent to the length of two first AD conversion circuit units, and the skew that occurs can be suppressed.

[0037] FIG. 7 is a diagram illustrating a second AD conversion circuit unit 700. FIG. 7 shows a schematic configuration of the circuit layout of the second AD conversion circuit unit. The second AD conversion circuit unit 700 shown in FIG. 7 is a diagram illustrating a second AD conversion circuit unit 700. nThis configuration is applicable to a case where the second AD conversion circuit unit 700 includes multiple second AD conversion circuit units. In FIG. 7, 701 is a control circuit that controls the AD conversion circuit included in the second AD conversion circuit unit 700 and outputs the AD conversion result. 702 is a driver circuit that receives and outputs the output (AD conversion result) of the control circuit 701. 703, 704, 705, and 706 are element circuit sections that include logic circuits such as NAND circuits and NOR circuits, which are element circuits that constitute a multiplexer circuit. In the second AD conversion circuit unit 700, the driver circuit 702 and element circuit sections 703, 704, 705, and 706 are arranged along the outer periphery. Furthermore, the output circuit (driver circuit 702) and first element circuit sections 703 and 704 of the second AD conversion circuit unit 700 are arranged to face the second element circuit sections 705 and 706 inside the second AD conversion circuit unit 700. The driver circuit 702 is an output circuit that receives the output of the control circuit 701 via wiring inside the second AD conversion circuit unit 700 and outputs it via NAND circuits and NOR circuits arranged in element circuit sections 703, 704, 705, and 706. Note that in the second AD conversion circuit unit 700, the remaining sections are circuit sections that perform AD conversion operations. Reference numerals 707, 708, and 709 denote intermediate connection wirings that connect the second AD conversion circuit units 700 together, and are arranged across the second AD conversion circuit units 700. center and at both ends. In this example, each of the intermediate connection wires 707, 708, and 709 is a data wire for the number of bits related to AD conversion. In this embodiment, the element circuits (logic circuits) and intermediate connection wires that configure the multiplexer circuit are distributed and arranged in the second AD conversion circuit unit 700 by the first element circuit sections 703 and 704, the second element circuit sections 705 and 706, and the intermediate connection wires 707, 708, and 709.

[0038] AD conversion device 2 nWhen the AD conversion device has AD conversion circuit units, by configuring the AD conversion device using second AD conversion circuit units 700, it is possible to make the path lengths the same for all paths. As shown in Fig. 8, an example will be described in which eight second AD conversion circuit units 700-1 to 700-8 are arranged (vertically stacked) along one direction (the direction in which intermediate connection wirings 707, 708, and 709 extend) with two adjacent second AD conversion circuit units 700 grouped together, and the output circuits (driver circuits 702) and first element circuits 703 and 704 of the second AD conversion circuit units 700 facing each other for each group. Fig. 8 is a diagram illustrating a second example of an AD conversion device.

[0039] 8 , the output signals of the second AD conversion circuit units 700-1 and 700-2 are input to a NAND circuit 801, and the output signals of the second AD conversion circuit units 700-3 and 700-4 are input to a NAND circuit 802. The output signals of the second AD conversion circuit units 700-5 and 700-6 are input to a NAND circuit 803, and the output signals of the second AD conversion circuit units 700-7 and 700-8 are input to a NAND circuit 804. The output signals of the NAND circuits 801 and 802 are input to a NOR circuit 805, and the output signals of the NAND circuits 803 and 804 are input to a NOR circuit 806. The output signals of the NOR circuits 805 and 806 are input to a NAND circuit 807, and the output signal of the NAND circuit 807 is input to a relay flip-flop 710.

[0040] The NAND circuit 801 is arranged in the first element circuit section 703, 704 between the second AD conversion circuit units 700-1, 700-2, and the NAND circuit 802 is arranged in the first element circuit section 703, 704 between the second AD conversion circuit units 700-3, 700-4. The NAND circuit 803 is arranged in the first element circuit section 703, 704 between the second AD conversion circuit units 700-5, 700-6, and the NAND circuit 804 is arranged in the first element circuit section 703, 704 between the second AD conversion circuit units 700-7, 700-8.

[0041] The NOR circuit 805 is arranged in the second element circuit sections 705 and 706 between the second AD conversion circuit units 700-2 and 700-3, and the NOR circuit 806 is arranged in the second element circuit sections 705 and 706 between the second AD conversion circuit units 700-6 and 700-7. The NAND circuit 807 is arranged in the second element circuit sections 705 and 706 between the second AD conversion circuit units 700-4 and 700-5.

[0042] Here, the output signal of the NAND circuit 801 is input to the NOR circuit 805 via the intermediate connection wiring 708 of the second AD conversion circuit unit 700-2, and the output signal of the NAND circuit 802 is input to the NOR circuit 805 via the intermediate connection wiring 707 of the second AD conversion circuit unit 700-3. In addition, the output signal of the NAND circuit 803 is input to the NOR circuit 806 via the intermediate connection wiring 708 of the second AD conversion circuit unit 700-6, and the output signal of the NAND circuit 804 is input to the NOR circuit 806 via the intermediate connection wiring 707 of the second AD conversion circuit unit 700-7. The output signal of the NOR circuit 805 is input to the NAND circuit 807 via the intermediate connection wiring 708 of the second AD conversion circuit unit 700-3 and the intermediate connection wiring 707 of the second AD conversion circuit unit 700-4, and the output signal of the NOR circuit 806 is input to the NAND circuit 807 via the intermediate connection wiring 707 of the second AD conversion circuit unit 700-6 and the intermediate connection wiring 708 of the AD conversion circuit unit 700-5. The output signal of the NAND circuit 807 is input to the relay flip-flop 710 via the intermediate connection wiring 709 of the second AD conversion circuit units 700-5, 700-6, 700-7, and 700-8.

[0043] By configuring in this manner, the path length from any of the second AD conversion circuit units 700-1 to 700-8 to the NAND circuit 807 is the wiring length of the three second AD conversion circuit units, and since there is no difference in wiring length and no difference in transmission delay occurs, it is possible to suppress the occurrence of skew.

[0044] FIG. 9 is a diagram for explaining a method for designing an AD conversion device according to this embodiment. The design method for an AD conversion device according to this embodiment can be realized by, for example, a computer (design device), and each process of the design method for an AD conversion device according to this embodiment is executed by a processor (CPU or the like) of the computer.

[0045] In step 901, the processor determines whether the number of AD conversion circuit units included in the AD conversion device is two. n It is determined whether the number of AD conversion circuit units in the AD conversion device is 2 or not. n If it is determined that there are multiple AD conversion circuit units (YES in step 901), in step 902, the processor determines whether the component circuits (logic circuits such as NAND circuits and NOR circuits) that constitute the multiplexer circuit can be placed on both sides of the AD conversion circuit unit, i.e., whether the second AD conversion circuit unit 700 can be placed.

[0046] If it is determined that element circuits can be placed on both sides of the AD conversion circuit unit (YES in step 902), in step 903, the processor arranges the multiple second AD conversion circuit units 700 in pairs of two adjacent second AD conversion circuit units 700, and arranges them (arranges them vertically) along one direction (the direction in which the intermediate connecting wirings 707, 708, 709 extend) so that the output circuit (driver circuit 702) and first element circuit units 703, 704 of the second AD conversion circuit units 700 face each other for each pair, as shown in an example in Figure 8, and arranges logic circuits that constitute multiplexer circuits in all element circuit units (first element circuit units 703, 704 and second element circuit units 705, 706) between adjacent second AD conversion circuit units 700 regardless of the pair.

[0047] On the other hand, if it is determined that element circuits cannot be placed on both sides of the AD conversion circuit unit (NO in step 902), the processor performs placement processing of the first-stage logic circuit in the multiplexer circuit (MUX first-stage processing) in step 904, as shown in an example in Fig. 10F (described later). In the placement processing in step 904, the multiple first AD conversion circuit units 300 are grouped into pairs of two adjacent first AD conversion circuit units 300, and the output circuits (driver circuits 302) and element circuit units 303 and 304 of the first AD conversion circuit units 300 for each pair are placed (vertically stacked) along one direction (the direction in which the intermediate connection wirings 305, 306, and 307 extend) so that they face each other, and logic circuits (NAND circuits) constituting the multiplexer circuit are placed in the element circuit units 303 and 304 between the two adjacent first AD conversion circuit units 300 for each pair. Next, in step 905, the processor performs a placement process for the second and subsequent stages of logic circuits in the multiplexer circuit (processing for the second and subsequent stages of MUX). In the placement process in step 905, two adjacent logic circuits in the previous stage are paired, and the first AD conversion circuit unit is placed along one direction (vertical stack placement). center The logic circuits that make up the multiplexer circuit are placed in the element circuit units 303 and 304 that are in the same positions as the logic circuits that are closest to the element circuit units 303 and 304. This placement process is repeated until there is only one logic circuit in one stage.

[0048] In step 901, the number of AD conversion circuit units included in the AD conversion device is 2. nIf it is determined that the number of AD conversion circuit units is not equal to or greater than 1 (NO), the processor performs placement processing of the first-stage logic circuit in the multiplexer circuit (MUX first-stage processing) in step 906. In the placement processing in step 906, the multiple first AD conversion circuit units 300 are grouped into pairs of two adjacent first AD conversion circuit units 300, and the output circuits (driver circuits 302) and element circuits 303 and 304 of the first AD conversion circuit units 300 for each pair are arranged (vertically stacked) along one direction (the direction in which the intermediate connection wirings 305, 306, and 307 extend) so that they face each other. If the AD conversion device has an even number of AD conversion circuit units, logic circuits that constitute the multiplexer circuit are arranged in the element circuits 303 and 304 between the two adjacent first AD conversion circuit units 300 for each pair, as shown in examples in FIGS. 10A, 10B, and 10C, which will be described later. Furthermore, when the number of AD conversion circuit units included in the AD conversion device is odd, as shown in examples in FIGS. 10D and 10E described later, at one end including the first AD conversion circuit unit 300 in which the output circuit (driver circuit 302) and element circuit sections 303 and 304 are arranged without facing other output circuits and element circuit sections, three adjacent first AD conversion circuit units 300 are grouped together and arranged along one direction of the AD conversion circuit units (vertical stack arrangement). center The logic circuits constituting the multiplexer circuits are arranged in the element circuit sections 303, 304 closest to the first AD conversion circuit units 300, and for the remaining pairs of two adjacent first AD conversion circuit units 300, the logic circuits constituting the multiplexer circuits are arranged in the element circuit sections 303, 304 between the two first AD conversion circuit units 300.

[0049] Next, in step 907, the processor performs placement processing (MUX (2 to n-1) stage processing) of logic circuits from the second stage to the (n-1) stage before the final stage in the multiplexer circuit. In the placement processing in step 907, the number of logic circuits in the previous stage is divided by 3, and as an example shown in Figures 10B, 10C, and 10E described later, sets of three logic circuits are provided from one side by the quotient number, and the number of sets of three logic circuits is centerIn the case where there are two remaining logic circuits, the logic circuits constituting the multiplexer circuit are arranged in the element circuit units 303 and 304 at the same positions as the logic circuits located at the other end. If there are two remaining logic circuits, as shown in an example in FIG. 10B described later, the logic circuits constituting the multiplexer circuit are arranged in one direction of the AD conversion circuit unit (vertical stack arrangement). center A logic circuit constituting the multiplexer circuit is placed in element circuit units 303 and 304 at the same position as the logic circuit closest to the left. If there is only one remainder, the logic circuit constituting the multiplexer circuit is placed in element circuit units 303 and 304 at the same position as that one logic circuit, as shown in examples in Figures 10C and 10E, which will be described later. This placement process is repeated until the number of logic circuits in one stage becomes two or three. As shown in examples in Figures 10A and 10D (described later), if the number of logic circuits in one stage is already two or three at the stage when step 906 is completed (the stage when step 907 starts), the placement process in step 907 is not performed and the process proceeds to step 908.

[0050] Next, in step 908, the processor performs placement processing (MUXn-th step processing) of the n-th logic circuit, which is the final step in the multiplexer circuit. In the placement processing in step 908, if the number of logic circuits in the previous step is two, the logic circuits constituting the multiplexer circuit are placed in the element circuit sections 303 and 304 between the two logic circuits, as shown in examples in FIGS. 10B and 10E, which will be described later. Also, if the number of logic circuits in the previous step is three, the logic circuits are placed in one direction of the AD conversion circuit unit (vertical stack placement), as shown in examples in FIGS. 10A, 10C, and 10D, which will be described later. center Logic circuits that constitute multiplexer circuits are arranged in element circuit units 303 and 304 on the side closer to the center. The above is the process of the AD conversion device design method according to this embodiment.

[0051] 10A to 10F show examples of the layout of logic circuits in a multiplexer circuit in an AD conversion device designed as described above. In FIGS. 10A to 10F, "◯" indicates a two-input logic circuit (NAND circuit or NOR circuit), and "●" indicates a three-input logic circuit (NAND circuit or NOR circuit). FIGS. 10A to 10C show examples of the layout of logic circuits in a multiplexer circuit in an AD conversion device designed as described above. n 10A shows an example in which the number of AD conversion circuit units is 6, FIG. 10B shows an example in which the number of AD conversion circuit units is 10, and FIG. 10C shows an example in which the number of AD conversion circuit units is 14. Also, FIGS. 10D and 10E show an example in which the number of AD conversion circuit units included in the AD conversion device is 2. n 10D shows an example in which the number of AD conversion circuit units is seven, and FIG. 10E shows an example in which the number of AD conversion circuit units is nine. Also, FIG. 10F shows an example in which the number of AD conversion circuit units included in the AD conversion device is two. n However, this example shows a case where it is not possible to place element circuits on both sides of the AD conversion circuit unit, and the number of AD conversion circuit units is eight.

[0052] As described above, according to this embodiment, in an AD conversion device that performs AD conversion by a time interleaving method using multiple AD conversion circuits, it is possible to suppress skew that occurs between output signals of multiple AD conversion circuit units without adding any circuits.

[0053] (Another embodiment of the present invention) 11 is a diagram showing an example of the configuration of a semiconductor integrated circuit device according to this embodiment. In FIG. 11, components having the same functions as those shown in FIG. 1 are assigned the same reference numerals, and redundant explanations will be omitted. The semiconductor integrated circuit device according to this embodiment includes an AD conversion device 1100 that performs AD conversion using a time interleaving method, and a signal processing circuit 1110, such as a logic circuit, that receives and processes digital signals from the AD conversion device 1100. The AD conversion device 1100 performs AD conversion on input analog signals and outputs the resulting digital signals. The digital signals output from the AD conversion device 1100 are input to the signal processing circuit 1110 by a flip-flop circuit 1111, and digital signal processing and the like are performed in the signal processing circuit 1110.

[0054] Furthermore, the above-described embodiments are merely examples of specific embodiments for carrying out the present invention, and the technical scope of the present invention should not be construed as being limited by these embodiments. In other words, the present invention can be carried out in various forms without departing from its technical idea or main features. [Industrial Applicability]

[0055] According to the present invention, it is possible to provide an AD conversion device that can suppress skew that occurs between output signals of multiple AD conversion circuit units that perform AD conversion using a time interleaving method, without adding any circuitry.

Claims

1. A plurality of AD conversion circuit units, each including an AD conversion circuit that performs analog-to-digital conversion using a time interleaving method and an output circuit that outputs the result of the AD conversion by the AD conversion circuit as an output signal; a multiplexer circuit that generates a digital signal from the output signals of the plurality of AD conversion circuit units, The multiplexer circuit is an AD conversion device in which a plurality of logic circuits are connected in a tournament configuration by a plurality of intermediate connection wires, In the circuit layout of the AD conversion device, the plurality of logic circuits and the plurality of intermediate connection wires are distributed among the plurality of AD conversion circuit units; In each of the AD converter circuit units, the output circuit and a first element circuit portion including the logic circuit are arranged along one side of an outer periphery perpendicular to a first direction, and the intermediate connection wiring is arranged to cross the first direction; The AD conversion device is characterized in that the multiple AD conversion circuit units are arranged along the first direction, with adjacent two AD conversion circuit units being grouped together, and the output circuit and the first element circuit portion of each AD conversion circuit unit facing each other for each group.

2. The AD conversion device according to claim 1, characterized in that the multiplexer circuit is constructed by connecting the logic circuit included in the first element circuit portion of the AD conversion circuit unit by the intermediate connection wiring within the AD conversion circuit unit.

3. 3. The AD conversion device according to claim 1, wherein each of the AD conversion circuit units is arranged at a center portion and at both ends so that the intermediate connection wiring crosses the first direction.

4. the intermediate connection wirings arranged at both ends are data wirings with a number of bits equal to half the number of bits related to AD conversion of the AD conversion circuit unit, 4. The AD conversion device according to claim 3, wherein the intermediate connection wiring arranged in the central portion is a data wiring for the number of bits related to AD conversion of the AD conversion circuit unit.

5. The AD conversion device described in claim 1, characterized in that each of the AD conversion circuit units has a second element circuit section, which is different from the first element circuit section and includes the logic circuit, arranged along another side of the outer periphery opposite to one side of the outer periphery on which the output circuit and the first element circuit section are arranged.

6. The AD conversion device described in claim 5, characterized in that the multiplexer circuit is constructed by connecting the logic circuits included in the first element circuit section and the second element circuit section of the AD conversion circuit unit by the intermediate connection wiring within the AD conversion circuit unit.

7. 7. The AD conversion device according to claim 5, wherein each of the AD conversion circuit units is arranged at a center portion and at both ends so that the intermediate connection wiring traverses the first direction.

8. 8. The AD conversion device according to claim 7, wherein the intermediate connection wirings arranged at both ends and the central portion are data wirings for the number of bits related to AD conversion of the AD conversion circuit unit.

9. 9. The AD conversion device according to claim 1, wherein the logic circuits constituting the multiplexer circuit are a NAND circuit and a NOR circuit.

10. an AD conversion device that performs analog-to-digital conversion using a time interleaving method; a signal processing circuit that receives a digital signal from the AD conversion device and performs a processing operation; The AD conversion device a plurality of AD conversion circuit units each including an AD conversion circuit that performs analog-to-digital conversion and an output circuit that outputs the result of the AD conversion by the AD conversion circuit as an output signal; a multiplexer circuit that generates a digital signal from the output signals of the plurality of AD conversion circuit units, The multiplexer circuit is an AD conversion device in which a plurality of logic circuits are connected in a tournament configuration by a plurality of intermediate connection wires, In the circuit layout of the AD conversion device, the plurality of logic circuits and the plurality of intermediate connection wires are distributed among the plurality of AD conversion circuit units; In each of the AD converter circuit units, the output circuit and a first element circuit portion including the logic circuit are arranged along one side of an outer periphery perpendicular to a first direction, and the intermediate connection wiring is arranged to cross the first direction; The semiconductor integrated circuit device is characterized in that the plurality of AD conversion circuit units are arranged along the first direction, with adjacent two AD conversion circuit units being grouped together, and the output circuit and the first element circuit portion of each AD conversion circuit unit facing each other for each group.

11. 11. The semiconductor integrated circuit device according to claim 10, wherein the multiplexer circuit is configured by connecting the logic circuit included in the first element circuit portion of the AD conversion circuit unit by the intermediate connection wiring within the AD conversion circuit unit.

12. 12. The semiconductor integrated circuit device according to claim 10, wherein each of the AD conversion circuit units is arranged at a center portion and at both ends so that the intermediate connection wiring crosses the first direction.

13. the intermediate connection wirings arranged at both ends of the AD conversion circuit unit are data wirings having a number of bits equal to half the number of bits involved in AD conversion of the AD conversion circuit unit, 13. The semiconductor integrated circuit device according to claim 12, wherein the intermediate connection wiring arranged in the central portion of the AD conversion circuit unit is a data wiring for the number of bits related to AD conversion of the AD conversion circuit unit.

14. 11. The semiconductor integrated circuit device according to claim 10, wherein each of the AD conversion circuit units has a second element circuit section, which is different from the first element circuit section and includes the logic circuit, arranged along another side of the periphery opposite to one side of the periphery on which the output circuit and the first element circuit section are arranged.

15. 15. The semiconductor integrated circuit device according to claim 14, wherein the multiplexer circuit is configured by connecting the logic circuits included in the first element circuit section and the second element circuit section of the AD conversion circuit unit by the intermediate connection wiring within the AD conversion circuit unit.

16. 16. The semiconductor integrated circuit device according to claim 14, wherein each of the AD conversion circuit units is arranged at a center portion and at both ends so that the intermediate connection wiring crosses the first direction.

17. 17. The semiconductor integrated circuit device according to claim 16, wherein the intermediate connection wirings arranged at both ends and the center of the AD conversion circuit unit are data wirings for the number of bits related to AD conversion of the AD conversion circuit unit.

18. A method for designing an AD conversion device having a plurality of AD conversion circuit units, each including an AD conversion circuit that performs analog-to-digital conversion in a time interleaved manner and an output circuit that outputs the result of AD conversion by the AD conversion circuit as an output signal, and a multiplexer circuit that generates a digital signal from the output signals of the plurality of AD conversion circuit units, wherein the multiplexer circuit is a circuit in which a plurality of logic circuits are connected in a tournament configuration by a plurality of intermediate connection wirings, a first step of arranging the plurality of AD converter circuit units, each of which has the output circuit and a first element circuit portion including the logic circuit arranged along one side of an outer periphery perpendicular to a first direction and the intermediate connecting wiring arranged to traverse the first direction, along the first direction, in a circuit layout of the AD converter device, with two adjacent AD converter circuit units grouped together, so that the output circuit and the first element circuit portion of the AD converter circuit unit in each group face each other; a second step of distributing the plurality of logic circuits and the plurality of intermediate connection wirings among the plurality of AD conversion circuit units in the circuit layout of the AD conversion device, connecting the plurality of logic circuits in a tournament configuration by the plurality of intermediate connection wirings, and arranging the multiplexer circuit.

19. The design method for an AD conversion device according to claim 18, characterized in that in the second step, the logic circuit is arranged in the first element circuit section between the AD conversion circuit units in the set for each number of stages of the tournament of the multiplexer circuit according to the number of the plurality of AD conversion circuit units.

20. When the number of the plurality of AD conversion circuit units is 2n, and in addition to the output circuit and the first element circuit unit, a second element circuit unit including the logic circuit different from the first element circuit unit can be arranged along another side of the outer periphery opposite to the side of the outer periphery on which the output circuit and the first element circuit unit are arranged, In the first step, the AD converter circuit units are arranged in pairs of two adjacent AD converter circuit units along the first direction such that the output circuit and the first element circuit portion of each pair face each other; 20. The design method for an AD conversion device according to claim 18 or 19, characterized in that in the second step, the logic circuit is placed in the first element circuit section and the second element circuit section between all of the AD conversion circuit units.

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