Method and system for scanning MEMS cantilevers

Abstract

A method for fabricating a cantilever beam having a device surface, a tapered surface, and an end region includes providing a semiconductor substrate having a first side and a second side opposite the first side, and etching a predetermined portion of the second side to form a plurality of recesses in the second side. Each of the plurality of recesses includes an etch-terminating surface. The method also includes anisotropically etching the etch-terminating surface to form the tapered surface of the cantilever beam, and etching a predetermined portion of the device surface to release the end region of the cantilever beam.

Description

[Technical Field]

[0001] This application claims the benefit of priority to U.S. Provisional Patent Application No. 63 / 029,258, filed May 22, 2020, and entitled "METHOD AND SYSTEM FOR SCANNING MEMS CANTILEVERS," the entire contents of which are incorporated herein by reference for all purposes. [Background technology]

[0002] Modern computing and display technology has facilitated the development of systems for so-called "virtual reality" or "augmented reality" experiences in which digitally reproduced images, or portions thereof, are presented to a viewer in a manner that appears or can be perceived as real. Virtual reality, or "VR," scenarios typically involve the presentation of digital or virtual image information without transparency to other actual, real-world visual input, while augmented reality, or "AR," scenarios typically involve the presentation of digital or virtual image information as an extension of the viewer's visualization of the real world around them.

[0003] Despite the advances made in these display technologies, there remains a need in the art for improved methods and systems relating to augmented reality systems, and particularly display systems. Summary of the Invention [Means for solving the problem]

[0004] The present invention relates generally to methods and systems for fabricating scanning microelectromechanical systems (MEMS) cantilevers. More specifically, embodiments of the present invention provide methods and systems for fabricating scanning MEMS cantilevers with tapered profiles. The present invention is applicable to a variety of applications in computer vision and image display systems.

[0005] According to an embodiment of the present invention, a method for fabricating a cantilever beam is provided. The method includes providing a semiconductor substrate including a first semiconductor layer, a first dielectric layer bonded to the first semiconductor layer, and a second semiconductor layer bonded to the first dielectric layer, forming a second dielectric layer bonded to the first semiconductor layer, forming a third dielectric layer bonded to the second semiconductor layer, and forming a first hard mask layer bonded to the second dielectric layer. The first hard mask layer includes a first set of openings that expose a first surface portion of the second dielectric layer. The method also includes etching the second dielectric layer using the first hard mask layer as a mask, etching the first semiconductor layer using the first hard mask layer as a mask, and etching the first dielectric layer using the first hard mask layer as a mask. The method further includes etching the second semiconductor layer using the first hard mask layer as a mask to form a plurality of recesses, each with a tapered surface, each having a first depth in a first region and a second depth in a second region that is greater than the first depth, and then removing the first hard mask layer.

[0006] Additionally, the method includes forming a second hard mask layer coupled to the third dielectric layer, the second hard mask layer having a second set of openings exposing second surface portions of the third dielectric layer, the second surface portions of the third dielectric layer being aligned with at least a portion of the second regions of each of the plurality of recesses. The method also includes using the second hard mask layer as a mask to etch the third dielectric layer and the second semiconductor layer to extend into the plurality of recesses, removing the second hard mask layer, removing the third dielectric layer, and removing the second dielectric layer.

[0007] In some embodiments, the above method also includes forming a chromium layer bonded to the second semiconductor layer.

[0008] In some embodiments, forming the second dielectric layer includes using a low pressure chemical vapor deposition (LPCVD) process.

[0009] In some embodiments, etching the third dielectric layer includes using a reactive ion etching (RIE) process.

[0010] In some embodiments, etching the first semiconductor layer includes using a deep RIE (DRIE) process.

[0011] In some embodiments, the first semiconductor layer is characterized by a (110) crystal orientation.

[0012] In some embodiments, the second semiconductor layer is characterized by a (111) crystal orientation.

[0013] In some embodiments where the first and second semiconductor layers are characterized by different crystal orientations, they are formed separately and then joined together using a bonding process.

[0014] In some embodiments, etching the second semiconductor layer includes using a potassium hydroxide (KOH) process for a predetermined period of time.

[0015] In some embodiments, the method also includes forming a protective dielectric layer coupled to the tapered surfaces of the plurality of recesses and the second dielectric layer.

[0016] In some embodiments, the step of forming a protective dielectric layer is performed after the step of etching the second semiconductor layer.

[0017] According to another embodiment of the present invention, a method for fabricating a cantilever beam having a device surface, a tapered surface, and an end region is provided. The method includes providing a semiconductor substrate having a first side and a second side opposite the first side, and etching a predetermined portion of the second side to form a plurality of recesses in the second side. Each of the plurality of recesses includes an etch-terminating surface. The method also includes anisotropically etching the etch-terminating surface to form the tapered surface of the cantilever beam, and etching a predetermined portion of the device surface to release the end region of the cantilever beam.

[0018] In some embodiments, the method also includes anisotropically etching the tapered surface of the cantilever to form a first lateral tapered surface perpendicular to the first side of the semiconductor substrate, the first lateral tapered surface tapering along a taper direction of the tapered surface of the cantilever.

[0019] In some embodiments, the method also includes anisotropically etching the tapered surface of the cantilever to form a second lateral tapered surface perpendicular to the first side of the semiconductor substrate, the second lateral tapered surface being formed opposite the first lateral tapered surface, and the second lateral tapered surface tapering along a taper direction of the tapered surface of the cantilever.

[0020] In some embodiments, the taper of the first lateral tapered surface is steeper than the taper of the second lateral tapered surface.

[0021] In some embodiments, the taper of the first lateral tapered surface is more gradual than the taper of the second lateral tapered surface.

[0022] In some embodiments, the taper of the first lateral tapered surface is the same as the taper of the second lateral tapered surface.

[0023] In some embodiments, the method also includes forming a chromium layer coupled to the first side of the semiconductor substrate.

[0024] In some embodiments, the method also includes forming a second dielectric layer bonded to the semiconductor substrate using a low pressure chemical vapor deposition (LPCVD) process.

[0025] In some embodiments, etching the predetermined portion of the second side includes using an RIE process.

[0026] In some embodiments, anisotropically etching the etch-terminating surface comprises using a potassium hydroxide (KOH), ethylenediamine and pyrocatechol (EDP), or tetramethylammonium hydroxide (TMAH) process.

[0027] In some embodiments, the semiconductor substrate includes a first semiconductor layer characterized by a (110) crystal orientation and a second semiconductor layer characterized by a (111) crystal orientation.

[0028] In some embodiments, etching predetermined portions of the device surface comprises using an RIE process.

[0029] According to a specific embodiment of the present invention, a method for fabricating a semiconductor cantilever beam is provided. The method includes providing a semiconductor substrate. The semiconductor substrate includes a first semiconductor layer, a first dielectric layer bonded to the first semiconductor layer, a second semiconductor layer bonded to the first dielectric layer, a second dielectric layer bonded to the second semiconductor layer, and a third dielectric layer bonded to the second dielectric layer. The method also includes forming a fourth dielectric layer bonded to the first semiconductor layer, forming a fifth dielectric layer bonded to the third dielectric layer, and forming a first hard mask layer bonded to the fourth dielectric layer. The first hard mask layer includes a first set of openings exposing a first surface portion of the fourth dielectric layer.

[0030] The method further includes etching the fourth dielectric layer using the first hard mask layer as a mask, etching the first semiconductor layer using the first hard mask layer as a mask, and etching the first dielectric layer using the first hard mask layer as a mask. The method also includes etching the second semiconductor layer using the first hard mask layer as a mask to form a plurality of recesses, each with a tapered surface. Each of the plurality of recesses has a first depth in a first region and a second depth greater than the first depth in a second region. The method includes removing the first hard mask layer. Additionally, the method includes forming a second hard mask layer coupled to the fifth dielectric layer. The second hard mask layer has a second set of openings exposing a second surface portion of the fifth dielectric layer, the second surface portion of the fifth dielectric layer being aligned with at least a portion of the second region of the tapered surface. The method further includes etching the fifth dielectric layer, the third dielectric layer, and the second semiconductor layer using the second hard mask layer as a mask to extend into the plurality of recesses; removing the second hard mask layer; removing the fifth dielectric layer; and removing the fourth dielectric layer.

[0031] In some embodiments, the method also includes forming a chromium layer coupled to the third dielectric layer.

[0032] In some embodiments, forming the fourth dielectric layer includes using an LPCVD process.

[0033] In some embodiments, etching the fourth dielectric layer includes using a RIE process.

[0034] In some embodiments, etching the first semiconductor layer includes using a DRIE process.

[0035] In some embodiments, the semiconductor substrate includes a first semiconductor layer characterized by a (110) crystal orientation and a second semiconductor layer characterized by a (111) crystal orientation.

[0036] In some embodiments, etching the second semiconductor layer includes using a KOH process for a predetermined period of time.

[0037] In some embodiments, the method also includes forming a protective dielectric layer coupled to the tapered surface and the fourth dielectric layer.

[0038] In some embodiments, the step of forming a protective dielectric layer is performed after etching the semiconductor layer.

[0039] Numerous benefits over conventional techniques are achieved by the methods of the present invention. For example, embodiments of the present invention provide methods and systems that can be used to fabricate cantilevers that can be integrated into fiber scanning display systems. Methods implemented by embodiments of the present invention can provide uniform quality to the cantilevers. Cantilevers fabricated using embodiments of the present invention can include tapered profiles that can be finely tuned. The size of the tapered tip of the cantilever can be finely controlled during the fabrication process to accommodate different fiber scanning display systems.

[0040] These and other embodiments of the present disclosure, along with many of its advantages and features, are described in more detail in conjunction with the following text and accompanying figures. [Brief explanation of the drawings]

[0041] [Figure 1] FIG. 1 is a simplified side view illustrating a cantilever beam, according to an embodiment of the present invention.

[0042] [Figure 2A] 2A-2K are partial cross-sectional views illustrating intermediate stages of a method for fabricating a cantilever beam, according to an embodiment of the present invention. [Figure 2B] 2A-2K are partial cross-sectional views illustrating intermediate stages of a method for fabricating a cantilever beam, according to an embodiment of the present invention. [Figure 2C] 2A-2K are partial cross-sectional views illustrating intermediate stages of a method for fabricating a cantilever beam, according to an embodiment of the present invention. [Figure 2D] 2A-2K are partial cross-sectional views illustrating intermediate stages of a method for fabricating a cantilever beam, according to an embodiment of the present invention. [Figure 2E] 2A-2K are partial cross-sectional views illustrating intermediate stages of a method for fabricating a cantilever beam, according to an embodiment of the present invention. [Figure 2F] 2A-2K are partial cross-sectional views illustrating intermediate stages of a method for fabricating a cantilever beam, according to an embodiment of the present invention. [Figure 2G] 2A-2K are partial cross-sectional views illustrating intermediate stages of a method for fabricating a cantilever beam, according to an embodiment of the present invention. [Figure 2H] 2A-2K are partial cross-sectional views illustrating intermediate stages of a method for fabricating a cantilever beam, according to an embodiment of the present invention. [Figure 2I] 2A-2K are partial cross-sectional views illustrating intermediate stages of a method for fabricating a cantilever beam, according to an embodiment of the present invention. [Figure 2J] 2A-2K are partial cross-sectional views illustrating intermediate stages of a method for fabricating a cantilever beam, according to an embodiment of the present invention. [Figure 2K] 2A-2K are partial cross-sectional views illustrating intermediate stages of a method for fabricating a cantilever beam, according to an embodiment of the present invention.

[0043] [Figure 2L] FIG. 2L is a perspective view illustrating a cantilever beam, according to an embodiment of the present invention.

[0044] [Figure 2M] FIG. 2M is a partial bottom view of a cantilever beam as shown in FIG. 2K.

[0045] [Figure 2N] FIG. 2N is a perspective view illustrating another cantilever beam, according to an embodiment of the present invention.

[0046] [Figure 2O] FIG. 2O is a partial bottom view illustrating a cantilever beam according to another embodiment of the present invention.

[0047] [Figure 2P] 2P and 2Q are simplified top views illustrating a cantilever beam, according to an embodiment of the present invention. [Figure 2Q] 2P and 2Q are simplified top views illustrating a cantilever beam, according to an embodiment of the present invention.

[0048] [Figure 3] FIG. 3 is a simplified flowchart illustrating a method for fabricating a cantilever beam, according to an embodiment of the present invention.

[0049] [Figure 4] FIG. 4 is a simplified side view illustrating a cantilever beam, according to an embodiment of the present invention.

[0050] [Figure 5A] 5A-5K are partial cross-sectional views illustrating a method of fabricating a cantilever beam according to an embodiment of the present invention. [Figure 5B] 5A-5K are partial cross-sectional views illustrating a method of fabricating a cantilever beam according to an embodiment of the present invention. [Figure 5C] 5A-5K are partial cross-sectional views illustrating a method of fabricating a cantilever beam according to an embodiment of the present invention. [Figure 5D] 5A-5K are partial cross-sectional views illustrating a method of fabricating a cantilever beam according to an embodiment of the present invention. [Figure 5E] 5A-5K are partial cross-sectional views illustrating a method of fabricating a cantilever beam according to an embodiment of the present invention. [Figure 5F]5A-5K are partial cross-sectional views illustrating a method of fabricating a cantilever beam according to an embodiment of the present invention. [Figure 5G] 5A-5K are partial cross-sectional views illustrating a method of fabricating a cantilever beam according to an embodiment of the present invention. [Figure 5H] 5A-5K are partial cross-sectional views illustrating a method of fabricating a cantilever beam according to an embodiment of the present invention. [Figure 5I] 5A-5K are partial cross-sectional views illustrating a method of fabricating a cantilever beam according to an embodiment of the present invention. [Figure 5J] 5A-5K are partial cross-sectional views illustrating a method of fabricating a cantilever beam according to an embodiment of the present invention. [Figure 5K] 5A-5K are partial cross-sectional views illustrating a method of fabricating a cantilever beam according to an embodiment of the present invention.

[0051] [Figure 5L] FIG. 5L is a perspective view illustrating a cantilever beam, according to an embodiment of the present invention.

[0052] [Figure 5M] FIG. 5M is a partial bottom view of the cantilever beam as shown in FIG. 5K.

[0053] [Figure 5N] FIG. 5N is a perspective view illustrating another cantilever beam, according to an embodiment of the present invention.

[0054] [Figure 5O] FIG. 5O is a partial bottom view illustrating a cantilever beam according to another embodiment of the present invention.

[0055] [Figure 5P] 5P and 5Q are simplified top views illustrating a cantilever beam, according to an embodiment of the present invention. [Figure 5Q] 5P and 5Q are simplified top views illustrating a cantilever beam, according to an embodiment of the present invention.

[0056] [Figure 6] FIG. 6 is a simplified flowchart illustrating a method for fabricating a cantilever beam, according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0057] Detailed Description Embodiments of the present invention relate to methods and systems for fabricating cantilevers for fiber scanning display systems. In some fiber scanning display systems, the scanning tip of the scanning element has a cross section that is significantly reduced compared to the normal cross section of an optical fiber. Cantilevers with tapered scanning tips can be used as scanning elements in fiber scanning display systems. Embodiments of the present invention provide such cantilevers fabricated on semiconductor substrates.

[0058] FIG. 1 is a simplified side view illustrating a cantilever beam 100 according to an embodiment of the present invention. Referring to FIG. 1, the cantilever beam 100 may include a first semiconductor layer 110, a first dielectric layer 120 bonded to the first semiconductor layer 110, and a second semiconductor layer 130 bonded to the first dielectric layer 120. In one embodiment, the cantilever beam 100 may be fabricated using a silicon-on-insulator (SOI) wafer. In this case, the first semiconductor layer 110 may include silicon and may have a thickness of approximately 300 μm. The first dielectric layer 120 may be a buried oxide (BOX) layer including SiO2 and may have a thickness of approximately 1 μm. The second semiconductor layer 130 may be a device layer including silicon and may have a thickness of approximately 115 μm. Second semiconductor layer 130 may include a device surface 132 in which a MEMS device may be fabricated or to which a MEMS device may be attached, with tapered surface 134 opposite device surface 132. Second semiconductor layer 130 is divided into a base portion 130a that is substantially aligned with first semiconductor layer 110 and first dielectric layer 120, and a cantilever portion 130b that protrudes from first semiconductor layer 110. Cantilever portion 130b may include tapered surface 134 and an end tip 136.

[0059] 2A-2L, a method of fabricating a cantilever beam 200 according to an embodiment of the present invention is described. FIG. 2A is a partial cross-sectional view illustrating a semiconductor substrate (e.g., an SOI wafer) comprising a first semiconductor layer 110, a first dielectric layer 120 bonded to the first semiconductor layer 110, and a second semiconductor layer 130 bonded to the first dielectric layer 120. For clarity, the side on which the second semiconductor layer 130 is disposed is designated as the first side of the semiconductor substrate, and the side on which the first semiconductor layer 110 is disposed is designated as the second side of the semiconductor substrate. In one embodiment, the first semiconductor layer 110 comprises silicon having a thickness of approximately 300 μm. The first dielectric layer 120 may be a buried oxide (BOX) layer, such as a SiO layer, having a thickness of approximately 1 μm. The second semiconductor layer 130 may comprise single-crystal silicon having a thickness of approximately 115 μm. It should be noted that the thicknesses of the first semiconductor layer 110, the first dielectric layer 120, and the second semiconductor layer 130 may vary depending on the needs of a particular application. In one embodiment, the first semiconductor layer 110 is characterized by a (100) or (110) crystal orientation, and the second semiconductor layer 130 is characterized by a (111) crystal orientation. In some embodiments, where the first semiconductor layer 110 and the second semiconductor layer 130 have different crystal orientations, they may be formed separately and then joined together using a bonding process. The second semiconductor layer 130 comprises a device surface 132 in which a MEMS device may be fabricated or to which a MEMS device may be attached. As an example, a metal layer (e.g., chromium) may be deposited on the device surface 132. A lift-off process may then be performed to pattern the metal layer.

[0060] Referring to FIG. 2B, a second dielectric layer 210 is formed on the first semiconductor layer 110, and a third dielectric layer 220 is formed on the second semiconductor layer 130. In one embodiment, the second dielectric layer 210 and the third dielectric layer 220 may comprise silicon nitride (SiN) having a thickness in the range of approximately 0.5 to 2 μm. In one embodiment, the second dielectric layer 210 and the third dielectric layer 220 may be formed using a low-pressure chemical vapor deposition (LPCVD) process. In some embodiments of the present invention, as described more fully below, a cantilever beam may be formed in which the device surface 132 serves as the device surface of the cantilever beam. Thus, the third dielectric layer 220 may protect the device surface 132 from subsequent etching processes. In some embodiments, the second dielectric layer 210 and / or the third dielectric layer 220 may not be utilized, depending on the needs of a particular application.

[0061] 2C, a first hard mask layer 230 is formed on the second dielectric layer 210. The first hard mask layer 230 is patterned with a first set of openings 232 through which a first surface portion 212 of the second dielectric layer 210 is exposed.

[0062] 2D-2F show intermediate stages of etching a predetermined portion of the second side of the semiconductor substrate to form a plurality of recesses in the second side, each of the plurality of recesses having an etch termination surface. Referring to FIG. 2D, an etching process is performed on the second dielectric layer 210 using the first hard mask layer 230 as a mask to form a plurality of recesses 240. In one embodiment, the etching process may include an RIE process.

[0063] 2E, an etching process is performed on the first hard mask layer 230 using the first hard mask layer 230 as a mask. In one embodiment, the etching process may include a DRIE process, which causes recesses 240 to extend through the first semiconductor layer 110.

[0064] 2F, an etching process is performed on the first dielectric layer 120 using the first hard mask layer 230 as a mask. In one embodiment, the etching process may include an RIE process that forms a recess 240 that passes through the first dielectric layer 120, forming an etch termination surface 242. The first hard mask layer 230 is then removed.

[0065] Referring to FIG. 2G, an etching process is performed on the etch termination surfaces 242 (shown in FIG. 2F) of each of the recesses 240 to form tapered surfaces 134 in the second semiconductor layer 130. In one embodiment, the first semiconductor layer 110 is characterized by a (110) crystal orientation, and the second semiconductor layer 130 is characterized by a (111) crystal orientation. The etching process may include a KOH-based etching process. In another embodiment, the etching process may include an EDP process or a TMAH process. In one embodiment, the etching process is performed for a predetermined period of time, such as 30 minutes. Note that the period of time may vary according to the thickness of the second semiconductor layer 130 and the particular etching process employed, as needed for a particular application. In each recess 240, the tapered surface 134 progresses from a base region 137, where the thickness h1 of the second semiconductor layer 130 remains substantially unchanged, to an end region 135, where the thickness h2 of the second semiconductor layer 130 is substantially reduced to a predetermined thickness, such as 10 μm.

[0066] 2H, a protective dielectric layer 250 is formed on tapered surface 134 and second dielectric layer 210. In one embodiment, protective dielectric layer 250 may comprise a SiO2 or photoresist layer having a thickness in the range of approximately 0.5-2 μm. In some embodiments of the present invention, protective dielectric layer 250 may protect tapered surface 134 from subsequent etching processes. In some other embodiments, the method may omit the process of forming protective dielectric layer 250, depending on the particular application.

[0067] 2I-2J illustrate intermediate stages of etching a predetermined portion of the device surface of the semiconductor substrate to release the cantilever end region 135. Referring to FIG. 2I, a second hard mask layer 260 is formed on the third dielectric layer 220. In one embodiment, the second hard mask layer 260 is patterned to define a second set of openings 262 through which the second surface portion 222 of the third dielectric layer 220 is exposed. In one embodiment, the second surface portion 222 is aligned with at least a portion of the end region 135 of the tapered surface 134 (as defined by the second set of openings 262) to enable the etching process to separate the cantilever end region 135 from the remainder of the second semiconductor layer 130. In one embodiment, the size of the second set of openings 262 is determined to provide a predetermined thickness h2 at the end region 135 after separation, such as 10 μm.

[0068] 2J, an etching process is performed on the third dielectric layer 220 using the second hard mask layer 260 as a mask. In one embodiment, the etching process may include an RIE process. Then, an additional etching process is performed on the second semiconductor layer 130 using the second hard mask layer 260 as a mask. In one embodiment, the additional etching process may include a buffered oxide etch (BOE) process. After the additional etching process, an end tip 136 is formed in the end region 135. In one embodiment, the thickness of the end tip 136 may be 10 μm.

[0069] 2K, the second hard mask layer 260, the third dielectric layer 220, the protective dielectric layer 250, and the second dielectric layer 210 are removed. As shown in FIG. 2K, the cantilever beam 200 is divided into a base portion 130a, which is aligned with the first dielectric layer 120 and the first semiconductor layer 110, and a cantilever portion 130b with a tapered surface 134 and an end tip 136.

[0070] 2L is a perspective view illustrating a cantilever beam 200 according to an embodiment of the present invention. Referring to FIG. 2L, the cantilever beam 200 may include a first semiconductor layer 110, a first dielectric layer 120, and a second semiconductor layer 130 having a device surface 132, a tapered surface 134, and an end tip 136. Additionally, the second semiconductor layer 130 may further include lateral surfaces 134b and 134c that are parallel to one another, as described with reference to FIG. 2L.

[0071] FIG. 2M is a partial bottom view of cantilever beam 200, as shown in FIG. 2K. Referring to FIG. 2M, a tapered structure defined by tapered surfaces 138a, 138b, and 138c is formed in second semiconductor layer 130 as a result of a KOH etching process, as described with reference to FIG. 2G. The hatched rectangle labeled by tapered surface 134 indicates the length and width of cantilever beam portion 130b, as shown in FIG. 2K. In one embodiment, an additional anisotropic etching process, such as a DRIE process, may be performed to remove portions of second semiconductor layer 130 indicated by tapered surfaces 138a, 138b, and 138c and form lateral surfaces 134b and 134c perpendicular to the first side of the semiconductor substrate. In one embodiment, lateral surfaces 134b and 134c are parallel to one another. In one embodiment, the passages 140a and 140b may be formed using an etching process, such as a DRIE process, to provide a path between the first semiconductor layer 110 and the second semiconductor layer 130.

[0072] FIG. 2N is a perspective view illustrating another cantilever beam 201 according to an embodiment of the present invention. The difference between the cantilever beam 201 shown in FIG. 2N and that shown in FIG. 2L is the triple-tapered surface provided for cantilever beam portion 130b (shown in FIG. 2K). Referring to FIG. 2N, cantilever beam 201 includes first semiconductor layer 110, first dielectric layer 120, and second semiconductor layer 130, which includes device surface 132, end tip 136, tapered surface 134, and lateral tapered surfaces 134b and 134c. With triple-tapered surfaces 134, 134b, and 134c, cantilever beam 201 can provide flexibility for adjusting the size of end tip 136. As discussed below, the positioning of end tip 136 about longitudinal axis L1 can be adjusted by controlling the taper of lateral tapered surfaces 134b and 134c.

[0073] FIG. 2O is a partial bottom view illustrating a cantilever beam 201 according to another embodiment of the present invention. Referring to FIG. 2O, when the portion of the second semiconductor layer 130 indicated by tapered surface 138a is etched to form the lateral surfaces 134b and 134c, the width of the cantilever beam portion 130b tapers from the base region 137 to the end region 135, forming two lateral tapered surfaces 134b and 134c. In one embodiment, the taper of the tapered surfaces 134b and 134c is symmetric about the longitudinal axis L1 of the cantilever beam 201. In another embodiment, the taper of the tapered surfaces 134b and 134c may be asymmetric about the longitudinal axis L1. For example, the taper of the tapered surface 134b may be steeper than that of the tapered surface 134c. In another embodiment, the taper of tapered surface 134b may be less steep than that of tapered surface 134c. The taper of tapered surfaces 134b and / or 134c may vary as needed for a particular application.

[0074] 2P and 2Q are simplified top views illustrating cantilever beam 201 according to an embodiment of the present invention. Referring to FIG. 2P, the taper of lateral tapered surface 134c is steeper than that of lateral tapered surface 134b. As a result, end tip 136 is positioned in such a manner that the center of end tip 136 is located to the left of longitudinal axis L1. Thus, as shown in FIG. 2N, when end tip 136 is viewed along direction V1, which is normal to device surface 132 and perpendicular to longitudinal axis L1, end tip 136 is offset to the left of longitudinal axis L1 in FIG. 2N. Referring to FIG. 2Q, the taper of lateral tapered surface 134c is more gradual than that of lateral tapered surface 134b. As a result, end tip 136 is offset to the right. Thus, as shown in FIG. 2N, when viewing end tip 136 along a direction V1 that is normal to device surface 132 and perpendicular to longitudinal axis L1, end tip 136 is offset to the right of longitudinal axis L1 in FIG. 2N.

[0075] A number of benefits may be provided by the flexibility to adjust end tip 136 by controlling triple tapered surfaces 134, 134b, and 134c, either alone or in combination. For example, cantilever beam 201 with differently configured end tips 136 may be used to accommodate different optical configurations of scanning fiber display devices.

[0076] FIG. 3 is a simplified flowchart illustrating a method 300 of fabricating a cantilever beam in accordance with an embodiment of the present invention. Referring to FIG. 3, method 300 includes providing (302) a semiconductor substrate including a first semiconductor layer, a first dielectric layer, and a second semiconductor layer. In the illustrated embodiment, the semiconductor substrate may include an SOI substrate comprising a first semiconductor layer (e.g., Si), a first dielectric layer (e.g., SiO 2 ) bonded to the first semiconductor layer, and a second semiconductor layer (e.g., Si) bonded to the first dielectric layer. In one embodiment, the first semiconductor layer may include a Si layer having a thickness of approximately 300 μm, the first dielectric layer may include a SiO 2 layer having a thickness of approximately 1 μm, and the second semiconductor layer may include a Si layer having a thickness of approximately 115 μm.

[0077] The method 300 may further include forming a second dielectric layer coupled to the first semiconductor layer and forming a third dielectric layer coupled to the second semiconductor layer (302). In one embodiment, the second and third dielectric layers may comprise silicon nitride (SiN) to protect the upper and lower surfaces of the semiconductor substrate during a subsequent etching process. In some embodiments, the method 300 may omit the process of forming the second dielectric layer.

[0078] The method 300 may further include forming 306 a first hard mask layer coupled to the second dielectric layer. The first hard mask layer may include a first set of openings exposing a first surface portion of the second dielectric layer.

[0079] The method 300 further includes etching (308) the second dielectric layer, the first semiconductor layer, and the first dielectric layer using the first hard mask layer as a mask. In an embodiment, the etching of the second dielectric layer may use a reactive ion etching (RIE) process. In another embodiment, the etching of the first semiconductor layer may use a deep RIE (DRIE) process, which provides a highly anisotropic etch and may produce steep side etch recesses. In one embodiment, the etching of the first dielectric layer may use a RIE process.

[0080] The method 300 may further include etching the second semiconductor layer using the first hard mask layer as a mask to form a plurality of recesses, each with a tapered surface (310). After the etching process is completed, the method may further include removing the first hard mask layer. Each of the plurality of recesses has a first depth in a first region and a second depth greater than the first depth in a second region. In one embodiment, the first semiconductor layer is characterized by a (110) crystal orientation, and the second semiconductor layer is characterized by a (111) crystal orientation. Etching the second semiconductor layer may use a potassium hydroxide (KOH) process that exhibits an etch rate selectivity with respect to the (100) crystal orientation that is 400 times higher than that of the (111) crystal orientation. In another embodiment, the etching of the second semiconductor layer can utilize an ethylenediamine and pyrocatechol (EDP) process and a tetramethylammonium hydroxide (TMAH) process to etch the second semiconductor layer and form a tapered surface.

[0081] The method 300 may further include forming a protective dielectric layer (312) coupled to the tapered surfaces of the plurality of recesses and the second dielectric layer. In one embodiment, the protective dielectric layer may include SiO2 or a resist material.

[0082] The method 300 may further include forming (314) a second hard mask layer coupled to the third dielectric layer. The second hard mask layer may include a second set of openings exposing second surface portions of the third dielectric layer. The second surface portions of the third dielectric layer may thus be aligned with at least a portion of each of the plurality of recesses.

[0083] The method 300 may then further include etching the third dielectric layer and the second semiconductor layer using the second hard mask layer as a mask to extend into the plurality of recesses (316). Thus, the etched areas may extend into the recesses because the openings in the hard mask are aligned with portions of the recesses. Thereafter, the method 300 may include removing the second hard mask layer, the third dielectric layer, and the second dielectric layer (318).

[0084] It should be understood that the specific steps illustrated in FIG. 3 provide a particular method of fabricating a cantilever beam in accordance with an embodiment of the present invention. Other sequences of steps may also be performed according to alternative embodiments. For example, alternative embodiments of the present invention may perform the steps outlined above in a different order. Furthermore, individual steps illustrated in FIG. 3 may include multiple sub-steps that may be performed in various sequences, depending on the needs of the individual step. Furthermore, additional steps may be added or removed depending on the particular application. Those skilled in the art will recognize many variations, modifications, and alternatives.

[0085] FIG. 4 is a simplified side view illustrating a cantilever beam according to an embodiment of the present invention. Referring to FIG. 4, the cantilever beam 400 may include a first semiconductor layer 410, a first dielectric layer 420 bonded to the first semiconductor layer 410, a second semiconductor layer 430 bonded to the first dielectric layer 420, a second dielectric layer 440 bonded to the second semiconductor layer 430, and a third dielectric layer 450 bonded to the second dielectric layer 440. In one embodiment, the cantilever beam 400 may be fabricated using a semiconductor substrate such as a silicon-on-insulator (SO-SOI) wafer. In this case, the first semiconductor layer 410 may include silicon and may have a thickness of approximately 400 μm. The first dielectric layer 120 may be a buried oxide (BOX) layer including SiO 2 and may have a thickness of approximately 1 μm. The second semiconductor layer 130 may be a first device layer comprising silicon and may have a thickness of approximately 105 μm. The second dielectric layer 440 may be another BOX layer comprising SiO2 and may have a thickness of 1 μm. The third dielectric layer 450 may be a second device layer comprising silicon and may have a thickness of 10 μm. The third dielectric layer 450 may include a device surface 452 in which a MEMS device may be fabricated or to which a MEMS device may be attached. The second semiconductor layer 430, the second dielectric layer 440, and the third dielectric layer 450 are horizontally divided into a base portion 430a and a cantilever portion 430b. The cantilever portion 430b of the second semiconductor layer 430 may include a tapered surface 434 and an end tip 436.

[0086] 5A-5K, a method of fabricating a cantilever beam 500 according to an embodiment of the present invention is described. FIG. 5A is a partial cross-sectional view illustrating a semiconductor substrate (e.g., an SO-SOI wafer) comprising a first semiconductor layer 510, a first dielectric layer 520 bonded to the first semiconductor layer 510, a second semiconductor layer 530 bonded to the first dielectric layer 520, a second dielectric layer 540 bonded to the second semiconductor layer 530, and a third dielectric layer 550 bonded to the second dielectric layer 540. For clarity, the side on which the third dielectric layer 550 is disposed is designated as the first side of the semiconductor substrate. The side on which the first semiconductor layer 510 is disposed is designated as the second side of the semiconductor substrate. In one embodiment, the first semiconductor layer 510 may comprise silicon having a thickness of approximately 400 μm. The second semiconductor layer 520 may be a BOX layer, such as a SiO2 layer, and may have a thickness of approximately 1 μm. The second semiconductor layer 530 may be a first device layer comprising single-crystal silicon and may have a thickness of approximately 105 μm. The second dielectric layer 540 may be another BOX layer, such as a SiO2 layer, and may have a thickness of approximately 1 μm. The third dielectric layer 550 may be a second device layer comprising single-crystal silicon and may have a thickness of approximately 10 μm. It should be noted that the thicknesses of the individual semiconductor layers, including the first semiconductor layer 510, the first dielectric layer 520, the second semiconductor layer 530, the second dielectric layer 540, and the third dielectric layer 550, may vary as needed for a particular application. In one embodiment, the first semiconductor layer 510 is characterized by a (100) or (110) crystal orientation, the second semiconductor layer 530 is characterized by a (111) crystal orientation, and the third dielectric layer 550 is characterized by a (100) crystal orientation. The third dielectric layer 550 may include a device surface 552 in which a MEMS device may be fabricated or to which a MEMS device may be attached. As an example, a metal layer (e.g., chromium) may be deposited on the device surface 552. A lift-off process may then be performed to pattern the metal layer.

[0087] Referring to FIG. 5B, a fourth dielectric layer 560 is formed on the first semiconductor layer 510, and a fifth dielectric layer 570 is formed on the third dielectric layer 550. In one embodiment, the fourth dielectric layer 560 and the fifth dielectric layer 570 may comprise silicon nitride (SiN) having a thickness in the range of approximately 0.5 to 2 μm. In one embodiment, the fourth dielectric layer 560 and the fifth dielectric layer 570 may be formed using an LPCVD process. In some embodiments of the present invention, as described more fully below, a cantilever beam may be formed in which the device surface 552 serves as the device layer of the cantilever beam. Thus, the fifth dielectric layer 570 may protect the device surface 552 during subsequent etching processes. In some embodiments, the fourth dielectric layer 560 and / or the fifth dielectric layer 570 may not be utilized, depending on the needs of a particular application.

[0088] 5C, a first hard mask layer 580 is formed on the fourth dielectric layer 560. The first hard mask layer 580 is patterned with a first set of openings 582 through which a first surface portion 562 of the fourth dielectric layer 560 is exposed.

[0089] 5D-5F show intermediate stages of etching predetermined portions of the second side of the semiconductor substrate to form a plurality of recesses in the second side, each of which may include an etch termination surface. Referring to FIG. 5D, an etching process is performed on the fourth dielectric layer 560 using the first hard mask layer 580 as a mask to form a plurality of recesses 512. In one embodiment, the etching process may include an RIE process.

[0090] 5E, an etching process is performed on the first semiconductor layer 510 using the first hard mask layer 580 as a mask. In one embodiment, the etching process may include a DRIE process, which causes recesses 512 to extend through the first semiconductor layer 510.

[0091] 5F, an etching process is performed on the first dielectric layer 520 using the first hard mask layer 580 as a mask. In one embodiment, the etching process may include an RIE process that passes through the first dielectric layer 520 to form a recess 512, forming an etch termination surface 514. The first hard mask layer 580 is then removed.

[0092] Referring to FIG. 5G , an etching process is performed on the second semiconductor layer 530 to form tapered surfaces 534 within each of the recesses 512. In one embodiment, the first semiconductor layer 510 is characterized by a (110) crystal orientation, and the second semiconductor layer 530 is characterized by a (111) crystal orientation. The etching process may include a KOH-based etching process, an EDP process, or a TMAH process. In one embodiment, the etching process is performed for a predetermined period of time, such as 30 minutes. Note that the period of time may vary depending on the thickness of the second semiconductor layer 530 and the particular etching process employed, as needed for a particular application. In each of the recesses 512, the tapered surfaces 534 progress from a base region 537, where the thickness h1 of the second semiconductor layer 530 remains substantially unchanged, to an end region 535, where the thickness h2 of the second semiconductor layer 530 is substantially reduced to a predetermined thickness, such as 10 μm.

[0093] 2H, a protective dielectric layer 526 is formed on tapered surface 534 and fourth dielectric layer 560. In one embodiment, protective dielectric layer 526 may comprise a SiO2 or photoresist layer having a thickness in the range of approximately 0.5-2 μm. In some embodiments of the present invention, protective dielectric layer 526 may protect tapered surface 534 from subsequent etching processes. In some other embodiments, the method may omit the process of forming protective dielectric layer 526, depending on the particular application.

[0094] 5I-5J illustrate intermediate stages of etching a predetermined portion of the device surface of the semiconductor substrate to release the cantilever end region 535. Referring to FIG. 5I, a second hard mask layer 590 is formed on the fifth dielectric layer 570. In one embodiment, the second hard mask layer 590 is patterned to define a second set of openings 592 through which the second surface portion 572 of the fifth dielectric layer 570 is exposed. In one embodiment, the second surface portion 572 is aligned with at least a portion of the end region 535 of the tapered surface 534 (as defined by the second set of openings 592) to enable the etching process to separate the cantilever end region 535 from the remainder of the second semiconductor layer 530. In one embodiment, the size of the third set of openings 592 is determined to provide a predetermined thickness h2 at the end region 535 after separation, such as 10 μm.

[0095] 5J, an etching process is performed on the fifth dielectric layer 570 using the second hard mask layer 590 as a mask. In one embodiment, the etching process may include an RIE process. Then, an additional etching process is performed on the third dielectric layer 550, the second dielectric layer 540, and the second semiconductor layer 530 using the second hard mask layer 590 as a mask. In one embodiment, the additional etching process may include a BOE process. After the additional etching process, an end tip 536 is formed in the end region 535. In one embodiment, the thickness of the end tip 536 may be 10 μm.

[0096] 5K, the second hard mask layer 590, the fifth dielectric layer 570, the protective dielectric layer 526, and the fourth dielectric layer 560 are removed. As shown in FIG. 5K, the cantilever beam 500 is divided into a base portion 530a and a cantilever portion 530b. In one embodiment, the first semiconductor layer 510 and the first dielectric layer 520 may include only the base portion 530a, while the second semiconductor layer 530, the second dielectric layer 540, and the third dielectric layer 550 may include both the base portion 530a and the cantilever portion 530b. In one embodiment, the cantilever portion 530b of the second semiconductor layer 530 includes a tapered surface 534 and an end tip 536, the cantilever portion 530b of the second dielectric layer 540 includes an end surface 546, and the cantilever portion 530b of the third dielectric layer 550 includes an end surface 556. In some embodiments, the end tip 536, the end surface 546, and the end surface 556 may be configured in combination to function as the light-emitting tip of a scanning fiber display device. In some other embodiments, only the end tip 536 can be used as the light-emitting tip of a scanning fiber display device.

[0097] 5L is a perspective view illustrating a cantilever beam 500 according to an embodiment of the present invention. Referring to FIG. 5L, the cantilever beam 500 may include a first semiconductor layer 510, a first dielectric layer 520, a second semiconductor layer 530, a second dielectric layer 540, and a third dielectric layer 550. The second semiconductor layer 530 includes a tapered surface 534 and an end tip 536. The second dielectric layer 540 includes an end surface 546. The third dielectric layer 550 includes a device surface 552 and an end surface 556. Additionally, the second semiconductor layer 530, the second dielectric layer 540, and the third dielectric layer 550 may include lateral surfaces 534b and 534c that are parallel to one another, as described below.

[0098] FIG. 5M is a partial bottom view of cantilever beam 500 as shown in FIG. 5K. Referring to FIG. 5M, a tapered structure defined by tapered surfaces 538a, 538b, and 538c is formed in second semiconductor layer 530 as a result of a KOH etching process, as described with reference to FIG. 5G. The hatched rectangle labeled by tapered surface 534 indicates the length and width of cantilever beam portion 530b, as shown in FIG. 5L. In one embodiment, an additional anisotropic etching process, such as a DRIE process, may be performed to remove portions of second semiconductor layer 530, second dielectric layer 540, and third dielectric layer 550 indicated by tapered surfaces 538a, 538b, and 538c, and form lateral surfaces 534b and 534c perpendicular to the first side of the semiconductor substrate. In one embodiment, lateral surfaces 534b and 534c are parallel to one another. In one embodiment, the passages 539a and 539b may be formed using an etching process, such as a DRIE process, to provide paths into the first semiconductor layer 510, the second semiconductor layer 530, and the third dielectric layer 550.

[0099] 5N is a perspective view illustrating another cantilever beam 501 according to another embodiment of the present invention. Referring to FIG. 5N, cantilever beam 501 includes a first semiconductor layer 510, a first dielectric layer 520, a second semiconductor layer 530, a second dielectric layer 540, and a third dielectric layer 550. Second semiconductor layer 530 includes a tapered surface 534 and an end tip 536. Second dielectric layer 540 includes an end surface 546, and third dielectric layer 550 includes an end surface 556. Second semiconductor layer 530, second dielectric layer 540, and third dielectric layer 550 include lateral tapered surfaces 534b and 534c on cantilever beam portion 530b. Cantilever beam 501, with triple tapered surfaces 534, 534b, and 534c, can provide flexibility for adjusting the size of end tip 536, end surface 546, and end surface 556. As discussed below, the positioning of end tip 536, end surface 546, and end surface 556 about longitudinal axis L1 can be adjusted by controlling the taper of lateral tapered surfaces 534b and 534c.

[0100] FIG. 5O is a partial bottom view illustrating a cantilever beam 501 according to another embodiment of the present invention. The difference between the cantilever beam 501 shown in FIG. 5O and that shown in FIG. 5M is the triple tapered surface provided for cantilever beam portion 530b (shown in FIG. 5N). Referring to FIG. 5O, upon etching the portions of second semiconductor layer 530, second dielectric layer 540, and third dielectric layer 550 indicated by tapered surface 538a, the width of cantilever beam portion 530b tapers from base region 537 to end region 535, forming two lateral tapered surfaces 534b and 534c. In one embodiment, the taper of tapered surfaces 534b and 534c is symmetric about longitudinal axis L1 of cantilever beam 501. In another embodiment, the taper of tapered surfaces 534b and 534c may be asymmetric about longitudinal axis L1. For example, the taper of tapered surface 534b may be steeper than that of tapered surface 534c. In another embodiment, the taper of tapered surface 534b may be less steep than that of tapered surface 534c. The taper of tapered surfaces 534b and 534c may vary as needed for a particular application.

[0101] 5P and 5Q are simplified top views illustrating cantilever beam 501 according to an embodiment of the present invention. Referring to FIG. 5P, the taper of lateral tapered surface 534c is steeper than that of lateral tapered surface 534b. As a result, end tip 536, end surface 546 (not shown), and end surface 556 (not shown) are positioned in such a manner that the center of the end tip is disposed to the left of longitudinal axis L1. Thus, as shown in FIG. 5N, when viewing end tip 536 along direction V1, which is normal to device surface 552 and perpendicular to longitudinal axis L1, end tip 536, end surface 546, and end surface 556 may be offset to the left of longitudinal axis L1 in FIG. 5N. Referring to FIG. 5Q, the taper of lateral tapered surface 534c is more gradual than that of lateral tapered surface 534b. Thus, as shown in FIG. 5N, when viewing end tip 536 along a direction V1 that is normal to device surface 552 and perpendicular to longitudinal axis L1, end tip 536, end surface 546, and end surface 556 may be offset to the right of longitudinal axis L1 in FIG. 5N.

[0102] A number of benefits may be provided by the flexibility to adjust end tip 536, end surface 546, and end surface 556 by controlling triple tapered surfaces 534, 534b, and 534c, alone or in combination. For example, cantilever beam 501 with differently configured end tip 536, end surface 546, and end surface 556 may be used to accommodate different optical configurations of scanning fiber display devices.

[0103] 6 is a simplified flowchart illustrating a method 600 of fabricating a cantilever beam in accordance with an embodiment of the present invention. Referring to FIG. 6, method 600 includes providing (602) a semiconductor substrate including a first semiconductor layer, a first dielectric layer, a second semiconductor layer, a second dielectric layer, and a third dielectric layer. In the illustrated embodiment, the semiconductor substrate may include an SO-SOI substrate including a first semiconductor layer (e.g., Si), a first dielectric layer (e.g., SiO2) bonded to the first semiconductor layer, a second semiconductor layer (e.g., Si) bonded to the first dielectric layer, a second dielectric layer (e.g., SiO2) bonded to the second semiconductor layer, and a third dielectric layer (e.g., Si) bonded to the second dielectric layer. In one embodiment, the first semiconductor layer may include a Si layer having a thickness of about 400 μm, the first dielectric layer may include a SiO layer having a thickness of about 1 μm, the second semiconductor layer may include a Si layer having a thickness of about 105 μm, the second dielectric layer may include a SiO layer having a thickness of about 1 μm, and the third dielectric layer may include a Si layer having a thickness of about 10 μm.

[0104] The method 600 may further include forming a fourth dielectric layer coupled to the first semiconductor layer and forming a fifth dielectric layer coupled to the third dielectric layer (604). In one embodiment, the fourth and fifth dielectric layers may comprise SiN and protect the lower and upper surfaces of the semiconductor substrate during subsequent etching processes. In some embodiments, the method 600 may omit the process of forming the fourth dielectric layer.

[0105] The method 600 may further include forming 606 a first hard mask layer coupled to the fourth dielectric layer. The first hard mask layer may include a first set of openings exposing a first surface portion of the fourth dielectric layer.

[0106] The method 600 may further include etching (608) the fourth dielectric layer, the first semiconductor layer, and the first dielectric layer using the first hard mask layer as a mask. In an embodiment, the etching of the fourth dielectric layer may use an RIE process. In another embodiment, the etching of the first semiconductor layer may use a DRIE process. In one embodiment, the etching of the first dielectric layer may use an RIE process.

[0107] The method 600 may further include etching the second semiconductor layer using the first hard mask layer as a mask to form a plurality of recesses, each with a tapered surface (610). Each of the plurality of recesses may include a first depth in a first region and a second depth greater than the first depth in a second region. After the etching process is completed, the method may further include removing the first hard mask layer. In one embodiment, the first semiconductor layer is characterized by a (110) crystal orientation, and the second semiconductor layer is characterized by a (111) crystal orientation. Etching the second semiconductor layer may use a KOH-based process. In another embodiment, etching the second semiconductor layer may utilize an EDP process and a TMAH process to etch the second semiconductor layer and form the tapered surface.

[0108] The method 600 may further include forming a protective dielectric layer (612) coupled to the tapered surfaces of the plurality of recesses and the fourth dielectric layer. In one embodiment, the protective dielectric layer may include SiO2 or a resist material.

[0109] The method 600 may further include forming (614) a second hard mask layer coupled to the fifth dielectric layer. The second hard mask layer may include a second set of openings exposing second surface portions of the fifth dielectric layer. The second surface portions of the fifth dielectric layer may thus be aligned with at least a portion of the second regions of each of the plurality of recesses.

[0110] The method may then further include etching the fifth dielectric layer, the third dielectric layer, and the second semiconductor layer to extend into the plurality of recesses using the second hard mask layer as a mask (616). Thereafter, the method may include removing the second hard mask layer, the fifth dielectric layer, and the fourth dielectric layer (618).

[0111] It should be understood that the specific steps illustrated in FIG. 6 provide a particular method of fabricating a cantilever beam in accordance with an embodiment of the present invention. Other sequences of steps may also be performed according to alternative embodiments. For example, alternative embodiments of the present invention may perform the steps outlined above in a different order. Furthermore, individual steps illustrated in FIG. 6 may include multiple sub-steps that may be performed in various sequences, depending on the needs of the individual step. Furthermore, additional steps may be added or removed depending on the particular application. Those skilled in the art will recognize many variations, modifications, and alternatives.

[0112] Embodiments of the present invention are described herein with reference to the accompanying drawings. However, the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this invention will be thorough and complete, and will fully convey the scope of possible embodiments to those skilled in the art. Features may not be drawn to scale and some details may be exaggerated relative to other elements for clarity. Like numbers refer to like elements throughout.

[0113] It should be understood that the drawings are not drawn to scale and like reference numerals are used to represent like elements. As used herein, the terms "exemplary embodiment," "exemplary embodiment," and "the present embodiment" do not necessarily refer to a single embodiment, and various exemplary embodiments may be readily combined and interchanged without departing from the scope or spirit of the present invention.

[0114] Furthermore, the terminology as used herein is for the purpose of describing example embodiments only and is not intended to be limiting of the present invention. In this regard, as used herein, the term "in" may include "in" and "on," and the terms "a," "an," and "the" may include singular and plural references. Furthermore, as used herein, the term "by" may also mean "from," depending on the context. Furthermore, as used herein, the term "if" may also mean "when" or "upon," depending on the context. Furthermore, as used herein, the word "and / or" may refer to and include any possible combination of one or more of the associated listed items.

[0115] While the terms "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers, and / or sections, it should be understood that these elements, components, regions, layers, and / or sections are not limited by these terms. These terms are used only to distinguish one element, component, region, layer, or section from another region, layer, or section. Thus, a first element, component, region, layer, or section discussed below could be referred to as a second element, component, region, layer, or section without departing from the teachings of the present invention.

[0116] The term "horizontal" as used herein is defined as a plane parallel to the conventional plane or surface of a wafer or substrate, regardless of the orientation of the wafer or substrate. The term "vertical" refers to a direction perpendicular to horizontal as defined above. Prepositions such as "on," "side" (as in "sidewall"), "below," "above," "higher," "lower," "over," and "under" are defined as being on the upper surface of the wafer or substrate, relative to the conventional plane or surface, regardless of the orientation of the wafer or substrate. It should be understood that these terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

[0117] It should be understood that the appended claims are not limited to the precise configurations illustrated in the drawings. Those skilled in the art will recognize that various modifications, substitutions, and variations may be made in the arrangements and steps of the methods and devices described above without departing from the scope of the present invention.

Claims

1. 1. A method for forming a cantilever beam, the method comprising: providing a semiconductor substrate comprising a first semiconductor layer, a first dielectric layer coupled to the first semiconductor layer, and a second semiconductor layer coupled to the first dielectric layer; forming a second dielectric layer coupled to the first semiconductor layer; forming a third dielectric layer coupled to the second semiconductor layer; forming a first hard mask layer coupled to the second dielectric layer, the first hard mask layer comprising a first set of openings exposing a first surface portion of the second dielectric layer; Etching the second dielectric layer using the first hard mask layer as a mask; Etching the first semiconductor layer using the first hard mask layer as a mask; Etching the first dielectric layer using the first hard mask layer as a mask; etching the second semiconductor layer using the first hard mask layer as a mask to form a plurality of recesses each with a tapered surface, each of the plurality of recesses having a first depth in a first region and a second depth in a second region that is greater than the first depth; removing the first hard mask layer; forming a second hard mask layer coupled to the third dielectric layer, the second hard mask layer having a second set of openings exposing second surface portions of the third dielectric layer, the second surface portions of the third dielectric layer overlapping in a stacking direction with at least a portion of a second region of each of the plurality of recesses; etching the third dielectric layer and the second semiconductor layer using the second hard mask layer as a mask, and extending holes formed in the third dielectric layer and the second semiconductor layer through to the plurality of recesses; removing the second hard mask layer; removing the third dielectric layer; removing the second dielectric layer; A method comprising:

2. The method of claim 1, wherein providing the semiconductor substrate further includes forming a chromium layer bonded to the second semiconductor layer on the side opposite to the side bonded to the first dielectric layer.

3. 10. The method of claim 1, wherein forming the second dielectric layer comprises using a low pressure chemical vapor deposition (LPCVD) process.

4. The method of claim 1 , wherein etching the third dielectric layer comprises using a reactive ion etching (RIE) process.

5. The method of claim 1 , wherein etching the first semiconductor layer comprises using a deep RIE (DRIE) process.

6. The method of claim 1 , wherein the first semiconductor layer is characterized by a (110) crystal orientation.

7. The method of claim 1 , wherein the second semiconductor layer is characterized by a (111) crystal orientation.

8. 10. The method of claim 1, wherein etching the second semiconductor layer comprises using a potassium hydroxide (KOH) process for a predetermined period of time.

9. The method of claim 1 , further comprising forming a protective dielectric layer coupled to the tapered surfaces of the plurality of recesses and the second dielectric layer.

10. 10. The method of claim 9, wherein forming the protective dielectric layer is performed after etching the second semiconductor layer.

11. 1. A method for forming a cantilever beam having a device surface, a tapered surface, and an end region, the method comprising: providing a semiconductor substrate having a first side and a second side opposite the first side; Etching a predetermined portion of the second side to form a plurality of recesses in the second side, each recess having an etch termination surface; anisotropically etching the etching termination surface to form a tapered surface of the cantilever beam; etching a predetermined portion of the device surface to release an end region of the cantilever; A method comprising:

12. 12. The method of claim 11, further comprising anisotropically etching the tapered surface of the cantilever beam to form a first lateral tapered surface perpendicular to a first side of the semiconductor substrate, the first lateral tapered surface tapering along a taper direction of the tapered surface of the cantilever beam.

13. 13. The method of claim 12, further comprising anisotropically etching the tapered surface of the cantilever to form a second lateral tapered surface perpendicular to the first side of the semiconductor substrate, the second lateral tapered surface being formed opposite the first lateral tapered surface, the second lateral tapered surface tapering along a taper direction of the tapered surface of the cantilever.

14. The method of claim 13 , wherein the taper of the first lateral tapered surface is steeper than the taper of the second lateral tapered surface.

15. The method of claim 13 , wherein the taper of the first lateral tapered surface is more gradual than the taper of the second lateral tapered surface.

16. The method of claim 13 , wherein the taper of the first lateral tapered surface is the same as the taper of the second lateral tapered surface.

17. The method of claim 11, wherein providing the semiconductor substrate further comprises forming a chromium layer bonded to a first side of the semiconductor substrate.

18. 12. The method of claim 11, further comprising forming a dielectric layer coupled to the semiconductor substrate using a low pressure chemical vapor deposition (LPCVD) process.

19. The method of claim 11 , wherein etching the predetermined portion of the second side comprises using a RIE process.

20. 12. The method of claim 11, wherein anisotropically etching the etch-terminating surface comprises using a potassium hydroxide (KOH), ethylenediamine and pyrocatechol (EDP), or tetramethylammonium hydroxide (TMAH) process.

21. 12. The method of claim 11, wherein the semiconductor substrate includes a first semiconductor layer characterized by a (110) crystal orientation and a second semiconductor layer characterized by a (111) crystal orientation.

22. The method of claim 11 , wherein the semiconductor substrate comprises a semiconductor layer characterized by a (111) crystal orientation.

23. The method of claim 11 , wherein etching the predetermined portion of the device surface comprises using a RIE process.

24. 1. A method for forming a semiconductor cantilever, the method comprising: providing a semiconductor substrate comprising: a first semiconductor layer; a first dielectric layer coupled to the first semiconductor layer; a second semiconductor layer coupled to the first dielectric layer; a second dielectric layer coupled to the second semiconductor layer; and a third dielectric layer coupled to the second dielectric layer; forming a fourth dielectric layer coupled to the first semiconductor layer; forming a fifth dielectric layer coupled to the third dielectric layer; forming a first hard mask layer coupled to the fourth dielectric layer, the first hard mask layer comprising a first set of openings exposing a first surface portion of the fourth dielectric layer; Etching the fourth dielectric layer using the first hard mask layer as a mask; Etching the first semiconductor layer using the first hard mask layer as a mask; Etching the first dielectric layer using the first hard mask layer as a mask; etching the second semiconductor layer using the first hard mask layer as a mask to form a plurality of recesses each with a tapered surface, each of the plurality of recesses having a first depth in a first region and a second depth in a second region that is greater than the first depth; forming a second hard mask layer coupled to the fifth dielectric layer, the second hard mask layer having a second set of openings exposing a second surface portion of the fifth dielectric layer, the second surface portion of the fifth dielectric layer overlapping in a stacking direction with at least a portion of a second region of the tapered surface; etching the fifth dielectric layer, the third dielectric layer, and the second semiconductor layer using the second hard mask layer as a mask, and extending holes formed in the fifth dielectric layer, the third dielectric layer, and the second semiconductor layer through to the plurality of recesses; removing the second hard mask layer; removing the fifth dielectric layer; removing the fourth dielectric layer; A method comprising:

25. 25. The method of claim 24, wherein providing the semiconductor substrate further comprises forming a chromium layer bonded to the third dielectric layer on a side opposite to that bonded to the second dielectric layer.

26. 25. The method of claim 24, wherein forming the fourth dielectric layer includes using a LPCVD process.

27. 25. The method of claim 24, wherein etching the fourth dielectric layer comprises using a RIE process.

28. 25. The method of claim 24, wherein etching the first semiconductor layer comprises using a DRIE process.

29. 25. The method of claim 24, wherein the first semiconductor layer is characterized by a (110) crystal orientation and the second semiconductor layer is characterized by a (111) crystal orientation.

30. 25. The method of claim 24, wherein the second semiconductor layer is characterized by a (111) crystal orientation.

31. 25. The method of claim 24, wherein etching the second semiconductor layer comprises using a potassium hydroxide (KOH) process for a predetermined period of time.

32. 25. The method of claim 24, further comprising forming a protective dielectric layer coupled to the tapered surface and the fourth dielectric layer.

33. 33. The method of claim 32, wherein forming the protective dielectric layer is performed after etching the second semiconductor layer.

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