Chip rank identification circuit

Abstract

To provide a chip rank identification circuit capable of achieving chip rank identification by effectively using a TSV region. A first control circuit couples the resistor circuit to a first operating voltage or a first contact based on whether the chip is connected to a subsequent chip. A second control circuit couples the resistor circuit to a second operating voltage or a third contact based on whether the chip is connected to a previous chip. An identification circuit determines the rank of the chip based on the reference voltage provided by the resistor circuit.

Description

[Technical Field]

[0001] The present invention relates to a detection circuit, and more particularly to a chip rank identification circuit. [Background technology]

[0002] Due to the limited area of ​​current dynamic random-access memory integrated circuits (DRAM ICs), in order to increase capacity, multiple DRAM ICs need to be connected and stacked via TSVs (through silicon vias). However, each stacked IC needs to know its rank location to correctly access the stacked DRAM rank. Summary of the Invention [Problem to be solved by the invention]

[0003] The present invention provides a chip rank identification circuit that can achieve chip rank identification by effectively using the TSV area. [Means for solving the problem]

[0004] The chip rank identification circuit of the present invention is suitable for detecting the rank of a chip. The chip rank identification circuit has a first contact and a second contact, and includes a detection circuit and an identification circuit. The detection circuit includes a first switching circuit, a resistance circuit, and a first control circuit. The first switching circuit is coupled to the first contact. The resistance circuit is coupled to the first switching circuit. The first control circuit is coupled to the first switching circuit and the second contact, and determines whether the chip is coupled to a post-stage chip based on a voltage at the second contact, and controls the first switching circuit to switch the resistance circuit to couple to the first contact or to couple the resistance circuit to a first operating voltage. The identification circuit is coupled to the resistance circuit, and determines the rank of the chip based on a reference voltage provided by the resistance circuit.

[0005] In one embodiment of the present invention, the detection circuit includes a third contact, a fourth contact, a second switching circuit, and a second control circuit, wherein the second control circuit is coupled to the second switching circuit and the fourth contact, and determines whether the chip is coupled to a pre-stage chip based on the voltage of the fourth contact, and controls the second switching circuit to switch the resistance circuit to be coupled to the third contact or to be coupled to the second operating voltage.

[0006] In one embodiment of the present invention, the identification circuit includes a voltage divider circuit, a selection circuit, and a determination circuit. The voltage divider circuit is coupled to the resistor circuit and divides a reference voltage to generate a first divided voltage. The selection circuit selects the reference voltage or the first divided voltage as an output signal based on the reference voltage, the first divided voltage, the first threshold voltage, and the second threshold voltage. The determination circuit determines the rank of the chip based on the output signal.

[0007] In one embodiment of the present invention, the selection circuit includes a first comparison circuit and a second comparison circuit. The positive and negative input terminals of the first comparison circuit are coupled to a first threshold voltage and a reference voltage. The positive and negative input terminals of the second comparison circuit are coupled to a second threshold voltage and a first divided voltage. The multiplexer circuit is coupled to the output terminals of the first comparison circuit and the second comparison circuit and outputs the reference voltage or the first divided voltage based on the comparison results of the first comparison circuit and the second comparison circuit. The determination circuit determines the rank of the chip based on the output signal.

[0008] In one embodiment of the present invention, the decision circuit includes a plurality of comparison circuits, a plurality of resistors, and a logic circuit. The positive input terminals of the plurality of comparison circuits receive the output signals. The plurality of resistors are connected in series between a first threshold voltage and ground, and a node between adjacent resistors is coupled to the negative input terminal of a corresponding comparison circuit. The logic circuit is coupled to the output terminals of the plurality of comparison circuits and the fourth contact, and outputs an identification signal indicating the rank of the chip based on the output voltages of the comparison circuits and the voltage of the fourth contact.

[0009] In one embodiment of the present invention, the resistance circuit includes a first resistor and a second resistor, the second resistor being connected in series with the first resistor between the first switching circuit and the second switching circuit, and a common node of the first resistor and the second resistor generating a reference voltage.

[0010] In one embodiment of the present invention, the first switching circuit is a multiplexer circuit, an input terminal of the multiplexer circuit is coupled to a first operating voltage and a first contact, an output terminal of the multiplexer circuit is coupled to the resistance circuit, and a control terminal of the multiplexer circuit is coupled to the first control circuit.

[0011] In one embodiment of the present invention, the first control circuit includes a transistor, a first terminal of which is coupled to the control terminal and the second contact of the multiplexer circuit, a second terminal of the transistor is coupled to ground, the control terminal of the transistor is controlled to be turned on by an enable signal, and the transistor generates a selection control signal based on the voltage of the first terminal of the transistor to control the multiplexer circuit to couple the resistance circuit to the first contact or the first operating voltage.

[0012] In one embodiment of the present invention, the second switching circuit is a multiplexer circuit, the input terminal of which is coupled to the second operating voltage and the third contact, the output terminal of the multiplexer circuit is coupled to the resistance circuit, and the control terminal of the multiplexer circuit is coupled to the second control circuit.

[0013] In one embodiment of the present invention, the second control circuit includes a transistor, a first terminal of which is coupled to the control terminal of the multiplexer circuit and the fourth contact, a second terminal of which is coupled to ground, the control terminal of which is controlled to be turned on by an enable signal, and the transistor generates a selection control signal based on the voltage of the first terminal of the transistor to control the multiplexer circuit to connect the resistance circuit to the third contact or the second operating voltage.

[0014] In one embodiment of the present invention, the third contact is directly or indirectly connected to the first upstream connection TSV.

[0015] In one embodiment of the present invention, the chip is coupled to the previous chip by a first previous-stage connection TSV.

[0016] In one embodiment of the present invention, the fourth contact is directly or indirectly connected to the second upstream TSV, and the chip is coupled to the upstream chip by the second upstream TSV.

[0017] In one embodiment of the present invention, the first contact is directly or indirectly connected to the first subsequent connection TSV.

[0018] In one embodiment of the present invention, the chip is coupled to the downstream chip by a first downstream connection TSV.

[0019] In one embodiment of the present invention, the second contact is directly or indirectly connected to a second downstream connection TSV, and the chip is coupled to the downstream chip by the second downstream connection TSV. [Effects of the Invention]

[0020] As described above, in an embodiment of the present invention, the first control circuit couples the resistance circuit to a first operating voltage or a first downstream-connecting TSV based on the connection status with the downstream chip. The second control circuit couples the resistance circuit to a second operating voltage or a first upstream-connecting TSV based on the connection status with the upstream chip. The identification circuit can determine the rank of the chip based on the reference voltage provided by the resistance circuit. In one embodiment of the present invention, only two TSVs are occupied between the two chips, thereby efficiently utilizing the TSV area and achieving chip rank identification.

[0021] In order to make the above features and advantages of the present invention more comprehensible, embodiments accompanied with drawings are described in detail below. [Brief explanation of the drawings]

[0022] [Figure 1] FIG. 2 is a schematic diagram of a chip rank identification circuit according to one embodiment of the present invention. [Figure 2] FIG. 2 is a schematic diagram of a chip rank identification circuit according to one embodiment of the present invention. [Figure 3] FIG. 1 is a schematic diagram of a resistor circuit of multiple chips coupled in series according to one embodiment of the present invention. [Figure 4] FIG. 1 is a diagram showing the relationship between chip rank and resistor size according to one embodiment of the present invention. [Figure 5] FIG. 2 is a schematic diagram of an identification circuit according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0023] FIG. 1 is a schematic diagram of a chip rank identification circuit according to one embodiment of the present invention. Referring to FIG. 1, a chip rank identification circuit 100 can be disposed in each chip in a chip stack, allowing each chip to automatically determine its chip rank. The chip rank identification circuit 100 can include a detection circuit 102 and an identification circuit 104. The detection circuit 102 has contacts CT1 to CT4 and can include a first switching circuit 106, a second switching circuit 108, a first control circuit 110, a second control circuit 112, and a resistance circuit 114. Because process structures for improving functionality or strengthening the structure may exist between the contacts and the TSVs, the contacts CT1, CT2, CT3, and CT4 are directly or indirectly connected to a first downstream connection TSV1, a second downstream connection TSV2, a first upstream connection TSV3, and a second upstream connection TSV4, respectively. The resistance circuit 114, the first switching circuit 106, and the second switching circuit 108 are coupled in series between contacts CT1 and CT3, the resistance circuit 114 is also coupled to the discrimination circuit 104, the first control circuit 110 is coupled to the first switching circuit 106 and contact CT2, and the second control circuit 112 is coupled to the second switching circuit 108 and contact CT4.

[0024] The first control circuit 110 determines whether the chip is coupled to a subsequent chip (i.e., whether a chip is stacked above the chip employing the chip rank identification circuit 100) based on the voltage of the second subsequent-connection TSV2, and can control the first switching circuit 106 to switch the resistance circuit 114 to be coupled to the first subsequent-connection TSV1 to couple to the resistance circuit of the subsequent chip, or to couple the resistance circuit 114 to the first operating voltage VCCP. For example, when the voltage of the second subsequent-connection TSV2 is the first preset voltage, the first control circuit 110 determines that the second subsequent-connection TSV2 is coupled to the subsequent chip, and can control the first switching circuit 106 to switch the resistance circuit 114 to be coupled to the first subsequent-connection TSV1 to couple to the resistance circuit of the subsequent chip. On the other hand, when the voltage of the second subsequent-connection TSV2 is not the first preset voltage, it can determine that the chip employing the chip rank identification circuit 100 is the top chip. At this time, the first control circuit 110 controls the first switching circuit 106 to switch the resistance circuit 114 to be coupled to the first operating voltage VCCP.

[0025] Similarly, the second control circuit 112 determines whether the chip is coupled to a previous-stage chip based on the voltage of the second previous-stage connection TSV4 (i.e., determines whether the chip employing the chip rank identification circuit 100 is stacked above the previous-stage chip), and controls the second switching circuit 108 to switch the resistance circuit 114 to be coupled to the first previous-stage connection TSV3 to couple to the resistance circuit of the previous-stage chip, or to be coupled to the second operation voltage VSS. Here, the second operation voltage VSS may be, for example, a ground voltage, but the present invention is not limited thereto. For example, when the voltage of the second previous-stage connection TSV4 is the second preset voltage, the second control circuit 112 determines that the second previous-stage connection TSV4 is coupled to the previous-stage chip, and controls the second switching circuit 108 to switch the resistance circuit 114 to be coupled to the first previous-stage connection TSV3 to couple to the resistance circuit of the previous-stage chip. On the other hand, if the voltage of the second upstream-connecting TSV4 is not the second preset voltage, it can be determined that the chip employing the chip rank identification circuit 100 is the bottom chip. At this time, the second control circuit 112 controls the second switching circuit 108 to switch the resistance circuit 114 to couple to the second operating voltage VSS.

[0026] The resistor circuit 114 can generate a reference voltage Vref1 for the identification circuit 104 that corresponds to the stacking status of the chip that employs the chip rank identification circuit 100 and other chips, and the identification circuit 104 can determine the rank of the chip that employs the chip rank identification circuit 100 based on this reference voltage Vref1.

[0027] More specifically, the chip rank identification circuit 100 may be implemented as shown in FIG. 2. The first switching circuit 106 and the second switching circuit 108 may be implemented as multiplexer circuits MUX1 and MUX2, respectively, and the first control circuit 110 and the second control circuit 112 may be implemented as transistors M1 and M2, respectively. The resistance circuit 114 may include, for example, resistors RD1 and RD2. Resistors RD1 and RD2 may have the same resistance value, but the present invention is not limited thereto.

[0028] An input terminal of the multiplexer circuit MUX1 is coupled to the first operating voltage VCCP and the first downstream connection TSV1. One end of the transistor M1 is coupled to the second downstream connection TSV2 and the control terminal of the multiplexer circuit MUX1. The other end of the transistor M1 is coupled to ground. The control terminal of the transistor M1 is controlled to be turned on by an enable signal VEN1. The transistor M1 generates a selection control signal for controlling the multiplexer circuit MUX1 at one end coupled to the second downstream connection TSV2, and controls the multiplexer circuit MUX1 to connect the resistor circuit 114 to the first downstream connection TSV1 or the first operating voltage VCCP. Resistors RD1 and RD2 are coupled in series between the output terminal of the multiplexer circuit MUX1 and the output terminal of the multiplexer circuit MUX2. A common node of the resistors RD1 and RD2 is coupled to the identification circuit 104. An input terminal of the multiplexer circuit MUX2 is coupled to the second operating voltage VSS and the first upstream connection TSV3, one end of the transistor M2 is coupled to the second upstream connection TSV4 and the control terminal of the multiplexer circuit MUX2, and one end of the transistor M 2 The other end of the transistor M1 is coupled to ground, and the control terminal of the transistor M2 is controlled to be turned on by an enable signal VEN2, and the transistor M2 generates a selection control signal for controlling the multiplexer circuit MUX2 at one end coupled to the second upstream connection TSV4, and can control the multiplexer circuit MUX2 to connect the resistance circuit 114 to the first upstream connection TSV3 or the second operating voltage VSS.

[0029] When the transistor M1 is in a conductive state and the second downstream-connection TSV2 is coupled to the downstream chip, the multiplexer circuit MUX1 is controlled by detecting the first preset voltage upVDD from the downstream chip via the second downstream-connection TSV2 and selects the first downstream-connection TSV1 to connect to the resistor circuit 114, but when the second downstream-connection TSV2 is not coupled to the downstream chip, the multiplexer circuit MUX1 is controlled by detecting the ground voltage (or a floating voltage) and selects the first operating voltage VCCP to connect to the resistor circuit 114. Similarly, when the transistor M2 is in a conductive state and the second upstream connection TSV4 is coupled to the upstream chip, the multiplexer circuit MUX2 is controlled by detecting the second preset voltage dnVDD from the upstream chip through the second upstream connection TSV4, and selects the first upstream connection TSV3 to be connected to the resistance circuit 114, but when the second upstream connection TSV4 is not coupled to the upstream chip, the multiplexer circuit MUX2 is controlled by detecting the ground voltage (or a floating voltage), and selects the second operation voltage VSS to be connected to the resistance circuit 114. In this way, the resistance circuit of each chip can output a reference voltage corresponding to its chip rank.

[0030] 3 shows an embodiment in which three chips are stacked (four chips in total), where the resistance circuit 114 of each chip includes two resistors R coupled in series, and the TSVs between the chips (including the first subsequent-stage connection TSV1 and the first subsequent-stage connection TSV3) have resistors Rtsv. Taking the case where the reference voltage Vref1 is output by the detection circuit 102-3 corresponding to chip rank 2 as an example, the voltage value of the reference voltage Vref1 can be expressed by the following equation (1):

[0031]

number

[0032] In particular, Rrank2 is the resistance corresponding to chip rank 2, and Rtotal is the sum of the resistances of the resistor circuits 114 of the four chips and the resistance of the TSVs between the chips. If VCCP is equal to 2.9 V, R is equal to 10 Ohms, and Rtsv is equal to 0.8 Ohms, then Vref1 is equal to 1.82 V. By analogy, the resistances Rrank0, Rrank1, and Rrank3 corresponding to chip ranks 0, 1, and 3 may be R, 3R+Rtsv, and 7R+3Rtsv, respectively, as shown in FIG. 4. In this way, the detection circuits 102-0 to 102-4 for different chip ranks can output reference voltages Vref1 having different voltage values, so that the identification circuit 104 of each chip can determine the rank of each chip based on the reference voltage Vref1 provided by the corresponding detection circuit 102. Also, as shown in FIG. 4, the number of stacked chips is not limited to that of the embodiment of FIG. 3. In other embodiments, fewer or more chips may be stacked, for example, one or seven chips.

[0033] Further, the identification circuit 104 may include a voltage divider circuit 202, a selection circuit 204, and a decision circuit 206, where the voltage divider circuit 202 is coupled to the resistance circuit 114 and the selection circuit 204, and the selection circuit 204 is coupled to the resistance circuit 114 and the decision circuit 206. The voltage divider circuit 202 may include n voltage divider resistor circuits. The first voltage divider resistor circuit divides the reference voltage Vref1 to generate a first divided voltage, and the nth voltage divider resistor circuit divides the n-1th divided voltage output by the n-1th voltage divider resistor circuit to generate an nth divided voltage, where n is an integer greater than 1. For example, in the embodiment of FIG. 2, the voltage divider circuit 202 includes voltage divider resistor circuits 210 and 212. The voltage divider resistor circuit 210 includes resistors RD3 and RD4, and the voltage divider resistor circuit 212 includes resistors RD5 and RD6. Resistors RD3 and RD4 are coupled in series between the common junction of resistors RD1 and RD2 and ground, and resistors RD5 and RD6 are coupled in series between the common junction of resistors RD3 and RD4 and ground. Resistors RD3 and RD4 may have the same resistance value, but the present invention is not limited thereto. The voltage dividing resistor circuit 210 may divide the reference voltage Vref1 provided by the resistor circuit 114 to generate a first divided voltage Vref2, and the voltage dividing resistor circuit 212 may divide the first divided voltage Vref2 provided by the voltage dividing resistor circuit 210 to generate a second divided voltage Vref3.

[0034] The selection circuit 204 can select one of the reference voltage Vref1, the first divided voltage Vref2, and the second divided voltage Vref3 as the output signal VO1 based on the reference voltage Vref1, the first divided voltage Vref2, the first threshold voltage V1, and the second threshold voltage V2. In particular, in the embodiment of FIG. 3, the first threshold voltage V1 and the second threshold voltage V2 can be set to a voltage value between 0.634 and 0.816 V based on the operating voltage VCCP, the operating voltage VSS, the resistor R, and the resistor Rtsv. For example, the first threshold voltage V1 and the second threshold voltage V2 are set to 0.8 V, but the present invention is not limited thereto. The first threshold voltage V1 and the second threshold voltage V2 can be voltages provided by, for example, a bandgap voltage reference circuit. The determination circuit 206 can determine the rank of the chip based on the output signal VO1 and output an identification signal SC1.

[0035] Further, the selection circuit 204 may include comparison circuits CP1, CP2 and a multiplexer circuit 208, wherein the positive and negative input terminals of the comparison circuit CP1 are respectively coupled to a reference voltage Vref1 and a first threshold voltage V1, and the positive and negative input terminals of the comparison circuit CP2 are respectively coupled to a first divided voltage Vref2 and a second threshold voltage V2, and the comparison circuits CP1 and CP2 output The terminal is coupled to a selection control terminal of a multiplexer circuit 208. An input terminal of the multiplexer circuit 208 receives the reference voltage Vref1, the first divided voltage Vref2, and the second divided voltage Vref3. An output terminal of the multiplexer circuit 208 is coupled to the decision circuit 206.

[0036] The multiplexer circuit 208 can select one of the reference voltage Vref1, the first divided voltage Vref2, and the second divided voltage Vref3 as an output signal VO1 based on the comparison voltage VP1 output by the comparator circuit CP1 after comparing the reference voltage Vref1 with the first threshold voltage V1 and the comparison voltage VP2 output by the comparator circuit CP2 after comparing the first divided voltage Vref2 with the second threshold voltage V2. The decision circuit 206 can determine the chip rank based on the output signal VO1 and output an identification signal SC1 accordingly.

[0037] Furthermore, the decision circuit 206 may be implemented, for example, as shown in FIG. 5. The decision circuit 206 may include resistors R1 to R7, comparison circuits CPA to CPF, and a logic circuit 502. The positive input terminals of the comparison circuits CPA to CPF receive the output signal VO1 provided by the selection circuit 204, and the output terminals of the comparison circuits CPA to CPF are respectively coupled to input terminals A to F of the logic circuit 502. The resistors R1 to R7 are coupled in series between a power supply voltage VDD and ground. The common junction of two adjacent resistors is coupled to the negative input terminal of the corresponding comparison circuit CPA to CPF. The input terminal G1 of the logic circuit 502 is coupled to the junction of the second upstream connection TSV4 and receives the second preset voltage dnVDD. When seven chips (a total of eight chips) or less are stacked, the logic circuit 502 may use, for example, a 3-bit signal as the identification signal SC1. The bit value CID of the identification signal SC1 is: <0> , C.I.D. <1> , and C.I.D. <2> may be as shown in the following formulas (2) to (4).

[0038]

number

[0039] In this way, the chip rank identification circuit 100 of each chip provides an identification signal SC1 indicating the chip rank, thereby effectively achieving chip rank identification.

[0040] As described above, in an embodiment of the present invention, the first control circuit couples the resistance circuit to a first operating voltage or a first downstream-connecting TSV based on the connection status with the downstream chip. The second control circuit couples the resistance circuit to a second operating voltage or a first upstream-connecting TSV based on the connection status with the upstream chip. The identification circuit can determine the rank of the chip based on the reference voltage provided by the resistance circuit. In one embodiment of the present invention, only two TSVs are occupied between the two chips, thereby efficiently utilizing the TSV area and achieving chip rank identification. [Industrial Applicability]

[0041] The chip rank identification circuit of the present invention can be applied to a DRAM IC. [Explanation of symbols]

[0042] 100 Chip rank identification circuit 102, 102-0 to 102-4 detection circuit 104 Identification circuit 106 First switching circuit 108 Second switching circuit 110 First control circuit 112 Second control circuit 114 Resistance circuit 202 Voltage divider circuit 204 Selection circuit 206 Judgment circuit 210, 212 voltage divider resistor circuit 502 Logic Circuit CT1~CT4 contacts TSV1 First downstream connection TSV TSV2 Second downstream connection TSV TSV3 1st front-end connection TSV TSV4 2nd front-end connection TSV VCCP First operating voltage VSS Second operating voltage VP1, VP2 comparison voltage Vref1 reference voltage MUX1, MUX2, 208 multiplexer circuit M1 and M2 transistors RD1~RD6 resistor VEN1, VEN2 enable signals upVDD First preset voltage dnVDD Second preset voltage R, Rtsv, R1~R7 resistor Vref2, Vref3 divided voltage V1, V2 threshold voltage SC1 identification signal CP1, CP2, CPA~CPF comparison circuit VDD Power supply voltage A1~G1 input terminals

Claims

1. A chip rank identification circuit suitable for detecting the rank of a chip, comprising: a detection circuit having a first contact and a second contact, the detection circuit comprising: a first switching circuit coupled to the first contact; a resistor circuit coupled to the first switching circuit; a first control circuit coupled to the first switching circuit and the second contact, for determining whether the chip is coupled to a subsequent chip based on a voltage at the second contact, and for controlling the first switching circuit to switch the resistor circuit to be coupled to the first contact or to be coupled to a first operating voltage; an identification circuit coupled to the resistor circuit and determining the rank of the chip based on a reference voltage provided by the resistor circuit; a chip rank identification circuit including:

2. The detection circuit A third contact point; A fourth contact point; a second switching circuit; a second control circuit coupled to the second switching circuit and the fourth contact, for determining whether the chip is coupled to a previous chip based on a voltage at the fourth contact, and for controlling the second switching circuit to switch the resistor circuit to be coupled to the third contact or to be coupled to a second operating voltage; 2. The chip rank identification circuit according to claim 1, comprising:

3. The identification circuit a voltage divider circuit coupled to the resistor circuit and configured to divide the reference voltage to generate a first divided voltage; a selection circuit that selects the reference voltage or the first divided voltage as an output signal based on the reference voltage, the first divided voltage, a first threshold voltage, and a second threshold voltage; a determination circuit that determines the rank of the chip based on the output signal; 3. The chip rank identification circuit according to claim 2, comprising:

4. The selection circuit a first comparison circuit having its positive and negative input terminals coupled to said reference voltage and said first threshold voltage, respectively; a second comparison circuit having its positive and negative input terminals coupled to the first divided voltage and the second threshold voltage, respectively; a multiplexer circuit coupled to the output terminals of the first comparison circuit and the second comparison circuit, for outputting the reference voltage or the first divided voltage based on the comparison results of the first comparison circuit and the second comparison circuit, and for the determination circuit to determine the rank of the chip based on the output signal; 4. The chip rank identification circuit according to claim 3, comprising:

5. The determination circuit a plurality of comparator circuits whose positive input terminals receive the output signals; a plurality of resistors coupled in series between the first threshold voltage and ground, with nodes between adjacent resistors coupled to negative input terminals of corresponding comparator circuits; a logic circuit coupled to the output terminal of the comparison circuit and the fourth contact, and adapted to output an identification signal indicating the rank of the chip based on the output voltage of the comparison circuit and the voltage at the fourth contact; 4. The chip rank identification circuit according to claim 3, comprising:

6. The resistor circuit is a first resistor; a second resistor coupled in series with the first resistor between the first switching circuit and the second switching circuit; 3. The chip rank identification circuit of claim 2, further comprising: a common junction of the first resistor and the second resistor to generate the reference voltage.

7. 2. The chip rank identification circuit of claim 1, wherein the first switching circuit is a multiplexer circuit, an input terminal of which is coupled to the first operating voltage and the first contact point, an output terminal of which is coupled to the resistance circuit, and a control terminal of which is coupled to the first control circuit.

8. 8. The chip rank identification circuit of claim 7, wherein the first control circuit includes a transistor having a first terminal coupled to the control terminal of the multiplexer circuit and the second contact point, a second terminal of the transistor coupled to ground, the control terminal of the transistor being controlled to be turned on by an enable signal, and the transistor generating a selection control signal based on the voltage of the first terminal of the transistor to control the multiplexer circuit to couple the resistance circuit to the first contact point or the first operating voltage.

9. 3. The chip rank identification circuit of claim 2, wherein the second switching circuit is a multiplexer circuit, an input terminal of which is coupled to the second operating voltage and the third contact, an output terminal of which is coupled to the resistance circuit, and a control terminal of which is coupled to the second control circuit.

10. 10. The chip rank identification circuit of claim 9, wherein the second control circuit includes a transistor having a first terminal coupled to the control terminal of the multiplexer circuit and the fourth contact point, a second terminal of the transistor coupled to ground, the control terminal of the transistor being controlled to be turned on by an enable signal, and the transistor generating a selection control signal based on the voltage of the first terminal of the transistor to control the multiplexer circuit to couple the resistance circuit to the third contact point or the second operating voltage.

11. The chip rank identification circuit according to claim 2 , wherein the third contact point is directly or indirectly connected to a first upstream connection TSV.

12. The chip rank identification circuit according to claim 11 , wherein the chip is coupled to a previous chip by the first previous-stage connection TSV.

13. 13. The chip rank identification circuit according to claim 12, wherein the fourth contact is directly or indirectly connected to a second upstream connection TSV, and the chip is coupled to the upstream chip by the second upstream connection TSV.

14. The chip rank identification circuit according to claim 2 , wherein the first contact point is directly or indirectly connected to a first subsequent-stage connecting via.

15. The chip rank identification circuit according to claim 14 , wherein the chip is coupled to a subsequent chip by the first subsequent connection TSV.

16. 16. The chip rank identification circuit according to claim 15, wherein the second contact is directly or indirectly connected to a second downstream connection TSV, and the chip is coupled to the downstream chip by the second downstream connection TSV.

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