Pixel circuit and method for vision sensor

Abstract

A pixel circuit for use in an image sensor is provided. The pixel circuit includes a photosensitive element configured to generate a current signal in response to the intensity of light incident on the photosensitive element, and a converter configured to receive the current signal from the photosensitive element and generate a voltage signal based on the received current signal. The pixel circuit also includes a capacitor electrically coupled in series with the converter and configured to receive the voltage signal from the converter, and an amplifier electrically coupled in series with the capacitor at an input and configured to generate an amplified signal at an output based on the output signal from the capacitor, where there is no feedback between the amplifier's output and input. The pixel circuit further includes a reset device configured to reset the amplifier in response to generation of a trigger signal.

Description

[Technical Field]

[0001] This application claims priority to U.S. Provisional Patent Application No. 63 / 004,110, filed April 2, 2020, the contents of which are incorporated herein by reference in their entirety.

[0002] The present disclosure relates generally to the field of sensors and pixel circuits for sensing. More specifically, but not by way of limitation, the present disclosure relates to systems and methods for providing pixel circuits and architectures, and systems and methods for implementing and using vision sensors having pixel circuits. The sensors and techniques disclosed herein can be used in a variety of applications and vision systems, such as security systems, autonomous vehicles, and other systems that benefit from fast and efficient motion detection and / or motion event-driven data acquisition. [Background technology]

[0003] Current image sensors use multiple pixels comprising a semiconductor charge-coupled device (CCD), complementary metal-oxide semiconductor (CMOS) sensor, n-type metal-oxide semiconductor (NMOS) sensor, or other sensor to capture a digital image of a scene. However, traditional image sensors take a long time to detect sudden motion because each frame is captured as a full image of the scene. Furthermore, such image sensors generate large amounts of data, exponentially increasing the amount of processing required to sift through the captured images for, for example, motion information.

[0004] Many systems do not require the vast amount of detail provided by existing image sensors that capture full images. For example, security and other surveillance systems may only be interested in data related to motion, and not in static portions of the image. As another example, autonomous vehicles must process captured data quickly and efficiently to make decisions comparable to human perception times (typically around 100 milliseconds or less). Such efficiency is limited if large amounts of data must be discarded (e.g., by post-processing) to obtain the portions of the captured data that are relevant to the situation. Summary of the Invention

[0005] An embodiment of the present disclosure may provide a sensor including a plurality of pixels, each pixel comprising: a photosensitive element configured to generate a current signal in response to an intensity of light incident on the photosensitive element; a converter configured to receive the current signal from the photosensitive element and generate a voltage signal based on the received current signal; a capacitor electrically coupled in series with the converter and configured to receive the voltage signal from the converter; an amplifier electrically coupled in series with the capacitor at an input and configured to generate an amplified signal at an output based on the output signal from the capacitor, where no feedback exists between the output and the input of the amplifier; and a reset device electrically coupled between the input and the output of the amplifier and configured to reset the amplifier in response to generation of a trigger signal.

[0006] In some embodiments, the sensor comprises at least one temporal contrast sensor, also referred to as a contrast detection sensor or dynamic vision sensor. Furthermore, the amplifier may have a defined gain, and in some embodiments, the amplifier comprises a controlled-gain amplifier. In some embodiments, the gain of the amplifier may be controllable or adjustable, while in other embodiments, the gain of the amplifier is neither controllable nor adjustable. In some embodiments, the gain of the amplifier may be defined by the number of stacked transistors in the amplifier, which is not adjustable. In other embodiments, the gain of the amplifier is controllable by switching in or out stacked transistors. In some embodiments, the gain of the amplifier is controllable by switching in or out amplifier stages as disclosed herein.

[0007] As disclosed herein, an amplifier embodiment may include a controlled gain amplifier. The controlled gain amplifier may include a plurality of stacked transistors. In some embodiments, the plurality of stacked transistors includes a transistor, the gate of which is electrically coupled to the drain or source of the transistor. One or more of such transistors may be used to implement the plurality of stacked transistors.

[0008] In some embodiments, the open loop gain of the amplifier is related to a number related to the number of stacked transistors. By way of example, in some embodiments, the gain of the amplifier is less than 10. In other embodiments, the gain is 10 or greater. In other embodiments, the gain of the amplifier is 20 or greater and 40 or less. In still further embodiments, the gain of the amplifier is less than 100. Furthermore, in some embodiments, the amplifier is implemented as a multi-stage amplifier, as disclosed herein.

[0009] In some embodiments, the pixel further comprises a comparator electrically coupled to the output of the amplifier and configured to generate a trigger signal when the amplified signal meets a condition, hi some embodiments, the condition includes the magnitude of the amplified signal being greater than or equal to a threshold value.

[0010] In some embodiments, the reset device includes a switch. As disclosed herein, the reset device may be configured to reset a voltage between the input and output of the amplifier by closing the switch. The reset device may be further configured to reset the amplifier by setting the voltage between the input and output of the amplifier to zero.

[0011] In some embodiments, the pixel further comprises a comparator electrically coupled to the output of the amplifier and configured to generate a trigger signal when the amplified signal meets a condition. In some embodiments, the comparator is configured to output the trigger signal to an external readout system. The external readout system may be configured to send an acknowledge signal to the pixel in response to the trigger signal. In some embodiments, the reset device may be configured to reset the amplifier in response to receiving the acknowledge signal. In other embodiments, the reset device may be configured to reset the amplifier after providing the trigger signal as an output to the external readout system. That is, the pixel does not need to receive an acknowledge signal from the external readout system to reset itself.

[0012] Consistent with embodiments of the present disclosure, each pixel may include another capacitor electrically coupled in series between the output of the amplifier and the input of the comparator, and another reset device electrically coupled between the input of the comparator and a reference signal and configured to set the reference signal as the input of the comparator. In some embodiments, the another reset device includes another switch. In some embodiments, the another reset device is further configured to set the reference signal as the input of the comparator by closing the another switch. In some embodiments, the reset device includes a switch that is different from the another switch of the another reset device.

[0013] In some embodiments, the reference signal comprises a reference voltage.

[0014] Consistent with embodiments of the present disclosure, each pixel may include a delay circuit electrically coupled between the switch and another switch and configured to set a time delay between operating the switch and another switch (e.g., a time delay between operating a first switch and a second switch). As will be understood from the present disclosure, the number of switches is not limited to the examples provided herein.

[0015] Embodiments of the present disclosure may also provide a pixel circuit for use in a vision sensor, the pixel circuit including: a photosensitive element configured to generate a current signal in response to a brightness of light incident on the photosensitive element; a converter configured to receive the current signal from the photosensitive element and generate a voltage signal based on the received current signal; a capacitor electrically coupled in series with the converter and configured to receive the voltage signal from the converter; an amplifier electrically coupled in series with the first capacitor at an input and configured to generate an amplified signal at an output based on the output signal from the capacitor, the amplifier having no feedback between the output and the input; and a reset device electrically coupled between the input and the output of the amplifier and configured to reset the amplifier when a trigger signal is generated.

[0016] An embodiment of the present disclosure may further provide a method for controlling a sensor having a plurality of pixels, the method including: receiving a current signal in response to light incident on a photosensitive element, converting the current signal to a voltage signal based on the current signal, generating an isolated voltage signal by a capacitor based on the voltage signal, the isolated voltage signal being isolated from the current signal, generating an amplified signal by an amplifier based on the isolated voltage signal, where no capacitive feedback exists between the amplified signal and the isolated voltage signal, generating a trigger signal when the amplified signal meets a condition, and resetting the amplifier when the trigger signal is generated.

[0017] The accompanying drawings that constitute a part of this specification illustrate various embodiments and, together with the description, serve to explain the principles and features of the disclosed embodiments. [Brief explanation of the drawings]

[0018] [Figure 1A] FIG. 2 is a schematic diagram of an exemplary superpixel, according to an embodiment of the present disclosure. [Figure 1B] FIG. 2 is a schematic diagram of another exemplary superpixel, according to an embodiment of the present disclosure. [Figure 1C] FIG. 10 is a schematic diagram of yet another exemplary superpixel, according to an embodiment of the present disclosure. [Figure 1D] FIG. 10 is a schematic diagram of yet a further exemplary superpixel, according to an embodiment of the present disclosure. [Figure 2] FIG. 2 is a schematic diagram of an exemplary pixel circuit according to an embodiment of the present disclosure. [Figure 3] FIG. 2 is a schematic diagram of another exemplary pixel circuit, according to an embodiment of the present disclosure. [Figure 4A] FIG. 1 is a schematic diagram of an exemplary amplifier, according to an embodiment of the present disclosure. [Figure 4B] FIG. 1 is a schematic diagram of another exemplary amplifier, according to an embodiment of the present disclosure. [Figure 4C]FIG. 1 is a schematic diagram of an exemplary amplifier with adjustable open-loop gain, in accordance with an embodiment of the present disclosure. [Figure 4D] FIG. 10 is a schematic diagram of yet another exemplary amplifier having adjustable open-loop gain, in accordance with an embodiment of the present disclosure. [Figure 4E] FIG. 1 is a schematic diagram of an exemplary amplifier having an adjustable amplifier stage, in accordance with an embodiment of the present disclosure. [Figure 5] 4 is an exemplary signal timing diagram for the pixel circuit of FIG. 3 in accordance with an embodiment of the present disclosure. [Figure 6] 1 is a flowchart of an exemplary method for controlling an image sensor, according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0019] The disclosed embodiments relate to systems and methods for vision sensing, including asynchronous, time-based sensing. The disclosed embodiments relate to pixels and pixel circuits, as well as the implementation and use of vision sensors having such pixels and pixel circuits. Advantageously, exemplary embodiments can provide fast and efficient sensing. Further advantages of the embodiments include the ability to optimally use advanced semiconductor manufacturing process technologies to implement vision sensors with competitive pixel sizes. Furthermore, embodiments of the present disclosure can be implemented and used in a variety of applications and vision systems, such as security systems, autonomous vehicles, and other systems that benefit from fast and efficient motion or event detection. While embodiments of the present disclosure are described with general reference to vision systems, it will be understood that such systems may be part of a camera, LIDAR, or other sensor system.

[0020] In current image or video processing systems, an image sensor may acquire and process visual information to reconstruct an image. The image or video acquisition and processing system may include an array of optical sensors, each of which may acquire visual information to reconstruct an image representation of a visual scene. This process may be repeated at a predetermined pace.

[0021] Event-based vision sensors track the temporal evolution of relative light changes by detecting temporal contrasts above a predetermined relative threshold for each pixel (contrast detection, CD; temporal contrast, TC) and can define sampling points for frame-free pixel-level measurements of absolute intensity (exposure measurement, EM). Vision sensors have become popular in high-speed, low-power machine vision applications due to their temporal precision in recorded data, their inherent suppression of temporal redundancy, which reduces post-processing costs, and their wide dynamic range within a scene. Information about temporal contrast (TC) can be encoded in the form of "events": data packets containing the original pixel's X and Y coordinates, a timestamp, and contrast polarity. To maximize the benefit of individual pixels' ability to sample visual information with high temporal precision, early timestamps and high readout throughput can be important to preserve the timing of events.

[0022] In some embodiments, for real-time artificial vision (also referred to as "computer vision" or "machine vision"), a vision acquisition and processing system may be configured to acquire and process only data representing changes in current visual information relative to previously acquired visual information. Such sensors or vision systems may not generate frames of images. Such vision sensors may include, for example, temporal contrast (TC) sensors, also known as contrast detection (CD) sensors, or dynamic vision sensors (DVS). Such sensors are referred to in this disclosure as "event-based vision sensors" or generally as "vision sensors."

[0023] For example, TC sensors do not record images frame by frame, as current imaging systems do. Instead, each pixel in a TC sensor can determine the time derivative of the light it senses. In some embodiments, the pixel can optionally perform further processing on the time derivative. When the time derivative exceeds a preset threshold, the pixel can generate an "event" by outputting a signal. With short latency, the pixel can further transmit data related to the event. In some embodiments, the transmitted data can include the location (e.g., x and y coordinates) of the pixel located within the TC sensor (e.g., having a two-dimensional pixel matrix). In some embodiments, the transmitted data can include a sign bit representing the polarity (e.g., positive or negative sign) of the temporal evolution of the light intensity sensed by the pixel. In some embodiments, the transmitted data can include a timestamp of the occurrence of the event. In some embodiments, the transmitted data of a pixel can include a flow of (x, y, s) values, where x and y represent the coordinates of the pixel and s represents the polarity. The value of s can represent a relative change in light intensity detected by the pixel, where the value of s can represent the magnitude of the change and the sign of s can represent the direction of the change (e.g., increase or decrease). In some embodiments, the pixel circuits of the TC sensor can operate asynchronously, where the pixel circuits of the TC sensor are typically not quantized (e.g., not clocked) with respect to a time base. In other embodiments, the pixel circuits of the TC sensor can operate synchronously, where the pixel circuits of the TC sensor are quantized (e.g., clocked) with respect to a time base.

[0024] As mentioned above, a vision sensor may include a contrast detection (CD) sensor or a temporal contrast (TC) sensor, also known as a dynamic vision sensor (DVS). Vision sensors can be implemented in many different ways, with or without exposure metering (EM) and with or without other operations or components, including an analog-to-digital converter (ADC). The number of components can also vary (e.g., one EM vs. multiple EMs), and the locations of the components can also vary (e.g., inside vs. outside the pixel). Furthermore, the components can operate asynchronously or synchronously, or have a combination of both. The specific arrangement and type of operation often depends on the application and requirements of the vision sensor.

[0025] Embodiments of the present invention provide pixel circuits and features that can be advantageously used in any vision sensor. By way of example, and not limitation, a vision sensor implemented with a TC sensor having a two-dimensional pixel matrix can incorporate embodiments of the present invention and its associated features. As a further example, a vision sensor using superpixels can incorporate embodiments of the present invention and its associated features. An exemplary superpixel is described below with reference to FIGS. 1A-1D. It will be understood that the following description of a superpixel is merely exemplary, and that other forms of vision sensors can be utilized with embodiments of the present invention. Indeed, as noted above, embodiments of the present invention can be advantageously incorporated into any type of vision sensor.

[0026] 1A is a schematic diagram of an exemplary superpixel 100A consistent with embodiments of the present disclosure. In some embodiments, a superpixel may be larger and contain more components than a conventional "pixel" because it may contain two or more photosensitive elements, e.g., elements 101 and 103, as well as control and communication logic, such as condition detector 105, ADCs 109 and 111, 113, etc.

[0027] The photosensitive elements may include photodiodes (e.g., pn junctions or PIN structures) or any other elements configured to convert light into an electrical signal. Each photodiode (e.g., element 101 or element 103) generates a current (e.g., I) based on the intensity of light incident on the photodiode. ph ) can be generated. For example, a current I ph is generated proportional to the intensity of the light incident on the photodiode.

[0028] As shown in the example of FIG. 1A, the superpixel includes a synchronous unit 100a and an asynchronous unit 100b. The asynchronous unit 100b includes a photosensitive element 101 (PD CD , for example, a photodiode), and the synchronization unit 100a may include at least one photosensitive element 103 (PD EM , for example, a photodiode).

[0029] The asynchronous unit 100b may further include a condition detector 105 (CD). As shown in the example of FIG. 1A, the detector 105 detects whether the first photosensitive element 101 (PD CD ) and configured to generate a trigger signal (labeled "SET" in the example of FIG. 1A ) when an analog signal intensity of light incident on the first photosensitive element 101 matches a condition. For example, the condition may include whether the analog signal exceeds a threshold (e.g., a voltage level or a current level). The analog signal may include a voltage signal or a current signal.

[0030] The synchronization unit 100a may include an exposure measurement sub-pixel 107. The exposure measurement sub-pixel 107 is connected to the second photosensitive element 103 (PD EM ) may be configured to generate an analog measurement based on the intensity of light incident on the voltage signal V FDAlthough depicted as a , the analog measurements may alternatively comprise current signals. The synchronization unit 100a may further comprise an analog-to-digital converter (ADC) 109 for converting the analog measurements into digital data (labeled "dig pix data" in the example of FIG. 1A). The combination of the exposure measurement sub-pixel 107 and the ADC 109 may be referred to as an "exposure measurement circuit." The exposure measurement circuit thus measures the second photosensitive element 103 (PD EM ) and may be configured to convert an analog signal based on the intensity of light incident on the second photosensitive element 103 into a digital signal. Unlike the asynchronous unit 100b, which outputs based on the condition detected by the condition detector CD, the synchronous unit 100a may be clocked, for example, such that digital data is output from the ADC only according to a clock cycle. In some embodiments, the exposure measurement sub-pixel 107 may also be configured to convert an analog signal based on the intensity of light incident on the second photosensitive element 103 (PD EM ) may be clocked such that the signal from the analog input is converted to an analog signal only according to a clock cycle.

[0031] As further shown in FIG. 1A, upon detecting a condition, condition detector 105 (CD) may send a signal (labeled “set” in the example of FIG. 1A) to control logic 111, which forms part of asynchronous unit 100b. Control logic 111 may trigger a switch (not shown) and / or logic gate 113 (depicted as an “OR” gate in the example of FIG. 1A) to enable (or “power up,” as depicted in the example of FIG. 1A) ADC 109. As used herein, “enable” may refer to activation such that ADC 109 may perform conversions using input ADC control signals, ramp codes, etc. Thus, ADC control signals, ramp codes, etc. may be continuously input to ADC 109 for use when enabled.

[0032] The combination of control logic 111 and switches (not shown) and / or logic gates 113 may be referred to as a "logic circuit." Thus, the logic circuit may be electrically connected to detector 105 and the exposure measurement circuit and configured to enable the exposure measurement circuit (or, in particular, ADC 109 of the exposure measurement circuit) in response to a trigger signal (labeled "set" in the example of FIG. 1A) and to disable the exposure measurement circuit (or, in particular, ADC 109 of the exposure measurement circuit) once a digital signal (labeled "dig pix data") is read from the exposure measurement circuit. In some embodiments, the logic circuit may temporarily enable the exposure measurement circuit (or, in particular, ADC 109 of the exposure measurement circuit) such that the exposure measurement circuit (or, in particular, ADC 109 of the exposure measurement circuit) is automatically disabled after outputting the digital signal.

[0033] Thus, after reading out the digital data to an external readout system (not shown), ADC 109 may generate a reset signal (labeled "clear" in the example of FIG. 1A) that is sent to control logic 111. Control logic 111 may then trigger a switch (not shown) and / or logic gate 113 to disable (or "power down," as depicted in the example of FIG. 1A) ADC 109. As used herein, "disable" may refer to deactivation, such as when ADC 109 performs a conversion using an input ADC control signal, ramp code, etc. However, ADC control signal, ramp code, etc. may still be input to ADC 109 after disabling.

[0034] In some embodiments, the logic circuitry of control logic 111 may temporarily enable synchronization unit 100a (or, in particular, ADC 109 of synchronization unit 100a) so that synchronization unit 100a (or, in particular, ADC 109 of synchronization unit 100a) automatically disables itself after outputting the digital signal. For example, a reset signal (labeled "clear" in the example of FIG. 1A) may be sent from ADC 109 to the logic circuitry of control logic 111 after being enabled by the logic circuitry in response to a trigger signal (labeled "set" in the example of FIG. 1A) so that the logic circuitry is ready to receive a new "set" signal from condition detector 105.

[0035] As further shown in FIG. 1A , the condition detector 105 (CD) may communicate a trigger signal (labeled “Req” in the example of FIG. 1A ) to the external readout system. The condition detector 105 (CD) may then receive an acknowledge signal (labeled “Ack” in the example of FIG. 1A ) that is used to reset the condition detector 105 (CD) so that the condition is again detected and a trigger can be generated. In some embodiments, the external readout system may also send control signals to the exposure measurement subpixels 107 and / or the ADC 109. All communication with the external readout system may be governed by a protocol such as the Address-Event Expression (AER) protocol and / or may be governed by clock cycles. Thus, the external readout system may include an event readout system configured to asynchronously read data from the superpixels and / or a clocked readout system configured to read data from the superpixels during predetermined clock cycles.

[0036] 1A, external control can also be provided to a switch (not shown) and / or logic gate 113 (or control logic 111) to activate a readout. For example, if superpixel 100A does not return a readout after a threshold number of clock cycles (e.g., if a condition is not met after the threshold number of clock cycles), the external readout system can send a control signal to force a readout. Additionally or alternatively, the external readout system can operate in a standard frame mode such that a superpixel, or at least a group of superpixels (e.g., superpixel 100A), is triggered to capture a full or partial frame regardless of whether a condition is detected.

[0037] 1B is another exemplary superpixel 100B consistent with embodiments of the present disclosure. The superpixel 100B of FIG. 1B functions similarly to the superpixel 100A of FIG. 1A, but includes a switch 115 (S EM ) Thus, using an external control signal applied to switch 115, superpixel 100B of FIG. 1B can suppress exposure measurement subpixel 107 whenever ADC 109 is disabled.

[0038] FIG. 1C depicts yet another exemplary superpixel 100C consistent with embodiments of the present disclosure. The superpixel 100C of FIG. 1C functions similarly to the superpixel 100A of FIG. 1A, but further includes multiple exposure measurement subpixels, e.g., subpixels 107a, 107b, and 107c. While depicted with three exposure measurement subpixels, the embodiment depicted in FIG. 1C may be implemented with any number of subpixels paired with an ADC 109. Thus, the embodiment of FIG. 1C may enable more accurate data capture by, for example, averaging, summing, or otherwise combining measurements from multiple exposure measurement subpixels before converting the combined measurements to a digital signal. Additionally or alternatively, measurements from multiple exposure measurement subpixels may be converted to digital signals sequentially to achieve higher resolution.

[0039] FIG. 1D depicts yet another exemplary superpixel 100D consistent with embodiments of the present disclosure. The superpixel 100D of FIG. 1D functions similarly to the superpixel 100C of FIG. 1C, but further includes a latch 115. The latch 115 may include, for example, a switch (e.g., one or more transistors configured to function as a switch), one or more bits of static random access memory (SRAM), or the like. While depicted as separate from the ADC 109, in some embodiments, the latch 115 may include at least one latch of an n-bit latch provided in the ADC 109 (e.g., as described below with respect to the ADC 300 of FIG. 3A).

[0040] In one embodiment, a trigger signal (labeled "SET" in the example of FIG. 1D ) may cause activation of control logic 111 during the first cycle N−1. In response, control logic 111 may send an enable signal (labeled "POWER UP" in the example of FIG. 1D ) to ADC 109. In response, ADC 109 may begin converting analog signals from one or more exposure measurement subpixels (e.g., subpixels 107 a, 107 b, and 107 c) in the second cycle N. Furthermore, ADC 109 may set latch 115 and send a signal (labeled "CLEAR" in the example of FIG. 1D ) to control logic 111 at or before the start of cycle N, so that control logic 111 is ready to generate a new trigger signal at any time during cycle N. Thus, as depicted in the example of FIG. 12 and as further described below, a new exposure / conversion is already enabled in the third cycle N+1. Latch 115 is further connected to the readout system (e.g., via the "dig pixel data" bus depicted in FIG. 1D) to signal the readout system to perform a readout at the end of cycle N. Thus, when the readout system extracts the digital signal from ADC 109 at the end of cycle N, latch 115 can be cleared by ADC 109.

[0041] In another embodiment, rather than sending a “power-up” signal to ADC 109, control logic 111 may activate latch 115. In such an embodiment, ADC 109 may poll the state of latch 115 at the beginning of each cycle to determine whether to perform a conversion in that cycle. In an embodiment in which ADC 109 is disabled rather than continuously operating, ADC 109 may be disabled for the cycle if latch 115 is not activated at the beginning of that cycle. If ADC 109 polls latch 115 and latch 115 is enabled, ADC 109 may clear latch 115 and begin converting analog signals from one or more exposure measurement subpixels (e.g., subpixels 107 a, 107 b, 107 c). In such an embodiment, ADC 109 may also set an internal status bit to notify the readout system to perform a readout at the end of the cycle. After reading, ADC 109 may disable itself and, at the start of the next cycle, again poll latch 115 to determine whether to re-enable it for another cycle. Alternatively, ADC 109 may poll latch 115 before disabling to determine whether to remain enabled for another conversion or to disable it.

[0042] In another embodiment (not depicted in FIG. 1D ), latch 115 may be external to superpixel 100D. In such an embodiment, superpixel 100D may exclude control logic 111. Instead, detector 105 may activate latch 115 in response to a condition being met, and ADC 109 may continuously perform a conversion in each cycle. Thus, a readout system may use latch 115 to determine whether to perform a readout at the end of each cycle. Otherwise, the conversion performed by ADC 109 may be deleted without being readout. While such an embodiment may use additional power for each ADC cycle, superpixel 100D can be made smaller by eliminating control logic 111 and using a smaller array of external latches, such as latch 115.

[0043] In embodiments where latch 115 is external to superpixel 100D, latch 115 may be connected to superpixel 100D using at least one of a direct hardwire connection and one or more arbiters. For example, latch 115 may form part of an array of external latches such that one or more arbiters can associate the memory address of latch 115 with the address of a corresponding superpixel (e.g., superpixel 100D).

[0044] Although depicted with three exposure measurement subpixels (e.g., subpixels 107a, 107b, and 107c), the embodiment depicted in FIG. 1D may be implemented with any number of subpixels paired with ADC 109, e.g., one subpixel, two subpixels, four subpixels, etc.

[0045] 1A, 1B, 1C, and 1D may be arranged in one or more arrays to form one or more vision sensors. For example, a vision sensor may include multiple superpixels arranged in one or more rows and one or more columns with respective row and column clock circuits for reading out digital data from the ADC to an external readout system. In another example, the superpixels may be arranged in a star pattern with a clock circuit at each node of the star for reading out digital data from the ADC to an external readout system.

[0046] Current pixel circuits for vision sensors can be implemented using switched-capacitor amplifiers to amplify detected signals. The switched-capacitor amplifier can include a high-gain amplifier (e.g., having a gain of hundreds or thousands) electrically connected to a first capacitor at the input to the high-gain amplifier, and a feedback loop between the input and output of the high-gain amplifier, the feedback loop including a second capacitor. The gain of such a switched-capacitor amplifier generally depends on the ratio of the capacitance of the first capacitor to the capacitance of the second capacitor. To obtain the required amplification factor (e.g., on the order of 20), the first capacitor must be designed to have a much larger capacitance (e.g., 20 times larger) than the second capacitor, which itself must be designed according to minimum manufacturing size rules. Overall, this switched-capacitor amplifier arrangement places large demands on the size of the capacitors, limiting the possibility of reducing the area consumed by such pixel circuits in integrated circuit chip implementations.

[0047] For sensor manufacturing purposes, it would be advantageous to minimize the size of the capacitor in each pixel circuit. However, due to the size limitations of the first capacitor in the above approach, the switched-capacitor amplifier may not be able to be further miniaturized. Therefore, the space consumed by the pixel circuit may be too large to further increase the pixel density of the vision sensor. Some current solutions replace the switched-capacitor amplifier with a complex feedback loop. However, such an approach requires many components and limits the size and scalability of the pixel array. Furthermore, current solutions may have complex bias requirements in the pre-amplification stage, which may limit the dynamic range of the amplifier.

[0048] Embodiments of the present disclosure provide pixel circuits that enable optimal utilization of advanced semiconductor manufacturing process technologies to implement vision sensors with competitive pixel sizes, thereby significantly improving the scalability of the pixel circuits and reducing the circuit complexity. The inventive pixel circuits disclosed herein use a feedback-less configuration and an amplifier with a defined gain (which may or may not be adjustable), exemplary embodiments of which are provided in the following description.

[0049] The following described embodiments of pixel circuits using a feedback-less configuration and a defined-gain amplifier may be applied to any vision sensor. The circuits described in FIGS. 1A-1D provide examples of such vision sensors but do not impose any limitations on the types of vision sensors in which embodiments of the present disclosure may be implemented. Thus, as explained above, embodiments of the present disclosure may be applied to any vision sensor, regardless of whether such vision sensor uses superpixels (e.g., as described in FIGS. 1A-1D). Furthermore, embodiments of the present disclosure may be applied to any vision sensor, regardless of whether such vision sensor performs exposure measurements, whether such vision sensor operates synchronously or asynchronously, or whether such vision sensor uses an ADC or other components.

[0050] 2 is a schematic diagram of an exemplary pixel circuit 200 according to an embodiment of the present disclosure. In some embodiments, pixel circuit 200 may be implemented as part of a superpixel, such as that shown and described in FIGS. 1A-1D, by way of non-limiting example. Similar to pixel circuit 100A, pixel circuit 200 may be used in a vision sensor (e.g., a temporal contrast sensor).

[0051] The pixel circuit 200 may output data when a change occurs in the light intensity detected by the photodetector. As shown in FIG. 2, the pixel circuit 200 generates a current signal ("I") in response to the brightness of light incident thereon. ph The pixel circuit 200 also includes a photosensitive element (e.g., a photodetector, denoted "PD") that generates a voltage (denoted "V"). ph receives the current signal I ph Based on (e.g., proportionally or logarithmically) a voltage signal ("V PR The pixel circuit 200 may include a converter (e.g., a current-to-voltage converter, denoted "I / V") that generates a voltage (denoted "V"). The pixel circuit 200 may include a capacitor (C C ) and this capacitor is PRThe pixel circuit 200 receives a capacitor C C The CG amp further includes an amplifier, for example, a controlled gain amplifier (labeled "CG amp") electrically coupled in series with the C C The amplifier generates an amplified signal based on the output signal from the amplifier. While a controlled gain amplifier is shown in and described with respect to FIG. 2, it will be understood from this disclosure that this is a non-limiting example. In some embodiments, the gain of the amplifier may be controllable or adjustable, while in other embodiments, the gain of the amplifier is neither controllable nor adjustable. In some embodiments, the gain of the amplifier may be defined by the number of stacked transistors in the amplifier, which is not adjustable. In other embodiments, the gain of the amplifier is controllable by switching stacked transistors in and out. In some embodiments, the gain of the amplifier is controllable by switching amplifier stages in and out, as further disclosed herein.

[0052] The pixel circuit 200 may further include one or more comparators. For example, in FIG. 2, two comparators are shown, labeled “comp1” and “comp2.” Each comparator is electrically coupled to the output (“out”) of the CG amp. Each comparator generates a trigger signal when the amplified signal matches a condition. In some embodiments, the condition may include the magnitude of the amplified signal generated by the CG amp being equal to or greater than a threshold. For example, comp1 or comp2 may compare the amplified signal with a threshold and generate a trigger signal having a polarity (e.g., positive or negative) when the amplified signal is equal to or greater than the threshold. In some embodiments, the threshold may be preset to represent a minimum change required to define a detected event. When comp1 or comp2 outputs a trigger signal, it may represent that the change in light intensity detected by the PD exceeds the minimum change required to be defined as a detected event. In some embodiments, comp1 or comp2 may output the trigger signal to an external readout system (not shown in FIG. 2).

[0053] 2 includes comp1 and comp2, it should be noted that in some embodiments comp1 and comp2 may be external to pixel circuit 200. That is, such a pixel circuit may not include a comparator. For example, multiple such pixel circuits may be provided that share one or more comparators that are external to the pixel circuit.

[0054] The pixel circuit 200 further includes a reset device (labeled "S1" in FIG. 2) electrically coupled between the in and out terminals of the CG amp. The reset device S1 may reset the CG amp in response to the generated trigger signal. As shown in FIG. 2, S1 may include a switch. The voltage between the input ("in") and output ("out") of the CG amp may be reset by closing the switch of the reset device S1. In some embodiments, S1 may reset the CG amp by setting the voltage between the in and out terminals of the CG amp to zero. In some embodiments, when comp1 or comp2 outputs a trigger signal to an external readout system, the external readout system may send an acknowledge signal to the pixel circuit 200 in response to receiving the trigger signal. Upon receiving the acknowledge signal, the pixel circuit 200 may generate a reset signal (labeled "reset" in FIG. 2) to close the switch of the reset device S1 and reset the controlled gain amplifier CG amp. After resetting the CG amp, the pixel circuit 200 is ready to detect a new event. In some embodiments, when comp1 or comp2 outputs a trigger signal to an external readout system, the pixel circuit 200 may generate a reset to close the switch of the reset device S1 and reset the controlled gain amplifier CG amp, regardless of receiving an acknowledge signal. For example, the pixel circuit 200 may generate a reset substantially simultaneously with comp1 or comp2 outputting the trigger signal or within a predetermined time after comp1 or comp2 outputting the trigger signal.

[0055] As shown in FIG. 2, the pixel circuit 200 has no feedback (no capacitive feedback) between the out and in of the controlled gain amplifier CG amp (i.e., no capacitor is placed or connected between the output and input of the amplifier). Therefore, V PR The amplification does not rely on feedback configurations or capacitance ratios as required by the current solutions described above. Instead, the CG amp is designed as an amplifier with well-controlled and well-matched gain (e.g., on the order of 20), while allowing the ability to optimally use advanced semiconductor manufacturing process techniques to implement vision sensors with competitive pixel sizes.

[0056] In Figure 2, before the controlled gain amplifier CG amp is reset, the capacitor C C I ph The charge may be stored based on (e.g., proportionally or logarithmically related to) the instantaneous value of C C is V PR is disconnected from the in of the CG amp, and I ph The operating point of the CG amp can be set independently of the value of the capacitor C C Since is independent of the gain of the CG amp, it can be configured to have a much smaller size than the capacitors in current solutions such as those described above. In this way, the overall size of the pixel circuit 200 can be significantly reduced, and the pixel density of the vision sensor can be significantly increased.

[0057] In some embodiments, before being provided as an input to a comparator (e.g., comp1 or comp2), the amplified signal generated by the controlled gain amplifier CG amp may be conditioned to suppress charge injection effects that may be caused, for example, by parasitic parameters (e.g., stray capacitance) associated with transistors or interconnect wires. To this end, in some embodiments, another capacitor may be placed between the out of CG amp and the input of the comparator, as further described below with reference to FIG.

[0058] 3 is a schematic diagram of an exemplary pixel circuit 300, according to an embodiment of the present disclosure. Pixel circuit 300 may be similar to pixel circuit 200 described above. However, compared to pixel circuit 200, pixel circuit 300 includes another capacitor C electrically coupled in series between the output of CG amp and the inputs (labeled "inc") of the comparators (e.g., comp1 and comp2). X Includes: C X The capacitance of C can be any value. X The capacitance of the capacitor can be configured to be small, thereby reducing its size.

[0059] The pixel circuit 300 also includes another reset device S2. As shown in FIG. 3, S2 includes a switch electrically coupled between inc and a reference signal, such as a reference voltage signal (labeled "vref" in FIG. 3). In some embodiments, S1 and S2 may be implemented differently (e.g., with different switches). When the CG amp is reset, S2 may be electrically switched to reset inc to vref. For example, if the reset device S2 is a switch, the switch of S2 may be closed to reset inc to vref. In some embodiments, vref may be configured to correspond to the input requirements of the comparators comp1 and comp2.

[0060] C X By including S1 and S2, the voltage headroom and dynamic range of the pixel circuit 300 may be optimized. The design of the pixel circuit 300 may also reduce the charge injection effect on the in of the CG amp caused by S1, especially when S1 is a single CMOS transistor.

[0061] In some embodiments, S1 may be electrically reset before S2 to better suppress charge injection effects into the amplifier input node. To do so, the pixel circuit 300 may include a delay circuit (e.g., labeled "Delay" in FIG. 3) electrically coupled between the reset devices S1 and S2. The delay circuit may set a time delay between the delivery of switching signals to S1 and S2. In some embodiments, for each reset switching operation, S1 may be released (thus completing its reset operation) slightly before S2. An example of this sequence is further described below with reference to FIG. 5.

[0062] In some embodiments, the CG amp may be an amplifier configured with a particular gain. For example, the particular gain may be a negative gain (e.g., −1, −5, −10, −20, −30, etc.). In some embodiments, the gain of the CG amp may vary during operation. In some embodiments, the CG amp may be implemented using multiple stacked transistors and / or multiple stages of circuitry connected in series to achieve higher gain. Exemplary embodiments of the CG amp are described further below.

[0063] 4A-4B show schematic representations of exemplary amplifiers 400A and 400B according to embodiments of the present disclosure. FIGS. 4C-4D show schematic diagrams of exemplary amplifiers 400C and 400D with adjustable open-loop gain according to embodiments of the present disclosure. As shown in FIGS. 4A-4D, amplifiers 400A-400D include multiple stacked transistors represented by M1, M2, M3, and M4. In FIGS. 4A-4D, M2 and M3 are diode-connected, with M2 having its gate electrically coupled to its drain and M3 having its gate electrically coupled to its drain. In amplifiers 400A and 400C, M2 and M3 may be NMOS-type transistors, and M 1 and M4 may be PMOS type transistors. In amplifiers 400B and 400D, M2 and M3 may be PMOS type transistors, and M1 and M4 may be NMOS type transistors.

[0064] In FIG. 4A , a bias voltage (labeled “bias”) may be used to adjust the input voltage level (labeled “in”) of amplifier 400A. For example, the input voltage level may be adjusted to be equal to the output voltage (labeled “out”) at the operating point of amplifier 400A. In some embodiments, the open-loop gain of amplifier 400A may be related to the number of stacked transistors. For example, in FIG. 4A , there are four stacked transistors. The gain of amplifier 400A is the number of stacked transistors minus one (i.e., amplifier 400A has a gain having a magnitude of 3 in FIG. 4A ). In some embodiments, a larger open-loop gain may be achieved by using more stacked diode-connected transistors or by connecting multiple stages of amplifiers similar to amplifier 400A in series. The open-loop gain of amplifier 400A may be configured to be any number in the manner described above. In some embodiments, the open-loop gain of amplifier 400A may have a magnitude less than 100 (e.g., less than 90, less than 80, less than 70, etc.). For example, in some embodiments, the magnitude of the amplifier gain is greater than or equal to 20 and less than or equal to 40. By way of further example, in some embodiments, the magnitude of the amplifier gain is less than 10. In other embodiments, the magnitude of the amplifier gain is greater than or equal to 10. In still further embodiments, the magnitude of the amplifier gain is less than or equal to 1.

[0065] In the example controlled gain amplifier 400B of FIG. 4B, a bias voltage (labeled “bias”) may be used to adjust the input voltage level (labeled “in”) of amplifier 400B. For example, the input voltage level may be adjusted to equal the output voltage (labeled “out”) at the operating point of amplifier 400B. In some embodiments, similar to amplifier 400A, the open-loop gain of amplifier 400B may be related to the number of stacked transistors. For example, in FIG. 4B, there are four stacked transistors. The magnitude of the gain of amplifier 400B is the number of stacked transistors minus one (i.e., amplifier 400B has a gain with a magnitude of 3 in FIG. 4B). In some embodiments, a larger open-loop gain can be achieved by using more stacked diode-connected transistors or by connecting multiple stages of amplifiers similar to amplifier 400B in series. The open-loop gain of amplifier 400B may be configured to be any number in the manner described above. In some embodiments, the open loop gain of amplifier 400B may have a magnitude less than 100 (e.g., less than 90, less than 80, less than 70, etc.). For example, in some embodiments, the magnitude of the amplifier gain is greater than or equal to 20 and less than or equal to 40. By way of further example, in some embodiments, the magnitude of the amplifier gain is less than 10. In other embodiments, the magnitude of the amplifier gain is greater than or equal to 10. In still further embodiments, the magnitude of the amplifier gain is less than or equal to 1.

[0066] In Figures 4A-4B, the gain of amplifiers 400A and 400B may be defined by the number of stacked transistors, which is not adjustable. In some embodiments, the gain of the amplifier may be adjustable, and the circuit may include switches disposed between the stacked transistors such that the gain is controllable or adjustable by switching in or out one or more of the stacked transistors or amplifier stages. Figures 4C-4D show amplifiers 400C and 400D with adjustable open-loop gain.

[0067] As shown in FIG. 4C, amplifier 400C may be similar to amplifier 400A, except for the addition of switch S1, which electrically couples the gate of M3 to the gate of M2. Furthermore, as shown in FIG. 4D, amplifier 400D may be similar to amplifier 400B, except for the addition of switch S1, which electrically couples the gate of M3 to the gate of M2. When S1 is open, amplifiers 400C and 400D may be functionally identical to amplifiers 400A and 400B, respectively. When S1 is closed, M3 may be shorted and bypassed in both amplifiers 400C and 400D, in which case the number of stacked transistors in amplifiers 400C and 400D may each be reduced by one. As a result, the open-loop gain of amplifiers 400C and 400D when S1 is closed may be reduced by one (i.e., from three to two). By controlling the opening and closing of S1, the stacked transistors of amplifiers 400C and 400D can be switched in and out to adjust the open-loop gain of amplifiers 400C and 400D. It should be noted that other switch embodiments and designs may be used in amplifiers 400C and 400D other than S1. For example, two or more switches may be used. As a further example, a switch may switch two or more transistors in and out. By designing different switches, the open-loop gain of the amplifiers may be controlled or adjusted in any manner suitable for the application.

[0068] FIG. 4E is a schematic diagram of an exemplary amplifier 400E having adjustable amplifier stages, according to an embodiment of the present disclosure. In FIG. 4E, amplifier 400E includes three stacked amplifier stages: amp stage 1 (input “in1” and output “out1”), amp stage 2 (input “in2” and output “out2”), and amp stage 3 (input “in3” and output “out3”) electrically coupled in series between respective inputs “in” and outputs “out.” In some embodiments, one or more of amp stage 1, amp stage 2, and amp stage 3 may be any of amplifiers 400A-400D. As shown in FIG. 4E, amplifier 400E includes two switches S1 and S2. The gain of amplifier 400E (i.e., the gain between in and out) can be adjusted by controlling the opening and closing of S1 and S2. For example, if S2 is closed (connecting out3 and out) and S1 is open, amp stage 1, amp stage 2, and amp stage 3 are all switched in series between in and out, and the gain of amplifier 400E is the product of the gains of amp stage 1, amp stage 2, and amp stage 3. As another example, if S2 is open and S1 is closed (connecting out1 and out), amp stage 2 and amp stage 3 are short-circuited and bypassed, and only amp stage 1 functions between in and out of amplifier 400E. In this case, the gain of amplifier 400E is adjusted to be equal to the gain of amp stage 1.

[0069] By using the design of FIG. 4A or 4B, a precise gain of amplifier 400A or 400B can be achieved. For example, amplifier 400A (or amplifier 400B) has a gain of magnitude 3 (e.g., −3). If a gain of, for example, negative 4 is required, this can be achieved by stacking additional transistors on amplifier 400A (or amplifier 400B). By using the design of FIG. 4C or 4D, an amplifier 400C or 400D with an adjustable or controllable gain can be achieved. For example, amplifier 400C (or amplifier 400D) has a gain of magnitude 3 (e.g., −3) when S1 is open. If a gain of, for example, negative 2 is required, this can be achieved by closing S2. In some embodiments, a higher magnitude gain can be realized by connecting several amplifier stages in series, such as amplifier 400E. For example, amplifier 400E's amp stage 1, amp stage 2, and amp stage 3 may have gains of 2, 4, and 3, respectively, and with S2 closed and S1 open, amplifier 400E may have an overall gain of 24. Also, as shown in Figures 4A-4E, amplifiers 400A-400E do not use capacitors or other capacitive components. The designs of Figures 4A-4E allow for greater scalability of the circuit because it is generally easier to miniaturize transistors in semiconductor manufacturing processes compared to capacitors.

[0070] It should be noted that other amplifier designs may be used other than the exemplary amplifiers 400A-400E. It should be understood that embodiments of the present disclosure are not limited to these examples, and other amplifier embodiments may be implemented in light of the present disclosure.

[0071] Figure 5 is an example signal timing diagram for the pixel circuit of Figure 3, according to an embodiment of the present disclosure. Figure 5 shows the operating phase (e.g., for event detection) and reset phase (e.g., for resetting the pixel circuit in preparation for the next event detection) of the waveforms of the signals in the pixel circuit 300.

[0072] During the operating phase, as shown in Figure 5, taking into account Figure 3, at time T1, I ph begins to change, which is V PR , CG amp in voltage ("V in "), CG amp out voltage ("V out "), inc voltage ("V inc The threshold value TH comp1 At time T2, V inc TH comp1 If comp1 exceeds , the trigger signal V indicates that the change in luminance detected by the PD meets the definition of an event. on may be generated.

[0073] During the reset phase, as shown in FIG. 5 and taking into account FIG. 3, S1 applies a reset signal ("Reset" in FIG. 3, "V" in FIG. 5) at time T3. リセットS1 Once V リセットS1 Upon receiving V, S1 in V out S2 can also be electrically switched to set the reset signal ("V リセットS2 " displayed). リセットS2 Upon receiving V, S2 will inc At T3, comp1 may stop outputting the trigger signal, at which time V on is returned to 0. At time T4, S1 can be electrically disconnected (i.e., opened) to complete the reset of the CG amp. At time T5, S2 x and can be electrically disconnected (ie, opened) to complete the reset of inc.

[0074] 6 is a flowchart of an exemplary method 600 for controlling a sensor according to an embodiment of the present disclosure. In some embodiments, the sensor may be at least one of a temporal contrast (TC) sensor. The sensor may include a pixel circuit (e.g., pixel circuit 200 or 300). In some embodiments, method 600 of FIG. 6 may be performed using the pixel circuit.

[0075] In step 602, the pixel circuit generates a current signal (e.g., I ph ) For example, the current signal may be received from the PD of the pixel circuit 200 or 300.

[0076] In step 604, the pixel circuit converts the current signal into a voltage signal (e.g., V in FIGS. 2-3). PR ) The voltage signal may be generated based on (e.g., proportional to or logarithmic with) the current signal. For example, the current signal may be converted by a current-to-voltage converter I / V of pixel circuit 200 or 300.

[0077] In step 606, the pixel circuit charges a first capacitor (e.g., C in FIGS. 2-3 ) based on the voltage signal. c ) provides an isolation voltage signal (e.g., V in Figure 5) in ) The isolated voltage signal may be isolated from the current signal.

[0078] In step 608, the pixel circuit generates a signal (e.g., V out ) There is no capacitive feedback between the amplified signal and the isolated voltage signal.

[0079] In step 610, the pixel circuit generates a trigger signal (e.g., V in FIG. 5) when the amplified signal meets a condition. on) in FIG. 5 . For example, the trigger signal may be generated by one or more comparators of the pixel circuit (e.g., comp1 and comp2 of pixel circuit 200 or 300). In some embodiments, the condition is that the magnitude of the amplified signal exceeds a threshold value (e.g., TH comp1 ) or more. In some embodiments, the pixel circuit may further output a trigger signal to an external readout system.

[0080] In step 612, the pixel circuit resets the amplifier when the trigger signal is generated. For example, the pixel circuit may close a switch (e.g., a first switch S1 of the pixel circuit 200 or 300) electrically coupled between the input (e.g., in of the pixel circuit 200 or 300) and the output (e.g., out of the pixel circuit 200 or 300) of the amplifier (e.g., CG amp). In some embodiments, after outputting the trigger signal, the pixel circuit may receive an acknowledge signal from the external readout system to reset the amplifier.

[0081] In some embodiments, method 600 may further include resetting another switch (e.g., second switch S2 of pixel circuit 200 or 300) electrically coupled between a reference signal (e.g., vref in FIG. 3 ) and an input of a comparator (e.g., inc of comp1 and comp2 of pixel circuit 300) to generate a trigger signal, where another capacitor is electrically coupled in series between the amplifier (e.g., CG amp) and the input of the comparator.

[0082] Additionally, in some embodiments, the method 600 may include opening a switch (e.g., S2) later than opening another switch (e.g., S1) after resetting the amplifier. For example, the pixel circuit may use a delay circuit (e.g., a delay in the pixel circuit 300) electrically coupled between S1 and S2 to set the time delay between switching the first switch S1 and the second switch S2.

[0083] The above description has been presented for purposes of illustration. It is not exhaustive and is not limited to the precise forms and embodiments disclosed. Modifications and adaptations of the embodiments will become apparent from consideration of the specification and practice of the disclosed embodiments. For example, while the described implementation includes hardware, systems and methods consistent with the present disclosure can be implemented using both hardware and software. In addition, while certain components are described as being coupled to each other, such components may also be integrated with each other or distributed in any suitable manner.

[0084] Furthermore, while exemplary embodiments are described herein, the scope includes any and all embodiments having equivalent elements, modifications, omissions, combinations (e.g., of aspects across various embodiments), adaptations, and / or alterations based on this disclosure. The claimed elements are to be interpreted broadly based on the terms employed in the claims and are not limited to the examples described herein or during this prosecution, and these examples are to be construed as non-exclusive. Furthermore, the steps of the disclosed methods can be modified in any manner, including rearranging and / or inserting or deleting steps.

[0085] The features and advantages of the present disclosure will be apparent from the detailed specification, and accordingly, the appended claims are intended to cover all systems and methods that fall within the true spirit and scope of the present disclosure. As used herein, the indefinite articles "a" and "an" mean "one or more." Similarly, the use of plural terms does not necessarily mean a plurality unless clearly indicated otherwise in a given context. Also, words such as "and" or "or" indicate "and / or" unless specifically indicated otherwise. Moreover, since numerous modifications and variations will readily occur from studying this disclosure, it is not desired to limit the disclosure to the exact construction and operation shown and described; therefore, all suitable modifications and equivalents may be resorted to and fall within the scope of the present disclosure.

[0086] Other embodiments will be apparent from consideration of the specification and practice of the embodiments disclosed herein. It is intended that the specification and examples be considered as exemplary only, with the true scope and spirit of the disclosed embodiments being indicated by the following claims.

Claims

1. A sensor comprising a plurality of pixels, each pixel comprising: a photosensitive element configured to generate a current signal in response to the intensity of light incident on the photosensitive element; a converter configured to receive the current signal from the photosensitive element and generate a voltage signal based on the received current signal; a capacitor electrically coupled in series with the transducer and configured to receive the voltage signal from the transducer; an open-loop amplifier electrically coupled at an input in series with the capacitor and configured to generate an amplified signal at an output based on an output signal from the capacitor, the open-loop amplifier comprising a plurality of stacked transistors providing a well-controlled and highly accurate open-loop gain of the open-loop amplifier, a first transistor of the plurality of stacked transistors configured to receive the output signal from the capacitor, a second transistor of the plurality of stacked transistors configured to receive at its gate a bias voltage that sets an operating point of the open-loop amplifier, the first transistor and the second transistor being of the same polarity, and each transistor in the plurality of stacked transistors apart from the first transistor and the second transistor being diode-connected; a reset device electrically coupled between the input and the output of the open-loop amplifier and configured to reset the open-loop amplifier in response to generation of a trigger signal; A sensor comprising:

2. A sensor as described in claim 1, wherein the gate of each transistor in the plurality of stacked transistors other than the first transistor and the second transistor is electrically coupled to its drain.

3. The sensor of claim 1 or 2, wherein the open loop amplifier comprises multiple amplifier stages.

4. 4. The sensor of claim 1, wherein each pixel further comprises a comparator electrically connected to an output of the open-loop amplifier and configured to generate the trigger signal when the amplified signal meets a condition.

5. A sensor as described in claim 4, wherein the condition includes the magnitude of the amplified signal being greater than or equal to a threshold value.

6. The sensor of claim 4 or 5, wherein the comparator is further configured to output the trigger signal to an external readout system.

7. the external readout system is configured to send an acknowledge signal to the pixel in response to the trigger signal, and the reset device is further configured to reset the open-loop amplifier in response to the acknowledge signal; and / or 7. The sensor of claim 6, wherein the reset device is further configured to reset the open-loop amplifier after the comparator outputs the trigger signal and regardless of receipt of an acknowledge signal from the external readout system.

8. another capacitor electrically coupled in series between the output of the amplifier and the input of the comparator; another reset device electrically coupled between the input of the comparator and a reference signal, the reset device configured to set the reference signal as the input of the comparator; The sensor of any one of claims 4 to 7, further comprising:

9. The sensor of claim 8 , wherein the further reset device comprises a further switch.

10. 10. The sensor of claim 8 or 9, wherein the further reset device is further configured to set the reference signal as an input to the comparator by activating the further reset device.

11. a delay circuit electrically coupled between the reset device and the further reset device and configured to set a time delay between operation of the reset device and the further reset device; The sensor of any one of claims 8 to 10, further comprising:

12. The sensor of any one of claims 8 to 11, wherein the reference signal comprises a reference voltage.

13. the absence of any capacitors between the input and output of said amplifier; the sensor comprising at least one temporal contrast sensor; the magnitude of the open loop gain of the open loop amplifier is less than 100; the reset device is further configured to reset the open-loop amplifier by setting a voltage between an input and an output of the open-loop amplifier to zero; The sensor according to any one of claims 1 to 12, further comprising any one or more of:

14. The sensor of any one of claims 1 to 13, wherein the reset device is further configured to reset the amplified signal to a reference signal isolated from the open-loop amplifier.

15. A pixel circuit, the pixel circuit comprising: a photosensitive element configured to generate a current signal in response to an intensity of light incident on the photosensitive element; a converter configured to receive the current signal from the photosensitive element and generate a voltage signal based on the received current signal; a capacitor electrically coupled in series with the transducer and configured to receive the voltage signal from the transducer; an open-loop amplifier electrically coupled at an input in series with the capacitor and configured to generate an amplified signal at an output based on an output signal from the capacitor, the open-loop amplifier comprising a plurality of stacked transistors providing a well-controlled and highly accurate open-loop gain of the open-loop amplifier, a first transistor of the plurality of stacked transistors configured to receive the output signal from the capacitor, a second transistor of the plurality of stacked transistors configured to receive at its gate a bias voltage that sets an operating point of the open-loop amplifier, the first transistor and the second transistor being of the same polarity, and each transistor in the plurality of stacked transistors apart from the first transistor and the second transistor being diode-connected; a reset device electrically coupled between the input and the output of the open-loop amplifier and configured to reset the open-loop amplifier when a trigger signal is generated; A pixel circuit comprising:

16. There is no capacitive feedback between the output and the input of the amplifier, or the pixel circuit further comprising a comparator electrically coupled to an output of the open-loop amplifier and configured to generate the trigger signal when the amplified signal meets a condition.

16. The pixel circuit of claim 15.

17. 1. A method for controlling a sensor including a plurality of pixels, the method comprising: receiving a current signal in response to light incident on the photosensitive element; converting the current signal into a voltage signal; generating an isolated voltage signal by a capacitor based on the voltage signal, the isolated voltage signal being isolated from the current signal; generating an amplified signal by an open-loop amplifier based on the isolated voltage signal, the open-loop amplifier comprising a plurality of stacked transistors providing a well-controlled and highly accurate open-loop gain of the open-loop amplifier, a first transistor of the plurality of stacked transistors configured to receive an output signal from the capacitor, a second transistor of the plurality of stacked transistors configured to receive at its gate a bias voltage that sets an operating point of the open-loop amplifier, the first transistor and the second transistor being of the same polarity, and each transistor in the plurality of stacked transistors other than the first transistor and the second transistor being diode-connected; generating a trigger signal when the amplified signal meets a condition; resetting the open loop amplifier when the trigger signal is generated; A method comprising:

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