Analog Circuit Design

Abstract

The primary design unit is configured to identify a plurality of circuit portions for forming the analog circuit, determine respective technical criteria for each circuit portion, and provide the respective technical criteria to at least one of a plurality of secondary design units. Each of the plurality of secondary design units is configured to design a respective circuit portion based on the technical criteria for the respective circuit portion and output a resulting initial design for the respective circuit portion. After at least the initial design of a given circuit portion is completed by at least other secondary design units, at least one of the secondary design units is configured to adapt its output initial design based on the context of the corresponding circuit portion.

Description

[Technical Field]

[0001] The present disclosure relates to methods and systems for analog circuit design, and more particularly to methods and systems for automating the analog circuit design process. [Background technology]

[0002] Analog components have the highest number of failures in chip manufacturing tests, accounting for as much as 95% of field failures. While digital circuit design has been automated to some extent in recent years, automating analog circuit design has been difficult due to issues such as parasitic effects. In traditional analog circuit design, designers often rely on past knowledge and experience to manually perform "best guess" estimates and guardband specifications, often resulting in over-engineered circuits that are inefficient and prone to failure. For this reason, there is a need to develop a more efficient and reliable process for analog circuit design. Summary of the Invention [Means for solving the problem]

[0003] Aspects of the invention are set out in the independent claims, with optional features set out in the dependent claims. Aspects of the invention may be provided in conjunction with one another, and features of one aspect may be applied to other aspects.

[0004] In a first aspect, an analog circuit design apparatus is provided. The analog circuit design apparatus comprises a primary design unit and a plurality of secondary design units; The primary design unit is Obtaining information that represents the technical requirements for the analog circuit; Identifying a plurality of circuit portions to form an analog circuit based on the acquired information; For each circuit portion of the plurality of circuit portions, determining a respective technical standard for the circuit portion; providing each of the technical criteria for each of the circuit portions to at least one of the plurality of secondary design units; Each of the plurality of secondary design units of the analog circuit design device comprises: designing each circuit portion of the plurality of circuit portions based on the technical criteria for each circuit portion provided by the primary design unit; outputting a resulting initial design for each circuit portion; After the initial design of at least the predetermined circuit portion is completed by at least one other secondary design unit, the at least one secondary design unit is configured to adapt the output initial design based on a context of the corresponding circuit portion, the context including technical criteria generated based on the completed design of the predetermined circuit portion completed by the at least one other secondary design unit; The primary design unit further: receiving a respective design for each circuit portion from at least one of a plurality of secondary design units; It is configured to generate at least an initial design for the analog circuit based on the received design.

[0005] The context may include information related to parameters and variables experienced by a corresponding portion of the circuit when used with at least some of the other portions of the circuit. For example, the context may consist of any one or combination of: silicon process, temperature range, output load, output impedance, input capacitance, input common-mode range, input differential swing, power supply voltage, available transistor types, output common-mode range, output swing, settling time, noise immunity, power supply rejection ratio (PSRR), common-mode range-input (input CMR), common-mode range-output (output CMR), linearity, maximum offset, bandwidth, minimum slew rate, intrinsic delay, minimum phase margin, dynamic power consumption, static power consumption, IP3 point, filter center frequency, filter bandwidth, load step response, line step response, output accuracy, noise figure, calibration range, noise floor, SNR, ENOB, SINAD, output frequency range, jitter-ptp, jitter-rms, output ripple-ptp, total harmonic distortion, start-up time, channel isolation, reference voltage, gain error, offset error, and gain drift.

[0006] It will be appreciated that adapting the design of a portion of a circuit based on context information may include adjusting the inputs and outputs that a component / portion of the circuit is configured to handle and / or may adapt the structure of the design to, for example, change the type, size and / or number of components that may form part of that portion of the design.

[0007] In some examples, each secondary design unit is configured to repeat the step of adapting the design of its corresponding circuit portion if a modification of the design of another circuit portion of the plurality of circuit portions causes a change in context for the corresponding circuit portion of the secondary design unit, and each secondary design unit may be configured to repeat the step of adapting the design of its corresponding circuit portion only if the change in context is greater than a selected threshold level.

[0008] In some examples, each secondary design unit is configured to adapt the design of its corresponding circuit portion only after at least the initial design of the corresponding circuit portion has been completed by all secondary design units.

[0009] The primary design unit may be configured to obtain the context of a corresponding circuit portion of a secondary design unit by simulating the performance of the given circuit portion completed by at least other of the secondary design units. Additionally or alternatively, each secondary design unit may be configured to obtain the context of its corresponding circuit portion by simulating the performance of the given circuit portion completed by at least other of the secondary design units.

[0010] In some examples, simulating the behavior of the circuit includes simulating the behavior of a selected portion of the circuit to obtain the context of the selected portion of the circuit. Alternatively, simulating the behavior of the circuit may include simulating the behavior of a portion of the circuit that is adjacent to and / or interacts with the selected portion of the circuit to obtain the context of the selected portion of the circuit. Alternatively, simulating the behavior of the circuit may include simulating the behavior of the entire circuit to obtain the context of the selected portion of the circuit.

[0011] It will be appreciated that the portions of the circuit may be selected based on the functionality provided by the portions of the circuit.

[0012] In some examples, each of the plurality of design units is configured to design each circuit portion of the plurality of circuit portions based on the technical criteria for the respective circuit portion provided by the primary design unit by performing a lookup of a database of designed circuits and / or circuit portions for circuit portions that meet the technical criteria. Additionally or alternatively, each of the plurality of design units is configured to design each circuit portion of the plurality of circuit portions, for example, by budgeting based on maximum and / or minimum specifications or values ​​associated with the technical criteria and / or by referencing calculated values ​​or values ​​determined from previous iterations.

[0013] In some examples, the analog circuit design apparatus further comprises a plurality of tertiary design units; At least one of the plurality of primary design units and / or secondary design units: Identifying a plurality of circuit subportions for forming an analog circuit based on the received technical criteria; determining, for each circuit subportion of the plurality of circuit subportions, a respective technical sub-criteria for the circuit subportion; providing each technical sub-criteria for each circuit sub-portion to at least one of a plurality of tertiary design units; further configured to design at least one respective circuit sub-portion of the plurality of circuit portions based on the technical criteria for the respective circuit portion provided by the primary design unit; Each of the plurality of third design units of the analog circuit design device designing each circuit subportion based on the technical sub-criteria for each circuit subportion provided by the secondary design unit; and outputting the resulting design for each circuit subportion.

[0014] After at least an initial design of a given circuit sub-portion is completed by at least one other of the tertiary design units, at least one of the tertiary design units is configured to adapt its initial output design based on a context for that circuit sub-portion, the context including technical sub-criteria generated based on the completed design of the given circuit sub-portion completed by at least one other of the tertiary design units.

[0015] In some examples, each secondary and / or tertiary design unit may include: Verify whether the corresponding designed circuit portion meets the corresponding technical standards; outputting the generated design when each designed circuit portion meets the technical criteria; When each circuit portion does not meet the technical standards, the design of each circuit portion is adapted.

[0016] Each secondary design unit is simulating the analog circuit based on each corresponding designed circuit portion design to generate at least one simulation output; Verify whether the circuit portion meets the corresponding technical standards; outputting the generated design when the simulated performance of each circuit portion meets the engineering criteria; When the simulated performance of each circuit portion does not meet the technical criteria, the design of the respective circuit portion may be adapted based on the difference between the simulated performance and the technical criteria.

[0017] The primary design unit is simulating an analog circuit based on the generated initial design to generate at least one simulation output; Verify whether the analog circuit meets the technical requirements of the analog circuit, If the analog circuit meets the technical requirements, output the generated design; When analog circuits do not meet the technical requirements, For at least one affected circuit portion of the plurality of circuit portions, determining modified engineering criteria for the affected circuit portion based on the simulation output and the engineering requirements; Providing at least one corresponding secondary design unit with revised technical standards for each affected circuit portion; receiving an updated design for each of the affected circuit portions from at least one corresponding secondary design unit; updating the set of designs with updated designs for each of the affected circuit portions; The steps of simulation, verification, and output may be repeated for each updated set of designs.

[0018] In some examples, the primary design unit is configured to adjust the technical criteria of the corresponding circuit portion of the at least one secondary design unit based on a context of the corresponding circuit portion of the at least one secondary design unit; The at least one secondary design unit is configured to adapt the design of the corresponding circuit portion based on the adjusted technical criteria of the corresponding circuit portion received from the parent.

[0019] However, in some examples, the secondary design units may additionally or alternatively be configured to adjust their own technical criteria for the corresponding circuit portion of at least one secondary design unit based on the context of that corresponding circuit portion; each secondary design unit is configured to adapt the design of a corresponding circuit portion based on the adjusted technical criteria for the corresponding circuit portion; It will be understood that.

[0020] In another aspect, a method for designing an analog circuit is provided, comprising: The method includes, in a primary design unit of an analog circuit design apparatus, Obtaining information that represents the technical requirements for the analog circuit; Identifying a plurality of circuit portions to form an analog circuit based on the acquired information; For each circuit portion of the plurality of circuit portions, determining a respective technical standard for the circuit portion; providing respective technical criteria for each circuit portion to at least one of a plurality of secondary design units; In each of a plurality of secondary design units of the analog circuit design apparatus, designing each circuit portion of the plurality of circuit portions based on the technical criteria for each circuit portion provided by the primary design unit; Output the resulting design for each circuit portion, After an initial design of at least a predetermined circuit portion is completed by one of the secondary design units, a design of the further circuit portion by the further secondary design unit is adapted based on a context for the further circuit portion, the context including technical criteria generated based on the completed design of the predetermined circuit portion; In the primary design unit, receiving a respective design for each circuit portion from at least one of a plurality of secondary design units; generating at least an initial design of the analog circuit based on the received design;

[0021] The context may include information related to parameters and variables experienced by a corresponding portion of the circuit when used with at least some of the other portions of the circuit. For example, the context may consist of any one or combination of: silicon process, temperature range, output load, output impedance, input capacitance, input common-mode range, input differential swing, power supply voltage, available transistor types, output common-mode range, output swing, settling time, noise immunity, power supply rejection ratio (PSRR), common-mode range-input (input CMR), common-mode range-output (output CMR), linearity, maximum offset, bandwidth, minimum slew rate, intrinsic delay, minimum phase margin, dynamic power consumption, static power consumption, IP3 point, filter center frequency, filter bandwidth, load step response, line step response, output accuracy, noise figure, calibration range, noise floor, SNR, ENOB, SINAD, output frequency range, jitter-ptp, jitter-rms, output ripple-ptp, total harmonic distortion, start-up time, channel isolation, reference voltage, gain error, offset error, and gain drift.

[0022] The method may further comprise adapting the initial design of the given circuit portion based on a context for the given circuit portion, the context including technical criteria generated based on the adapted design of the further circuit portion.

[0023] In some examples, the method further includes repeating the step of adapting the design of the additional circuit portion if a modification to the design of another circuit portion of the plurality of circuit portions causes a change in context for the additional circuit portion. Repeating the step of adapting the design of the additional circuit portion may occur only if the change in context is greater than a selected threshold level. Additionally or alternatively, repeating the step of adapting may include performing guardbanding, budgeting, or calculations, for example, based on maximum and / or minimum specifications or values ​​associated with technical criteria and / or by referencing calculated values ​​or values ​​determined from previous iterations.

[0024] In some examples, the method further includes adapting the design of the circuit portion output from each of the plurality of secondary design units based on the respective context after at least an initial design of the corresponding circuit portion has been completed by each corresponding secondary design unit.

[0025] The design of further circuit portions may be adapted only after all other portions of the circuit have been designed by multiple secondary design units based on corresponding technical criteria.

[0026] It will be appreciated that the respective technical criteria of each circuit portion may be provided to all secondary design units in parallel.

[0027] In some examples, each technical criterion for each circuit portion is transmitted from the primary design unit to at least one secondary design unit, and then from the at least one secondary design unit to further secondary design units.

[0028] It will be appreciated that further circuit portion context may be obtained by simulating the performance of a given circuit portion.

[0029] Simulating the behavior of the circuit may include simulating the behavior of a selected portion of the circuit to obtain the context of the selected portion of the circuit. Alternatively, simulating the behavior of a portion of the circuit that is adjacent to and / or interacts with the selected portion of the circuit to obtain the context of the selected portion of the circuit. Alternatively, simulating the behavior of the circuit may include simulating the behavior of the entire circuit to obtain the context of the selected portion of the circuit.

[0030] It will be appreciated that the portions of the circuit may be selected based on the functionality provided by the portions of the circuit.

[0031] Adapting or modifying a selected portion of the circuit based on the context of that portion may include modifying or adapting a criterion for the selected portion of the circuit.

[0032] In some examples, designing each circuit portion of the plurality of circuit portions based on technical criteria for the respective circuit portion provided by the primary design unit includes performing a lookup of a database of designed circuits and / or circuit portions for circuit portions that meet the technical criteria.

[0033] Designing each circuit portion of the plurality of circuit portions with each of the plurality of secondary design units includes: Identifying a plurality of circuit subportions for forming an analog circuit based on the received technical criteria; determining, for each circuit subportion of the plurality of circuit subportions, a respective technical sub-criteria for the circuit subportion; providing each technical sub-criteria for each circuit sub-portion to at least one of a plurality of tertiary design units; In each of a plurality of tertiary design units of the analog circuit design device, designing each circuit subportion based on the technical sub-criteria for each circuit subportion provided by the secondary design unit; The method may further comprise outputting the resulting design of each circuit sub-portion.

[0034] Furthermore, after at least an initial design of a given circuit sub-portion is completed by one of the tertiary design units, the design of the further circuit sub-portion by the further tertiary design unit may be adapted based on the context of the further circuit sub-portion, and the context may include technical sub-criteria generated based on the completed design of the given circuit sub-portion.

[0035] In some examples, the method includes, in each of a plurality of secondary or tertiary design units of the analog circuit design apparatus: Verify whether each corresponding designed circuit portion meets the corresponding technical standards; outputting the generated design when each designed circuit portion meets the technical criteria; Further comprising adapting the design of each circuit portion if the respective circuit portion does not meet the technical criteria.

[0036] In some examples, the method includes, in each of a plurality of secondary or tertiary design units of the analog circuit design apparatus: simulating the analog circuit based on each corresponding designed circuit portion design to generate at least one simulation output; Verify whether the circuit portion meets the corresponding technical standards; outputting the generated design when the simulated performance of each circuit portion meets the engineering criteria; When the simulated performance of each circuit portion does not meet the engineering criteria, the method further comprises adapting the design of each circuit portion based on the difference between the simulated performance and the engineering criteria.

[0037] In some examples, the method includes, in a primary design unit: simulating an analog circuit based on the generated initial design to generate at least one simulation output; Verify whether the analog circuit meets the technical requirements of the analog circuit, If the analog circuit meets the technical requirements, output the generated design; When analog circuits do not meet the technical requirements, For at least one affected circuit portion of the plurality of circuit portions, determining modified engineering criteria for the affected circuit portion based on the simulation output and the engineering requirements; providing at least one corresponding secondary design unit with revised technical criteria for each affected circuit portion; receiving an updated design for each of the affected circuit portions from at least one corresponding secondary design unit; updating the set of designs with updated designs for each of the affected circuit portions; The method further comprises repeating the steps of simulating, verifying, and outputting for the updated set of designs.

[0038] It will be appreciated that portions of the circuit may be selected by the primary design unit based on the functionality to be provided by those portions of the circuit, for example as dictated by technical requirements.

[0039] Adapting the design of the selected portion of the circuit based on the context of the portion may include adjusting the technical criteria of the selected portion of the circuit, for example, may be performed locally at a secondary design unit or may be performed at a primary design unit.

[0040] It will be appreciated that the method may further include fabricating an analog circuit for the output design.

[0041] In another aspect, there is provided a computer-readable non-transitory storage medium comprising a program for a computer configured to cause a processor to perform any of the methods described above. [Brief explanation of the drawings]

[0042] [Figure 1A] FIG. 1A shows a functional schematic diagram of an example of an analog circuit. [Figure 1B] FIG. 1B shows the functional schematic of FIG. 1A divided into conceptual blocks. [Figure 2] Figure 2 shows a functional schematic of a computer-implemented hierarchical model for analog circuit design. [Figure 3] FIG. 3 shows a functional schematic diagram of another implementation of a computer-implemented model for analog circuit design. [Figure 4] FIG. 4 shows a functional schematic flow chart of a method for designing an analog circuit using, for example, the exemplary computer-implemented model of FIG. 2 or FIG. [Figure 5] FIG. 5 shows a functional schematic flow chart of another exemplary method for designing an analog circuit, for example, using the exemplary computer-implemented model of FIG. 2 or FIG. [Figure 6] FIG. 6 shows a functional schematic flow chart of another exemplary method for designing an analog circuit, for example, using the exemplary computer-implemented model of FIG. 2 or FIG. [Figure 7] FIG. 7 shows a functional schematic flow chart of another exemplary method for designing an analog circuit using, for example, the exemplary computer-implemented model of FIG. 2 or FIG. [Figure 8A] FIG. 8A shows a portion of an analog circuit designed by a computer-implemented hierarchical model, such as the models described with reference to any of FIGS. 1A through 7. [Figure 8B] FIG. 8B shows an example of a designed analog circuit made up of the circuit portions of FIG. 8A. DETAILED DESCRIPTION OF THE INVENTION

[0043] Embodiments of the present disclosure will now be described, by way of example only, with reference to the accompanying drawings, in which:

[0044] FIG. 1A is a simplified functional schematic diagram of an exemplary analog electronic circuit, in this example, an analog-to-digital converter (ADC) 1000. The analog circuit may include numerous portions or components, such as a comparator 1001, a DAC 1002, a level shifter 1003, and an operational amplifier 1004. While each portion or component may initially be considered in isolation, the context or environment in which that portion or component operates when applied in situ to the circuit as a whole can affect how that component / block operates and even whether that portion or component is suitable for use in that circuit. This impacts the design of analog circuits and is one of the reasons why analog circuit design is difficult to automate. Furthermore, analog circuit design has proven difficult to automate due to the complex feedback loops and mathematical relationships involved between the various portions / components of an analog circuit.

[0045] The claimed embodiments relate to methods and systems for automating the design of analog circuits that consider the context of other portions or components of the circuit to design more efficient circuits. The inventors have accomplished this by developing a computer-implemented model that delegates responsibility for designing portions or components of the analog circuit to respective units or "blocks." An example of this model is shown in FIG. 2. Such a hierarchical model involves the use of a primary design unit, referred to as a "parent block" 900, which acts as the controlling entity, and multiple secondary design units, referred to as "child blocks" 950a-d, which receive instructions from the primary design unit or parent block about what needs to be designed. Each secondary design unit or child block 950a-d is configured to design a respective component or portion of the analog circuit based on the instructions received from the parent 900. The instructions include not only the technical requirements ("criteria") that the component or portion must meet (e.g., functional requirements), but also information related to the context of the component or portion of the circuit—in other words, what the portion or component of the circuit will experience when placed in situ in a completed circuit.

[0046] The computer-implemented hierarchical model is iterative. As parent block 900 instructs each child block 950a-d to design its respective portion or component, some redesign of the circuit and its portions or components may be necessary to account for the portions or components designed by the other child blocks 950a-d, and thus the context in which each portion or component operates. Thus, once an initial design for a circuit portion or component is designed by one of child blocks 950a-d, the designs of other circuit portions or components by the other child blocks 950a-d may need to be adapted based on the context provided by the initial design. This process may be repeated to account for further adaptation of the design as it is performed—for example, as the design of other circuit portions or components is performed, the design of the circuit portion or component designed by the first child block may need to be adapted because the context of the circuit portion or component designed by the first child block may have changed (based on the design of the other circuit portions), and so on. The process of adapting the design of circuit portions or components based on these contexts may be repeated iteratively by child blocks 950a-d, for example, until the context caused by any adjustments to other portions or components of the analog circuit has been taken into account. For example, the process may be repeated iteratively until any change in context is less than a selected threshold level of change in context.

[0047] As described above, context may include technical criteria generated based on the design and may include parameters and variables that a circuit portion or component experiences during use. The context for any given circuit portion or component may be generated based on a simulation of the performance of circuit portion(s) or component(s) that interact with the given circuit portion or component, or by a simulation of a completed circuit that includes the given circuit portion or component. For example, parent block 900 may be configured to assemble a completed circuit from portions or components designed by each of child blocks 950a-d and simulate the operation of the assembled circuit. The context for any given circuit portion or component may additionally or alternatively be generated based on mathematical calculations or extractions.

[0048] The inventors have found that such an iterative hierarchical model can advantageously automate the design of analog circuits, which in turn advantageously means that over-designed analog circuits can be avoided and more efficient circuits can be designed and created instead.

[0049] As mentioned above, FIG. 1A illustrates an exemplary analog circuit 1000, which in this example is an analog-to-digital converter (ADC). Conceptually, the circuit can be divided into functional blocks corresponding to different portions or components of the circuit, e.g., based on their respective functionality. For example, an ADC may include a comparator 1001, a digital-to-analog converter (DAC) 1002, multiple level shifters 1003, and one or more operational amplifiers 1004. In the example illustrated in FIG. 1A, the circuit can be conceptually divided into blocks corresponding to these different portions or components. For example, as shown in FIG. 1B, the comparator may be conceptually divided into a first "child block" 950a, the DAC into a second child block 950b, the level shifters into a third child block 950c, and the operational amplifier into a fourth child block 950d. The ADC as a whole may be conceptually classified as its own block (labeled "parent" 900 in FIG. 1B). It will be appreciated that the ADC itself may form a conceptual building block within a larger analog circuit.

[0050] As mentioned above, there are interactions between different blocks of an analog circuit when used in situ. The interactions between these blocks in situ, and the resulting parameters and variables each block experiences when placed in the circuit, affect the performance of the circuit. For example, the specifications of an op-amp used in a circuit may depend on many parameters and variables resulting from the selection and design of comparators, DACs, and / or level shifters, and the connections between them.

[0051] For this reason, the design and selection of the portions or components that make up a block must take into account their interactions and be done in such a way that the block as a whole can handle the parameters and variables that the components are subjected to as a result of the interactions.

[0052] A non-exhaustive list of example parameters and variables that may influence the selection and design of these different blocks may include silicon process, temperature range, output load, output impedance, input capacitance, input common-mode range, input differential swing, supply voltage, type of transistors available, output common-mode range, output swing, settling time, noise immunity, power supply rejection ratio (PSRR), common-mode range-input (input CMR), common-mode range-output (output CMR), linearity, maximum offset, bandwidth, minimum slew rate, intrinsic delay, minimum phase margin, dynamic power consumption, static power consumption, IP3 point, filter center frequency, filter bandwidth, load step response, line step response, output accuracy, noise figure, calibration range, noise floor, SNR, ENOB, SINAD, output frequency range, jitter-ptp, jitter-RMS, output ripple-ptp, total harmonic distortion, start-up time, channel isolation, reference voltage, gain error, offset error, gain drift.

[0053] These parameters and variables may be referred to as the "context" or environment in which the block resides. Knowing this context can improve the design of the circuit to create an optimal analog circuit. However, it will be appreciated that analog circuit design is an iterative process, and the selection and adjustment of one block may affect the context of other blocks. Thus, as components of one block are selected / adjusted, components of other blocks may need to be adjusted or reselected to take into account the new context in which the block resides. Such an iterative process is impractical to perform manually, prone to errors, and can only be detected through communication.

[0054] As mentioned above, an example of a computer-implemented model for use in a method for automating the design of analog circuits is shown in Figure 2. Figure 2 shows a schematic of the blocks shown in Figure 1B and the interactions between the blocks described above.

[0055] In the example shown in FIG. 2, each block of the model is responsible for the design of the component / functionality represented by that block. In FIG. 2, child 1-950a is responsible for the design of comparator 1001, child 2-950b is responsible for the design of DAC 1002, child 3-950c is responsible for the design of level shifter 1003, and child 4-950d is responsible for the design of operational amplifier 1004. Parent block 900 is responsible for the design of ADC 1000 as a whole and delegates responsibility for the design of portions / components / functionality of the ADC to child blocks 950a-d. In some examples, parent block 900 may select how many child blocks 950a-d are required and the responsibilities assigned to each block. While child blocks 950a-d are shown in order, it should be understood that this order does not necessarily represent the order in which portions of the circuit are designed. For example, parent block 900 may instruct child block 950d, responsible for the operational amplifier, to design that portion of the circuit first. In some examples, the child blocks 950a-d may be configured to first design the output and work backward from there.

[0056] While each portion or component of a block may initially be selected in isolation, the context in which the component / block operates when applied to an entire circuit in place can affect how that component / block operates and even whether that component is suitable for use in that circuit. Thus, while a parent block may instruct each child block to design its own portion or component, once the initial version of the designed circuit is assembled by parent 900 from the portions or components designed by each child block 950a-d, circuit 1000 and its portions or components may need to be redesigned to some extent to take into account the portions or components selected by the other child blocks 950a-d and, therefore, the context in which each component / block operates. As discussed above, this is an iterative process.

[0057] Thus, the parent block 900 acts as a controller and is configured to process and handle the design process performed by each child block. To perform this function, the parent block 900 may be composed of a number of different modules, each configured to perform a different function as part of the design process, as shown in Figure 2. The parent block in Figure 2 includes an instructor module 901, an assembly module 902, and a verification and simulator module 903.

[0058] The instructor module 901 is configured to receive customer requirements for the circuit to be designed, along with other requirements such as PDK / conditions / control parameters dictated by the foundry, and translate these into a set of technical criteria that each child block 950a-d must meet when designing its respective component of the circuit. It is also configured to create and send instructions to each child block 950a-d regarding what each child block 950a-d needs to design and the criteria it must meet when doing so. The instructions may also include the context of other designed portions of the circuit designed by other child blocks, as well as the broader context of the circuit in which the component or portion of the circuit is intended to operate. For example, the technical criteria may be adjusted to take the context into account.

[0059] The assembly module 902 is configured to receive and collate all of the respective designed portions or components of the analog circuit provided by each of the child blocks 950a-d and assemble a complete analog circuit based on the respective designed portions or components. The completed analog circuit may then be tested by the verification and simulator module 903.

[0060] The verification and simulator module 903 is configured to receive the designed components from each of the child blocks and compare them to a set of technical requirements to determine whether the designed portion or component is satisfactory. This may include, for example, comparing the performance of each designed circuit portion or component to customer requirements by verifying whether it meets corresponding technical criteria and / or whether the designed analog circuit meets customer requirements. It may also or alternatively include verification checks to determine whether the designed circuit is valid, in the sense that it can operate within certain technical limits.

[0061] The verification module 903 may also include a simulator module configured to act as a "test bed" and simulate the functionality of assembled components of the circuit. Such simulation may provide contextual information. The simulator module may compare the simulated functionality of the circuit with customer requirements and, optionally, verify whether the designed circuit portions meet corresponding technical criteria and / or whether the designed analog circuit meets customer requirements. It will be understood that in some examples, the simulator module may replace the verification module 903.

[0062] Additionally, each child block 950a-d includes a number of different modules, each configured to perform a different function as part of the design process. In the example shown in Figure 2, each child block 950a-d includes a converter module 951a-d, an assembly module 952a-d, and a simulator module 953a-d. It will be appreciated that in some examples, each child block 950a-d may further include additional modules for instructing tertiary design units or "grandchild" blocks, similar to the way that parent block 900 of Figure 2 includes modules such as an instructor module and a validation module for instructing and validating the design process from its child blocks 950a-d, as described in more detail below with reference to Figures 3-6.

[0063] The converter modules 951a-d of each child block 950a-d are configured to receive the technical criteria received from the parent block 900, and optionally the context of the overall circuit, as well as the context of other components of the circuit, and convert them into a set of requirements for designing portions or components of the analog circuit to meet those criteria. It will be appreciated that in some examples, the context information may be provided and received as part of the technical criteria, while in other examples, it may be provided in addition to (e.g., separately from) the technical criteria.

[0064] Assembly modules 952a-d are configured to select and / or design electronic components to satisfy desired requirements that meet criteria dictated by the context of the parent blocks and the overall circuit and / or the context of other components of the circuit.

[0065] The simulator modules 953a-d may also be configured to simulate how the design portions or components designed by the assembly module will behave in situ to verify / validate whether those components are technically feasible.

[0066] In use, parent block 900 receives a set of requirements for an analog circuit 1000 to be designed. In the example shown in Figure 2, parent block 900 receives a set of requirements for an ADC to be designed, with characteristics including performance as dictated by, for example, the foundry that will manufacture the ADC. Parent block 900 receives these requirements, and instructor module 901 translates them into a set of technical criteria. These technical criteria are then sent to each of child blocks 950a-d.

[0067] The instructor module 901 may send these technical criteria to each of the child blocks 950a-d in parallel (i.e., all at the same time) or serially (e.g., criteria are sent to child 1, then child 2, then child 3, etc.). In some examples, the instructor module 901 may wait until it receives the design circuit from the first child before sending a set of technical criteria to the next child, and in some examples, the instructor module may be configured to adjust the technical criteria sent to the next child based on the design circuit received from the previous child—in other words, based on the context of the design circuit received from the previous child.

[0068] In examples where technical criteria are transmitted serially to child blocks 950a-d, the technical criteria may include a means for distinguishing which portions of the technical criteria are relevant to which child blocks 950a-d—for example, the technical criteria may include headers or flags that identify whether a particular portion of the technical criteria is relevant to a child block 950a-d. These headers or flags may be determined by the parent block 900, and the technical criteria may be adjusted accordingly to incorporate them.

[0069] Each child block 950a-d receives these technical criteria from parent block 900, and each converter module 951a-d converts these into a set of requirements for designing portions or components of an analog circuit to meet these technical criteria. Assembly modules 952a-d receive these requirements and design components / portions of the circuit that meet these requirements. It will be appreciated that this design process may comprise a lookup in a database of known circuit designs (or portions) and finding the circuit design that best meets the technical criteria.

[0070] Simulator modules 953a-d then check whether the designed components / portions of the circuit designed by the assembly module are technically feasible and / or simulate how these components / portions work in situ to verify whether the corresponding designed respective circuit portion meets its corresponding technical criteria. If the designed circuit portion meets the corresponding technical criteria, child blocks 950a-d are then configured to send or output the designed portion or component of the circuit back to parent 900. If the designed circuit portion does not meet its corresponding technical criteria, child blocks 950a-d are then configured to adapt the design of that circuit portion and repeat the process.

[0071] Once the parent 900 receives all of the designed portions or components of the circuit from all of the child blocks 950a-d, the assembly module 902 of the parent 900 then assembles a completed circuit (in this case, an ADC) from the portions or components designed by each child block and verifies, via the verification and simulator module 903, whether the designed circuit meets technical requirements. This may be done by simulating how the assembled circuit operates and comparing this simulated performance to customer and / or technical requirements. It will be appreciated that in some examples, the simulated performance of the completed analog circuit design may provide context (e.g., relative to another design unit), and the parent 900 may adjust technical criteria based on the context gained through simulation of the completed analog circuit design.

[0072] If the simulated performance of the designed circuit does not meet the customer or technical requirements (e.g., a parameter of the simulated circuit is greater than a threshold level that differs from the parameter dictated by the technical requirements), the verification module 903 communicates this to the instructor module 901. The instructor module 901 may then adjust the technical criteria based on the difference between the simulated performance of the circuit and the technical requirements and send these modified technical criteria back to the child blocks 950a-d.

[0073] In some examples, the parent block 900 (e.g., the validation module 903 / the instructor module 901) may determine which portion or component of the circuit is causing the circuit to fail to meet the technical requirements, and if the child block(s) 950a-d can be identified, the parent block 900 may be configured to send modified technical criteria only to the child block(s) responsible for the problematic portion or component of the circuit. However, in other examples, the modified criteria may be sent back to all child blocks 950a-d. It will also be understood that in some examples, the parent module 900 may additionally and / or alternatively determine which child blocks 950a-d and / or grandchild blocks may be required to design the associated portion or component of the circuit to, for example, meet the modified technical criteria.

[0074] The process then continues iteratively, with converter modules 951a-d of each child block 950a-d receiving these modified or adapted technical criteria from the parent block 900 and converting them into a new set of requirements for designing portions or components of the analog circuit to meet these adapted technical criteria. Assembly modules 952a-d receive these new requirements and design components / portions of the circuit that meet these requirements. Simulator modules 953a-d then simulate how the redesigned circuit components / portions will operate in situ and check whether the circuit components / portions designed by the assembly modules are technically feasible. The child blocks 950a-d are then configured to send the (re)designed components / portions of the circuit back to the parent 900.

[0075] Once the parent 900 has received all of the components / portions of the (re)designed circuit from all of the child blocks 950a-d, the parent 900 then assembles a completed circuit (in this case, an ADC) from the components / portions designed by each child block, simulates how the assembled circuit will work, and verifies whether the designed circuit meets the technical requirements via the verification and simulator module 903, which can compare the simulated performance with the technical requirements. If the simulated performance does not meet the technical requirements, the process is repeated by sending a modified set of criteria back to the child blocks 950a-d.

[0076] It will also be appreciated that the child blocks 950a-d and / or the parent block 900 may include a loop mitigation module to prevent the occurrence of endless redesign loops. For example, the loop mitigation module may have a record of previously designed circuits and be configured to output a loop indication if components / portions or the completed circuit of the redesigned circuit are identical to or differ from the components / portions or the completed circuit of the previously designed circuit by less than a selected threshold level of difference. For example, the parent block 900 may include a loop mitigation module and be configured to terminate the design process and accept the final designed circuit as the completed circuit if the loop mitigation module provides a loop indication. Additionally or alternatively, the parent block 900 may be configured to reduce the selected threshold level of difference, for example, if the design process is repeated for a selected number of iterations. This can have the effect of finding a “best compromise” functional circuit that meets technical requirements.

[0077] Figure 3 is a functional schematic diagram of another example computer-implemented model for designing analog circuits. The implementation of this model is similar in many respects to the model shown in Figure 2, and the functionality described above with respect to parent block 900 and child blocks 950a-d with respect to Figure 2 may be attributed to the parent and child blocks in Figure 3. Additionally, some of the functionality described in Figure 2 with respect to primary design unit or parent block 900 may be attributed to secondary design units or child blocks 950a-d in Figure 3, where that child block has tertiary design units or "grandchild" blocks below it, etc.

[0078] More specifically, as shown in Figure 3, the model hierarchy includes a core design layer that includes primary design units or parent blocks. While only one parent block 900 is shown in the core design layer of Figure 3, it will be understood that in some examples, there may be multiple parent blocks 900, such as when each parent block 900 operates in parallel. For example, each parent block 900 may be configured to design different aspects of an analog circuit (e.g., functionally and / or structurally different from one another).

[0079] Below the core design layer is a first design layer. The first design layer comprises secondary design units or child blocks 950 that are coupled to parent blocks 900 in the layer above (in this case, the core design layer). In this example, there are six child blocks, all coupled to parent blocks in the core design layer. The child blocks 950 are grouped into a first group consisting of child blocks 1, 2, and 3, and a second group consisting of child blocks 3, 4, and 5. Each child block 950 is coupled to the parent block 900. The two groups may represent different functional regions or areas of the analog circuit that the parent block 900 directs to be designed in parallel.

[0080] In the illustrated example, a first group of child blocks 950 are coupled in parallel to parent block 900 in the core design layer, and a second group of child blocks 950 are coupled in parallel to parent block 900 in the core design layer. Child blocks 950 may be grouped in this manner to design different regions or aspects of an analog circuit (e.g., functionally and / or structurally distinct from one another). However, it will be understood that in some examples, not all child blocks 950 in the first design layer need be coupled in parallel to parent blocks in the core design layer. For example, child blocks 1 and 3 in the first design layer may be coupled to parent block 900 in the core design layer, and child block 2 in the first design layer may be coupled in series to child blocks 1 and 3 in the first design layer, respectively.

[0081] The grouping of child blocks 950 may be determined by parent block 900 in the core design layer. For example, parent block 900 may be configured to group child blocks in the first design layer to design different aspects of an analog circuit (e.g., functionally and / or structurally different from one another). Parent block 900 in the core design layer may be configured to do this based on determining requirements from a customer specification.

[0082] Below the first design layer is a second design layer. The second design layer includes tertiary design units or grandchild blocks 1, 2, 3, 4, 5, 6, 7, 8-960. Grandchild block 960 is coupled to a child block in the upper (first) design layer. Not all child blocks in the first design layer are coupled to grandchild blocks in the second design layer. In the illustrated example, grandchild blocks 1, 2, and 3 in the second design layer are coupled in parallel to child block 2 in the first design layer. However, as discussed above with respect to child block 950 in the first design layer, it will be understood that in some examples, not all grandchild blocks in the second design layer need be coupled in parallel to child blocks in the first design layer. For example, grandchild blocks 1 and 3 in the second design layer may be coupled to child block 2 in the first design layer, and grandchild block 2 in the second design layer may be coupled in series to grandchild blocks 1 and 3, respectively, in the second design layer.

[0083] Below the second design layer is another (nth) design layer. The nth design layer includes great-grandchild blocks 1, 2, 3, 4-970. The great-grandchild blocks 970 are connected to the grandchild blocks 960 in the upper (second) design layer in much the same way that the grandchild blocks 960 in the second design layer are connected to the child blocks 950 in the first design layer. Thus, it will be appreciated that there may be multiple additional design layers below the second design layer, each with its own blocks connected to blocks in the layer above.

[0084] 3 is structured in the block hierarchy such that blocks at different layers of the model are configured to design aspects or portions of an analog circuit at different levels of complexity. For example, a parent block 900 may be configured to design a complete analog circuit, a child block 950 may be configured to design a functional component of the analog circuit (e.g., an operational amplifier, an AC / DC converter, a level shifter, a comparator, a voltage regulator, a power switch, etc.), and a grandchild block 960 may be configured to design a component of that functional component (e.g., the arrangement of resistors, transistors, capacitors, diodes, inductors, etc. for that component). However, it will be understood that a grandchild block 960 may be configured to design a more hierarchical block, such as an operational amplifier or a voltage reference or a comparator.

[0085] A parent block 900 (in a core design layer) may be configured to determine the level of complexity that blocks in a selected layer are configured to design, and / or blocks in a layer may be configured to determine the level of complexity that blocks in lower layers are configured to design.

[0086] Additionally or alternatively, the block hierarchy shown in Figure 3 may be structured such that blocks in different layers of the model are configured to design aspects or portions of the analog circuit based on different functional or structural requirements. For example, one layer may include blocks configured to design aspects or portions of the analog circuit based on one functional requirement (e.g., size), while another layer may include blocks configured to design another functional requirement (e.g., current or voltage).

[0087] FIG. 4 shows a functional schematic flow chart of a method for designing an analog circuit using, for example, the example computer-implemented hierarchical model of FIG. 2 or FIG.

[0088] More specifically, in step 300, parent block 900 receives customer requirements. The customer requirements may define, for example, the functionality of the circuit and specific constraints required from the circuit, such as peak current, voltage, etc. The customer requirements may also specify other characteristics, such as the PDK / foundry where the circuit will be manufactured. Parent block 900 is configured to translate customer requirements 302 into a set of technical criteria. Parent block 900 may additionally or alternatively be configured to determine whether to send these technical criteria to child blocks 950 in parallel or serially, and / or whether to send different sets of criteria to descendent child blocks 950.

[0089] Also at this stage, parent block 900 may be configured to determine the number of layers of the model, or alternatively, each layer block may be configured to determine whether a lower layer block is necessary when designing the portion of the circuit that it has been tasked with designing by a higher layer block.

[0090] Once the parent block 900 converts the customer requirements into criteria (302), it then sends them to the first-tier child blocks (304). In the illustrated example, the parent block 900 sends the technical criteria to child 1, child 2, and child 3 in parallel (304).

[0091] In this example, upon receiving the technical criteria, Child 1 determines (306) that it needs to involve a lower-level block (Grandchild block 960) and instructs Grandchild 1 to design the first portion of the circuit based on the technical criteria. Simultaneously, Child 2 designs (307) the first third portion of the circuit based on the technical criteria, and Child 3 designs (308) the first fourth portion of the circuit based on the technical criteria.

[0092] Grandchild 1 designs (308) a first portion of the circuit based on the technical criteria and sends (312) this designed first portion back to child 1, which forwards it to the parent (optionally after first performing some simulation / verification). Child 1 then instructs grandchild 2 to design (314) a second portion of the circuit based on the criteria. Grandchild 2 then designs (316) the second portion of the circuit based on the criteria and sends (318) this back to child 1, which may forward it to the parent.

[0093] Once Child 1 has designed the first and second portions of the circuit (via Grandchild 1 and Grandchild 2), Child 1 sends context information to Child 2 (320). Child 2 may adapt or adjust the technical criteria received from the parent based on the context information obtained from Child 1. Child 2 then adapts the third portion of the originally designed circuit based on the context information received from Child 1.

[0094] 4 , once the third portion of the circuit is designed by Child 2, the adapted design of the third portion may be sent to the parent, and context information may be sent to Child 3 (324). The context information may include the context created by the first, second, and third portions of the circuit. Child 3 then adapts (326) the initial design of the fourth portion of the circuit based on the received context information and sends (328) the designed fourth portion to Parent Block 900.

[0095] Once the parent block 900 receives all the designed portions of the circuit, the parent block 900 checks or verifies whether the designed completed circuit meets the customer requirements 330. As mentioned above, the parent block may do this by employing a verification and simulator module to simulate the performance of the completed circuit.

[0096] If the designed, completed circuit does not meet the customer requirements, the parent block may resend (332) the adjusted criteria directly to the block responsible for designing the portion of the circuit that caused the non-compliance, along with additional information about what needs to be adjusted (and optionally by which block)—e.g., the criteria may be adjusted to take into account the additional information for redesigning the block to meet the customer requirements. In some examples, the parent block 900 may only send (332) the portion of the designed circuit back to the block responsible for designing that portion—e.g., as shown in FIG. 5 (discussed below), the parent block 900 may send, for example, the first portion of the analog circuit back to its grandchild 1, along with information about what needs to be adjusted and / or the adjusted criteria.

[0097] It will be understood that in the above examples, the first, second, third, and fourth portions of the analog circuit may be independent portions of the circuit and / or may be functionally dependent on one another. In other examples, the first, second, third, and fourth portions of the analog circuit may be selected subsets of the analog circuit. For example, the second portion may be part of the first portion, the third portion may be part of the first and second portions, and the fourth portion may be part of the first, second, and third portions.

[0098] FIG. 5 is a functional schematic flow chart of a method for designing an analog circuit using, for example, the exemplary computer-implemented hierarchical model of FIG. 2 or FIG.

[0099] The method of Figure 5 has many features in common with the method of Figure 4. However, it is notable that rather than multiple child blocks 950 passing information between each other (such as references and designed circuit portions or components), in the example shown in Figure 5, each child block 950 is configured to report directly to the parent block 900 and send designed portions or components of the analog circuit that it is responsible for designing directly back to the parent block 900, and the child blocks 950 are configured to operate independently.

[0100] This arrangement may be advantageous in that the parent block 900 may be operable to adjust all of the designs of the various portions or components of the analog circuit in parallel. For example, in a first iteration, all of the child blocks 950 may be configured to simultaneously design their respective portions of the analog circuit. After receiving these designed portions of the analog circuit, the parent block 900 may be configured, in a second iteration, to instruct all (or, in some examples, a subset) of the child blocks 950 to redesign their respective portions or components based on the context provided by the design in the first iteration. It will be appreciated that such an approach may improve the speed at which a model can design an analog circuit.

[0101] More specifically, in step 400, parent block 900 receives customer requirements. Similar to the example described above with reference to FIG. 4, the customer requirements may define, for example, the functionality of the circuit and specific limitations required from the circuit—peak current, voltage, etc. The customer requirements may also specify other characteristics, such as the PDK / foundry where the circuit will be manufactured. Parent block 900 is configured to translate 402 the customer requirements into a set of criteria. Parent block 900 may additionally or alternatively be configured to determine whether to send these criteria to child block 950 in parallel or serial, and / or whether to send a different set of criteria to child block 950 in a lower design layer.

[0102] At this stage, parent block 900 may also be configured to determine the number of design layers of the model, or alternatively, blocks in each design layer may be configured to determine whether blocks in lower design layers are necessary when designing the portion of the circuit they are tasked with designing by blocks in higher design layers.

[0103] Once the parent block 900 converts the customer requirements into criteria (402), it then sends these to child block 1 of the first design layer (404). The criteria may specify how many child blocks 950 of this design layer to use and which child blocks 950 to design which portions of the analog circuit. In the example shown in FIG. 5, the parent block 900 directs each child block 950 serially, i.e., sending the criteria to child 1 first and waiting for child 1 to return its design portions / components of the circuit before directing child 2, etc. However, it will be understood (as discussed above) that in other examples, the parent block 900 may coordinate all child blocks 950 in parallel, such that criteria are sent to all child blocks 950 simultaneously.

[0104] In this example, upon receiving the criteria, Child 1 determines (406) that it needs to involve a lower-level block (grandchild block 960) and instructs Grandchild 1 to design a first portion of the circuit based on the criteria. Grandchild 1 designs (408) the first portion of the circuit based on the criteria and sends (410) this first portion of the design back to Child 1, which may then forward it to the parent (optionally after first performing some simulation / verification). Child 2 then instructs Grandchild 2 to design (412) a second portion of the circuit based on the criteria. Grandchild 2 designs (414) the second portion of the circuit based on the criteria.

[0105] It will be understood that in various implementations of this model, blocks communicate with blocks in immediately adjacent layers. However, in some examples, blocks may also communicate with blocks in layers that are not immediately adjacent. In the example shown in Figure 5, grandchild 2 may be configured to send 416 a second portion of the designed circuit directly back to parent 900, and parent 900 may be configured to send reference and context information back to grandchild 2.

[0106] Once Child 1 designs the first and second portions of the circuit (via Grandchild 1 and Grandchild 2), Parent Block 900 may adjust the criteria based on the first and second portions of the designed circuit and send the adjusted criteria to Child 2 (420). Child 2 may then design the third portion of the circuit based on these adjusted criteria. It will be appreciated that adjusting the criteria in this manner is one way of taking into account the context created by the first and second portions of the circuit designed by Child 1 / Grandchild 2—e.g., similar to the example described above in connection with FIG. 4 , Parent Block 900 may be configured to adjust the criteria based on the context provided by the first and second portions of the designed circuit. For example, in examples where Parent Block 900 includes a verification and simulator module, the verification and simulator module may simulate the performance of portions or components of the designed circuit to obtain the context.

[0107] However, in other examples, parent block 900 may not adjust the criteria, but instead simply send context information (such as the first and second portions of the circuit designed by child 1 / grandchild 1 and 2) in parallel with the criteria. The criteria may be the same as the criteria sent to child 1, or the criteria may be adjusted by parent block 900 so that the criteria are configured to be specific to each child block 950, and thus to each portion or component of the circuit that each corresponding child block 950 is instructed to design.

[0108] 5, once the third portion of the circuit is designed by Child 2, the parent may send 424 the adjusted criteria (e.g., taking into account the context created by the first, second, and third portions of the circuit). Child 3 then designs 426 the fourth portion of the circuit based on the adjusted criteria and sends 427 the designed fourth portion to parent block 900.

[0109] Once the parent block 900 receives all the designed portions of the circuit, the parent block 900 checks or verifies that the designed completed circuit meets the customer requirements 428. As mentioned above, the parent block may do this by employing a verification and simulator module to simulate the performance of the completed circuit.

[0110] If the designed, completed circuit does not meet the customer requirements, the parent block may resend (432) the adjusted criteria directly to the block responsible for designing the portion of the circuit that caused the non-compliance, along with additional information about what needs to be adjusted (and optionally by which block)—e.g., the criteria may be adjusted to take into account the additional information for redesigning the block to meet the customer requirements. In some examples, the parent block 900 may only send (432) only the portion of the designed circuit back to the block responsible for designing that portion—e.g., as shown in FIG. 5, the parent block 900 may send, for example, the first portion of the analog circuit back to its grandchild 1, along with information about what needs to be adjusted and / or the adjusted criteria.

[0111] It will be understood in the above examples that the first, second, third, and fourth portions of the analog circuit may be independent portions of the circuit and / or may be functionally dependent on one another. In other examples, the first, second, third, and fourth portions of the analog circuit may be selected subsets of the analog circuit. For example, the second portion may be part of the first portion, the third portion may be part of the first and second portions, and the fourth portion may be part of the first, second, and third portions.

[0112] Figure 6 is a functional schematic flow chart of a method for designing an analog circuit using, for example, the exemplary computer-implemented hierarchical model of Figure 2 or Figure 3. The method of Figure 6 has many features in common with the methods of Figures 4 and 5.

[0113] In step 500, the parent block 900 receives customer requirements. Similar to the methods described above in connection with FIGS. 4 and 5, the customer requirements may define the functionality of the circuit and specific constraints required from the circuit, such as peak current, voltage, etc. The customer requirements may also specify other characteristics, such as the PDK / foundry where the circuit will be manufactured. The parent block 900 is configured to translate the customer requirements into a set of criteria (5202). The parent block 900 may additionally or alternatively be configured to determine whether to send these criteria to the child blocks 950 in parallel or serially, and / or whether to send different sets of criteria to descendent child blocks 950.

[0114] Also at this stage, parent block 900 may be configured to determine the number of layers of the model, or alternatively, each layer block may be configured to determine whether a lower layer block is necessary when designing the portion of the circuit that it has been tasked with designing by a higher layer block.

[0115] Once the parent block 900 converts the customer requirements into criteria (502), it then sends these to the child block 1 in the first design layer (504). These criteria can specify how many child blocks 950 in this layer to use and which child blocks 950 are responsible for designing each portion of the analog circuit.

[0116] Upon receiving the criteria, child 1 designs a first portion of the analog circuit based on the received criteria 506. It will be appreciated that child 1 may be configured to design the first portion of the analog circuit based on a subset / first portion of the criteria applicable to it as determined by the parent block.

[0117] When Child 1 designs a first portion of an analog circuit, the criteria received from Parent block 900 may instruct Child 1 to send the designed first portion of the circuit and the criteria to a second child (Child 2) in the same layer. Child 2 may design a second portion of the analog circuit based on the received criteria, and in some instances may design the second portion of the analog circuit based on only a subset of the criteria (e.g., only the portion applicable to it) or based on all of the criteria.

[0118] Additionally, Child 2 adapts the design of the second portion of the analog circuit based on the context created by the designed first portion of the analog circuit designed by Child 1. In some examples, this context may be expressed in the form of a coordinated set of criteria—e.g., Child 1 and / or the parent block may be configured to coordinate criteria based on the context provided by the designed first portion of the circuit designed by Child 1, although it will be understood that in other examples, the context may be provided in addition to / separate from the criteria. For example, in examples where the parent block includes a verification and simulator module, the verification and simulator module may simulate the performance of the designed portion or component of the circuit to obtain the context. Additionally or alternatively, in examples where each child block includes a verification and simulator module, the verification and simulator module may simulate the performance of the designed portion or component of the circuit to obtain the context.

[0119] In some examples, Child 2 may determine that it needs to use lower-level blocks to design the portion of the circuit it is tasked with designing, and / or determine whether to use these lower-level blocks in series and / or parallel. Additionally or alternatively, the criteria received by Child 2 may instruct Child 2 to use lower-level blocks (and whether to use these blocks in series or parallel) to design the portion of the circuit it is tasked with designing. For example, as shown in FIG. 6 , Child 2 may optionally instruct Grandchild 1 and Grandchild 2 to design subsets of a second portion of an analog circuit (512). In such an example, Child 2 may optionally verify (513) whether the portions of the circuit designed by the lower-level blocks (in the illustrated example, Grandchild 1 and Grandchild 2) meet their required criteria.

[0120] Child 2 then sends the designed first portion, the designed second portion, and the criteria to Child 3 (514). In some examples, the criteria may be modified by a previous child. For example, the criteria may be modified by Child 1 and / or Child 2 before being sent to the next child. For example, Child 2 may be configured to modify the criteria it sends to Child 3 based on the designed first portion of the circuit and / or the designed second portion of the circuit.

[0121] Next, child 3 additionally or alternatively designs a third portion of the analog circuit based on the received criteria and the designed first portion and / or the designed second portion (516).

[0122] Child 3 then sends the completed circuit to the parent block (518), which checks whether the designed completed circuit meets the customer requirements (520). As mentioned above, the parent block may do this by employing a verification and simulator module to simulate the performance of the completed circuit.

[0123] If the designed, completed circuit does not meet the customer requirements, the parent block may resend the designed, completed circuit to child 1 (522) along with additional information about what needs to be adjusted (and optionally by which block). Additionally or alternatively, if the designed, completed circuit does not meet the customer requirements, the parent block may send only a portion of the designed circuit back to the block responsible for designing that portion (524)—for example, the parent block may send a second portion of an analog circuit back to child 2, e.g., along with information about what needs to be adjusted and / or along with the adjusted criteria. Child 2 may then design that portion of the circuit and either send it directly back to the parent block to check whether it meets the customer requirements, or send it to child 3, which may redesign a third portion of the circuit based on the redesigned second portion of the circuit (and / or optionally based on the adjusted criteria).

[0124] It will be appreciated in the above examples that the first, second, and third portions of the analog circuit may be independent portions of the circuit and / or may be functionally dependent on each other. In other examples, the first, e.g., second portion of the analog circuit may form part of the first portion, and the third portion may form part of both the first and second portions.

[0125] Figure 7 is a functional schematic flowchart of another method for designing an analog circuit using, for example, the exemplary computer-implemented hierarchical model of Figure 2 or Figure 3. The method of Figure 7 shares many features with the method of Figure 6 in that information, such as criteria and / or context information, is shared directly between children. Furthermore, in the example shown in Figure 7, the context information is provided separately from the criteria (i.e., the criteria are not adjusted based on the context).

[0126] More specifically, in step 600, the parent block 900 receives customer requirements. Similar to the examples described above with reference to FIGS. 4, 5, 6, and 7, the customer requirements may define, for example, the functionality of the circuit and specific constraints required from the circuit, such as peak current, voltage, etc. The customer requirements may also specify other capabilities, such as the PDK / foundry where the circuit will be manufactured. The parent block 900 is configured to translate the customer requirements into a set of criteria (602). The parent block 900 may additionally or alternatively be configured to determine whether to send these criteria to the child blocks 950 in parallel or serially, and / or whether to send different sets of criteria to descendent child blocks 950.

[0127] Also at this stage, parent block 900 may be configured to determine the number of layers of the model, or alternatively, each layer block may be configured to determine whether a lower layer block is necessary when designing the portion of the circuit that it has been tasked with designing by a higher layer block.

[0128] Once parent block 900 converts customer requirements into criteria (602), it then sends them to child block 1 in the first design layer (604). The criteria may specify how many child blocks 950 in this layer to use and which child blocks 950 to design which portions of the analog circuit. In the example shown in Figure 6, parent block 900 directs each child block 950 serially, first sending the criteria to child 1, which then directs child 2, and so on.

[0129] In this example, upon receiving the criteria, Child 1 determines 606 that it needs to involve a lower-level block (grandchild block 960) and instructs Grandchild 1 to design a first portion of the circuit based on a first subset of the criteria 607. As part of this process, Child 1 may divide the criteria into subsets relevant to itself and / or its grandchildren as directed.

[0130] Grandchild 1 designs (608) a first portion of the circuit based on a first subset of the criteria and sends (610) the first portion back to child 1. Child 1 then instructs grandchild 2 to design (614) a second portion of the circuit based on a second subset of the criteria. Grandchild 2 designs (616) the second portion of the circuit based on the criteria and sends (616) the second portion back to child 1. While this process is described serially (i.e., child 1 instructs grandchild 2 only after grandchild 1 has designed its portion of the circuit), it will be understood that in other examples child 1 may instruct both grandchild 1 and grandchild 2 in parallel. Furthermore, it will be understood that in some examples child 1 may simulate the operation of the first portion of the circuit designed by grandchild 1 and send this context information along with the criteria to grandchild 1 (and optionally other child blocks) to gain context provided by the portion of the circuit designed by grandchild 1.

[0131] Once Child 1 has designed the first and second portions of the circuit (via Grandchild 1 and Grandchild 2), Child 1 may simulate the behavior of the first and second portions of the circuit to obtain their context (612) and send the criteria and the context provided by the designed first and second portions of the circuit to Child 2 (622). Child 1 may also send the designed first and second portions together to Child 2 for forwarding to parent block 900. Child 2 may then design a third portion of the circuit (624) based on the subset of criteria associated with it and the context information provided by Child 1.

[0132] 6 , once the third portion of the circuit is designed by Child 2, Child 2 may simulate (626) the operation of the third portion of the circuit and send (628) this context information along with the criteria to Child 3 (as well as the designed first, second, and third portions for forwarding to Parent Block 900). It will be appreciated that in some examples, context information associated with other portions of the circuit (if available), such as from the designed first and second portions, may also be sent to Child 3. Child 3 then designs (630) a fourth portion of the circuit based on the criteria (or a subset of the criteria associated therewith), simulates (632) the operation of the designed fourth portion of the circuit, and sends (634) the designed fourth portion to Parent Block 900 along with the other designed portions and context information.

[0133] Once the parent block 900 receives all the designed portions of the circuit, the parent block 900 checks or verifies whether the designed completed circuit meets the customer requirements 636. As mentioned above, the parent block 900 may do this by employing a verification and simulator module to simulate the performance of the completed circuit.

[0134] If the designed completed circuit does not meet the customer requirements, the parent block may resend the criteria to the child block 1 and repeat the process, along with the context information provided in the previous iteration. The process then repeats as described above. In some examples, the parent block 900 may adjust the criteria sent to the child block based on differences between the designed completed circuit and the customer requirements, for example, based on simulated behavior of the completed circuit compared to the customer requirements.

[0135] It will be understood in the above examples that the first, second, third, and fourth portions of the analog circuit may be independent portions of the circuit and / or may be functionally dependent on one another. In other examples, the first, second, third, and fourth portions of the analog circuit may be selected subsets of the analog circuit. For example, the second portion may be part of the first portion, the third portion may be part of the first and second portions, and the fourth portion may be part of the first, second, and third portions.

[0136] FIG. 8A shows a portion of an analog circuit designed using a computer-implemented hierarchical model, such as the model described above with reference to any of FIGS. 1A through 7, and FIG. 8B shows an example of a designed analog circuit, in this case an ADC, that includes the circuit portion of FIG. 8A.

[0137] Figure 8A shows an input buffer, level shifter, DAC, and comparator, each of which may form portions of a complete analog circuit, such as the complete ADC shown in Figure 8B.

[0138] The example shown in FIGS. 8A and 8B was designed using the computer-implemented hierarchical model described above. A parent block (or primary design unit) is responsible for the overall ADC design, and child blocks (or secondary design units) are responsible for each of the input buffers, level shifters, DACs, and comparators. The parent block receives technical requirements from the user and translates them into technical criteria, which are then used by each child block to design its respective portion of the circuit. The context of other portions of the circuit is considered and used by the child blocks when designing their respective portions of the circuit. This model is also iterative in that once the parent block 900 instructs each child block 950a-d to design its respective portion or component, some degree of redesign of the circuit and its portions is performed so that the context provided by other portions of the circuit is used in the design of each circuit portion and the circuit as a whole. As described above, each child block and / or parent block may perform verification / validation to determine whether the designed portion / completed circuit meets the required technical requirements.

[0139] In the designed circuit shown in Figure 8B, there are two DACs to operate a differential ADC, and there are multiple input buffers (three in the example shown), two to buffer the two inputs and also to buffer the reference as an input.

[0140] In the context of this disclosure, it will be understood that a non-exhaustive list of exemplary analog parameters that may form the basis of the criteria includes noise immunity, power supply rejection ratio (PSRR), common mode range - input (input CMR), common mode range - output (output CMR), linearity, maximum offset, bandwidth, minimum slew rate, intrinsic delay, minimum phase margin, dynamic power consumption, static power consumption, IP3 point, filter center frequency, filter bandpass range, load step response, line step response, output accuracy, noise figure, calibration range, noise floor, SNR, ENOB, SINAD, output frequency range, jitter - ptp, jitter - RMS, output ripple ptp, total harmonic distortion, start-up time, channel separation, reference voltage, gain error, offset error, gain drift.

[0141] It will also be understood that a design unit (e.g., primary, secondary, tertiary design unit) may be implemented in software or hardware, e.g., as dedicated circuitry. For example, a design unit may be implemented as part of a computer system. The computer system may include a bus or other communication mechanism for communicating information data, signals, and information between various components of the computer system. The components may include input / output (I / O) components that process user (i.e., sender, receiver, service provider) actions, such as selecting a key from a keypad / keyboard or selecting one or more buttons or links, and send corresponding signals to the bus. The I / O components may include output components, such as a display and cursor control (keyboard, keypad, mouse, etc.). A transceiver or network interface may send and receive signals between the computer system and other devices, such as other user devices, merchant servers, or service provider servers, over a network. In one embodiment, transmission is wireless, although other transmission media and methods may be suitable. A processor, which may be a microcontroller, digital signal processor (DSP), or other processing component, processes these various signals, e.g., for display on the computer system or for transmission to other devices over a communication link. The processor may also control the transmission of information such as cookies and IP addresses to other devices.

[0142] The components of a computer system may include a system memory component (e.g., RAM), a static storage component (e.g., ROM), and / or a disk drive (e.g., solid state drive, hard drive). The computer system performs certain operations through a processor and other components by executing one or more sequences of instructions contained in the system memory component.

[0143] Logic may be encoded in a computer-readable medium, which may refer to any medium that participates in providing instructions to a processor for execution. Such media may take many forms, including but not limited to non-volatile media, volatile media, and transmission media. In various implementations, non-volatile media include optical or magnetic disks, volatile media include dynamic memory such as system memory components, and transmission media include coaxial cables, copper wire, and fiber optics. In one embodiment, logic is encoded in a non-transitory computer-readable medium. In one example, transmission media may take the form of acoustic or light waves, such as those generated during radio wave, optical, and infrared data communications.

[0144] Common forms of computer-readable media include, for example, floppy disks, flexible disks, hard disks, magnetic tape, other magnetic media, CD-ROMs, other optical media, punch cards, paper tape, other physical media with patterns of holes, RAM, PROM, EPROM, Flash-EPROM, other memory chips or cartridges, or other media designed to be read by a computer.

[0145] In various embodiments of the present disclosure, execution of sequences of instructions for practicing the present disclosure may be performed by a computer system. In various other embodiments of the present disclosure, multiple computer systems 600 coupled by communication links to a network (e.g., a LAN, a WLAN, a PTSN, and / or various other wired or wireless networks including telecommunications, mobile, and cellular networks) may cooperate with each other to execute sequences of instructions for practicing the present disclosure.

[0146] It will also be understood that aspects of the present disclosure may be implemented using hardware, software, or a combination of hardware and software. Furthermore, where applicable, various hardware and / or software components described herein may be combined into composite components consisting of software, hardware, and / or both, without departing from the spirit of the present disclosure. Furthermore, where applicable, various hardware and / or software components described herein may be separated into subcomponents consisting of software, hardware, or both, without departing from the scope of the present disclosure. Furthermore, where applicable, software components may be implemented as hardware components, and vice versa.

[0147] Software according to the present disclosure, such as program code and / or data, may be stored on one or more computer-readable media. It is also contemplated that the software specified herein may be implemented using one or more networked and / or other general-purpose or special-purpose computers and / or computer systems. Where applicable, the order of various steps described herein may be changed, combined into composite steps, and / or separated into substeps to provide the features described herein.

[0148] Various features and steps described herein may be implemented as a system including one or more memories storing various information described herein, and one or more processors coupled to the one or more memories and a network, the one or more processors operable to perform the steps described herein, as a non-transitory machine-readable medium including a plurality of machine-readable instructions that, when executed by the one or more processors, are adapted to cause the one or more processors to perform methods including the steps described herein, and methods performed by one or more devices, such as hardware processors, user devices, servers, and other devices described herein.

[0149] Other examples and variations of the apparatus and methods described herein will be apparent to those of ordinary skill in the art in the context of this disclosure.

Claims

1. An analog circuit design device, a primary design unit and a plurality of secondary design units; The primary design unit comprises: Obtaining information that represents the technical requirements for the analog circuit; Identifying a plurality of circuit portions for forming the analog circuit based on the acquired information; For each circuit portion of the plurality of circuit portions, determining a respective engineering criterion for the circuit portion; providing each of the technical criteria for each of the circuit portions to at least one of the plurality of secondary design units; Each of the plurality of secondary design units of the analog circuit design device comprises: designing each circuit portion of the plurality of circuit portions based on the engineering criteria for each circuit portion provided by the primary design unit; outputting a resulting initial design for each of said circuit portions; After an initial design of at least a predetermined circuit portion is completed by at least one other secondary design unit, at least one of the secondary design units is configured to adapt the output initial design based on a context of the corresponding circuit portion, the context including technical criteria generated based on the completed design of the predetermined circuit portion completed by the at least one other secondary design unit; The primary design unit further comprises: receiving a respective design for each of the circuit portions from at least one of the plurality of secondary design units; generating an initial design for at least the analog circuit based on the received design; at least one of the plurality of secondary design units is configured to design each of the plurality of circuit portions based on the technical criteria for each circuit portion provided by the primary design unit by performing a lookup in a database of designed circuits and / or circuit portions for circuit portions that meet the technical criteria; Analog circuit design equipment.

2. 2. The analog circuit design device according to claim 1, each said secondary design unit is configured to repeat the step of adapting the design of a corresponding circuit portion if a change in the design of another circuit portion of the plurality of circuit portions causes a change in the context of the circuit portion corresponding to the secondary design unit; Analog circuit design equipment.

3. 3. The analog circuit design device according to claim 2, each said secondary design unit is configured to repeat said step of adapting the design of the corresponding said circuit portion only if the change in context is greater than a selected threshold level; Analog circuit design equipment.

4. 4. The analog circuit design device according to claim 1, each said secondary design unit is configured to adapt the design of a corresponding said circuit portion only after at least an initial design of the corresponding said circuit portion has been completed by all said secondary design units; Analog circuit design equipment.

5. 5. The analog circuit design device according to claim 1, the primary design unit is configured to obtain a context for the circuit portion corresponding to the secondary design unit by simulating the performance of the given circuit portion completed by at least one other of the secondary design units; Analog circuit design equipment.

6. 6. The analog circuit design device according to claim 1, each said secondary design unit is configured to obtain a context for a corresponding circuit portion by simulating the performance of said given circuit portion completed by at least one other said secondary design unit; Analog circuit design equipment.

7. 7. The analog circuit design device according to claim 1, The analog circuit design device further comprises a plurality of tertiary design units; At least one of the plurality of primary design units and / or secondary design units: Identifying a plurality of circuit subportions for forming said analog circuit based on received technical criteria; determining, for each circuit sub-portion of the plurality of circuit sub-portions, a respective technical sub-criteria for the circuit sub-portion; providing each technical sub-criteria for each circuit sub-portion to at least one of a plurality of tertiary design units; further configured to design a respective circuit sub-portion of at least one of the plurality of circuit portions based on the engineering criteria for the respective circuit portion provided by the primary design unit; Each of the plurality of tertiary design units of the analog circuit design device comprises: designing each circuit sub-portion based on the technical sub-criteria for each circuit sub-portion provided by the secondary design unit; outputting a resulting design for each of the circuit subportions. Analog circuit design equipment.

8. 8. The analog circuit design device according to claim 7, After at least an initial design of a given circuit sub-portion is completed by at least another one of the tertiary design units, at least one of the tertiary design units is configured to adapt an initial output design based on a context of the circuit sub-portion, the context including technical sub-criteria generated based on the completed design of the given circuit sub-portion completed by at least another one of the tertiary design units. Analog circuit design equipment.

9. 9. The analog circuit design device according to claim 7, Each of the secondary and / or tertiary design units comprises: Verify whether the corresponding designed circuit portion meets the corresponding technical standards; outputting the generated design when each of the designed circuit portions meets the technical criteria; and adapting the design of each of the circuit portions when the respective circuit portions do not meet the technical criteria. Analog circuit design equipment.

10. 10. The analog circuit design device according to claim 1, Each of the secondary design units comprises: simulating an analog circuit based on each corresponding designed circuit portion design to generate at least one simulation output; Verifying whether the circuit portion meets the corresponding technical standards; outputting the generated design when the simulated performance of each of the circuit portions meets the engineering criteria; and when the simulated performance of each of the circuit portions does not meet the engineering criteria, adapting the design of each of the circuit portions based on a difference between the simulated performance and the engineering criteria. Analog circuit design equipment.

11. 11. The analog circuit design device according to claim 1, The primary design unit comprises: simulating an analog circuit based on the generated initial design to generate at least one simulation output; Verifying whether the analog circuit satisfies the technical requirements of the analog circuit; outputting the generated design if the analog circuit meets the technical requirements; When the analog circuit does not meet the technical requirements, For at least one affected circuit portion of the plurality of circuit portions, determining modified engineering criteria for the affected circuit portion based on the simulation output and the engineering requirements; providing the revised engineering criteria for each affected circuit portion to at least one corresponding secondary design unit; receiving an updated design for each of the affected circuit portions from at least one corresponding said secondary design unit; updating said set of designs with respective updated designs for each affected circuit portion; repeating the steps of simulating, verifying, and outputting for the updated set of designs. Analog circuit design equipment.

12. 12. The analog circuit design device according to claim 1, the primary design unit and / or the secondary design unit are configured to adjust the technical criteria of the corresponding circuit portion of at least one of the secondary design units based on the context of the corresponding circuit portion of at least one of the secondary design units; at least one of the secondary design units is configured to adapt the design of the corresponding circuit portion based on the adjusted technical criteria of the corresponding circuit portion received from the primary design unit; Analog circuit design equipment.

13. 1. A method for designing an analog circuit, comprising: The method includes: obtaining information describing technical requirements for the analog circuit; Identifying a plurality of circuit portions for forming the analog circuit based on the acquired information; For each circuit portion of the plurality of circuit portions, determining a respective engineering criterion for the circuit portion; providing each of the technical criteria for each of the circuit portions to at least one of a plurality of secondary design units; In each of the plurality of secondary design units of the analog circuit design device, designing each circuit portion of the plurality of circuit portions based on the engineering criteria for each circuit portion provided by the primary design unit; outputting a resulting design for each said circuit portion; after an initial design of at least a predetermined circuit portion is completed by one of the secondary design units, designs of further circuit portions by further secondary design units are adapted based on a context for the further circuit portions, the context including technical criteria generated based on the completed design of the predetermined circuit portion; In the primary design unit, receiving a respective design of each circuit portion from at least one of a plurality of secondary design units; generating at least an initial design of the analog circuit based on the received design; In at least one of the plurality of secondary design units, designing each of a plurality of circuit portions based on the technical criteria for each circuit portion provided by the primary design unit by performing a lookup in a database of designed circuits and / or circuit portions for circuit portions that meet the technical criteria; method.

14. 14. The method of claim 13, adapting the initial design of the given circuit portion based on the context of the given circuit portion, the context including technical criteria generated based on the adapted design of the further circuit portion. method.

15. 15. The method of claim 13 or 14, repeating the step of adapting the design of another circuit portion of the plurality of circuit portions if a change in the design of the other circuit portion causes a change in the context of the further circuit portion. method.

16. 16. The method of claim 15, repeating the step of adapting the design of the further circuit portion occurs only if the change in context is greater than a selected threshold level. method.

17. 17. The method according to any one of claims 13 to 16, and adapting the design of the circuit portion output from each of the plurality of secondary design units based on a respective context after at least an initial design of the corresponding circuit portion has been completed by each of the secondary design units. method.

18. 18. The method of any one of claims 13 to 17, the design of the further circuit portion is adapted only after all other portions of the circuit have been designed by the plurality of secondary design units based on corresponding technical criteria; method.

19. 19. The method of any one of claims 13 to 18, the technical criteria for each of the circuit portions are provided to all of the secondary design units in parallel; method.

20. 20. The method of any one of claims 13 to 19, the technical criteria for each of the circuit portions are transmitted from the primary design unit to at least one of the secondary design units and from the at least one secondary design unit to further secondary design units; method.

21. 21. The method of any one of claims 13 to 20, the context of the further circuit portion is obtained by simulating the performance of the given circuit portion; method.

22. 22. The method of any one of claims 13 to 21, designing each circuit portion of the plurality of circuit portions in each of the plurality of secondary design units includes: Identifying a plurality of circuit subportions for forming said analog circuit based on received technical criteria; determining, for each circuit sub-portion of the plurality of circuit sub-portions, a respective technical sub-criteria for the circuit sub-portion; providing each technical sub-criteria for each circuit sub-portion to at least one of a plurality of tertiary design units; In each of the plurality of tertiary design units of the analog circuit design device, designing each circuit sub-portion based on technical sub-criteria for each circuit sub-portion provided by the secondary design unit; outputting the resulting design of each circuit subportion. method.

23. 23. The method of claim 22, after at least an initial design of a given circuit sub-portion is completed by one of the tertiary design units, designs of further circuit sub-portions by further tertiary design units are adapted based on a context of the further circuit sub-portion, the context including technical sub-criteria generated based on the completed design of the given circuit sub-portion; method.

24. 24. The method of claim 22 or 23, In each of the plurality of secondary design units or tertiary design units of the analog circuit design device, Verifying whether each of the corresponding designed circuit portions meets the corresponding technical standards; outputting the generated design when each of the designed circuit portions meets the technical criteria; and adapting the design of the respective circuit portion if the respective circuit portion does not meet the technical criteria. method.

25. 25. The method of any one of claims 22 to 24, In each of the plurality of secondary or tertiary design units of the analog circuit design device, simulating the analog circuit based on each corresponding designed circuit portion design to generate at least one simulation output; Verify whether the circuit portion meets the corresponding technical standards; outputting the generated design when the simulated performance of each circuit portion meets the engineering criteria; and when the simulated performance of the respective circuit portion does not meet the engineering criteria, adapting the design of the respective circuit portion based on a difference between the simulated performance and the engineering criteria. method.

26. 26. The method of any one of claims 13 to 25, In the primary design unit, simulating an analog circuit based on the generated initial design to generate at least one simulation output; Verifying whether the analog circuit meets the technical requirements for the analog circuit; outputting the generated design if the analog circuit meets the technical requirements; If the analog circuit does not meet the technical requirements, For at least one affected circuit portion of the plurality of circuit portions, determining revised engineering criteria for the affected circuit portion based on the simulation output and the engineering requirements; providing the revised engineering criteria for each of the affected circuit portions to at least one corresponding secondary design unit; receiving an updated design for each of the affected circuit portions from at least one corresponding secondary design unit; updating the set of designs with the updated designs for each of the affected circuit portions; repeating the steps of simulating, verifying, and outputting for the updated set of designs. method.

27. 27. The method of any one of claims 13 to 26, the context includes information related to parameters and variables experienced by the corresponding portion of the circuit when used with at least some of the other portions of the circuit; method.

28. 28. The method of any one of claims 13 to 27, the portions of the circuit are selected based on the functionality provided by the portions of the circuit; method.

29. 29. The method of any one of claims 13 to 28, Adapting the design of the selected portion of the circuit based on the context of the portion includes adjusting the technical criteria of the selected portion of the circuit. method.

30. 30. The method of any one of claims 13 to 29, fabricating an analog circuit for the output design; method.

31. A computer-readable non-transitory storage medium comprising a program for a computer configured to cause a processor to perform the method of any one of claims 13 to 30.

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