Method for producing porous silicon structure

Abstract

To provide a manufacturing method of a porous silicon structure body, capable of securing accuracy and stability of an etching depth of the porous silicon structure body, and significantly improving a production yield.SOLUTION: A manufacturing method of a porous silicon structure body, forms an epitaxial layer 200 onto a substrate 100, and forms a protection layer 300 onto the epitaxial layer. The protection layer includes an open region. In the open region, an electrochemical etching is performed to form a porous silicon structure body 400 to the epitaxial layer. By removing the protection layer, a wafer having the porous silicon structure body can be obtained.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a method for manufacturing a porous silicon structure, and more particularly to a method for manufacturing a porous silicon structure that avoids wafer warpage and cracks in the porous silicon. [Background technology]

[0002] Porous silicon is a commonly used material in semiconductor manufacturing and microfabrication, and is widely used in various electronic components and devices due to its excellent thermal insulation and light weight. However, the manufacturing process of porous silicon structures has several technical challenges, such as wafer warpage and crack formation in porous silicon.

[0003] Electrochemical etching is one of the key steps in the fabrication of porous silicon structures. However, etching can cause wafer warpage due to non-uniform stress on the substrate during the etching process. In addition, insufficient etching depth can result in poor thermal retention of porous silicon structures due to insufficient formation of the pore structure in the porous silicon.

[0004] In view of the above circumstances, the present invention provides a method for manufacturing a porous silicon structure that can ensure accuracy and stability in the etching depth of the porous silicon structure and significantly improve the production yield. Summary of the Invention

[0005] An object of the present invention is to provide a method for manufacturing a porous silicon structure. The present invention designs the resistance of the epitaxial layer to be at least 10 times the resistance of the substrate, monitors the lateral etching width of the protective layer during the electrochemical etching process, estimates the etching depth of the porous silicon structure, and determines whether to stop the electrochemical etching based on the etching depth of the porous silicon structure. This ensures accuracy and stability of the etching depth of the porous silicon structure. This not only avoids wafer warpage and the formation of cracks in the porous silicon structure, but also significantly improves production yield.

[0006] To achieve the above object, the present invention discloses a method for manufacturing a porous silicon structure, including the steps of forming an epitaxial layer on a substrate, forming a protective layer having an opening region on the epitaxial layer, performing electrochemical etching in the opening region to form a porous silicon structure in the epitaxial layer, and removing the protective layer.

[0007] In an embodiment of the present invention, when the electrochemical etching is performed, the etching rate of the epitaxial layer is 10 times or more the etching rate of the substrate.

[0008] In an embodiment of the present invention, the resistance value of the epitaxial layer is 10 times or more the resistance value of the substrate.

[0009] In an embodiment of the present invention, the thickness of the epitaxial layer is from 20 micrometers (μm) to 80 micrometers.

[0010] In an embodiment of the present invention, the substrate is a silicon substrate.

[0011] In an embodiment of the present invention, the epitaxial layer is a P-type doped epitaxial layer.

[0012] In an embodiment of the present invention, the thickness of the protective layer is from 200 nanometers (nm) to 500 nanometers.

[0013] In an embodiment of the present invention, the electrochemical etching involves anodically etching the epitaxial layer using an etching solution consisting of hydrofluoric acid (HF) and ethanol (C2H5OH).

[0014] In an embodiment of the present invention, the epitaxial layer has a porous silicon region and a non-porous silicon region, and the thickness of the porous silicon region is the same as the thickness of the non-porous silicon region.

[0015] Those skilled in the art can understand other objects of the present invention, as well as the technical means and embodiments of the present invention, by referring to the drawings and the embodiments described below. [Brief explanation of the drawings]

[0016] [Figure 1] 1 is a cross-sectional view of a wafer according to the present invention before etching; [Figure 2] 1 is a cross-sectional view of a wafer according to the present invention after etching; [Figure 3] FIG. 1 is a cross-sectional view of a wafer according to the present invention after etching and removal of the protective layer. DETAILED DESCRIPTION OF THE INVENTION

[0017] The present invention will be described below through examples. Note that the examples of the present invention are merely examples of embodiments and are not intended to limit the present invention to the environments, applications, or specific aspects described in the examples. Therefore, the explanation of the examples is intended to explain the present invention, but does not limit the present invention. Note that components not directly related to the present invention are omitted and not shown in the embodiments and drawings. The dimensional relationships between the components in the drawings are intended to facilitate understanding and do not limit the actual dimensions.

[0018] 1 to 3 are cross-sectional views showing each stage of a manufacturing process for a porous silicon (PS) structure. First, an epitaxial layer 200 is formed on a substrate 100, and a protective layer 300 is formed on the epitaxial layer 200. The substrate 100 is a silicon substrate. The epitaxial layer 200 is a P-type doped epitaxial layer.

[0019] In the present invention, to avoid wafer warpage and crack formation in the porous silicon structure, the resistivity of the epitaxial layer 200 should be at least 10 times that of the substrate 100. The thickness of the epitaxial layer 200 should be between 20 micrometers (μm) and 80 micrometers. The thickness of the substrate 100 is typically 500 micrometers or more.

[0020] In another embodiment, the optimum resistivity of epitaxial layer 200 is 10 to 15 times the resistivity of substrate 100. The optimum thickness of epitaxial layer 200 is 40 to 50 micrometers.

[0021] The thickness of the protective layer 300 is typically 200 nanometers (nm) to 500 nanometers. The protective layer 300 has an open region 310. Electrochemical etching is performed in the open region 310 to form a porous silicon structure 400 in the epitaxial layer 200. The initial width D1 of the open region 310 is the same as the width D5 of the porous silicon structure 400. In the electrochemical etching, the epitaxial layer 200 is anodic etched using an etching solution consisting of hydrofluoric acid (HF) and ethanol (C2H5OH).

[0022] As shown in FIGS. 1 and 2, the protective layer 300 is a silicon nitride dielectric layer. During the electrochemical etching process, the protective layer 300 shrinks on both sides. The shrinkage distance of the protective layer 300 is monitored, and the etching depth of the porous silicon structure is calculated from the lateral etching width of the protective layer 300. The lateral etching width D3 of the protective layer 300 is equal to the etching depth D4 of the porous silicon structure. When the lateral etching width D3 reaches a length equal to the desired etching depth D4, the etching is immediately stopped. This ensures the accuracy and stability of the etching depth of the porous silicon structure 400.

[0023] In an embodiment of the present invention, the etching depth D4 of the porous silicon structure 400 is the same as the thickness of the epitaxial layer 200. Specifically, the epitaxial layer 200 has a porous silicon region 210 and a non-porous silicon region 230. The porous silicon structure 400 is located in the porous silicon region. The thickness of the porous silicon region is the same as the thickness of the epitaxial layer.

[0024] Because the protective layer 300 shrinks during the electrochemical etching process, the post-etch width D2 of the opening region 310 is wider than the initial width D1 of the opening region 310. Also, during electrochemical etching, the etching rate of the epitaxial layer 200 is more than 10 times faster than the etching rate of the substrate 100. In other words, when the electrochemical etching reaches the substrate 100, the etching rate slows down and eventually stops.

[0025] Finally, after the electrochemical etching is completed, the protective layer 300 is removed, resulting in a wafer having a porous silicon structure 400 .

[0026] As described above, the method for manufacturing a porous silicon structure according to the present invention involves designing the resistance of a P-type doped epitaxial layer to be at least 10 times the resistance of a P-type silicon substrate, and providing a silicon nitride dielectric layer as a protective layer on the P-type doped epitaxial layer. The protective layer has an opening region for electrochemical etching. The lateral etching width of the protective layer is monitored during the electrochemical etching process to estimate the etching depth of the porous silicon structure, and a decision is made as to whether to stop the electrochemical etching based on the etching depth of the porous silicon structure. This ensures accuracy and stability of the etching depth of the porous silicon structure. This not only avoids wafer warpage and crack formation in the porous silicon structure, but also significantly improves production yield.

[0027] The above examples are intended to explain embodiments of the present invention and to explain the characteristic configurations of the present invention. The present invention is not limited to the above examples. Modifications or equivalent arrangements that can be easily made by those skilled in the art are also within the scope of the present invention. The scope of protection of the rights of the present invention is based on the claims. [Explanation of symbols]

[0028] 100 boards 200 epitaxial layer 210 Porous silicon region 230 Non-porous silicon region 300 protective layer 310 Opening area 400 Porous silicon structure D1 initial width D2 Width after etching D3 Lateral etching width D4 Etching depth D5 Width of porous silicon structure

Claims

1. A method for manufacturing a porous silicon structure, comprising the steps of: forming an epitaxial layer on a substrate; forming a protective layer having an open region on the epitaxial layer; performing electrochemical etching in the open areas to form porous silicon structures in the epitaxial layer; removing the protective layer; A method for producing a porous silicon structure, wherein the etching rate of the epitaxial layer is at least 10 times the etching rate of the substrate when the electrochemical etching is performed.

2. A method for producing a porous silicon structure, comprising: forming an epitaxial layer on a substrate; forming a protective layer having an open region on the epitaxial layer; performing electrochemical etching in the open areas to form porous silicon structures in the epitaxial layer; removing the protective layer; 10. A method for producing a porous silicon structure, wherein the resistance of the epitaxial layer is at least 10 times the resistance of the substrate.

3. 2. The method for producing a porous silicon structure according to claim 1, wherein the thickness of the epitaxial layer is from 20 micrometers (μm) to 80 micrometers.

4. 2. The method for producing a porous silicon structure according to claim 1, wherein the substrate is a silicon substrate.

5. 2. The method for producing a porous silicon structure according to claim 1, wherein the epitaxial layer is a P-type doped epitaxial layer.

6. 2. The method for manufacturing a porous silicon structure according to claim 1, wherein the thickness of the protective layer is 200 to 500 nanometers (nm).

7. In the electrochemical etching, hydrofluoric acid (HF) and ethanol (C ２ H ５ 2. The method for producing a porous silicon structure according to claim 1, wherein the epitaxial layer is anodic etched using an etching solution containing HCl, HCl(OH), and HCl(OH).

8. 2. The method for manufacturing a porous silicon structure according to claim 1, wherein the epitaxial layer has a porous silicon region and a non-porous silicon region, and the thickness of the porous silicon region is the same as the thickness of the non-porous silicon region.

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