Printed wiring board manufacturing method and semiconductor package manufacturing method

Abstract

To provide a method for manufacturing a printed wiring board which is excellent in forming accuracy, can form a circuit pattern having high adhesion, and is excellent in working environment, and a method for manufacturing a semiconductor package using the printed wiring board obtained by the manufacturing method.SOLUTION: There are provided a method of manufacturing a printed wiring board including specific steps 1 to 6 in this order and a method of manufacturing of a semiconductor package using the printed wiring board obtained by the manufacturing method.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] The present embodiment relates to a method for manufacturing a printed wiring board and a method for manufacturing a semiconductor package. [Background technology]

[0002] The information society has seen remarkable development in recent years, with consumer devices such as personal computers and mobile phones becoming smaller, lighter, and more powerful and functional. Meanwhile, industrial devices, including network-related equipment such as wireless base stations, optical communication devices, servers, and routers, are demanding improved functionality regardless of their size. Furthermore, as the volume of information transmitted increases, the signals they handle tend to become higher in frequency, spurring the development of high-speed processing and transmission technologies. For example, along with the increasing speed and functionality of large-scale integration (LSI) devices such as central processing units (CPUs), digital signal processing (DSPs), and various types of memory, new high-density packaging technologies such as system-on-chip (SoC) and system-in-package (SiP) are being actively developed. Therefore, to accommodate higher frequencies, higher-density wiring, and higher functionality, build-up multilayer wiring boards with fine wiring widths and spaces (L / S) have begun to be used for semiconductor chip mounting substrates and motherboards.

[0003] In recent years, the semi-additive process (SAP, hereinafter also referred to as the "SAP process") has generally been considered useful for forming fine wiring. In the semi-additive process, first, an electroless copper plating layer called a seed layer is provided on an insulating resin, and then a dry film resist layer is provided on the copper plating layer. Then, a resist pattern is formed by exposure through a photomask (photolithography) or by direct drawing and exposure with laser light. Next, after performing plasma treatment as needed, a circuit pattern is formed by electrolytic copper plating in areas where there is no resist pattern, the resist pattern is removed, and finally, the seed layer in unnecessary areas is removed by etching (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2017-208471 Summary of the Invention [Problem to be solved by the invention]

[0005] In conventional SAP processes, a seed layer with a certain thickness, for example, 0.5 μm or more, must be formed to fully function as a seed layer. However, a thick seed layer increases the amount of etching required to remove unnecessary seed layer, resulting in a problem of increased circuit pattern miniaturization. Another possible method is to reverse-calculate the circuit pattern miniaturization and design the circuit pattern width before etching to be thicker. However, this requires reducing the resist pattern width, which can lead to problems such as poor resist pattern adhesion. This problem becomes more pronounced as the L / S becomes smaller. Furthermore, as the L / S becomes smaller, it becomes more difficult to completely remove the seed layer, resulting in problems such as a loss of insulation reliability due to seed layer residue. On the other hand, simply reducing the thickness of the seed layer makes it difficult to form a uniform seed layer, as pinholes, voids, etc. may occur in the seed layer. Furthermore, the increase in etching amount when thickening the seed layer and the occurrence of pinholes when thinning the seed layer can cause undercutting, peeling, etc. of the circuit pattern, leading to a decrease in the adhesion of the circuit pattern. In particular, the seed layer formed by electroless copper plating using conventional methods is subject to accelerated oxidation by palladium, which is an electroless copper plating catalyst present in the vicinity, making the problems of undercutting and peeling of the circuit pattern even more pronounced. Furthermore, after etching the seed layer to form a circuit pattern, CZ treatment is generally performed as a pretreatment for forming an insulating resin such as a solder resist or build-up material on the circuit pattern. CZ treatment is a roughening treatment performed by etching, for example, to a depth of about 1.0 to 1.5 μm. This treatment further promotes undercutting and peeling of the circuit pattern. Furthermore, in the conventional SAP method, the electroless copper plating solution used to form the seed layer contains highly toxic compounds such as formalin and cyanide compounds. From the viewpoint of improving the working environment and safety, a method that does not use these compounds is desired.

[0006] Therefore, an object of the present embodiment is to provide a method for manufacturing a printed wiring board that is excellent in formation accuracy, can form a circuit pattern with high adhesion, and is excellent in the working environment, and a method for manufacturing a semiconductor package that uses a printed wiring board obtained by this manufacturing method. [Means for solving the problem]

[0007] As a result of extensive research into solving the above problems, the present inventors have found that the above problems can be solved by the present embodiment described below. That is, this embodiment relates to the following [1] to [6]. [1] A method for producing a printed wiring board, comprising the following steps 1 to 6 in this order: Step 1: A step of providing an insulating material pattern and an insulating material pattern non-forming portion, which is a space corresponding to the gap between the insulating material patterns and exposes the surface (S1), on a surface (S1) of a substrate selected from a composite material containing a glass cloth and a cured product of a thermosetting resin, and a composite material with an adhesive auxiliary layer formed on the surface of the composite material. Step 2: A step of forming a first catalyst-adhered surface (S3) by adhering a first catalyst onto a surface (S2) composed of the surface of the insulating material pattern and a portion of the surface (S1) exposed in the insulating material pattern non-forming portion. Step 3: A step of contacting the first catalyst-adhered treated surface (S3) with an electroless nickel plating solution using hypophosphite as a reducing agent to form a second catalyst-adhered treated surface (S4) having a second catalyst containing at least nickel attached thereto. Step 4: A step of contacting the second catalyst-adhered surface (S4) with an electroless copper plating solution containing hypophosphite as a reducing agent to form a seed layer on the second catalyst-adhered surface (S4). Step 5: A step of electrolytic copper plating the surface of the seed layer to form a copper layer on the seed layer. Step 6: A step of removing the copper layer, the seed layer, the first catalyst, and the second catalyst adhering to the upper surface of the insulating material pattern, thereby obtaining a circuit pattern formed in the insulating material pattern non-forming portion. [2] The method for producing a printed wiring board according to [1] above, further comprising the following step 7: Step 7: A step of laminating an insulating resin material on the insulating material pattern and the circuit pattern. [3] The method for producing a printed wiring board according to the above [1] or [2], wherein the pH of the electroless nickel plating solution is 7 to 10. [4] The method for producing a printed wiring board according to any one of the above [1] to [3], wherein the phosphorus content in the second catalyst is 6 mass % or less. [5] The method for producing a printed wiring board according to any one of the above [1] to [4], wherein the seed layer has a thickness of 0.4 μm or less. [6] A method for producing a semiconductor package, comprising producing a printed wiring board by the method for producing a printed wiring board according to any one of [1] to [5] above, and mounting a semiconductor element on the printed wiring board. [Effects of the Invention]

[0008] According to the present embodiment, it is possible to provide a method for manufacturing a printed wiring board that is excellent in formation accuracy, can form a circuit pattern with high adhesion, and is excellent in the working environment, and a method for manufacturing a semiconductor package that uses a printed wiring board obtained by this manufacturing method. [Brief explanation of the drawings]

[0009] [Figure 1] 2A to 2C are cross-sectional views illustrating steps of a manufacturing method according to the present embodiment. [Figure 2] 10A to 10C are schematic cross-sectional views showing subsequent steps of the manufacturing method of the present embodiment. [Figure 3] 10A to 10C are schematic cross-sectional views showing subsequent steps of the manufacturing method of the present embodiment. [Figure 4] 10A to 10C are schematic cross-sectional views showing subsequent steps of the manufacturing method of the present embodiment. [Figure 5] 10A to 10C are schematic cross-sectional views showing subsequent steps of the manufacturing method of the present embodiment. [Figure 6] 10A to 10C are schematic cross-sectional views showing subsequent steps of the manufacturing method of the present embodiment. [Figure 7] 10A to 10C are schematic cross-sectional views showing subsequent steps of the manufacturing method of the present embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] In this specification, a numerical range indicated using "to" indicates a range that includes the numerical values ​​before and after "to" as the minimum and maximum values, respectively. For example, the expression "X to Y" (X and Y are real numbers) means a range of values ​​equal to or greater than X and equal to or less than Y. In this specification, the expression "equal to or greater than X" means X and a value greater than X. In this specification, the expression "equal to or less than Y" means Y and a value less than Y. The lower and upper limits of any numerical range described herein may be combined with any lower or upper limit of any other numerical range. In the numerical ranges described in this specification, the lower or upper limit of the numerical range may be replaced with values ​​shown in the examples.

[0011] Unless otherwise specified, each of the components and materials exemplified in this specification may be used alone or in combination of two or more.

[0012] The mechanism of action described in this specification is speculation and does not limit the mechanism by which the effects of this embodiment are achieved.

[0013] In this specification, the term "layer" includes layers that are partially missing and layers in which vias or patterns are formed.

[0014] In this specification, the term "printed wiring board" is a concept that also includes "multilayer printed wiring boards."

[0015] Any combination of the features described in this specification is also included in this embodiment.

[0016] [Printed wiring board manufacturing method and printed wiring board] The method for producing a printed wiring board of this embodiment is a method for producing a printed wiring board that includes the following steps 1 to 6 in this order. Step 1: A step of providing an insulating material pattern and an insulating material pattern non-forming portion, which is a space corresponding to the gap between the insulating material patterns and exposes the surface (S1), on a surface (S1) of a substrate selected from a composite material containing a glass cloth and a cured product of a thermosetting resin, and a composite material with an adhesive auxiliary layer formed on the surface of the composite material. Step 2: A step of forming a first catalyst-adhered surface (S3) by adhering a first catalyst onto a surface (S2) composed of the surface of the insulating material pattern and a portion of the surface (S1) exposed in the insulating material pattern non-forming portion. Step 3: A step of contacting the first catalyst-adhered treated surface (S3) with an electroless nickel plating solution using hypophosphite as a reducing agent to form a second catalyst-adhered treated surface (S4) having a second catalyst containing at least nickel attached thereto. Step 4: A step of contacting the second catalyst-adhered surface (S4) with an electroless copper plating solution containing hypophosphite as a reducing agent to form a seed layer on the second catalyst-adhered surface (S4). Step 5: A step of electrolytic copper plating the surface of the seed layer to form a copper layer on the seed layer. Step 6: A step of removing the copper layer, the seed layer, the first catalyst, and the second catalyst adhering to the upper surface of the insulating material pattern, thereby obtaining a circuit pattern formed in the insulating material pattern non-forming portion.

[0017] According to the method for manufacturing a printed wiring board of this embodiment, the insulating material pattern used to form the circuit pattern is used as an insulating layer without being removed. Therefore, according to the method for manufacturing a printed wiring board of this embodiment, removal of the resist pattern and etching of the seed layer after removing the resist pattern are unnecessary, and problems such as shrinkage of the side surface of the circuit pattern and undercut of the circuit pattern do not occur. Therefore, the printed wiring board manufactured by the manufacturing method of this embodiment has excellent formation precision.

[0018] In addition, in the method for manufacturing a printed wiring board of this embodiment, a circuit pattern is formed on the surface (S1) of a substrate selected from a composite material containing glass cloth and a cured product of a thermosetting resin, and a composite material with an adhesive auxiliary layer formed on the surface of the composite material. Since the composite material containing glass cloth and a cured product of a thermosetting resin has high rigidity, the printed wiring board manufactured by the manufacturing method of this embodiment is one in which the occurrence of warping is suppressed.

[0019] Furthermore, according to conventional methods, when a circuit pattern is formed on the surface of a composite material containing a highly rigid glass cloth and a cured product of a thermosetting resin, sufficient adhesion to the circuit pattern is sometimes not achieved. This is thought to be due to the fact that the composite material is designed to increase rigidity, making it difficult to achieve both this and a material design that increases adhesion to the circuit pattern. On the other hand, the method for manufacturing a printed wiring board of this embodiment includes a step of depositing a first catalyst before forming a seed layer, and then contacting the first catalyst with an electroless nickel plating solution containing hypophosphite as a reducing agent to deposit a second catalyst containing at least nickel. This improves the seed layer's coverage, resulting in excellent adhesion even when the substrate is made of a highly rigid composite material. Furthermore, in a circuit pattern formed by a conventional SAP method, the seed layer is formed from a palladium catalyst and copper, so the copper forming the wiring is electrochemically more base than the seed layer and is easily corroded. On the other hand, in the circuit pattern of the printed wiring board of this embodiment, the seed layer contains nickel, which is electrochemically more base than copper, so the potential difference between the seed layer and the copper forming the wiring is small, making the copper forming the wiring less susceptible to corrosion and achieving high HAST resistance.

[0020] Furthermore, in the method for manufacturing a printed wiring board of this embodiment, an electroless copper plating solution containing hypophosphite as a reducing agent is used to form the seed layer, so there is no need to use highly toxic formalin, cyanide compounds, etc., and this is excellent in improving the working environment and safety.

[0021] Hereinafter, each step of this embodiment will be described in detail with reference to the drawings. In the following description, the same or equivalent parts are denoted by the same reference numerals, and duplicated explanations will be omitted. Furthermore, unless otherwise specified, the positional relationships, such as up, down, left, and right, are based on the positional relationships shown in the drawings. Furthermore, the dimensional ratios of the drawings are not limited to those shown in the drawings.

[0022] <Step 1: Formation of insulating material pattern> Step 1 is a step of providing an insulating material pattern and an insulating material pattern non-forming portion, which is a space corresponding to the gap between the insulating material patterns and exposes the surface (S1), on the surface (S1) of a substrate (hereinafter simply referred to as "substrate") selected from a composite containing glass cloth and a cured product of a thermosetting resin, and a composite with an adhesive auxiliary layer formed on the surface of the composite.

[0023] A preferred method for forming an insulating material pattern on the surface (S1) of the substrate is to form a photosensitive resin layer on the surface (S1) of the substrate, and then expose and develop the photosensitive resin layer.

[0024] FIG. 1(a) shows a step of forming a photosensitive resin layer 2 on a surface S1 of a substrate 1.

[0025] The substrate 1 is a substrate selected from a composite material containing glass cloth and a cured product of a thermosetting resin, and a composite material with an adhesive auxiliary layer formed on the surface of the composite material. When the substrate 1 is a composite material with an adhesive auxiliary layer, the photosensitive resin layer 2 is formed on the surface of the adhesive auxiliary layer.

[0026] The composite material used as the substrate 1 can be a known material used for printed wiring boards, and it is preferable that it is made by, for example, curing a prepreg made by impregnating glass cloth with a resin composition containing a thermosetting resin.

[0027] Examples of thermosetting resins include epoxy resins, phenolic resins, urea resins, melamine resins, alkyd resins, cyanate compounds, bismaleimide compounds, reaction products of bismaleimide compounds with at least one selected from the group consisting of monoamine compounds and diamine compounds, acrylic resins, unsaturated polyester resins, diallyl phthalate resins, polybenzimidazole resins, polyamide resins, polyamideimide resins, silicone resins, resins synthesized from cyclopentadiene, resins containing tris(2-hydroxyethyl)isocyanurate, resins synthesized from aromatic nitriles, trimerized aromatic dicyanamide resins, furan resins, ketone resins, xylene resins, thermosetting resins containing condensed polycyclic aromatic compounds, benzocyclobutene resins, bisallylnadiimide resins, and benzoxazine compounds. In addition to the thermosetting resin, the resin composition may contain a thermoplastic resin, a curing agent, a curing accelerator, an inorganic filler, an organic filler, a flame retardant, a thickener, an ultraviolet absorber, an adhesion promoter, a colorant, etc. Examples of glass cloth include glass cloth made of E glass, C glass, D glass, S glass, etc., glass cloth made of short fibers bonded with an organic binder, and a mixture of glass fibers and cellulose fibers.

[0028] The adhesive auxiliary layer is a layer provided on the surface of the composite material for the purpose of improving the adhesive strength with the insulating material pattern and the circuit pattern, and is also called a primer layer. The adhesive auxiliary layer is not particularly limited as long as it can achieve the purpose of improving adhesive strength, but is preferably formed from a resin composition containing a thermosetting resin. The thickness of the adhesive auxiliary layer is not particularly limited, but is preferably 0.5 to 20 μm, more preferably 0.7 to 15 μm, and even more preferably 1 to 10 μm.

[0029] The thickness of the substrate 1 is not particularly limited, but from the viewpoint of thinning and mechanical strength of the printed wiring board, it is preferably 1 to 500 μm, more preferably 2 to 300 μm, even more preferably 3 to 100 μm, and particularly preferably 5 to 50 μm.

[0030] As the substrate 1, for example, products manufactured by Showa Denko Materials Co., Ltd. such as "GEA-700G(R)", "GEA-795G", "GEA-770G(R)", "GEA-770G(F)", "GEA-705G", "GEA-705G(F)", "GH-200", "GH-100", "GWA-900", and "GWA-910" are commercially available. Furthermore, as the substrate 1 with an adhesive auxiliary layer, for example, products such as "PF-EL" and "PF-EL(SP)" manufactured by Showa Denko Materials Co., Ltd. are commercially available.

[0031] The photosensitive resin layer 2 is preferably formed from a photosensitive resin composition. The method for forming the photosensitive resin layer 2 using the photosensitive resin composition may be, for example, a method of applying a varnish-like photosensitive resin composition to the surface S1 of the substrate 1, or a method of attaching a film-like photosensitive resin composition (hereinafter also referred to as a "photosensitive resin film") to the surface S1 of the substrate 1.

[0032] The photosensitive resin film is, for example, a film formed from a photosensitive resin composition on the surface of a support, and any known photosensitive resin film for forming an insulating layer can be used. As such a photosensitive resin film, for example, "PV-F008" and the like, which are photosensitive build-up films in the PV-F series manufactured by Showa Denko Materials Co., Ltd., are commercially available.

[0033] The photosensitive resin layer 2 can be formed by disposing a photosensitive resin film on the surface S1 side of the substrate 1 and then thermally laminating it using a laminator such as a roll laminator.

[0034] The thickness of the photosensitive resin layer 2 may be appropriately determined depending on the thickness and shape of the circuit pattern to be formed, but is preferably 5 to 100 μm, more preferably 7 to 50 μm, and even more preferably 10 to 30 μm.

[0035] Figure 1(b) illustrates a process of exposing and developing a portion of the photosensitive resin layer 2 to light to form an insulating material pattern 3 and an insulating material pattern non-forming portion 4, which is a space corresponding to the gap between the insulating material patterns 3 and exposes the surface S1.

[0036] The exposure conditions for the photosensitive resin layer 2 are not particularly limited, and may be determined appropriately depending on the type of photosensitive resin composition used to form the photosensitive resin layer 2, etc. After the photosensitive resin layer is exposed to light, the unexposed areas are dissolved and removed with a dilute alkaline aqueous solution, followed by development. If necessary, residues are removed by oxygen plasma ashing, followed by heat treatment and desmearing, to form an insulating material pattern 3 and an insulating material pattern non-forming area 4.

[0037] <Step 2: Attachment of the first catalyst> Step 2 is a step of adhering a first catalyst onto a surface (S2) consisting of the surface of the insulating material pattern and the portion of the surface (S1) exposed in the insulating material pattern non-forming area, thereby forming a first catalyst-adhered treated surface (S3).

[0038] Figures 2(a) and (b) illustrate the process of adhering a first catalyst onto a surface S2 consisting of a surface Sα of the insulating material pattern 3 and a portion Sβ of the surface S1 exposed in the insulating material pattern non-forming portion 4, thereby forming a first catalyst-adhered surface S3. 2(b), the first catalyst-attached surface S3 is shown as a layer for convenience, but the first catalyst does not have to be formed in a layer and is usually scattered on the surface S2. When the first catalyst is scattered, the first catalyst-attached surface S3 does not refer only to the portion where the first catalyst is attached, but refers to the entire surface that has been treated to attach the first catalyst, including the portion where the first catalyst is not attached.

[0039] The first catalyst is a catalyst for accelerating electroless nickel plating, which will be described later. The first catalyst is preferably a palladium catalyst, but is not particularly limited as long as it is a catalyst that promotes electroless nickel plating, as described below. In the following description, an embodiment in which a palladium catalyst is used as the first catalyst will be mainly described.

[0040] The first catalyst can be attached to the surface S2, for example, by treating the surface S2 with an electroless plating catalyst (first catalyst). Specifically, the first catalyst is preferably attached to the surface S2 by subjecting the surface S2 to a cleaning treatment step, a soft etching treatment step, a neutralization treatment step, a treatment step with the electroless plating catalyst (first catalyst), and a reduction treatment step in this order.

[0041] The cleaner treatment step can be carried out, for example, using an alkaline cleaner treatment liquid, preferably at 40 to 70° C. for 1 to 10 minutes, followed by rinsing with hot water and water.

[0042] The soft etching treatment step can be carried out using a treatment solution containing, for example, a sulfuric acid-hydrogen peroxide mixed solution and a sodium persulfate solution, preferably at 15 to 30°C for preferably 0.5 to 2 minutes, followed by rinsing with water.

[0043] The neutralization step can be carried out by treating the surface with, for example, an aqueous sulfuric acid solution, preferably at 20 to 30° C., for preferably 0.5 to 1 minute, followed by washing with water.

[0044] In the treatment step with the electroless plating catalyst (first catalyst), for example, a plating catalyst solution containing a palladium salt can be used. Note that as a pretreatment for applying the electroless plating catalyst, a pre-dip treatment solution may be used, preferably at 20 to 40°C for preferably 0.5 to 2 minutes, followed by treatment with an alkaline palladium application solution, preferably at 30 to 50°C for preferably 3 to 7 minutes, followed by rinsing with water.

[0045] The reduction treatment step can be carried out, for example, by treating the product with a palladium reduction treatment solution, preferably at 20 to 40° C. for preferably 3 to 7 minutes, followed by washing with water.

[0046] The amount of the first catalyst deposited in step 2 is preferably 0.5 to 50 mg / m from the viewpoint of allowing the deposition of the second catalyst in step 3 to proceed appropriately. 2 , more preferably 1 to 30 mg / m 2 , and more preferably 5 to 20 mg / m 2 is.

[0047] <Step 3: Attachment of the second catalyst> Step 3 is a step of contacting the first catalyst-adhered treated surface (S3) with an electroless nickel plating solution using hypophosphite as a reducing agent to form a second catalyst-adhered treated surface (S4) having a second catalyst containing at least nickel attached thereto.

[0048] FIG. 3 illustrates the step of depositing a second catalyst on the first catalyst-deposited treated surface S3 to form a second catalyst-deposited treated surface S4. 3, the second catalyst-attached surface S4 is shown as a layer for convenience, but the second catalyst does not have to be formed in a layer and is usually scattered on the first catalyst-attached surface S3. When the second catalyst is scattered, the second catalyst-attached surface S4 does not refer only to the portion where the second catalyst is attached, but refers to the entire surface that has been treated to attach the second catalyst, including the portion where the second catalyst is not attached.

[0049] The second catalyst mainly contains nickel, but may also contain phosphorus derived from the reducing agent. In this case, this step can be said to be electroless nickel-phosphorus plating. However, in this specification, the step of applying the second catalyst may be referred to as "electroless nickel plating" for convenience.

[0050] The phosphorus content in the second catalyst is preferably as low as possible to facilitate etching, and is preferably 6% by mass or less, more preferably 4% by mass or less, and even more preferably 3% by mass or less. On the other hand, from the viewpoint of ease of production, the phosphorus content in the second catalyst may be 1% by mass or more.

[0051] The electroless nickel plating solution may contain, in addition to a nickel source such as nickel sulfate and a hypophosphite as a reducing agent, a pH adjuster such as sodium hydroxide; a complexing agent such as an organic acid salt; a pH buffer such as an organic acid or an inorganic acid; an accelerator such as a sulfide; a stabilizer; a surfactant; etc. The nickel concentration in the electroless nickel plating solution is, for example, 0.01 to 1.0 g / L. The hypophosphite serving as the reducing agent is preferably sodium hypophosphite. The concentration of the hypophosphite in the electroless nickel plating solution is, for example, 0.1 to 0.5 mol / L. The organic acid salt serving as the complexing agent is preferably a citrate. The concentration of the complexing agent in the electroless nickel plating solution is, for example, 0.01 to 0.1 mol / L. The organic acid that is the pH buffer is preferably boric acid. The concentration of the pH buffer in the electroless nickel plating solution is, for example, 0.1 to 1.0 mol / L. As the electroless nickel plating solution using hypophosphite as a reducing agent, a commercially available plating solution can also be used.

[0052] The temperature at which the first catalyst-adhered treated surface S3 is brought into contact with the electroless nickel plating solution is preferably 20 to 50° C., more preferably 25 to 45° C., and even more preferably 30 to 40° C. When the contact temperature is within the above range, the adhered second catalyst has a low phosphorus content and is easily removed by etching. The time for which the first catalyst-adhered treated surface S3 is brought into contact with the electroless nickel plating solution may be, for example, 5 to 20 minutes, or 10 to 15 minutes.

[0053] The pH of the electroless nickel plating solution is preferably 7 to 10, more preferably 7.5 to 9.5, and even more preferably 8 to 9. When the pH of the electroless nickel plating solution is within the above range, the adhered second catalyst has a low phosphorus content and is easily removed by etching.

[0054] The amount of the second catalyst deposited in step 3 is preferably 10 to 300 mg / m from the viewpoint of appropriately adjusting the thickness of the seed layer in step 4. 2 , more preferably 20 to 200 mg / m 2 , and more preferably 50 to 150 mg / m 2 is.

[0055] <Step 4: Formation of seed layer> Step 4 is a step of contacting the second catalyst-adhered surface (S4) with an electroless copper plating solution containing hypophosphite as a reducing agent to form a seed layer on the second catalyst-adhered surface (S4).

[0056] FIG. 4 shows the step of forming a seed layer 5 on the second catalyst deposition treatment surface S4.

[0057] The electroless copper plating solution to be brought into contact with the second catalyst-adhered surface S4 may contain, in addition to a copper source such as copper sulfate and a reducing agent such as hypophosphite, a pH adjuster such as sodium hydroxide; a complexing agent such as an organic acid salt; a pH buffer such as an organic acid or an inorganic acid; an accelerator such as a metal salt or a sulfide; a stabilizer; a surfactant; etc. The copper concentration in the electroless copper plating solution is, for example, 0.5 to 0.7 g / L. The hypophosphite that serves as the reducing agent is preferably sodium hypophosphite. The concentration of hypophosphite in the electroless copper plating solution is, for example, 0.1 to 0.5 mol / L. The organic acid salt serving as the complexing agent is preferably a citrate. The concentration of the complexing agent in the electroless copper plating solution is, for example, 0.01 to 0.1 mol / L. The organic acid that is the pH buffer is preferably boric acid. The concentration of the pH buffer in the electroless copper plating solution is, for example, 0.1 to 1.0 mol / L. An example of the metal salt that serves as the accelerator is nickel sulfate. As the electroless copper plating solution using hypophosphite as a reducing agent, a commercially available plating solution can also be used.

[0058] The temperature at which the second catalyst-adhered surface S4 is brought into contact with the electroless copper plating solution may be, for example, 30 to 80°C, or 60 to 70°C. The time for which the second catalyst-adhered treated surface S4 is brought into contact with the electroless copper plating solution may be, for example, 5 to 20 minutes, or 10 to 15 minutes. The pH of the electroless copper plating solution is preferably 7 to 10, more preferably 7.5 to 9.5, and even more preferably 8 to 9.

[0059] From the viewpoint of forming a circuit pattern excellent in fine wiring property and insulation reliability, the thickness of the seed layer 5 is preferably 0.4 μm or less, more preferably 0.35 μm or less, and even more preferably 0.3 μm or less. Furthermore, from the viewpoint of fully exhibiting the function as a seed layer, the thickness of the seed layer 5 may be 0.1 μm or more, or may be 0.12 μm or more. In this specification, the thickness of the seed layer refers to the average thickness (n=10) of the seed layer measured by forming a cross section of the seed layer using a focused ion beam (FIB) and observing the cross section with a scanning ion microscope (SIM) at an ion irradiation angle of 45 degrees.

[0060] After the seed layer 5 is formed, in order to remove excess plating solution, washing with water or an organic solvent, drying by heating, or the like may be carried out as necessary.

[0061] <Step 5: Formation of copper layer> Step 5 is a step of electrolytic copper plating the surface of the seed layer to form a copper layer on the seed layer.

[0062] FIG. 5 shows a step of forming a copper layer 6 on the seed layer 5 by electrolytic copper plating.

[0063] As the electrolytic copper plating solution used in the electrolytic copper plating treatment, a commercially available electrolytic copper plating solution such as an electrolytic copper plating solution containing copper sulfate can be used.

[0064] <Step 6: Removal of seed layer and catalyst> Step 6 is a step of obtaining a circuit pattern formed in the non-forming area of ​​the insulating material pattern by removing the copper layer, the seed layer, the first catalyst, and the second catalyst adhering to the upper surface of the insulating material pattern.

[0065] Figure 6 illustrates a process of removing the seed layer 5 and copper layer 6 formed on the upper surface of the insulating material pattern 3, and the first catalyst and second catalyst attached to the upper surface of the insulating material pattern 3, to obtain a circuit pattern 7.

[0066] The copper layer 6, the seed layer 5, the first catalyst and the second catalyst are preferably removed by chemical etching. As a removal liquid for removing the copper layer 6 and the seed layer 5, for example, an acidic etching liquid such as a sulfuric acid-hydrogen peroxide solution etching liquid, a nitric acid-hydrogen peroxide solution etching liquid, or a ferric chloride-hydrochloric acid etching liquid can be used. As a remover for removing the first catalyst and the second catalyst, for example, an acidic etching solution such as a nitric acid-hydrogen peroxide solution, a ferric chloride-hydrochloric acid etching solution, etc. Alternatively, a commercially available etching solution can be used as long as it can remove the first catalyst and the second catalyst. The seed layer 5, the first catalyst, and the second catalyst can also be removed simultaneously using an acidic etching solution such as a nitric acid-hydrogen peroxide solution or a ferric chloride-hydrochloric acid etching solution. The method for removing the copper layer 6, the seed layer 5, the first catalyst, and the second catalyst is not limited to the above method, and they may be removed by, for example, mechanical polishing or CMP (Chemical Mechanical Planarization). Through the above steps, a circuit pattern 7 is formed in the area where the insulating material pattern non-forming portion 4 was formed.

[0067] <Process 7: Multilayering process> The production method of this embodiment preferably further includes the following step 7. Step 7: A step of laminating an insulating resin material on the insulating material pattern and the circuit pattern.

[0068] FIG. 7 illustrates a step of laminating an insulating resin material 8 on the circuit pattern 7 and the insulating material pattern 3 formed in steps 1 to 6.

[0069] The insulating resin material 8 may be the same as or different from the photosensitive resin composition used to form the photosensitive resin layer 2 in step 1. Before laminating the insulating resin material 8, the circuit pattern 7 and the insulating material pattern 3 may be subjected to a surface roughening treatment such as the above-mentioned CZ treatment.

[0070] In the method for manufacturing a printed wiring board according to the present embodiment, the above steps may be repeated to form a multilayer printed wiring board.

[0071] [Semiconductor package manufacturing method] The method for manufacturing a semiconductor package of this embodiment is a method for manufacturing a semiconductor package in which a printed wiring board is manufactured by the method for manufacturing a printed wiring board of this embodiment, and a semiconductor element is mounted on the printed wiring board. The method for manufacturing a semiconductor package of this embodiment is, for example, a method for mounting semiconductor elements such as semiconductor chips and memories at predetermined positions on the printed wiring board of this embodiment, and sealing the semiconductor elements with sealing resin or the like. [Example]

[0072] Next, the present embodiment will be described in more detail with reference to the following examples, but the present embodiment is not limited to these examples. Each step will be described below with reference to FIGS.

[0073] Example 1 (Step 1: Formation of insulating material pattern) As the substrate 1, a substrate made of a composite material containing glass cloth and a cured product of a thermosetting resin (manufactured by Showa Denko Materials Co., Ltd., product name "GEA-770G(R)", thickness 30 μm) was prepared. 1(a), a photosensitive resin film for forming an insulating layer (manufactured by Showa Denko Materials Co., Ltd., product name "PV-F008", thickness 25 μm) was placed on the surface S1 of the substrate 1 so that the photosensitive resin film was in contact with the composite material. Next, lamination was performed by atmospheric pressure lamination under conditions of a roll pressure of 0.4 MPa, a processing temperature of 120°C, and a conveying speed of 1.0 m / s, to form a photosensitive resin layer 2 on the surface S1 of the substrate 1.

[0074] Next, the formed photosensitive resin layer 2 was exposed to 55 mJ / cm 2 using a direct imaging exposure machine "DE-1UH" (product number, manufactured by Via Mechanics Co., Ltd.). 2 The pattern was exposed to light with a line / space of 15 μm / 15 μm under the following conditions: Next, the film was developed by processing it with a 1% sodium carbonate developer at a spray pressure of 0.17 MPa at 30°C for 50 seconds, and then by oxygen plasma ashing to remove any residue. The developed photosensitive resin layer was then heated at 170°C for 60 minutes. Next, as a desmearing treatment, the substrate was immersed in "Swelling Dip Securigant P" (manufactured by Atotech Japan, product name) at 70°C for 5 minutes, then rinsed with hot water for 1 minute, and then rinsed with water for 3 minutes. Next, the substrate was immersed in "Concentrate Compact CP" (manufactured by Atotech Japan, product name) at 70°C for 5 minutes, then rinsed with hot water for 2 minutes, and then rinsed with water for 3 minutes. Subsequently, as a neutralization treatment, the substrate was immersed in "Reduction Solution Securigant P500" (manufactured by Atotech Japan, product name) at 40°C for 5 minutes, then rinsed with water for 3 minutes, thereby forming an insulating material pattern 3 and an insulating material pattern non-forming portion 4 on the surface S1 of the substrate 1, as shown in FIG. 1(b).

[0075] (Step 2: Attachment of the first catalyst) 2(a) and 2(b), a first catalyst was deposited on a surface S2 consisting of a surface Sα of the insulating material pattern 3 and a portion Sβ of the surface S1 exposed in the insulating material pattern non-forming portion 4, to form a first catalyst deposition treated surface S3. Step 2 was performed as follows. First, as a cleaning treatment step, the substrate 1 on which the insulating material pattern 3 was formed was immersed in "Cleaner Securigant 902" (product name, manufactured by Atotech Japan Co., Ltd.) at 60°C for 5 minutes, then rinsed with hot water for 1 minute and then with water for another 3 minutes. Next, as a neutralization treatment step, the specimen was immersed in a 5% sulfuric acid solution at 30°C for 0.5 minutes, followed by rinsing with water for 1 minute. Subsequently, as a treatment step using an electroless plating catalyst, the specimen was immersed in a mixed solution of 20 ml / L of "Pre-Dip Neogant B" (trade name, manufactured by Atotech Japan Co., Ltd.) and 1 ml / L of 98% sulfuric acid at 30°C for 1 minute. Further, the specimen was immersed in a mixed solution of 40 ml / L of "Activator Neogant 834" (trade name, manufactured by Atotech Japan Co., Ltd.), 5 g / L of boric acid solution, and 4 g / L of sodium hydroxide solution at 40°C for 5 minutes, followed by rinsing with water for 1 minute. Subsequently, as a reduction treatment step, the specimen was immersed in a mixed solution of 5 ml / L of "Reducer Neogant WA" (trade name, manufactured by Atotech Japan Co., Ltd.) and 5 g / L of boric acid at 30°C for 5 minutes, followed by rinsing with water for 0.5 minutes. The amount of the first catalyst attached in step 2 was 10 mg / m 2 It was.

[0076] (Step 3: Attachment of the second catalyst) Next, as shown in Figure 3, the first catalyst-adhered surface S3 was contacted with an electroless nickel plating solution containing hypophosphite as a reducing agent to form a second catalyst-adhered surface S4 on which a second catalyst containing at least nickel was adhered. Note that step 3 was carried out as follows. First, an electroless nickel plating solution using sodium hypophosphite as the reducing agent was prepared using an aqueous solution of 0.2 g / L nickel sulfate hexahydrate, 30.0 g / L sodium hypophosphite monohydrate, 25 g / L trisodium citrate, and 30 g / L boric acid. The pH of the electroless nickel plating solution was adjusted to 9 with sodium hydroxide. The substrate 1 to which the first catalyst had been attached in step 2 was immersed in the electroless nickel plating solution at 35°C for 10 minutes to attach the second catalyst to the substrate 1 to which the first catalyst had been attached. The amount of the second catalyst attached in step 3 was 100 mg / m 2 It was.

[0077] (Step 4: Formation of seed layer) 4, the second catalyst-adhered surface S4 was brought into contact with an electroless copper plating solution containing hypophosphite as a reducing agent to form a seed layer 5 on the second catalyst-adhered surface S4. Step 4 was performed as follows. First, an electroless copper plating solution using sodium hypophosphite as the reducing agent was prepared using an aqueous solution of 2.4 g / L copper sulfate pentahydrate, 30.0 g / L sodium hypophosphite monohydrate, 25 g / L trisodium citrate, and 30 g / L boric acid. The pH of the electroless copper plating solution was adjusted to 9 with sodium hydroxide. The substrate 1 to which the second catalyst had been attached in step 3 was immersed in the electroless copper plating solution prepared above at 65°C to perform electroless copper plating, followed by rinsing with water and drying to form a seed layer 5 (thickness 0.30 μm) on the second catalyst-attached surface S4.

[0078] (Step 5: Formation of copper layer) 5, a copper layer 6 was formed on the seed layer 5 by electrolytic copper plating. Step 5 was performed according to the following procedure. The substrate 1 on which the seed layer 5 was formed in step 4 was immersed in a 5% sulfuric acid solution at 30° C. for 10 seconds. Next, an electrolytic copper plating solution (200 g / L of copper sulfate pentahydrate, 50 g / L of 98% sulfuric acid, 40 mg / L of chloride ions, 20 ml / L of "Cu-Brite VF-IIA" (trade name, manufactured by JCU Corporation), and 1 ml / L of "Cu-Brite VF-IIB" (trade name, manufactured by JCU Corporation)) was used at 23° C. and 1.0 A / dm 2 Then, electrolytic copper plating was carried out to form a copper layer 6 (thickness: 10 μm).

[0079] (Step 6: Removal of seed layer and catalyst) 6, the seed layer 5 and copper layer 6 formed on the upper surface of the insulating material pattern 3, and the first catalyst and second catalyst attached to the upper surface of the insulating material pattern 3 were removed to form a circuit pattern 7. Step 6 was performed according to the following procedure. The substrate 1 on which the copper layer 6 was formed in step 5 was etched using a sulfuric acid-hydrogen peroxide etching solution (100 ml / L of 98% sulfuric acid, 100 g / L of DL-malic acid, 30 ml / L of hydrogen peroxide, and 1 g / L of 1,2,3-benzotriazole) at 30°C and a spray pressure of 0.14 MPa to remove the copper layer 6 and the seed layer 5. Next, the first catalyst and the second catalyst were removed using a nitric acid-hydrogen peroxide etching solution (nitric acid 100 ml / L, DL-malic acid 100 g / L, hydrogen peroxide 10 ml / L, 1,2,3-benzotriazole 1 g / L) at 30°C and a spray pressure of 0.14 MPa. In this way, a circuit pattern 7 was formed in the insulating material pattern non-forming portion 4.

[0080] Comparative Example 1 A circuit pattern was formed in the same manner as in Example 1, except that step 3 in Example 1 was not performed.

[0081] [Evaluation of copper layer peel strength] In Example 1, steps 2 to 5 were carried out without forming an insulating material pattern on substrate 1, and a copper layer (thickness: 20 μm) was formed on substrate 1, which was used as test piece 1. In addition, in Comparative Example 1, steps 2, 4 and 5 were carried out without forming an insulating material pattern on substrate 1, and a copper layer (thickness: 20 μm) was formed on substrate 1, which was used as test piece 2. The copper layer of each of the test pieces 1 and 2 was etched into a 5 mm wide straight line, and the straight line copper foil was attached to an autograph AC-100C (Shimadzu Corporation, product number). The copper layer peel strength was measured by peeling the straight line copper layer in a 90° direction at a peeling speed of 50 mm / min. As a result, the copper layer peel strength of test piece 1 was 0.55 kN / m, and the copper layer peel strength of test piece 2 was 0.10 kN / m. This shows that the method for manufacturing a printed wiring board of this embodiment, by carrying out the second catalyst adhesion step, can obtain high adhesion to the copper layer even when the substrate is a composite material containing glass cloth and a cured product of a thermosetting resin. [Explanation of symbols]

[0082] 1 board 2 Photosensitive resin layer 3. Insulating material pattern 4. Insulating material pattern non-forming area 5 Seed layer 6 copper layers 7 Circuit Pattern 8. Insulating resin materials S1 Surface of substrate 1 Sα Surface of insulating material pattern 3 Sβ: a portion of the surface S1 exposed in the insulating material pattern non-forming portion 4 S2 Surface composed of Sα and Sβ S3 First catalyst-treated surface S4 Second catalyst-treated surface

Claims

1. A method for manufacturing a printed wiring board, comprising the following steps 1 to 6 in this order: Step 1: A step of providing an insulating material pattern and an insulating material pattern non-forming portion, which is a space corresponding to the gap between the insulating material patterns and exposes the surface (S1), on a surface (S1) of a substrate selected from a composite material containing a glass cloth and a cured product of a thermosetting resin, and a composite material with an adhesive auxiliary layer formed on the surface of the composite material. Step 2: A step of adhering a first catalyst onto a surface (S2) composed of the surface of the insulating material pattern and the portion of the surface (S1) exposed in the insulating material pattern non-forming portion to form a first catalyst-adhered surface (S3). Step 3: A step of contacting the first catalyst-adhered surface (S3) with an electroless nickel plating solution containing hypophosphite as a reducing agent at 20 to 50°C, and dotting the first catalyst-adhered surface (S3) with a second catalyst containing at least nickel in an amount of 10 to 300 mg / m 2 to form a second catalyst-adhered surface (S4). Step 4: A step of contacting the second catalyst-adhered surface (S4) with an electroless copper plating solution containing hypophosphite as a reducing agent to form a seed layer having a thickness of 0.4 μm or less on the second catalyst-adhered surface (S4). Step 5: A step of electrolytic copper plating the surface of the seed layer to form a copper layer on the seed layer. Step 6: A step of removing the copper layer, the seed layer, the first catalyst, and the second catalyst adhering to the upper surface of the insulating material pattern, thereby obtaining a circuit pattern formed in the insulating material pattern non-forming portion.

2. The method for producing a printed wiring board according to claim 1, further comprising the following step 7: Step 7: Laminating an insulating resin material on the insulating material pattern and the circuit pattern

3. 3. The method for producing a printed wiring board according to claim 1, wherein the electroless nickel plating solution has a pH of 7 to 10.

4. 4. The method for producing a printed wiring board according to claim 1, wherein the second catalyst has a phosphorus content of 6 mass % or less.

5. The method for producing a printed wiring board according to any one of claims 1 to 4, wherein the seed layer has a thickness of 0.1 to 0.35 µm.

6. A method for manufacturing a semiconductor package, comprising manufacturing a printed wiring board by the method for manufacturing a printed wiring board according to any one of claims 1 to 5, and mounting a semiconductor element on the printed wiring board.

Images