Semiconductor Devices

Abstract

To provide a semiconductor device having a structure in which a JFET and a spiral-shaped resistive element are arranged on the same semiconductor chip, the structure being capable of avoiding a variation in resistance value of the resistive element.SOLUTION: A semiconductor device includes:an n+-type drain region 5 at an upper part of a p-type semiconductor base body 1; an n-type drift region 3 in contact with the n+-type drain region 5; an n+-type source region 4 opposed to the n+-type drain region 5 with the n-type drift region 3 interposed therebetween; a p-type gate region 2 in contact with the n-type drift region 3; an interlayer insulating film 9 covering the n-type drift region 3; a resistive element 20 provided inside the interlayer insulating film 9, the resistive element having a spiral-shaped planar shape; a drain electrode wire 11 connected to the n+-type drain region 5 and one end of the resistive element 20; a source electrode wire 12 connected to the n+-type source region 4; a gate electrode wire 10 connected to the p-type gate region 2; and a potential-dividing terminal wire 21 connected to the resistive element 20. The source electrode wire 12 has a portion where a gap d1 between the source electrode wire and an outermost circumference of the resistive element 20 is constant.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] A known startup element, which is a high-voltage device in a startup circuit used in conventional switching power supplies, is a high-voltage junction field-effect transistor (JFET) in which multiple source regions are arranged in a circumferential planar layout around a circular input pad (see Patent Document 1). In Patent Document 1, a JFET and a resistor element connected in parallel to the JFET for monitoring (voltage sensing) the input voltage to the JFET are arranged on the same semiconductor chip.

[0003] The resistive element is connected between the input pad and gate electrode wiring of the JFET. The resistive element is formed of a thin-film resistor such as polysilicon (Poly-Si) arranged in a spiral planar shape on the voltage-resistant structure of the JFET. The resistive element is connected at its inner peripheral end to the VH terminal wiring, which is a high-voltage input line, via a drain contact portion that penetrates the interlayer insulating film on the resistive element. The resistive element is also connected at its outer peripheral end to the ground terminal wiring via a ground contact portion that penetrates the interlayer insulating film. The resistive element is also connected to the voltage-dividing terminal wiring via a voltage-dividing point contact portion that is located more inward than the ground contact portion.

[0004] The voltage divider resistor of the resistive element connects to the non-inverting input terminal of the comparator in the control circuit. By dividing the high input voltage to the VH terminal by, for example, 100:1, the resistors can detect the high input voltage at a low voltage. An example of an application of this high-voltage sensing function is the brownout function. When a switching power supply is unplugged from the outlet and the AC input voltage is cut off, the primary input voltage drops. If the switching power supply continues to operate in this state, the on-time of the MOS switch in the control circuit increases, causing heat generation and, in the worst case, destruction. To prevent this problem, switching power supplies are equipped with a brownout function that stops the power supply's switching operation when the input voltage drops. For example, if the primary input voltage drops, the voltage at the non-inverting input terminal of the comparator connected to the voltage divider point of the voltage divider resistor mentioned above becomes smaller than the voltage at the inverting input terminal connected to the reference power supply. This inverts the driver output signal in the control circuit and goes low, stopping switching operation.

[0005] In Patent Document 2, the ground terminal wiring and the voltage dividing terminal wiring are connected closer to the inner periphery of the resistance element than the outermost periphery, and the source electrode wiring is not covered over the voltage dividing resistor portion that functions as a resistor, thereby suppressing variations in resistance value due to the hydrogen absorption effect of titanium (Ti), which is a barrier metal used for the source electrode wiring, and preventing erroneous detection due to fluctuations in the voltage dividing point. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2008-153636 [Patent Document 2] Patent No. 6657982 specification Summary of the Invention [Problem to be solved by the invention]

[0007] In recent years, there has been an increasing demand for ultra-low standby power in communication devices, home appliances, etc., and technology is being sought to minimize power consumption in switching power supplies both during standby and operation. One way to achieve this is to increase the sheet resistance by reducing the impurity concentration of the polysilicon resistor, which is the resistive element connected to the VH terminal and ground terminal of the startup element, and to form a high-resistance element on the order of several hundred MΩ by increasing the number of turns of the polysilicon resistor as much as possible.

[0008] However, if the sheet resistance of a polysilicon resistor is increased to, for example, about 10 kΩ / □, the proximity of metal wiring such as source electrode wiring to low-impurity polysilicon leads to a resistance shift due to the hydrogen absorption effect of titanium (Ti), resulting in variations in the voltage division point. Furthermore, while the source electrode wiring is arranged concentrically around the circular drain region when viewed from above, the polysilicon resistor is spiral-shaped, meaning that the distance from the outermost voltage division resistor to the source electrode wiring is not constant. The closer to the outer periphery (toward ground potential), the closer it is to the source electrode wiring, which affects variations in resistance. If the source electrode wiring is uniformly moved back toward the periphery to avoid this, the width of the source electrode wiring will be locally narrowed, exceeding the allowable current density and potentially resulting in wiring burnout.

[0009] In view of the above problems, an object of the present invention is to provide a semiconductor device that can suppress variations in the resistance value of a resistor element in a structure in which a JFET and a spiral resistor element are arranged on the same semiconductor chip. [Means for solving the problem]

[0010] One aspect of the present invention is a semiconductor device comprising: (a) a first region of a second conductivity type provided on an upper portion of a semiconductor substrate of a first conductivity type; (b) a second region of the second conductivity type provided on the upper portion of the semiconductor substrate and in contact with the first region; (c) a third region of the second conductivity type provided on the upper portion of the semiconductor substrate, facing the first region across the second region and in contact with the second region; (d) a fourth region of the first conductivity type provided on the upper portion of the semiconductor substrate and in contact with the second region; (e) an interlayer insulating film covering the second region; and (f) a fourth region of the first conductivity type provided inside the interlayer insulating film and having a spiral planar shape. The gist of the present invention is that the semiconductor device comprises a resistive element, (g) a first electrode wiring electrically connected to the first region and one end of the resistive element, (h) a second electrode wiring electrically connected to the third region and provided around the resistive element, (i) a third electrode wiring electrically connected to the fourth region and provided around the resistive element, and (j) a voltage dividing terminal wiring electrically connected to the resistive element, wherein the metal wiring facing the outermost periphery that functions as a resistor of the resistive element has a portion where the distance between the metal wiring and the outermost periphery is constant. [Effects of the Invention]

[0011] According to the present invention, it is possible to provide a semiconductor device that can suppress variations in the resistance value of a resistor element in a structure in which a JFET and a spiral resistor element are arranged on the same semiconductor chip. [Brief explanation of the drawings]

[0012] [Figure 1] 1 is a plan view showing a semiconductor device according to a first embodiment of the present invention. [Figure 2] FIG. 2 is a cross-sectional view taken along the line AA′ in FIG. [Figure 3] FIG. 2 is a cross-sectional view taken along the line BB′ in FIG. [Figure 4] FIG. 2 is an enlarged plan view of an area C in FIG. [Figure 5] FIG. 1 is a plan view showing a semiconductor device according to a first comparative example. [Figure 6] 10 is a graph showing the relationship between the distance between a polysilicon resistor and a metal wiring and the rate of change in the resistance value of the polysilicon resistor. [Figure 7]FIG. 10 is a plan view showing a semiconductor device according to a second comparative example. [Figure 8] FIG. 10 is a cross-sectional view showing a semiconductor device according to a modified example of the first embodiment. [Figure 9] FIG. 10 is a plan view showing a semiconductor device according to a modified example of the first embodiment. [Figure 10] FIG. 10 is a plan view showing a semiconductor device according to a second embodiment. [Figure 11] FIG. 10 is a plan view showing a semiconductor device according to a third embodiment. [Figure 12] FIG. 10 is a plan view showing a semiconductor device according to a fourth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0013] Hereinafter, first to fourth embodiments of the present invention will be described with reference to the drawings. In the description of the drawings, identical or similar parts are designated by identical or similar reference numerals, and redundant explanations will be omitted. However, the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each layer, etc. may differ from the actual ones. Furthermore, parts with different dimensional relationships and ratios may be included between the drawings. Furthermore, the first to fourth embodiments shown below are examples of devices and methods for embodying the technical concept of the present invention, and the technical concept of the present invention does not limit the materials, shapes, structures, arrangements, etc. of component parts to those described below.

[0014] Furthermore, the definitions of directions such as up / down and left / right in the following explanation are merely for the convenience of explanation and do not limit the technical idea of ​​the present invention. For example, if an object is rotated 90 degrees and observed, up / down is converted to left / right and read as such, and if it is rotated 180 degrees and observed, up / down is obviously read as reversed.

[0015] In the following description, the first conductivity type is p-type and the second conductivity type is n-type. However, the conductivity types may be reversed, with the first conductivity type being n-type and the second conductivity type being p-type. The "+" and "-" affixed to "n" and "p" indicate a semiconductor region with a relatively higher or lower impurity concentration, respectively, compared to a semiconductor region without the "+" and "-" affixed. However, semiconductor regions with the same "n" and "n" affixed do not necessarily have the same impurity concentration. Furthermore, in the following description, components and regions with the "first conductivity type" and "second conductivity type" affixed refer to components and regions made of semiconductor material, even if not otherwise explicitly stated.

[0016] (First embodiment) FIG. 1 is a plan view of a semiconductor device according to a first embodiment. FIG. 2 is a cross-sectional view taken along line A-A' in FIG. 1. FIG. 3 is a cross-sectional view taken along line B-B' in FIG. 1. As shown in FIGS. 1 to 3, the semiconductor device according to the first embodiment is an integrated circuit (IC) in which a high-voltage JFET 30 and a resistive element 20 having a spiral (spiral) planar shape are integrated on the same semiconductor chip (p-type semiconductor substrate) 1. The JFET 30 is a startup element of a startup circuit used in a switching power supply device (not shown). The resistive element 20 can implement a brownout function and the like by monitoring (voltage sensing) the input voltage to the JFET 30.

[0017] 2 and 3, the JFET 30 is provided on a p-type semiconductor substrate 1. The p-type semiconductor substrate 1 is made of, for example, a silicon (Si) substrate. The p-type semiconductor substrate 1 may also be made of a semiconductor substrate such as silicon carbide (SiC), gallium nitride (GaN), gallium arsenide (GaAs), or diamond. The p-type semiconductor substrate 1 may also be made of a p-type epitaxial layer provided on a semiconductor substrate.

[0018] On the top of the p-type semiconductor substrate 1, + The p-type semiconductor substrate 1 is selectively provided with an n-type drain region (first region) 5. +In contact with the n-type drain region 5, + An n-type drift region (second region) 3 having a lower impurity concentration than the p-type drain region 5 is selectively provided on the upper portion of the p-type semiconductor substrate 1. + A region having a higher impurity concentration than the n-type drift region 3 is spaced from the n-type drain region 5. + A type source region (third region) 4 is selectively provided. + The n-type source region 4 is in contact with the n-type drift region 3, and has the n-type drift region 3 therebetween. + The n-type drain region 5 faces the n-type drain region 5. + Type source region 4 and n + The n-type drain region 5 is formed to be deeper than the n-type drift region 3, but this is not limited thereto, and the n-type drain region 5 may be formed to be shallower than the n-type drift region 3, or may have the same depth as the n-type drift region 3.

[0019] As shown in FIG. 2, the upper part of the p-type semiconductor substrate 1 is + A p-type gate region (fourth region) 2 is selectively provided in contact with the n-type source region 4. As shown in FIG. 3, the p-type gate region 2 is in contact with the n-type drift region 3. A p-type gate region (fourth region) having a higher impurity concentration than the p-type gate region 2 is provided above the p-type gate region 2. + A p-type contact region 6 is selectively provided. The p-type gate region 2 is formed to be deeper than the n-type drift region 3, but this is not limiting, and the p-type gate region 2 may be formed to be shallower than the n-type drift region 3, or may have the same depth as the n-type drift region 3.

[0020] As shown in Figure 1, + The n-type drain region 5 has a substantially circular planar shape. + The n-type drift region 3 has, for example, a gear-like shape in plan view, and extends into parts (for example, 20 locations) of the p-type gate region 2 with a predetermined width. + The n-type source region 4 +A plurality of p-type gate regions 2 are provided on a circumference at equal intervals from the n-type drain region 5, and are provided at locations where the n-type drift region 3 penetrates. + Type source region 4 and n + In the direction perpendicular to the direction connecting the n-type drain region 5 + The p-type gate region 2 has a planar shape sandwiching the n-type source region 4. + In the portion sandwiching the n-type source region 4, + From the outside of the source region 4, + Type source region 4 to n + It is provided so as to extend to the side of the drain region 5 .

[0021] 2 and 3, an element isolation insulating film 8 such as a local insulating film (LOCOS film) is provided on the n-type drift region 3. A gate polysilicon electrode 7 is provided on the element isolation insulating film 8. As shown in FIG. 1, the gate polysilicon electrode 7 has a ring-shaped planar shape so as to straddle the position where the n-type drift region 3 and the p-type gate region 2 contact each other. The gate polysilicon electrode 7 is electrically connected to a gate electrode wiring 10 (described later) via a gate polysilicon contact portion 25. The gate polysilicon electrode 7 raises the potential of a source electrode wiring 12 (described later) to separate the p-type gate region 2 and the n-type gate region 2. + When the pn junction between the source region 4 and the source electrode wiring 12 is reverse biased, the depletion layer extending from the pn junction is widened, thereby suppressing the potential rise of the source electrode wiring 12.

[0022] As shown in FIGS. 2 and 3, the element isolation insulating film 8, the gate polysilicon electrode 7, and the p + Type contact region 6, n + type source region 4 and n +An interlayer insulating film 9 is provided so as to cover the upper surface of the type drain region 5. Metal wirings, namely, a drain electrode wiring (first electrode wiring) 11, a source electrode wiring 12 (second electrode wiring), and a gate electrode wiring (third electrode wiring) 10, are provided on the interlayer insulating film 9. In FIG. 1, the drain electrode wiring 11, the source electrode wiring 12, and the gate electrode wiring 10 are schematically shown by dotted lines.

[0023] As shown in FIG. 1, the drain electrode wiring 11 is + 2 and 3, the drain electrode wiring 11 has an n-type insulating film 9 therebetween and has a substantially circular planar shape concentric with the n-type drain region 5. + The drain electrode wiring 11 faces the n-type drain region 5. The drain electrode wiring 11 is connected to the n-type drain region 5 via a drain contact portion 14 and a contact plug 18 that penetrate the interlayer insulating film 9. + The drain electrode wiring 11 is electrically connected to the first drain region 5. The drain electrode wiring 11 extends on the interlayer insulating film 9 so as to protrude outward, and faces the innermost part of a resistor element 20 (described later) in the depth direction across the interlayer insulating film 9. As shown in FIG. 2 , the drain electrode wiring 11 is electrically connected to the innermost part of the resistor element 20 via a resistor element contact portion 16 that penetrates the interlayer insulating film 9.

[0024] 1, the gate electrode wiring 10 has a substantially ring-shaped planar shape. The outer periphery of the ring-shaped gate electrode wiring 10 is + The inner periphery of the ring-shaped gate electrode wiring 10 is surrounded by the gear-shaped n-type drift region 3 and the n-type drain region 5. + The inner (n + 2 and 3, the gate electrode wiring 10 faces the p-type gate region 2 in the depth direction with the interlayer insulating film 9 therebetween. As shown in FIG. 3, the gate electrode wiring 10 is connected to the p-type gate region 2 via a gate contact portion 13 and a contact plug 17 that penetrate the interlayer insulating film 9. + The gate electrode wiring 10 is electrically connected to the contact region 6. The gate electrode wiring 10 is always grounded.

[0025] 1, the source electrode wiring 12 has a substantially ring-shaped planar shape, and the ring-shaped planar shape is separated near the position of the outer peripheral end of the resistance element 20. The outer peripheral side of the substantially ring-shaped source electrode wiring 12 is separated from the gate electrode wiring 10 and is connected to the gear-shaped n-type drift region 3 and n + The source electrode wiring 12 extends outward along the source region 4 at a predetermined width. A lead wire 12a is connected to the source electrode wiring 12 for electrical connection to the outside. Although FIG. 1 illustrates an example in which the lead wire 12a is provided on the right side of FIG. 1, the position of the lead wire 12a is not particularly limited. Furthermore, the number of lead wires connected to the source electrode wiring 12 is not limited.

[0026] As shown in FIG. 2, the source electrode wiring 12 is formed in an n-type layer in the depth direction with the interlayer insulating film 9 sandwiched therebetween. + The source electrode wiring 12 is connected to the n-type source region 4 via a source contact portion 15 and a contact plug 19 that penetrate the interlayer insulating film 9. + The source electrode wiring 12 is electrically connected to the gate source region 4. The source electrode wiring 12 extends on the interlayer insulating film 9 so as to protrude inward, and faces the gate polysilicon electrode 7 in the depth direction with the interlayer insulating film 9 therebetween.

[0027] Each of the metal wirings of the gate electrode wiring 10, the drain electrode wiring 11, and the source electrode wiring 12 is a metal laminate film in which, for example, a barrier metal, an aluminum (Al) metal film, and an anti-reflection film are laminated in this order. The portions of the metal laminate film embedded in the contact holes become the gate contact portion 13, the drain contact portion 14, the source contact portion 15, and the resistor element contact portion 16. The contact plugs 17, 18, and 19 are metal laminate films in which a barrier metal and a tungsten (W) film are laminated in this order. The aluminum metal film is a metal film containing aluminum, and may be, for example, an aluminum-copper (Al-Cu) film or an aluminum-silicon-copper (Al-Si-Cu) film.

[0028] The barrier metals of the gate electrode wiring 10, the drain electrode wiring 11, the source electrode wiring 12, etc., have the function of preventing diffusion of metal atoms toward the p-type semiconductor substrate 1 and mutual reaction between the p-type semiconductor substrate 1 and a metal film. The barrier metal may be, for example, a laminated film in which a titanium (Ti) film and a titanium nitride (TiN) film are laminated in this order. The barrier metals of the contact plugs 17, 18, and 19 are silicided (reduced in resistance) by reaction with the semiconductor portion. The anti-reflective film may be a laminated film in which a titanium film and a titanium nitride film are laminated in this order. The anti-reflective film has the function of preventing diffuse reflection of light from the aluminum metal film when exposing a resist mask for patterning the aluminum metal film.

[0029] Each of the metal wirings of the gate electrode wiring 10, the drain electrode wiring 11, and the source electrode wiring 12 may be multi-layer wiring. Fig. 2 shows a case where the drain electrode wirings 11 and 32 are multi-layer wiring. An interlayer insulating film 31 is provided on the interlayer insulating film 9, the gate electrode wiring 10, and the first-layer drain electrode wiring 11 and source electrode wiring 12. A second-layer drain electrode wiring 32 is disposed on the interlayer insulating film 31, facing the first-layer drain electrode wiring 11 in the depth direction with the interlayer insulating film 31 sandwiched therebetween. The second-layer drain electrode wiring 32 is electrically connected to the first-layer drain electrode wiring 11 via a drain contact portion 33 that penetrates the interlayer insulating film 31.

[0030] As shown in FIG. 1, the resistor element 20 has n + The resistor element 20 is provided to surround the periphery of the type drain region 5 and to form a spiral (spiral) planar shape. Although Fig. 1 illustrates a case where the resistor element 20 is right-handed, i.e., clockwise toward the outer periphery, the resistor element 20 may be left-handed, i.e., counterclockwise toward the outer periphery.

[0031] 2 and 3, the resistor element 20 is provided inside the interlayer insulating film 9 in a portion facing the n-type drift region 3 in the depth direction with the element isolation insulating film 8 sandwiched therebetween. The resistor element 20 is provided inside the gate polysilicon electrode 7 and spaced apart from the gate polysilicon electrode 7. As shown in FIG. 2, the innermost portion of the resistor element 20 is electrically connected to the drain electrode wiring 11 via the resistor element contact portion 16 as described above.

[0032] The inner diameter of the resistor element 20 is narrower than the diameter of the drain electrode wiring 11 to such an extent that a resistor element contact portion 16 with the drain electrode wiring 11 can be formed. The outer diameter of the resistor element 20 is narrower than the inner diameter of the source electrode wiring 12 so that the resistor element 20 does not overlap with the source electrode wiring 12. The innermost portion of the resistor element 20 is the spiral line that is located on the innermost side of the spiral line of the resistor element 20 and is not adjacent to any other spiral line on that inner side. The outermost portion of the resistor element 20 is the spiral line that is located on the outermost side of the spiral line of the resistor element 20 and is not adjacent to any other spiral line on that outer side.

[0033] 4 is an enlarged plan view of a region C including the outer peripheral end of the resistor element 20 in FIG. 1. As shown in FIG. 4, the approximately ring-shaped planar shape of the gate electrode wiring 10 is separated near the position of the outer peripheral end of the resistor element 20. As shown in FIGS. 3 and 4, the outer peripheral end of the resistor element 20 is connected to the gate electrode wiring 10 via a ground contact portion 23 that penetrates the interlayer insulating film 9. Note that the ground contact portion 23 may be connected to a ground terminal wiring different from the gate electrode wiring 10, and the ground terminal wiring may be drawn out and grounded.

[0034] As shown in FIG. 4 , the resistor element 20 is connected to a voltage-dividing terminal wiring 21 at a position more inward than the position where it is connected to the ground contact 23 via a voltage-dividing point contact 24 that penetrates the interlayer insulating film 9. The voltage-dividing terminal wiring 21 is a terminal for sensing the input voltage to the input pad of the JFET 30, dividing the input voltage and outputting it to the voltage sense circuit. The closer to the inner periphery the resistor element 20 is connected to the voltage-dividing terminal wiring 21, the higher the potential of the voltage-dividing terminal wiring 21 output to the voltage sense circuit. For this reason, the voltage-dividing terminal wiring 21 is connected to a position where the input voltage to the input pad of the JFET 30 can be divided below the withstand voltage of the voltage sense circuit. For example, the voltage-dividing terminal wiring 21 is connected to a position where a potential that is 1 / 100 of the input voltage to the input pad of the JFET 30 can be extracted.

[0035] The voltage-dividing terminal wiring 21 is disposed in the same layer as the source electrode wiring 12 and the gate electrode wiring 10, and is made of the same material as the source electrode wiring 12 and the gate electrode wiring 10. The voltage-dividing terminal wiring 21 extends so as to face a part of the outermost periphery of the resistor element 20, and is drawn out at a position where the approximately ring-shaped source electrode wiring 12 and the gate electrode wiring 10 are separated. At the portion where the voltage-dividing terminal wiring 21 extends so as to face a part of the outermost periphery of the resistor element 20, the source electrode wiring 12 recedes outward, forming a space for the voltage-dividing terminal wiring 21. The voltage-dividing terminal wiring 21 may be disposed in a layer different from the source electrode wiring 12 and the gate electrode wiring 10. For example, the source electrode wiring 12 and the gate electrode wiring 10 may be disposed in the first layer of a multilayer wiring, and the voltage-dividing terminal wiring 21 may be disposed in the second layer of the multilayer wiring.

[0036] In such a JFET 30, whether or not to turn off the JFET 30 is determined based on the potential of the voltage dividing terminal wiring 21. For example, based on the potential of the voltage dividing terminal wiring 21, a voltage sense circuit (not shown) electrically connected to the source electrode wiring 12 raises the potential of the source electrode wiring 12, + The pn junction between the p-type source region 4 and the p-type gate region 2 is reverse biased. +The depletion layers extending from the p-type gate region 2 on both sides of the n-type source region 4 are called n + The opening between the n-type source region 4 and the n-type drift region 3 (n + By connecting the n-type source region 4 at the interface with the n-type drift region 3, the current in the JFET 30 is cut off, and the JFET 30 is turned off.

[0037] 1, in the semiconductor device according to the first embodiment, the source electrode wiring 12, which is a metal wiring, faces the outermost periphery that functions as a resistor of the resistor element 20. The source electrode wiring 12 has a portion where the distance d1 between the source electrode wiring 12 and the outermost periphery that functions as a resistor of the resistor element 20 is constant. In this specification, the term "constant distance" includes not only a case where the distance is absolutely constant, but also a case where the distance is not strictly constant and the members are approximately parallel to each other.

[0038] The source electrode wiring 12 faces the outermost periphery of the resistor element 20 over more than half the circumference, i.e., approximately one circumference, of the resistor element 20. The distance d1 between the inner periphery of the source electrode wiring 12 and the outermost periphery of the resistor element 20 is constant over more than half the circumference, i.e., approximately one circumference, of the resistor element 20. That is, the inner periphery of the approximately ring-shaped source electrode wiring 12 is + The electrode is not provided concentrically with the type drain region 5, but is provided parallel to the outermost periphery of the spiral planar resistor element 20. The distance d1 is, for example, about 1 μm to 2 μm, and can be adjusted as appropriate.

[0039] The source electrode wiring 12 has a slope portion 12b at the end of a portion where the distance d1 between the source electrode wiring 12 and the resistor element 20 is constant. In the slope portion 12b, the width w1 of the source electrode wiring 12 gradually narrows toward the position where the approximately ring shape of the source electrode wiring 12 is separated, and the distance d1 between the source electrode wiring 12 and the resistor element 20 gradually widens. The longer the length of the slope portion 12b, the shorter the length of the portion where the distance d1 between the source electrode wiring 12 and the resistor element 20 is constant. The length of the slope portion 12b and the length of the portion where the distance d1 between the source electrode wiring 12 and the resistor element 20 is constant can be adjusted as appropriate.

[0040] 4, the voltage-dividing terminal wiring 21, which is a metal wiring, faces the outermost periphery of the resistor element 20, and has a portion where the distance d3 between the voltage-dividing terminal wiring 21 and the outermost periphery of the resistor element 20 is constant. That is, at the position where the voltage-dividing terminal wiring 21 faces the outermost periphery of the resistor element 20, the voltage-dividing terminal wiring 21 is provided in a curved shape parallel to the spiral-shaped resistor element 20. The distance d3 between the voltage-dividing terminal wiring 21 and the outermost periphery of the resistor element 20 is equal to the distance d1 between the source electrode wiring 12 and the outermost periphery of the resistor element 20.

[0041] At the position where the voltage-dividing terminal wiring 21 is provided along the outermost periphery of the resistor element 20, the source electrode wiring 12 is set back outward, so that the distance d2 between the source electrode wiring 12 and the outermost periphery of the resistor element 20 is wider than the distance d1. Therefore, the range in which the distance d1 between the source electrode wiring 12 and the resistor element 20 is constant is from the vicinity of the position of the voltage-dividing point contact portion 24 to the slope portion 12b.

[0042] <Comparative Example> Next, semiconductor devices according to first and second comparative examples will be described. As shown in Fig. 5, the semiconductor device according to the first comparative example differs from the semiconductor device according to the first embodiment shown in Fig. 1 in that the ground contact portion 23 and the voltage dividing point contact portion 24 are provided one turn inward from the outermost periphery of the resistor element 20, and the portion inward from the position connected to the ground contact portion 23 of the resistor element 20 functions as an effective resistor. Also, in the semiconductor device according to the first comparative example, the inner periphery of the ring-shaped source electrode wiring 12 is + The difference from the semiconductor device according to the first embodiment is that the second electrode is arranged concentrically with respect to the first drain region 5.

[0043] In the semiconductor device according to the first comparative example, if the sheet resistance of the polysilicon resistor of the resistor element 20 is increased to, for example, about 10 kΩ / □, the polysilicon with a low impurity concentration will experience a resistance value shift due to the hydrogen absorption effect of titanium (Ti), causing variations in the voltage division point, simply by arranging metal wiring such as the source electrode wiring 12 in close proximity. That is, when performing hydrogen annealing, which is a heat treatment in a hydrogen gas atmosphere to terminate dangling bonds on the surface of the resistor element 20 with hydrogen atoms, if metal wiring such as the source electrode wiring 12 is arranged in close proximity to the resistor element 20, Ti contained in the barrier metal in the lowest layer of the metal wiring will absorb hydrogen atoms, making it impossible to terminate the dangling bonds on the surface of the resistor element 20 with hydrogen atoms, resulting in variations in the resistance value.

[0044] Figure 6 shows the relationship between the distance between the polysilicon resistor and the metal wiring and the rate of change in the resistance value of the polysilicon resistor. As shown in Figure 6, the rate of change in the resistance value of the polysilicon resistor increases as the distance between the polysilicon resistor and the metal wiring decreases.

[0045] In the semiconductor device according to the first comparative example, the inner periphery of the source electrode wiring 12 is + While the resistor element 20 is arranged concentrically with the source drain region 5, the resistor element 20 has a spiral shape, and therefore the distance d11 from the outermost part of the resistor element 20 that functions as a resistor (the part one circumference inward from the outermost part of the resistor element 20) to the inner circumference of the source electrode wiring 12 is not constant, and the resistor element 20 gets closer to the source electrode wiring 12 as it moves toward the outer periphery, which affects the variation in the voltage division point.

[0046] In order to avoid this variation in the voltage dividing points, the semiconductor device according to the second comparative example differs from the semiconductor device according to the first comparative example shown in Fig. 5 in that the source electrode wirings 12 are uniformly set back outward as shown in Fig. 7. The semiconductor device according to the second comparative example also differs from the semiconductor device according to the first comparative example in that the ground contact portion 23 and the voltage dividing point contact portion 24 are provided at the outermost periphery of the resistor element 20.

[0047] In the semiconductor device according to the second comparative example, the source electrode wiring 12 is uniformly recessed outward, so that the width w11 of the source electrode wiring 12 is locally narrowed, causing a problem that the allowable current density is exceeded and wiring burnout occurs at positions P11 and P12 connected to the lead wire 12a of the source electrode wiring 12. Furthermore, in the semiconductor device according to the second comparative example, as in the semiconductor device according to the first comparative example, the distance d12 between the outermost periphery functioning as a resistor of the resistive element 20 and the source electrode wiring 12 varies, so that when the line width of the resistive element 20 becomes thicker due to processing variations, the resistance value of the resistive element 20 fluctuates greatly, causing large variations in the voltage division ratio.

[0048] <Effects> In contrast to these semiconductor devices according to the first and second comparative examples, in the semiconductor device according to the first embodiment, as shown in FIGS. 1 to 4, the planar shape of the source electrode wiring 12 is + The resistors 20 are arranged along the outermost periphery of the spiral resistor element 20, rather than concentrically with the type drain region 5, and the voltage dividing terminal wiring 21 is also arranged along the outermost periphery of the resistor element 20. This makes it possible to equalize the rate of change in resistance value of the resistor elements 20 on the outer periphery, which are highly sensitive to variations in the voltage dividing points in the voltage dividing resistor section, and thus reduces variations in the voltage dividing ratio.

[0049] Furthermore, according to the semiconductor device of the first embodiment, by making the distance d1 between the outermost periphery functioning as a resistor of the resistor element 20 and the source electrode wiring 12, and the distance d3 between the outermost periphery functioning as a resistor of the resistor element 20 and the voltage division terminal wiring 21 constant, even if the line width of the resistor element 20 becomes thicker due to processing variations, the fluctuation in the resistance value of the resistor element 20 is small, and the influence of deviation on the voltage division ratio can be suppressed.

[0050] Furthermore, in contrast to the semiconductor device according to the second comparative example, in the semiconductor device according to the first embodiment, the width w1 of the source electrode wiring 12 increases clockwise, thereby avoiding localized narrowing of the wiring width. Therefore, the width w1 of the source electrode wiring 12 can be ensured at positions P1 and P2 connected to the lead-out line 12a of the source electrode wiring 12, thereby mitigating the current density of the source electrode wiring 12 and preventing burnout of the source electrode wiring 12 due to the startup current. Therefore, a high-resistance polysilicon voltage dividing resistor can be realized that is inexpensive, high-quality, and has little variation, without increasing the number of layers of the source electrode wiring 12.

[0051] Furthermore, by arranging the source electrode wiring 12 along the spiral resistance element 20, a gap with an inward protrusion length occurs in the approximately ring-shaped cut-off portion of the source electrode wiring 12, but by making this gap portion into a slope portion 12b, + This makes it possible to avoid localized electric field concentration at the end of the source electrode wiring 12 when a high voltage is applied to the type drain region 5, and to prevent a decrease in breakdown voltage.

[0052] (Modification of the first embodiment) As shown in FIGS. 8 and 9, the semiconductor device according to the modification of the first embodiment has n + type drain region 5 and n + The configuration of the n-type source region 4 is different from that of the semiconductor device according to the first embodiment. Fig. 8 is a cross-sectional view of the semiconductor device according to the first embodiment, corresponding to Fig. 2. As shown in Fig. 8, + type drain region 5 and n + The n-type source region 4 is selectively provided above the n-type drift region 3. Fig. 9 is a plan view of the semiconductor device according to the first embodiment, corresponding to Fig. 4. As shown in Fig. 9, the n + The n-type source region 4 is not in contact with the p-type gate region 2, and the n-type drift region 3 is +8 and 9, the semiconductor device according to the modification of the first embodiment can achieve the same effects as the semiconductor device according to the first embodiment.

[0053] (Second embodiment) 10, the semiconductor device according to the second embodiment differs from the semiconductor device according to the first embodiment shown in Fig. 1 in that the gate electrode wiring 10 is provided more inward than the source electrode wiring 12. In the semiconductor device according to the second embodiment, the outer periphery of the gate electrode wiring 10 has a gear-like planar shape, and the inner periphery of the source electrode wiring 12 has a gear-like planar shape.

[0054] In the semiconductor device according to the second embodiment, the gate electrode wiring 10 faces the outermost periphery of the spiral resistive element 20, and has a portion where the distance d4 between the gate electrode wiring 10 and the outermost periphery of the resistive element 20 is approximately constant. Fig. 10 shows a plan view of a portion of the semiconductor device according to the second embodiment, but the gate electrode wiring 10 may face the outermost periphery of the resistive element 20 over more than half the outermost periphery of the resistive element 20, and the distance d4 between the gate electrode wiring 10 and the outermost periphery of the resistive element 20 may be approximately constant.

[0055] According to the semiconductor device of the second embodiment, when the gate electrode wiring 10 is configured to face the outermost periphery of the resistor element 20, the gate electrode wiring 10 is arranged parallel to the outermost periphery of the resistor element 20 so that the distance d4 between the gate electrode wiring 10 and the outermost periphery of the resistor element 20 is approximately constant, thereby achieving the same effect as in the first embodiment.

[0056] (Third embodiment) 11, the semiconductor device according to the third embodiment differs from the semiconductor device according to the first embodiment shown in FIG. 1 in that the ground contact portion 23 is provided on the inner side of the outer end of the spiral resistance element 20. In FIG. 11, the ground contact portion 23 is provided one turn inward from the outermost periphery. The voltage dividing point contact portion 24 is provided on the inner side of the ground contact portion 23.

[0057] The area outside the connection position of the resistor element 20 with the ground contact portion 23 does not function as an effective resistor and becomes a dummy area. In this case, one turn inside the resistor element 20 from the ground contact portion 23 is defined as the outermost periphery that effectively functions as a resistor. The inner periphery of the approximately ring-shaped source electrode wiring 12 is located inside the outermost periphery that does not function as a resistor of the resistor element 20. The inner periphery of the approximately ring-shaped source electrode wiring 12 is located at a constant distance d5 from the outermost periphery that effectively functions as a resistor of the resistor element 20.

[0058] The semiconductor device according to the third embodiment achieves the same effects as the first embodiment by arranging the source electrode wiring 12 along the outermost periphery that functions as a resistor of the resistor element 20. In the semiconductor device according to the first embodiment, the ground contact portion 23 is provided at the end of the outer periphery of the resistor element 20, and therefore the outermost periphery of the resistor element 20 is the outermost periphery that functions as a resistor of the resistor element 20.

[0059] (Fourth embodiment) As shown in Fig. 12, the semiconductor device according to the fourth embodiment differs from the semiconductor device according to the first embodiment shown in Fig. 1, in that the drain contact portion 14 and the spiral resistive element 20 have an approximately racetrack shape in outer shapes. Fig. 12 schematically shows the planar shapes of the drain contact portion 14, the resistive element 20, and the source electrode wiring 12, which are some of the components of the semiconductor device according to the fourth embodiment.

[0060] The resistor element 20 has straight portions 20a extending parallel to each other and U-shaped curved portions 20b connecting the straight portions 20a. The source electrode wiring 12 is generally ring-shaped and faces the outermost straight portion 20a and curved portion 20b of the resistor element 20. The shape of the inner periphery of the roughly ring-shaped source electrode wiring 12 is not similar to that of the drain contact portion 14, and is provided so that a distance d6 between the inner periphery of the roughly ring-shaped source electrode wiring 12 and the outermost straight portion 20a and curved portion 20b of the resistor element 20 is generally constant.

[0061] Although not shown in the drawings, the external shape of the resistance element 20 may be substantially elliptical. In this case, similarly, metal wiring such as the source electrode wiring 12 may be provided so as to have a portion where the distance between the metal wiring and the outermost periphery of the resistance element 20 is substantially constant.

[0062] (Other embodiments) As described above, the present invention has been described with reference to the first to fourth embodiments, but the descriptions and drawings that form part of this disclosure should not be understood as limiting the present invention. Various alternative embodiments, examples, and operating techniques will become apparent to those skilled in the art from this disclosure.

[0063] For example, in the semiconductor devices according to the first to fourth embodiments, the resistive element 20 is exemplified as an element for sensing the voltage of the startup element of the startup circuit, but it is applicable to all circuits that use a polysilicon resistor having a spiral planar shape as a resistive element.

[0064] Furthermore, in the semiconductor devices according to the first to fourth embodiments, semiconductor devices using JFETs have been exemplified, but the present invention can also be applied to insulated gate field effect transistors such as MOSFETs instead of JFETs.

[0065] Furthermore, in the semiconductor devices according to the first to fourth embodiments, the source electrode wiring 12, the voltage dividing terminal wiring 21, and the gate electrode wiring 10 are each arranged so that the distances d1, d3, and d4 from the outermost periphery that functions as a resistor of the resistive element 20 are approximately constant. However, if there is a metal wiring that has a barrier metal containing titanium (Ti) that faces the outermost periphery that functions as a resistor of the resistive element 20 in addition to the source electrode wiring 12, the voltage dividing terminal wiring 21, and the gate electrode wiring 10, then the metal wiring may be arranged so that the distance from the outermost periphery that functions as a resistor of the resistive element 20 is approximately constant.

[0066] Furthermore, the configurations disclosed in the first to fourth embodiments can be appropriately combined within a range that does not cause contradictions. As such, the present invention naturally includes various embodiments not described here. Therefore, the technical scope of the present invention is defined only by the invention-specifying matters according to the claims that are appropriate from the above description. [Explanation of symbols]

[0067] 1...p-type semiconductor substrate (semiconductor chip) 2...p-type gate region 3...n-type drift region 4...n + Type Source Area 5...n + Type drain region 6...p + Mold contact area 7...Gate polysilicon electrode 8...Element isolation insulating film 9,31...Interlayer insulating film 10...Gate electrode wiring 11, 32...Drain electrode wiring 12...Source electrode wiring 12a...Pull-out wire 12b...Slope section 13...Gate contact part 14, 33...Drain contact section 15...Source contact part 16...Resistor element contact part 17~19...Contact plug 20...Resistance element 20a...Straight section 20b…Curved part 21...Voltage dividing terminal wiring 23...Ground contact part 24...Voltage dividing point contact part 25...Gate polysilicon contact

Claims

1. a first region of a second conductivity type provided on an upper portion of a semiconductor substrate of a first conductivity type; a second region of a second conductivity type provided on the semiconductor substrate and in contact with the first region; a third region of the second conductivity type provided on the semiconductor substrate, facing the first region across the second region and in contact with the second region; a fourth region of the first conductivity type provided on the semiconductor substrate and in contact with the second region; an interlayer insulating film covering the second region; a resistor element provided inside the interlayer insulating film and having a spiral planar shape; a first electrode wiring electrically connected to the first region and one end of the resistor element; a second electrode wiring electrically connected to the third region and provided around the resistor element; a third electrode wiring electrically connected to the fourth region and provided around the resistor element; a voltage dividing terminal wiring electrically connected to the resistor element; Equipped with The semiconductor device is characterized in that a metal wiring facing the outermost periphery that functions as a resistor of the resistance element has a portion where the distance between the metal wiring and the outermost periphery is constant.

2. 2. The semiconductor device according to claim 1, wherein the metal wiring is at least one of the second electrode wiring, the third electrode wiring, and the voltage dividing terminal wiring.

3. 3. The semiconductor device according to claim 2, wherein the second electrode wiring has a portion that faces the outermost periphery over at least half of the outermost periphery, and the distance between the second electrode wiring and the outermost periphery is constant.

4. the voltage dividing terminal wiring has a portion that faces the outermost periphery and has a constant interval between the voltage dividing terminal wiring and the outermost periphery; 4. The semiconductor device according to claim 3, wherein the distance between the voltage dividing terminal wiring and the outermost periphery is equal to the distance between the second electrode wiring and the outermost periphery.

5. 4. The semiconductor device according to claim 3, wherein the second electrode wiring has a sloped portion at an end of a portion where the distance between the second electrode wiring and the outermost periphery is constant.

6. 6. The semiconductor device according to claim 1, wherein the resistive element has a planar outer shape that is circular, elliptical, or racetrack-shaped.

7. 7. The semiconductor device according to claim 1, wherein the sheet resistance of the resistor element is 1 kΩ / □ or more.

8. 8. The semiconductor device according to claim 1, wherein the resistor element is a polysilicon resistor.

9. The semiconductor device according to any one of claims 1 to 8, characterized in that the resistor element is electrically connected to the third electrode wiring at a position on the outer periphery of the resistor element relative to a position where the voltage dividing terminal wiring is electrically connected.

10. The fourth region is provided so as to extend from the outside of the third region to the first region side of the third region.

10. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating layer and a second insulating layer.

11. 11. The semiconductor device according to claim 10, wherein the fourth region has a planar shape that sandwiches the third region in a direction perpendicular to a direction connecting the first region and the third region.

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