Semiconductor device and manufacturing method thereof

Abstract

To reduce the restriction on an electrode to be connected to a semiconductor element.SOLUTION: A semiconductor substrate 10 includes: a GaN substrate 11 with a hexagonal crystal in which a first main surface 11a is an m-plane, one direction in a plane direction of the first main surface 11a is a direction along a c-axis direction, and a second main surface 11b on the opposite side of the first main surface 11a forms the other surface 10b of the semiconductor substrate 10; a plurality of first column regions 12 disposed on the first main surface 11a of the GaN substrate and formed of a first nitride semiconductor layer; and second column regions 13 disposed on the first main surface 11a of the GaN substrate 11, formed of a second nitride semiconductor layer with a higher band gap than the first nitride semiconductor layer, and forming a PSJ structure 14 with the first column regions. The first column regions and the second column regions are alternately disposed along the c-axis direction on the first main surface. Current flows between one surface 10a and the other surface 10b of the semiconductor substrate 10.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device having a polarization super junction (hereinafter simply referred to as PSJ) structure composed of a first nitride semiconductor layer and a second nitride semiconductor layer, and a method for manufacturing the same. [Background technology]

[0002] Semiconductor devices with a PSJ structure have been proposed (see, for example, Non-Patent Document 1). Specifically, this semiconductor device includes a semiconductor substrate with a PSJ structure in which a first nitride semiconductor layer, a second nitride semiconductor layer, and another first nitride semiconductor layer are stacked in this order on a substrate. The first nitride semiconductor layer is, for example, a gallium nitride layer (hereinafter simply referred to as a GaN layer), and the second nitride semiconductor layer is, for example, an aluminum gallium nitride layer (hereinafter simply referred to as an AlGaN layer). In the PSJ structure, two-dimensional electron gas (hereinafter simply referred to as a 2DEG) is generated on one side of the interface between the GaN layer and the AlGaN layer, and two-dimensional hole gas (hereinafter simply referred to as a 2DHG) is generated on the other side.

[0003] This semiconductor device is configured by forming a semiconductor element such as a MOSFET (short for Metal Oxide Semiconductor Field Effect Transistor) using the semiconductor substrate. Furthermore, a gate electrode, a source electrode, a drain electrode, and the like connected to the semiconductor element are formed together on one surface of the semiconductor substrate opposite to the substrate. Therefore, in this semiconductor device, when a predetermined voltage is applied to the gate electrode, a current flows along the surface of the semiconductor substrate. [Prior art documents] [Non-patent literature]

[0004] [Non-Patent Document 1] Akira Nakajima, Yasunobu Sumida, Mahesh H. Dhyani, Hiroji Kawai and EM Sankara Narayanan “High Density Two-Dimensional Hole Gas Induced by Negative Polarization at GaN / AlGaN Heterointerface,” Published 10 December 2010, The Japan Society of Applied Physics Summary of the Invention [Problem to be solved by the invention]

[0005] However, in the semiconductor device described above, the gate electrode, source electrode, and drain electrode are all disposed on one surface of the semiconductor substrate, which tends to impose large restrictions on the width and thickness of each electrode.

[0006] In view of the above, it is an object of the present invention to provide a semiconductor device that can reduce the restrictions on electrodes connected to semiconductor elements, and a method for manufacturing the same. [Means for solving the problem]

[0007] Claim 1 to achieve the above object and 4a semiconductor device having a semiconductor element formed thereon, the semiconductor substrate having one surface (10a) and another surface (10b), the semiconductor element formed thereon, one-surface-side electrodes (19, 21, 51, 52, 61) disposed on the one surface side of the semiconductor substrate and electrically connected to the semiconductor element, and another-surface-side electrodes (22, 53, 62) disposed on the other surface side of the semiconductor substrate and electrically connected to the semiconductor element, the semiconductor substrate being hexagonal, the first main surface (11a) being an m-plane, one direction in the plane direction of the first main surface being a direction along the c-axis direction, and the second main surface (11b) opposite to the first main surface being a GaN The semiconductor substrate (11) comprises: a substrate (11); a plurality of first column regions (12) arranged on a first main surface of the GaN substrate, each of which is composed of a first nitride semiconductor layer and extends in one direction in the surface direction of the GaN substrate; and second column regions (13) arranged on the first main surface of the GaN substrate, each of which is composed of a second nitride semiconductor layer having a band gap higher than that of the first nitride semiconductor layer, each of which is arranged between the first column regions and which form a PSJ structure (14) together with the first column regions, the first column regions and the second column regions being arranged alternately along the c-axis direction on the first main surface, allowing a current to flow between one surface and the other surface of the semiconductor substrate. In addition, claim 1 has a base layer (15) arranged on a polarization super junction structure and having a first conductivity type or a second conductivity type, and the one-side electrode has a base layer electrode (21, 52) connected to the base layer, an emitter layer (41) arranged on the base layer in a state exposing a portion of the base layer, and an emitter electrode (51) as a one-side electrode connected to the emitter layer. In claim 4, the first column region and the second column region are made of doped layers, and charge balance is maintained. .

[0008] This arrangement allows the PSJ structures to be arranged along the surface of the GaN substrate, allowing current to flow in the thickness direction of the semiconductor substrate. This allows the electrodes connected to the semiconductor element to be separated into one-side and other-side electrodes, and arranged on both sides of the semiconductor substrate. This reduces the constraints on the electrodes connected to the semiconductor element.

[0009] Claim 8 is a method for manufacturing a semiconductor device related to claim 1, comprising the steps of: preparing a GaN substrate; epitaxially growing a second column region-forming layer (130) that forms the second column region on a first main surface of the GaN substrate; forming a burying trench (131) in a portion of the second column region-forming layer where the first column region is to be disposed, and designating a portion different from the portion where the burying trench is formed as the second column region; epitaxially growing a first column region-forming layer (120) that forms the first column region so that the burying trench is filled, and designating the portion located in the burying trench as the first column region, thereby configuring a PSJ structure having a first column region and a second column region.

[0010] This allows the fabrication of a semiconductor device in which the PSJ structures are arranged along the surface of the GaN substrate and current flows in the thickness direction of the semiconductor substrate, thereby making it easier to reduce the constraints on the electrodes connected to the semiconductor element.

[0011] Claim 11 is a method for manufacturing a semiconductor device according to claim 1, comprising the steps of: preparing a GaN substrate; epitaxially growing a first column region-forming layer (120) that forms a first column region on a first main surface of the GaN substrate; forming a burying trench (121) in a portion of the first column region-forming layer where the second column region is to be disposed, and designating a portion different from the portion where the burying trench is formed as the first column region (12); epitaxially growing a second column region-forming layer (130) that forms the second column region so that the burying trench is filled, and designating a portion located in the burying trench as the second column region, thereby constructing a PSJ structure having a first column region and a second column region. In the polarization superjunction structure, a first column region and a second column region are formed by doping layers. .

[0012] This allows the fabrication of a semiconductor device in which the PSJ structures are arranged along the surface of the GaN substrate and current flows in the thickness direction of the semiconductor substrate, thereby making it easier to reduce the constraints on the electrodes connected to the semiconductor element.

[0013] The reference symbols in parentheses attached to each component indicate an example of the correspondence between the component and the specific components described in the embodiments described below. [Brief explanation of the drawings]

[0014] [Figure 1] 1 is a cross-sectional view of a semiconductor device according to a first embodiment. [Figure 2] FIG. 1 is a schematic diagram showing the crystal orientation of a GaN substrate. [Figure 3] FIG. 1 is an energy band diagram of a PSJ structure. [Figure 4A] FIG. 2 is a schematic diagram illustrating the semiconductor device according to the first embodiment in an on state. [Figure 4B] FIG. 2 is a schematic diagram illustrating the semiconductor device according to the first embodiment in an off state. [Figure 5A] 2A to 2C are cross-sectional views illustrating a manufacturing process of the semiconductor device according to the first embodiment. [Figure 5B] 5B is a cross-sectional view showing the manufacturing process of the semiconductor device subsequent to FIG. 5A. [Figure 5C] FIG. 5C is a cross-sectional view showing the manufacturing process of the semiconductor device subsequent to FIG. 5B. [Figure 5D] 5D is a cross-sectional view showing the manufacturing process of the semiconductor device subsequent to FIG. 5C. [Figure 6A] 5A to 5C are cross-sectional views showing a manufacturing process of a semiconductor device according to a modified example of the first embodiment. [Figure 6B] 6B is a cross-sectional view showing the manufacturing process of the semiconductor device subsequent to FIG. 6A. [Figure 6C] FIG. 6C is a cross-sectional view showing the manufacturing process of the semiconductor device subsequent to FIG. 6B. [Figure 6D] FIG. 6D is a cross-sectional view showing the manufacturing process of the semiconductor device subsequent to FIG. 6C. [Figure 7] FIG. 10 is a cross-sectional view of a semiconductor device according to a second embodiment. [Figure 8A] FIG. 10 is a schematic diagram illustrating the semiconductor device according to the second embodiment in an on state. [Figure 8B] FIG. 10 is a schematic diagram of the semiconductor device according to the second embodiment in an off state. [Figure 9] FIG. 10 is a cross-sectional view of a semiconductor device according to a third embodiment. [Figure 10] FIG. 10 is an energy band diagram of a PSJ structure according to a third embodiment. [Figure 11] FIG. 2 is an enlarged view of the vicinity of the Fermi level in the energy band diagram of the first embodiment. [Figure 12] FIG. 11 is an enlarged view of the vicinity of the Fermi level in the energy band diagram of the third embodiment. [Figure 13A] FIG. 10 is a schematic diagram illustrating a semiconductor device according to a third embodiment in an on state. [Figure 13B] FIG. 10 is a schematic diagram illustrating the semiconductor device according to the third embodiment in an off state. [Figure 14A] 10A to 10C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to a third embodiment. [Figure 14B] 14B is a cross-sectional view showing the manufacturing process of the semiconductor device subsequent to FIG. 14A. [Figure 14C] FIG. 14C is a cross-sectional view showing the manufacturing process of the semiconductor device subsequent to FIG. 14B. [Figure 15A] 10A to 10C are cross-sectional views showing a manufacturing process of a semiconductor device according to a modification of the third embodiment. [Figure 15B] 15B is a cross-sectional view showing the manufacturing process of the semiconductor device subsequent to FIG. 15A. [Figure 15C] FIG. 15C is a cross-sectional view showing the manufacturing process of the semiconductor device subsequent to FIG. 15B. [Figure 16] FIG. 10 is a cross-sectional view of a semiconductor device according to a fourth embodiment. [Figure 17A] FIG. 10 is a schematic diagram illustrating a semiconductor device according to a fourth embodiment in an on state. [Figure 17B] FIG. 10 is a schematic diagram illustrating a semiconductor device according to a fourth embodiment in an off state. [Figure 18] FIG. 10 is a cross-sectional view of a semiconductor device according to another embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0015] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In the following embodiments, parts that are identical or equivalent to each other will be denoted by the same reference numerals.

[0016] (First embodiment) A first embodiment will be described with reference to the drawings. The semiconductor device of this embodiment is suitable for use, for example, in a vehicle such as an automobile, for driving various electronic devices for the vehicle. In this embodiment, a semiconductor device in which an inversion-type MOSFET with a trench gate structure is formed as the semiconductor element will be described. Furthermore, when indicating a crystal orientation, a bar (-) should normally be placed above the desired number. However, due to limitations on expression based on electronic filing, a bar is placed before the desired number in this specification.

[0017] 1, the semiconductor device of this embodiment has a GaN substrate 11 having a first main surface 11a and a second main surface 11b. Specifically, the GaN substrate 11 is formed by ion implantation or an epitaxial layer. + Typed n + The GaN substrate 11 is a GaN substrate, which constitutes the drain region in this embodiment. The GaN substrate 11 has a hexagonal crystal structure. In this case, the crystal orientation of the GaN substrate 11 is as shown in FIG. 2. In this embodiment, the first and second major surfaces 11a and 11b of the GaN substrate 11 are {1-100} m-planes, and one direction in the plane directions of the first and second major surfaces 11a and 11b is along the <0001> c-axis direction. In this embodiment, the left-right direction of the paper in FIG. 1 is along the c-axis direction, with the left side of the paper being the Ga-plane side and the right side of the paper being the N-plane side.

[0018] A PSJ structure 14 is disposed on a GaN substrate 11. The PSJ structure 14 has a first column region 12 made of an undoped u-GaN layer and a second column region 13 made of an undoped u-AlGaN layer. In this embodiment, the u-GaN layer corresponds to the first nitride semiconductor layer, and the u-AlGaN layer corresponds to the second nitride semiconductor layer having a band gap higher than that of the first nitride semiconductor layer. The u-AlGaN layer constituting the second column region 13 is made of Al 1-x Ga x When N is used, the layer is formed so as to satisfy 0≦x<1. Furthermore, the undoped layer in this embodiment is a layer that is not doped with impurities, or contains n-type impurities and p-type impurities but has a fixed charge of 5×10 16 / cm 3 Even if n-type and p-type impurities are included, the fixed charge is less than 5 × 10 16 / cm 3 "Less than" means that n-type or p-type impurities are unintentionally included during manufacturing, rather than being actively doped with impurities. Furthermore, the term "fixed charge" here refers to the concentration of positively charged ionized impurities after emitting electrons in the case of n-type, and the concentration of negatively charged ionized impurities after emitting holes in the case of p-type.

[0019] The first column regions 12 and the second column regions 13 are each composed of an epitaxial layer. The first column regions 12 and the second column regions 13 extend in one direction along the surface of the GaN substrate 11 as the longitudinal direction, and are arranged alternately in a direction intersecting the longitudinal direction. In other words, the first column regions 12 and the second column regions 13 are arranged in a stripe pattern. The first column regions 12 and the second column regions 13 are arranged alternately along the c-axis direction.

[0020] In the PSJ structure 14 thus formed on the GaN substrate 11, 2DEG (i.e., negative polarization charges) and 2DHG (i.e., positive polarization charges) are induced at the AlGaN / GaN interface, which is the interface between the first column region 12 and the second column region 13, due to polarization effects and the like. Specifically, as shown in FIG. 3, in the first column region 12, 2DEG is generated on the Ga-face side, and 2DHG is generated on the N-face side. As a result, in the second column region 13, 2DEG is generated on the Ga-face side, and 2DHG is generated on the N-face side. Note that FIG. 3 is an energy band diagram of a portion along line III-III in FIG. 1.

[0021] 1, a base layer 15 made of a p-GaN layer doped with p-type impurities is disposed on the PSJ structure 14. The base layer 15 is made of an epitaxial layer, and although not particularly limited, the doping amount of the p-type impurity Mg (i.e., magnesium) is preferably 1×10 19 / cm 2 The thickness is said to be about 500 nm.

[0022] The surface layer of the base layer 15 is + A source region 16 is provided, which is an n-GaN layer doped with an n-type impurity. The source region 16 is formed of an epitaxial layer or an ion-implanted layer formed by ion implantation. In this embodiment, the source region 16 corresponds to an impurity region.

[0023] As described above, in this embodiment, semiconductor substrate 10 is configured to include GaN substrate 11, PSJ structure 14, base layer 15, source region 16, etc. One surface 10a of semiconductor substrate 10 in this embodiment is configured as source region 16, and the other surface 10b is configured as second main surface 11b of GaN substrate 11.

[0024] A plurality of gate trenches 17 are formed in the semiconductor substrate 10 so as to penetrate from the one surface 10a side through the source region 16 and the base layer 15 to reach the first column region 12. The plurality of gate trenches 17 extend in one direction of the planar direction of the one surface 10a of the semiconductor substrate 10 (i.e., the depth direction in FIG. 1 ) so as to form equally spaced stripes. Specifically, the plurality of gate trenches 17 extend along the longitudinal direction of the first column region 12.

[0025] Each gate trench 17 is filled with a gate insulating film 18 formed to cover the wall surface of the gate trench 17, and a gate electrode 19 made of polysilicon or the like formed on the gate insulating film 18. This forms a trench gate structure.

[0026] Furthermore, contact trenches 20 are formed in the semiconductor substrate 10 between adjacent trench gate structures so as to penetrate the source region 16 from the one surface 10a side and reach the base layer 15. Note that the contact trenches 20 in this embodiment are formed so as to reach the base layer 15 located above the second column region 13.

[0027] A source electrode 21 is disposed in the contact trench 20. The source electrode 21 in this embodiment is made of a plurality of metals, such as Ni / Al. Specifically, the portion of the source electrode 21 that contacts the portion that constitutes the n-type region (i.e., the source region 16) is made of a metal that can make ohmic contact with the n-type region. The portion of the source electrode 21 that contacts the p-type region (i.e., the base layer 15) is made of a metal that can make ohmic contact with the p-type region. In this embodiment, the source electrode 21 has a first portion 21a that contacts the base layer 15 and contains Ni, and a second portion 21b that contacts the source region 16 and contains Al / Ti. In this embodiment, the gate electrode 19 and the source electrode 21 correspond to one-side electrodes. In this embodiment, the source electrode 21 corresponds to a base layer electrode.

[0028] A drain electrode 22 is formed on the other surface 10b side of the semiconductor substrate 10 and is electrically connected to the GaN substrate 11. In this embodiment, the drain electrode 22 corresponds to the other surface electrode.

[0029] In the semiconductor device of this embodiment, an n-channel inversion type trench gate MOSFET is configured with such a structure. + type, n - The a-type corresponds to the first conductivity type, and the p-type corresponds to the second conductivity type.

[0030] Next, the operation and effects of the semiconductor device of this embodiment will be described with reference to Figures 4A and 4B. Note that GaN substrate 11 and drain electrode 22 are omitted in Figures 4A and 4B.

[0031] First, in the PSJ structure 14, as shown in FIG. 4A , 2DEG 31 and 2DHG 32 are generated at the interface between the first column region 12 and the second column region 13. When a voltage equal to or greater than the threshold voltage, e.g., 6 V, is applied to the gate electrode 19, an inversion layer is formed on the surface of the base layer 15 that contacts the gate trench 17. This causes electrons to be supplied from the source electrode 21, resulting in an on-state in which current flows to the drain electrode 22 via the 2DEG 31 formed in the first column region 12. In other words, a current flows through the semiconductor device along the thickness direction of the semiconductor substrate 10. In this case, because the 2DHG 32 does not have any portions that are easily extracted, the current flowing through the semiconductor device is dominated by electron current.

[0032] As shown in FIG. 4B, when the gate voltage applied to the gate electrode 19 becomes less than the threshold voltage, e.g., 0 V, no inversion layer is formed in the base layer 15, and no new electrons are supplied from the source electrode 21. Therefore, even if a positive voltage, e.g., 300 V, is applied to the drain electrode 22, the semiconductor device enters an off state, where no current flows. At this time, electrons supplied to the first column region 12 are discharged from the drain electrode 22. Holes generated in the first column region 12 are discharged from the source electrode 21. This depletes the PSJ structure 14, resulting in a charge balance state where the polarization charges are balanced. The dotted lines in FIG. 4B represent electric field intensity contours.

[0033] Therefore, such a semiconductor device ideally has a breakdown voltage characteristic of up to 3 MV / cm, which is the breakdown field strength of GaN. In other words, for example, by making the thickness of the PSJ structure 14 1 μm, a breakdown voltage of 300 V can be obtained.

[0034] For example, it has been reported that a semiconductor device having a silicon-based superjunction structure has a maximum breakdown strength of 0.3 MV / cm. Therefore, compared to such a semiconductor device, the semiconductor device of this embodiment can achieve the same maximum breakdown strength with a column thickness (i.e., column depth) that is 1 / 10 of that of the semiconductor device having a silicon-based superjunction structure. In other words, the semiconductor device of this embodiment can have a PSJ structure 14 with a thinner column thickness than a semiconductor device having a silicon-based superjunction structure, which facilitates the manufacturing process. The column thickness, in other words, is the length along the stacking direction of the GaN substrate 11 and the PSJ structure 14.

[0035] 4B, the electric field intensity is less likely to concentrate in the PSJ structure 14 of this embodiment, which prevents a large electric field intensity from being applied to the gate insulating film 18, thereby improving the reliability of the gate insulating film 18.

[0036] Next, a method for manufacturing the semiconductor device will be described with reference to FIGS. 5A to 5D.

[0037] First, as shown in FIG. 5A, the first main surface 11a and the second main surface 11b are m-planes, and the n + A GaN substrate 11 is prepared as a mold. Then, a second column region-forming layer 130 that forms the second column region 13 is disposed by epitaxial growth on the first main surface 11a of the GaN substrate 11. The second column region-forming layer 130 is formed of an undoped u-AlGaN layer.

[0038] 5B, a resist 100 is placed on the second column region-forming layer 130, and the resist 100 is patterned so as to expose a region where the first column region 12 is to be formed. Then, dry etching such as ICP-RIE (abbreviation for Inductively Coupled Plasma-Reactive Ion Etching) is performed using the resist 100 as a mask to form burying trenches 131 for disposing the first column region 12. As a result, the second column region 13 is formed in a portion of the second column region-forming layer 130 that is sandwiched between the burying trenches 131. In other words, the second column region 13 is formed in a portion of the second column region-forming layer 130 where the burying trenches 131 are not formed.

[0039] 5C , a first column region-forming layer 120 that constitutes the first column region 12 is disposed by epitaxial growth so as to fill the burying trench 131. As a result, the first column region 12 is formed in the portion disposed in the burying trench 131, and a PSJ structure 14 having the first column region 12 and the second column region 13 is formed. The first column region-forming layer 120 is formed of an undoped u-GaN layer.

[0040] Subsequently, as shown in FIG. 5D, the first column region forming layer 120 formed on the second column region forming layer 130 is removed by polishing or CMP (short for Chemical Mechanical Polishing) or the like.

[0041] Thereafter, although detailed steps are omitted, a predetermined semiconductor manufacturing process is carried out to form the base layer 15, source region 16, trench gate structure, source electrode 21, drain electrode 22, etc., thereby manufacturing the semiconductor device.

[0042] According to the present embodiment described above, the PSJ structures 14 are arranged along the surface direction of the GaN substrate 11, and current flows in the thickness direction of the semiconductor substrate 10. This allows the electrodes 19, 21, and 22 connected to the semiconductor element to be arranged separately on the one surface 10a side and the other surface 10b side of the semiconductor substrate 10, making it easier to reduce the restrictions on the electrodes 19, 21, and 22.

[0043] In this embodiment, a base layer 15 made of a p-GaN layer is disposed on the PSJ structure 14. Therefore, when manufacturing a semiconductor device, after performing the step of Fig. 5C, the base layer 15 may be formed by depositing a p-GaN layer directly on the u-GaN layer without performing the step of Fig. 5D.

[0044] (1) In this embodiment, a MOSFET is formed as the semiconductor element, and the base layer 15 disposed on the PSJ structure 14 is connected to the source electrode 21. Therefore, when the device is off, holes that may be present in the first column region 12 can be extracted from the source electrode 21, and the PSJ structure 14 can be brought into a state where the polarization charges are balanced.

[0045] (2) In this embodiment, the first column regions 12 and the second column regions 13 are arranged along the surface of the GaN substrate 11, and current flows in the thickness direction of the semiconductor substrate 10. This facilitates the flow of large currents compared to a case where a PSJ structure is formed by stacking GaN layers and AlGaN layers and then using this PSJ structure to form a MOSFET. A semiconductor device having a PSJ structure in which GaN layers and AlGaN layers are stacked can be considered a semiconductor device in which a MOSFET is formed by arranging a gate electrode on the PSJ structure. However, in this semiconductor device, if too many GaN layers and AlGaN layers are stacked, the on and off states of the semiconductor device may not be switched by the gate voltage applied to the gate electrode. In contrast, in this embodiment, the first column regions 12 and the second column regions 13 are arranged along the surface of the GaN substrate 11, and current flows in the thickness direction of the semiconductor substrate 10. This allows the number of first column regions 12 and second column regions 13 to be adjusted as needed, making it easier to accommodate large currents.

[0046] (3) In this embodiment, the first column region 12 and the second column region 13 are formed of undoped layers. Therefore, compared to a third embodiment described later in which the first column region 12 and the second column region 13 are formed of doped layers, the amount of impurities is small, which allows holes to escape more quickly when the device is turned off, thereby increasing the switching speed.

[0047] (Modification of the first embodiment) A modification of the first embodiment will be described. In the first embodiment, the PSJ structure 14 may be formed on the GaN substrate 11 as follows. That is, as shown in FIG. 6A, after preparing the GaN substrate 11, a first column region-forming layer 120 that forms the first column region 12 is disposed on the first main surface 11a of the GaN substrate 11 by epitaxial growth. Next, as shown in FIG. 6B, a resist 100 is disposed on the first column region-forming layer 120, and dry etching is performed to form burying trenches 121 in which the second column region 13 will be disposed. As a result, the first column region 12 is formed in the portion of the first column region-forming layer 120 that is sandwiched between the burying trenches 121. That is, the first column region 12 is formed in the portion of the first column region-forming layer 120 where the burying trenches 121 are not formed.

[0048] 6C, a second column region forming layer 130 is disposed by epitaxial growth so as to fill the burying trench 121. As a result, a second column region 13 is formed in the portion disposed in the burying trench 121, and a PSJ structure 14 having the first column region 12 and the second column region 13 is formed.

[0049] 6D, the second column region forming layer 130 formed on the first column region forming layer 120 is removed. In this manner, the PSJ structure 14 may be disposed on the GaN substrate 11.

[0050] (Second embodiment) A second embodiment will be described. This embodiment differs from the first embodiment in that the semiconductor element is changed. As the rest of the configuration is the same as the first embodiment, a description thereof will be omitted here.

[0051] 7, the semiconductor device of this embodiment is configured by forming an HBT (abbreviation of Heterojunction Bipolar Transistor) as a semiconductor element. Specifically, an emitter layer 41 made of an n-type n-GaN layer is disposed on the base layer 15 at a portion located on the opposite side of the base layer 15 from the first column region 12. An n-type n-GaN layer having a higher impurity concentration than the emitter layer 41 is disposed on the emitter layer 41. + Type n + The base layer 15 of this embodiment is doped with p-type impurity Mg at a concentration of 1×10 20 / cm 2 The thickness is set to 100 nm or less.

[0052] One surface 10a of semiconductor substrate 10 is composed of contact layer 42, and the other surface 10b is composed of second main surface 11b of GaN substrate 11. Therefore, it can be said that semiconductor substrate 10 of this embodiment has exposing trenches 43 formed in one surface 10a of semiconductor substrate 10 so that base layer 15 is exposed between emitter layers 41.

[0053] An emitter electrode 51 is disposed on the contact layer 42. A base electrode 52 is disposed on a portion of the base layer 15 that is exposed from the emitter layer 41. A collector electrode 53 is disposed on the other surface 10b of the semiconductor substrate 10. In this embodiment, the emitter electrode 51 and the base electrode 52 correspond to one-surface electrodes, and the collector electrode 53 corresponds to the other-surface electrode.

[0054] Next, the operation and effects of the semiconductor device of this embodiment will be described with reference to FIGS. 8A and 8B.

[0055] 8A, in the PSJ structure 14, as in the first embodiment, the 2DEG 31 and the 2DHG 32 are generated at the interface between the first column region 12 and the second column region 13. When, for example, 3 to 4 V is applied to the base electrode 52, electrons are supplied from the emitter electrode 51, and a current flows to the collector electrode 53 via the 2DEG 31 formed in the first column region 12. In this case, since there is no part of the 2DHG 32 that is easily extracted, the current flowing through the semiconductor device is dominated by an electron current.

[0056] As shown in FIG. 8B, when the voltage applied to the base electrode 52 becomes, for example, 0 V, the base potential rises and no new electrons are supplied from the emitter electrode 51. Therefore, even if a positive voltage, for example, 300 V, is applied to the collector electrode 53, the semiconductor device enters an off state in which no current flows. At this time, the electrons supplied to the first column region 12 are discharged from the collector electrode 53. Holes generated in the first column region 12 are discharged from the base electrode 52. This depletes the PSJ structure 14, resulting in a charge balance state in which the polarization charges are balanced. The dotted lines in FIG. 8B represent electric field intensity contours.

[0057] According to the present embodiment described above, the PSJ structures 14 are arranged along the surface direction of the GaN substrate 11, and current flows in the thickness direction of the semiconductor substrate 10. Therefore, the same effects as those of the first embodiment can be obtained.

[0058] (1) In this embodiment, an HBT is formed as the semiconductor element, and the base layer 15 disposed on the PSJ structure 14 is connected to the base electrode 52. Therefore, during the off state, holes that may be present in the first column region 12 can be extracted from the base electrode 52, and the PSJ structure 14 can be brought into a state where the polarization charges are balanced.

[0059] (Third embodiment) A third embodiment will now be described. This embodiment is different from the first embodiment in that the configurations of the first column region 12 and the second column region 13 are changed. As the rest of the configuration is the same as the first embodiment, a description thereof will be omitted here.

[0060] The basic configuration of the semiconductor device of this embodiment is the same as that of the first embodiment. However, in this embodiment, as shown in Fig. 9, the first column region 12 is composed of an n-GaN layer doped with n-type impurities, and the second column region 13 is composed of a p-AlGaN layer doped with p-type impurities. In other words, the first column region 12 and the second column region 13 are composed of doped layers.

[0061] An example of an n-type impurity doped into the first column region 12 is Si (i.e., silicon). An example of a p-type impurity doped into the second column region 13 is Mg. The impurity concentrations of the first column region 12 and the second column region 13 are adjusted according to the width along the arrangement direction (i.e., the C-axis direction) and the activation rate of the doped impurity so as to maintain charge balance. Here, configuring the first column region 12 and the second column region 13 so as to maintain charge balance means configuring the first column region 12 and the second column region 13 as follows. That is, the first column region 12 and the second column region 13 are configured so that the product of the width of the first column region 12, the n-type impurity concentration, and the activation rate of the n-type impurity is equal to the product of the width of the second column region 13, the p-type impurity concentration, and the activation rate of the p-type impurity.

[0062] The first column region 12 and the second column region 13 are formed of a doped layer that is actively doped with impurities, and have a fixed charge of 5×10 16 / cm 3 In the GaN layer, the activation rate of p-type Mg is approximately 10% at maximum, and the activation rate of n-type Si is approximately 100% at room temperature.

[0063] In such a PSJ structure 14, 2DEG and 2DHG are induced at the AlGaN / GaN interface, which is the interface between the first column region 12 and the second column region 13, due to polarization effects and the like. In this embodiment, the first column region 12 is formed of an n-GaN layer, and the second column region 13 is formed of a p-AlGaN layer. Therefore, as shown in FIG. 10 , compared to FIG. 3 above, the energy band in the first column region 12 changes to be convex downward, and the energy band in the second column region 13 changes to be convex upward. Note that FIG. 10 is an energy band diagram of a portion along line XX in FIG. 9 .

[0064] 11 and 12, in the semiconductor device of this embodiment, the region where the conductor bottom energy Ec is lower than the Fermi level (i.e., quantum well width d1) is wider than in the semiconductor device of the first embodiment. As a result, the 2DEG generated on the Ga-face side of the first column region 12 increases. Note that in the semiconductor device of this embodiment, the region where the valence band top energy Ev is higher than the Fermi level (i.e., quantum well width d2) is narrower than in the semiconductor device of the first embodiment. As a result, the 2DHG generated on the N-face side of the first column region 12 decreases.

[0065] Next, the operation and effects of the semiconductor device of this embodiment will be described with reference to Figures 13A and 13B. Note that GaN substrate 11 and drain electrode 22 are omitted in Figures 13A and 13B.

[0066] 13A, in the semiconductor device of this embodiment, 2DEG 31 and 2DHG 32 are generated at the interface between the first column region 12 and the second column region 13, as in the first embodiment. Furthermore, since the first column region 12 is configured as an n-type layer, fixed positive charges 33 are generated, and since the second column region 13 is configured as a p-type layer, fixed negative charges 34 are generated. Furthermore, as described above, the amount of 2DEG 31 generated on the Ga-face side of the first column region 12 increases. Therefore, the electron current can be increased when the semiconductor device is in the on state, improving the current capability.

[0067] 13B, when the gate voltage applied to the gate electrode 19 becomes less than the threshold voltage, no inversion layer is formed in the base layer 15, and new electrons are no longer supplied from the source electrode 21. The electrons previously supplied to the first column region 12 are then discharged from the drain electrode 22, and the holes generated in the first column region 12 are discharged from the source electrode 21, resulting in an OFF state. The PSJ structure 14 then becomes depleted, entering a charge balance state where the polarization charges are balanced and the fixed charges are balanced. The dotted lines in FIG. 13B represent the electric field intensity contours.

[0068] Next, a method for manufacturing the above semiconductor device will be described with reference to FIGS. 14A to 14C.

[0069] First, as shown in FIG. 14A, the first main surface 11a and the second main surface 11b are m-planes, and the n + A GaN substrate 11 having a p-type structure is prepared. Then, a second column region-forming layer 130 that forms the second column region 13 is disposed on the first main surface 11a of the GaN substrate 11 by epitaxial growth. At this time, in this embodiment, the second column region-forming layer 130 is disposed while being doped with a p-type impurity such as Mg. In other words, the second column region-forming layer 130, which is a doped layer, is disposed.

[0070] 14B, a resist 100 is placed on the second column region forming layer 130, and dry etching is performed to form burying trenches 131 for disposing the first column regions 12. As a result, the second column regions 13 made of p-AlGaN layers are formed in the portions of the second column region forming layer 130 that are sandwiched between the burying trenches 131.

[0071] Next, as shown in FIG. 14C , a first column region-forming layer 120 that constitutes the first column region 12 is disposed by epitaxial growth so as to fill the burying trench 131. In this embodiment, the first column region-forming layer 120 is disposed while being doped with an n-type impurity such as Si. That is, the first column region-forming layer 120, which is a doped layer, is disposed. As a result, the first column region 12 is formed in the portion disposed in the burying trench 131, and a PSJ structure 14 having the first column region 12 and the second column region 13 is formed. The impurity concentrations of the first column region-forming layer 120 and the second column region-forming layer 130 are adjusted so as to maintain charge balance when the first column region 12 and the second column region 13 are formed.

[0072] Thereafter, although not particularly shown, the steps from FIG. 5D onwards are carried out in the same manner as in the first embodiment, thereby manufacturing the semiconductor device of this embodiment.

[0073] According to the present embodiment described above, the PSJ structures 14 are arranged along the surface direction of the GaN substrate 11, and current flows in the thickness direction of the semiconductor substrate 10. Therefore, the same effects as those of the first embodiment can be obtained.

[0074] (1) In this embodiment, the first column region 12 is made of an n-GaN layer doped with n-type impurities, and the second column region 13 is made of a p-AlGaN layer doped with p-type impurities. Charge balance is maintained between the first column region 12 and the second column region 13. Therefore, when the semiconductor device is turned on, the 2DEG can be increased, and current performance can be improved.

[0075] (Modification of the third embodiment) A modification of the third embodiment will be described. In the third embodiment, a PSJ structure 14 may be formed on a GaN substrate 11, as in the modification of the first embodiment. That is, as shown in FIG. 15A, after preparing a GaN substrate 11, a first column region-forming layer 120 that forms a first column region 12 is formed by epitaxial growth on the first main surface 11a of the GaN substrate 11. The first column region-forming layer 120 is formed while being doped with an n-type impurity such as Si. Next, as shown in FIG. 15B, a resist 100 is formed on the first column region-forming layer 120, and dry etching is performed to form burying trenches 121 for arranging the second column region 13. This forms the first column region 12 in the portion of the first column region-forming layer 120 that is sandwiched between the burying trenches 121. Next, as shown in FIG. 15C, a second column region-forming layer 130 is formed by epitaxial growth so as to fill the burying trenches 121. At this time, the second column region forming layer 130 is disposed while being doped with a p-type impurity such as Mg. As a result, the second column region 13 is formed in the portion disposed in the burying trench 121, and a PSJ structure 14 having the first column region 12 and the second column region 13 is formed.

[0076] Thereafter, although not specifically shown, the PSJ structure 14 may be disposed on the GaN substrate 11 by performing the step of FIG. 6D in the same manner as in the modified example of the first embodiment. Note that a base layer 15 made of a p-GaN layer is disposed on the PSJ structure 14. Therefore, when manufacturing a semiconductor device, after performing the step of FIG. 15C, the second column region-forming layer 130 formed on the first column region-forming layer 120 may not be removed, and a p-GaN layer may be formed as is to form the base layer 15. In other words, the Al constituting the second column region 13 may be removed. 1-x Ga x By setting x to 1 in the N layers, the PSJ structure 14 and the base layer 15 may be formed continuously.

[0077] (Fourth embodiment) A fourth embodiment will now be described. This embodiment is different from the second embodiment in that the configurations of the first column region 12 and the second column region 13 are changed. As the rest of the configuration is the same as the second embodiment, a description thereof will be omitted here.

[0078] 16, the semiconductor device of this embodiment is configured by forming an HBT similar to that of the second embodiment. However, in the semiconductor device of this embodiment, like the third embodiment, the first column region 12 is configured by an n-GaN layer doped with n-type impurities, and the second column region 13 is configured by a p-AlGaN layer doped with p-type impurities. In other words, the first column region 12 and the second column region 13 are configured by doped layers. Note that, like the third embodiment, the widths and impurity concentrations of the first column region 12 and the second column region 13 are adjusted so as to maintain charge balance.

[0079] Next, the operation and effects of the semiconductor device of this embodiment will be described with reference to FIGS. 17A and 17B.

[0080] As in the second embodiment, in the PSJ structure 14, as shown in FIG. 17A, 2DEG 31 and 2DHG 32 are generated at the interface between the first column region 12 and the second column region 13. As in the third embodiment, fixed positive charges 33 are generated in the first column region 12, and fixed negative charges 34 are generated in the second column region 13. Furthermore, in the first column region 12, the amount of 2DEG 31 (i.e., negative polarization charges) generated on the Ga surface side increases. This increases the electron current when the semiconductor device is in the on state, thereby improving the current capability.

[0081] As shown in FIG. 17B, when the voltage applied to the base electrode 52 becomes, for example, 0 V, the base potential rises and no new electrons are supplied from the emitter electrode 51. Therefore, even if a positive voltage, for example, 300 V, is applied to the collector electrode 53, the semiconductor device enters an off state, in which no current flows. At this time, the electrons supplied to the first column region 12 are discharged from the collector electrode 53. Holes generated in the first column region 12 are discharged from the base electrode 52. This depletes the PSJ structure 14, resulting in a charge balance state in which the polarization charges are balanced and the fixed charges are balanced. The dotted lines in FIG. 17B represent the electric field intensity contours.

[0082] According to the present embodiment described above, the PSJ structures 14 are arranged along the surface direction of the GaN substrate 11, and current flows in the thickness direction of the semiconductor substrate 10. Therefore, the same effects as those of the first embodiment can be obtained.

[0083] (1) In this embodiment, the first column region 12 is composed of an n-GaN layer doped with n-type impurities, and the second column region 13 is composed of a p-AlGaN layer doped with p-type impurities. The widths and impurity concentrations of the first column region 12 and the second column region 13 are adjusted to maintain charge balance. Therefore, when the semiconductor device is turned on, the 2DEG 31 can be increased, thereby improving current performance.

[0084] (Other embodiments) Although the present disclosure has been described with reference to the embodiments, it is understood that the present disclosure is not limited to the embodiments or structures. The present disclosure also encompasses various modifications and modifications within the scope of equivalents. In addition, various combinations and forms, as well as other combinations and forms including only one element, more than one element, or less than one element, are also within the scope and spirit of the present disclosure.

[0085] For example, the first and third embodiments described semiconductor devices including MOSFETs as semiconductor elements, and the second and fourth embodiments described semiconductor devices including HBTs as semiconductor elements. However, the semiconductor elements may be other semiconductor elements, such as diodes, as shown in FIG. 18 . Specifically, in this semiconductor device, a PSJ structure 14 is disposed on a GaN substrate 11 to form a semiconductor substrate 10. One surface 10a of the semiconductor substrate 10 corresponds to the PSJ structure 14, and the other surface 10b corresponds to the second main surface 11b of the GaN substrate 11. An anode electrode 61 serving as a one-surface electrode is disposed on the one surface 10a of the semiconductor substrate 10, and a cathode electrode 62 serving as a other-surface electrode is disposed on the other surface 10b. In this case, the first column region 12 and the second column region 13 may be formed of doped layers, as in the third and fourth embodiments.

[0086] In the first and third embodiments, an n-channel type trench gate structure MOSFET in which the first conductivity type is n-type and the second conductivity type is p-type has been described as an example. However, the semiconductor device may have a p-channel type trench gate structure MOSFET formed therein in addition to the n-channel type. Furthermore, the semiconductor device may have a configuration in which an IGBT having a similar structure is formed therein, in addition to the MOSFET. In the case of an IGBT, the n-channel type MOSFET in the first and third embodiments may have a p-channel type trench gate structure formed therein. + The p-type GaN substrate 11 + The GaN substrate 11 is changed to a vertical MOSFET of the same type as that of the first embodiment.

[0087] In the second and fourth embodiments, an npn-type HBT in which the first conductivity type is n-type and the second conductivity type is p-type has been described as an example of the semiconductor element. However, the semiconductor device may be configured with a pnp-type HBT formed as the semiconductor element.

[0088] In the third and fourth embodiments, the semiconductor device in which the first column region 12 is doped with n-type impurities and the second column region 13 is doped with p-type impurities has been described. However, the first column region 12 may be configured as a doped layer doped with p-type impurities and the second column region 13 may be configured as a doped layer doped with n-type impurities. In this case, compared to when the first column region 12 and the second column region 13 are undoped layers, the region where the upper end energy Ev of the valence band is higher than the Fermi level (i.e., the quantum well width d2) increases, resulting in a higher hole concentration. Therefore, such a semiconductor device is preferably applied to a configuration in which hole current is dominant in the on-state.

[0089] In the third and fourth embodiments, examples have been described in which the first column region 12 and the second column region 13 are formed as doped layers by epitaxial growth while doping with impurities. However, the first column region 12 and the second column region 13, which are doped layers, may be formed as follows. For example, after performing the step of FIG. 5D in the first embodiment, impurity ions may be implanted to form the first column region 12 composed of an n-GaN layer and the second column region 13 composed of a p-AlGaN layer.

[0090] (Features of the present invention) [Claim 1] A semiconductor device in which a semiconductor element is formed, a semiconductor substrate (10) having one surface (10a) and another surface (10b) and on which the semiconductor element is formed; One-surface electrodes (19, 21, 51, 52, 61) disposed on one surface of the semiconductor substrate and electrically connected to the semiconductor element; and an other-surface electrode (22, 53, 62) disposed on the other surface side of the semiconductor substrate and electrically connected to the semiconductor element, The semiconductor substrate is a gallium nitride substrate (11) that is hexagonal, has a first main surface (11a) that is an m-plane, one direction in the plane direction of the first main surface is a direction along the c-axis direction, and has a second main surface (11b) opposite to the first main surface that constitutes the other surface of the semiconductor substrate; a plurality of first column regions (12) disposed on a first main surface of the gallium nitride substrate, each of which is composed of a first nitride semiconductor layer and extends in one direction in the surface direction of the gallium nitride substrate; and second column regions (13) disposed on the first main surface of the gallium nitride substrate, each of which is composed of a second nitride semiconductor layer having a band gap higher than that of the first nitride semiconductor layer, each of which is disposed between the first column regions and which together with the first column regions form a polarization super junction structure (14), the first column regions and the second column regions are alternately arranged along the c-axis direction on the first main surface, A semiconductor device in which a current flows between one surface and the other surface of the semiconductor substrate. [Claim 2] a base layer (15) disposed on the polarization superjunction structure and having a first conductivity type or a second conductivity type; 2. The semiconductor device according to claim 1, wherein the one-surface electrode has a base layer electrode (21, 52) connected to the base layer. [Claim 3] an impurity region (16) disposed on the base layer and connected to the base layer electrode; 3. The semiconductor device according to claim 2, further comprising: a trench gate structure having a gate insulating film (18) formed on a wall surface of a trench (17) that penetrates the base layer and reaches the polarization super junction structure; and a gate electrode (19) as the one-side electrode formed on the gate insulating film. [Claim 4] an emitter layer (41) disposed on the base layer in a state in which a portion of the base layer is exposed; 3. The semiconductor device according to claim 2, further comprising an emitter electrode (51) as the one-surface electrode connected to the emitter layer. [Claim 5] 2. The semiconductor device according to claim 1, wherein the one-surface electrode is disposed on the polarization super junction structure and is directly connected to the polarization super junction structure. [Claim 6] 6. The semiconductor device according to claim 1, wherein the first column region and the second column region are made of undoped layers. [Claim 7] 6. The semiconductor device according to claim 1, wherein the first column region and the second column region are formed of doped layers, and a charge balance is maintained. [Claim 8] a semiconductor substrate (10) having one surface (10a) and another surface (10b) and on which a semiconductor element is formed; One-surface electrodes (19, 21, 51, 52, 61) disposed on one surface of the semiconductor substrate and electrically connected to the semiconductor element; and an other-surface electrode (22, 53, 62) disposed on the other surface side of the semiconductor substrate and electrically connected to the semiconductor element, The semiconductor substrate is a gallium nitride substrate (11) that is hexagonal, has a first main surface (11a) that is an m-plane, one direction in the plane direction of the first main surface is a direction along the c-axis direction, and has a second main surface (11b) opposite to the first main surface that constitutes the other surface of the semiconductor substrate; a plurality of first column regions (12) disposed on a first main surface of the gallium nitride substrate, each of which is composed of a first nitride semiconductor layer and extends in one direction in the surface direction of the gallium nitride substrate; and second column regions (13) disposed on the first main surface of the gallium nitride substrate, each of which is composed of a second nitride semiconductor layer having a band gap higher than that of the first nitride semiconductor layer, each of which is disposed between the first column regions and which together with the first column regions form a polarization super junction structure (14), the first column regions and the second column regions are alternately arranged along the c-axis direction on the first main surface, A method for manufacturing a semiconductor device in which a current flows between one surface and another surface of the semiconductor substrate, providing the gallium nitride substrate; epitaxially growing a second column region forming layer (130) that forms the second column region on a first main surface of the gallium nitride substrate; forming a burying trench (131) in a portion of the second column region forming layer where the first column region is to be disposed, and defining a portion different from the portion where the burying trench is formed as the second column region; epitaxially growing a first column region forming layer (120) that forms the first column region so that the burying trench is filled, and configuring the polarization super junction structure having the first column region and the second column region, with the portion located in the burying trench being the first column region. [Claim 9] a semiconductor substrate (10) having one surface (10a) and another surface (10b) and on which a semiconductor element is formed; One-surface electrodes (19, 21, 51, 52, 61) disposed on one surface of the semiconductor substrate and electrically connected to the semiconductor element; and an other-surface electrode (22, 53, 62) disposed on the other surface side of the semiconductor substrate and electrically connected to the semiconductor element, The semiconductor substrate is a gallium nitride substrate (11) that is hexagonal, has a first main surface (11a) that is an m-plane, one direction in the plane direction of the first main surface is a direction along the c-axis direction, and has a second main surface (11b) opposite to the first main surface that constitutes the other surface of the semiconductor substrate; a plurality of first column regions (12) disposed on a first main surface of the gallium nitride substrate, each of which is composed of a first nitride semiconductor layer and extends in one direction in the surface direction of the gallium nitride substrate; and second column regions (13) disposed on the first main surface of the gallium nitride substrate, each of which is composed of a second nitride semiconductor layer having a band gap higher than that of the first nitride semiconductor layer, each of which is disposed between the first column regions and which together with the first column regions form a polarization super junction structure (14), the first column regions and the second column regions are alternately arranged along the c-axis direction on the first main surface, A method for manufacturing a semiconductor device in which a current flows between one surface and another surface of the semiconductor substrate, providing the gallium nitride substrate; epitaxially growing a first column region forming layer (120) that forms the first column region on a first main surface of the gallium nitride substrate; forming a burying trench (121) in a portion of the first column region forming layer where the second column region is to be disposed, and defining a portion different from the portion where the burying trench is formed as the first column region; epitaxially growing a second column region forming layer (130) that forms the second column region so that the burying trench is filled, and configuring the polarization super junction structure having the first column region and the second column region, with the portion located in the burying trench being the second column region. [Claim 10] 10. The method for manufacturing a semiconductor device according to claim 8, wherein the first column region and the second column region are formed of undoped layers by forming the polarization super junction structure. [Claim 11] 10. The method for manufacturing a semiconductor device according to claim 8, wherein the first column region and the second column region are formed of doped layers by forming the polarization super junction structure. [Explanation of symbols]

[0091] 10. Semiconductor substrate 11 GaN substrate 11a 1st main surface 11b 2nd principal surface 10a one side 10b Other side 12 First column area 13 Second column area 14 PSJ structure 21 Source electrode (one-side electrode) 22 Drain electrode (other side electrode)

Claims

1. A semiconductor device in which a semiconductor element is formed, a semiconductor substrate (10) having one surface (10a) and another surface (10b) and on which the semiconductor element is formed; One-surface electrodes (19, 21, 51, 52, 61) disposed on one surface of the semiconductor substrate and electrically connected to the semiconductor element; and an other-surface electrode (22, 53, 62) disposed on the other surface side of the semiconductor substrate and electrically connected to the semiconductor element, The semiconductor substrate is a gallium nitride substrate (11) having a hexagonal crystal structure, a first main surface (11a) being an m-plane, one direction in the plane direction of the first main surface being a direction along the c-axis direction, and a second main surface (11b) opposite to the first main surface constituting the other surface of the semiconductor substrate; a plurality of first column regions (12) arranged on a first main surface of the gallium nitride substrate, each of which is composed of a first nitride semiconductor layer and extends in one direction in the surface direction of the gallium nitride substrate; and second column regions (13) arranged on the first main surface of the gallium nitride substrate, each of which is composed of a second nitride semiconductor layer having a band gap higher than that of the first nitride semiconductor layer, each of which is arranged between the first column regions and which together with the first column regions form a polarization super junction structure (14), the first column regions and the second column regions are alternately arranged along the c-axis direction on the first main surface, A current flows between one surface and the other surface of the semiconductor substrate, a base layer (15) disposed on the polarization superjunction structure and having a first conductivity type or a second conductivity type; The one-surface electrode has a base layer electrode (21, 52) connected to the base layer, an emitter layer (41) disposed on the base layer in a state where a part of the base layer is exposed; an emitter electrode (51) as the one-surface electrode connected to the emitter layer.

2. 2. The semiconductor device according to claim 1, wherein the first column region and the second column region are formed of undoped layers.

3. 2. The semiconductor device according to claim 1, wherein the first column region and the second column region are formed of doped layers, and a charge balance is maintained.

4. A semiconductor device in which a semiconductor element is formed, a semiconductor substrate (10) having one surface (10a) and another surface (10b) and on which the semiconductor element is formed; One-surface electrodes (19, 21, 51, 52, 61) disposed on one surface of the semiconductor substrate and electrically connected to the semiconductor element; and an other-surface electrode (22, 53, 62) disposed on the other surface side of the semiconductor substrate and electrically connected to the semiconductor element, The semiconductor substrate is a gallium nitride substrate (11) having a hexagonal crystal structure, a first main surface (11a) being an m-plane, one direction in the plane direction of the first main surface being a direction along the c-axis direction, and a second main surface (11b) opposite to the first main surface constituting the other surface of the semiconductor substrate; a plurality of first column regions (12) arranged on a first main surface of the gallium nitride substrate, each of which is composed of a first nitride semiconductor layer and extends in one direction in the surface direction of the gallium nitride substrate; and second column regions (13) arranged on the first main surface of the gallium nitride substrate, each of which is composed of a second nitride semiconductor layer having a band gap higher than that of the first nitride semiconductor layer, each of which is arranged between the first column regions and which together with the first column regions form a polarization super junction structure (14), the first column regions and the second column regions are alternately arranged along the c-axis direction on the first main surface, A current flows between one surface and the other surface of the semiconductor substrate, The first column region and the second column region are formed of doped layers, and a charge balance is maintained.

5. a base layer (15) disposed on the polarization superjunction structure and having a first conductivity type or a second conductivity type; 5. The semiconductor device according to claim 4, wherein the one-surface electrode has a base layer electrode (21, 52) connected to the base layer.

6. an impurity region (16) disposed on the base layer and connected to the base layer electrode; 6. The semiconductor device according to claim 5, further comprising: a trench gate structure having a gate insulating film (18) formed on a wall surface of a trench (17) that penetrates the base layer and reaches the polarization super junction structure; and a gate electrode (19) formed on the gate insulating film as the one-side electrode.

7. The semiconductor device according to claim 4 , wherein the one-surface electrode is disposed on the polarization super junction structure and is directly connected to the polarization super junction structure.

8. a semiconductor substrate (10) having one surface (10a) and another surface (10b) and on which a semiconductor element is formed; One-surface electrodes (19, 21, 51, 52, 61) disposed on one surface of the semiconductor substrate and electrically connected to the semiconductor element; and an other-surface electrode (22, 53, 62) disposed on the other surface side of the semiconductor substrate and electrically connected to the semiconductor element, The semiconductor substrate is a gallium nitride substrate (11) having a hexagonal crystal structure, a first main surface (11a) being an m-plane, one direction in the plane direction of the first main surface being a direction along the c-axis direction, and a second main surface (11b) opposite to the first main surface constituting the other surface of the semiconductor substrate; a plurality of first column regions (12) arranged on a first main surface of the gallium nitride substrate, each of which is composed of a first nitride semiconductor layer and extends in one direction in the surface direction of the gallium nitride substrate; and second column regions (13) arranged on the first main surface of the gallium nitride substrate, each of which is composed of a second nitride semiconductor layer having a band gap higher than that of the first nitride semiconductor layer, each of which is arranged between the first column regions and which together with the first column regions form a polarization super junction structure (14), the first column regions and the second column regions are alternately arranged along the c-axis direction on the first main surface, A method for manufacturing a semiconductor device in which a current flows between one surface and another surface of the semiconductor substrate, providing the gallium nitride substrate; epitaxially growing a second column region forming layer (130) that forms the second column region on a first main surface of the gallium nitride substrate; forming a buried trench (131) in a portion of the second column region forming layer where the first column region is to be disposed, and defining a portion different from the portion where the buried trench is formed as the second column region; epitaxially growing a first column region forming layer (120) that forms the first column region so that the burying trench is filled, and configuring the polarization super junction structure having the first column region and the second column region, with the portion located in the burying trench being the first column region.

9. The method for manufacturing a semiconductor device according to claim 8 , wherein the polarization super junction structure is formed by forming the first column region and the second column region each made of an undoped layer.

10. The method for manufacturing a semiconductor device according to claim 8 , wherein the polarization super junction structure comprises forming the first column region and the second column region each made of a doped layer.

11. a semiconductor substrate (10) having one surface (10a) and another surface (10b) and on which a semiconductor element is formed; One-surface electrodes (19, 21, 51, 52, 61) disposed on one surface of the semiconductor substrate and electrically connected to the semiconductor element; and an other-surface electrode (22, 53, 62) disposed on the other surface side of the semiconductor substrate and electrically connected to the semiconductor element, The semiconductor substrate is a gallium nitride substrate (11) having a hexagonal crystal structure, a first main surface (11a) being an m-plane, one direction in the plane direction of the first main surface being a direction along the c-axis direction, and a second main surface (11b) opposite to the first main surface constituting the other surface of the semiconductor substrate; a plurality of first column regions (12) arranged on a first main surface of the gallium nitride substrate, each of which is composed of a first nitride semiconductor layer and extends in one direction in the surface direction of the gallium nitride substrate; and second column regions (13) arranged on the first main surface of the gallium nitride substrate, each of which is composed of a second nitride semiconductor layer having a band gap higher than that of the first nitride semiconductor layer, each of which is arranged between the first column regions and which together with the first column regions form a polarization super junction structure (14), the first column regions and the second column regions are alternately arranged along the c-axis direction on the first main surface, A method for manufacturing a semiconductor device in which a current flows between one surface and another surface of the semiconductor substrate, providing the gallium nitride substrate; epitaxially growing a first column region forming layer (120) that forms the first column region on a first main surface of the gallium nitride substrate; forming a buried trench (121) in a portion of the first column region forming layer where the second column region is to be disposed, and defining a portion different from the portion where the buried trench is formed as the first column region; epitaxially growing a second column region forming layer (130) that forms the second column region so that the burying trench is filled, and configuring the polarization superjunction structure having the first column region and the second column region, with the portion located in the burying trench being the second column region; A method for manufacturing a semiconductor device in which the polarization super junction structure is formed by forming the first column region and the second column region each formed of a doped layer.

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