Semiconductor Devices

Abstract

To obtain RC-IGBT with a relatively small leakage current and capable of performing high-speed operation.SOLUTION: A first crystal defect layer D1 and a second crystal defect layer D2 are formed locally on a p+ layer 16 side in a region I and a p- layer 12 side in a region II in an n- layer 11. In the region I, the first crystal defect layer D1 is formed in a region near the p+ layer 16 to shorten a life of the small number of carriers in this region, thereby a speed of an operation from on to off of the IGBT can be increased. The second crystal defect layer D2 is formed in the region II in plan view such that a peak of crystal defect concentration is located at a position that is on the p- layer 12 side with respect to the first crystal defect layer D1 and shallower than a bottom of a groove T, and the crystal defect concentration is locally increased so as to reduce the crystal defect concentration on the n+ layer 17 side.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a structure of a semiconductor device in which an IGBT (Insulated Gate Bipolar Transistor) and a freewheel diode are formed on the same semiconductor substrate. [Background technology]

[0002] Switching elements capable of high-speed switching operations at high power are widely used, for example, to control motors. When an IGBT is used as such a switching element, it is often combined with a freewheel diode, which passes a current in the opposite direction to when the IGBT is on, to suppress the occurrence of a flyback voltage when the IGBT is off. One such semiconductor device is known as the RC-IGBT (Reverse Conducting IGBT), in which a freewheel diode (diode) is formed on the same semiconductor substrate as the IGBT.

[0003] The basic structure of an RC-IGBT can be realized by partially modifying a normal IGBT. FIG. 12 is a cross-sectional view showing an example of the structure of a semiconductor device 900 that is a trench-type RC-IGBT. Here, an IGBT is formed in region I (IGBT region: first region) on the left side of the figure, and a diode is formed in region II (diode region: second region) on the right side of the figure. In FIG. 12, n - On the layer (n-type first semiconductor region) 91, - A p-type second semiconductor region in the region I and a p-type fifth semiconductor region in the region II are formed on the surface side of the semiconductor substrate 90. - Through layer 92 - A trench T is formed in the gate electrode 81, reaching the layer 91. A plurality of trenches T are formed in parallel, extending in a direction perpendicular to the plane of the paper in FIG. 12. An oxide film (gate insulating film) 93 is uniformly formed on the inner surface (side surface) of the trench T, and then a gate electrode 81 is formed to fill the trench T.

[0004] On the surface side of the semiconductor substrate 90 in the region I, n + A layer (third semiconductor region) 94 is formed on the surface of the semiconductor substrate 90. An emitter electrode 82 is formed on the surface of the semiconductor substrate 90. On the surface side of the trench T, an interlayer insulating film 95 is formed so as to cover the gate electrode 81 (trench T). Therefore, the emitter electrode 82 is in contact with the n-type semiconductor layer 94 through the portion where the interlayer insulating film 95 is not formed. + Layer 94 and p - The gate electrode 81 is electrically connected to both the first and second layers 92 .

[0005] A collector electrode 83 is formed on the entire back surface of the semiconductor substrate 90. Here, the collector electrode 83 and n - Between the layers 91, in region I, p + In region II, a layer (collector layer: fourth semiconductor region) 96 is provided. + The sixth semiconductor region 97 is formed in the region I. + Layer 94 is the emitter region, p - Layer 92 is the base region, p + An IGBT is formed with layer 96 as the collector region, and n - Layer 91 becomes the drift layer of this IGBT. On the other hand, in region II, p - Layer 92 is the anode side semiconductor, n - Layer 91(n + A pn diode is formed with the layer 97) as the cathode side semiconductor. In this case, the boundary between region I and region II is p + Layer (collector layer) 96 and n + 12, the region II also has a trench T, and an electrode or the like is formed in the trench T via an insulating film, as in the region I, but the form of these may be set appropriately.

[0006] RC-IGBTs require a small collector-emitter saturation voltage (VCEsat) in the IGBT. On the other hand, the forward voltage VF of the diode (freewheeling diode) must be small. Furthermore, for the high-speed operation of RC-IGBTs, there is also a need for improved (faster) recovery characteristics immediately after the diode changes from forward to reverse direction.

[0007] To improve the recovery characteristics of a diode, it is effective to quickly eliminate the minority carriers present in large numbers in the semiconductor during forward current flow, and therefore it is effective to shorten the minority carrier lifetime in the portion of the semiconductor layer that functions as a diode. To shorten the minority carrier lifetime in this way, a technique for introducing crystal defects into the semiconductor layer is used, and ion implantation of light ions such as protons and He is effective for this purpose. Ion implantation can easily introduce such crystal defects into a localized region of the semiconductor layer.

[0008] In Patent Document 1, the anode side semiconductor (p - Layer 92) - This document describes a method for locally introducing crystal defects only into the region of layer 91. Furthermore, Patent Document 2 describes a structure in which, in an RC-IGBT in which IGBTs and diodes are arranged repeatedly, crystal defects are not introduced between or immediately below the base regions of the IGBTs.

[0009] Furthermore, Patent Document 3 describes a manufacturing method in which, after shielding a region I on the front side of a semiconductor substrate where an IGBT is formed, light ions are irradiated onto the front side of the semiconductor substrate in a region II where a diode is formed, and light ions are irradiated onto the back side of the semiconductor substrate in a region I where an IGBT is formed, after shielding a region II on the back side of the semiconductor substrate where a diode is formed. [Prior art documents] [Patent documents]

[0010] [Patent Document 1] International Publication No. WO2013 / 046377 [Patent Document 2] Japanese Patent Application Laid-Open No. 2007-103770 [Patent Document 3] Japanese Patent Application Laid-Open No. 2013-197306 Summary of the Invention [Problem to be solved by the invention]

[0011] The techniques described in Patent Documents 1 and 2 can increase the speed of diodes but do not improve the operation of IGBTs. In contrast, the technique described in Patent Document 3 can increase the speed of both diodes and IGBTs. However, in the structure described in Patent Document 3, a crystal defect layer is formed in a wide region in the thickness direction of the semiconductor substrate, from the p-layer (anode-side semiconductor) to the N-layer (cathode-side semiconductor), and the leakage current (reverse current) of the diode formed by this pn junction increases. This causes the RC-IGBT to heat up and, in some cases, may even destroy it.

[0012] For this reason, there was a demand for RC-IGBTs that have relatively small leakage current and are capable of high-speed operation.

[0013] The present invention has been made in view of the above problems, and an object of the present invention is to provide an invention that solves the above problems. [Means for solving the problem]

[0014] In order to solve the above problems, the present invention has the following configurations. A semiconductor device of the present invention comprises a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type opposite to the first conductivity type formed on the first semiconductor region, a third semiconductor region of the first conductivity type formed on a surface side of the second semiconductor region, a fourth semiconductor region of the second conductivity type formed below the first semiconductor region, an emitter electrode electrically connected to the second semiconductor region and the third semiconductor region, and a collector electrode electrically connected to the fourth semiconductor region, wherein an insulated gate field effect transistor in which a current between the emitter electrode and the collector electrode is controlled by a gate electrode formed on the surface side of the second semiconductor region is formed in the first region in a plan view, and a trench penetrating a fifth semiconductor region in a thickness direction, wherein a diode formed by electrically connecting the emitter electrode to the fifth semiconductor region and electrically connecting the collector electrode to the sixth semiconductor region is formed in a second region adjacent to the first region in a plan view, and the first semiconductor region is provided with: a first crystal defect layer formed in the first region in a plan view, the crystal defect concentration having a peak on the fourth semiconductor region side in the thickness direction and locally increased on the second semiconductor region side so that the crystal defect concentration is lower on the second semiconductor region side; and a second crystal defect layer formed in the second region in a plan view, the crystal defect concentration having a peak on the fifth semiconductor region side of the first crystal defect layer and shallower than a bottom of the trench in the thickness direction, and locally increased on the sixth semiconductor region side so that the crystal defect concentration is lower on the sixth semiconductor region side. a first-region-side second crystal defect layer, the peak of the crystal defect concentration being located closer to the second semiconductor region than the first crystal defect layer and shallower than the bottom of the trench, and the peak value of the crystal defect concentration being lower than the peak value of the crystal defect concentration in the second crystal defect layer in the second region, and the first crystal defect layer being formed below the first-region-side second crystal defect layer It is characterized by: Further, a semiconductor device of the present invention comprises a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type opposite to the first conductivity type formed on the first semiconductor region, a third semiconductor region of the first conductivity type formed on a surface side of the second semiconductor region, a fourth semiconductor region of the second conductivity type formed below the first semiconductor region, an emitter electrode electrically connected to the second semiconductor region and the third semiconductor region, and a collector electrode electrically connected to the fourth semiconductor region, wherein an insulated gate field effect transistor in which a current between the emitter electrode and the collector electrode is controlled by a gate electrode formed on the surface side of the second semiconductor region is formed in the first region in a plan view, and a sixth semiconductor region of the first conductivity type adjacent to the first region in a planar view, wherein a diode configured by electrically connecting the emitter electrode and the fifth semiconductor region and electrically connecting the collector electrode and the sixth semiconductor region is formed in a second region adjacent to the first region in a planar view, and the first semiconductor region is provided with a first crystal defect layer formed in the first region in a planar view, the first crystal defect layer having a peak on the fifth semiconductor region side in a thickness direction and the crystal defect concentration locally increased so that the crystal defect concentration is lower on the second semiconductor region side, and a second crystal defect layer formed in the second region in a planar view, the peak on the fifth semiconductor region side of the first crystal defect layer in a thickness direction and the crystal defect concentration locally increased so that the crystal defect concentration is lower on the sixth semiconductor region side. The second crystal defect layer does not extend to the boundary between the fourth semiconductor region and the sixth semiconductor region in a plan view. It is characterized by: Further, a semiconductor device of the present invention comprises: a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type opposite to the first conductivity type formed on the first semiconductor region; a third semiconductor region of the first conductivity type formed on a surface side of the second semiconductor region; a fourth semiconductor region of the second conductivity type formed below the first semiconductor region; an emitter electrode electrically connected to the second semiconductor region and the third semiconductor region; and a collector electrode electrically connected to the fourth semiconductor region, wherein an insulated gate field effect transistor in which a current between the emitter electrode and the collector electrode is controlled by a gate electrode formed on the surface side of the second semiconductor region is formed in the first region in a planar view; a diode in which a collector electrode and the fifth semiconductor region are electrically connected and a collector electrode and the sixth semiconductor region are electrically connected, is formed in a second region adjacent to the first region in a planar view; and a first crystal defect layer is formed in the first semiconductor region in a planar view, the first crystal defect layer having a peak on the fourth semiconductor region side in a thickness direction and locally increased in crystal defect concentration on the second semiconductor region side so that the crystal defect concentration is lower on the second semiconductor region side; and a second crystal defect layer is formed in the second region in a planar view, the peak on the fifth semiconductor region side of the first crystal defect layer in a thickness direction and locally increased in crystal defect concentration on the sixth semiconductor region side, and neither the first crystal defect layer nor the second crystal defect layer extends to a boundary between the fourth semiconductor region and the sixth semiconductor region in a planar view. [Effects of the Invention]

[0015] Since the present invention is configured as described above, it is possible to obtain an RC-IGBT that has a relatively small leakage current and is capable of high-speed operation. [Brief explanation of the drawings]

[0016] [Figure 1] 1 is a cross-sectional view showing a structure of a semiconductor device according to a first embodiment of the present invention. [Figure 2] FIG. 2 is a cross-sectional view showing the structure of a first modified example of the semiconductor device according to the first embodiment of the present invention. [Figure 3] FIG. 10 is a cross-sectional view showing the structure of a second modified example of the semiconductor device according to the first embodiment of the present invention. [Figure 4] FIG. 10 is a cross-sectional view showing the structure of a third modified example of the semiconductor device according to the first embodiment of the present invention. [Figure 5] FIG. 10 is a cross-sectional view showing the structure of a fourth modified example of the semiconductor device according to the first embodiment of the present invention. [Figure 6] FIG. 4 is a cross-sectional view showing the structure of a semiconductor device according to a second embodiment of the present invention. [Figure 7] FIG. 10 is a cross-sectional view showing the structure of a semiconductor device according to a third embodiment of the present invention. [Figure 8] FIG. 11 is a cross-sectional view showing the structure of a first modified example of the semiconductor device according to the third embodiment of the present invention. [Figure 9] FIG. 11 is a cross-sectional view showing the structure of a second modified example of the semiconductor device according to the third embodiment of the present invention. [Figure 10] FIG. 10 is a cross-sectional view showing the structure of a third modified example of the semiconductor device according to the third embodiment of the present invention. [Figure 11] FIG. 10 is a cross-sectional view showing the structure of a fourth modified example of the semiconductor device according to the third embodiment of the present invention. [Figure 12] FIG. 1 is a cross-sectional view showing the structure of a conventional semiconductor device. DETAILED DESCRIPTION OF THE INVENTION

[0017] A semiconductor device according to an embodiment of the present invention will be described below. This semiconductor device is an RC-IGBT in which a trench IGBT and a freewheeling diode (diode) are formed on a common semiconductor substrate. Therefore, its basic structure is the same as that shown in FIG.

[0018] (First embodiment) FIG. 1 is a cross-sectional view of the semiconductor device 1 according to the first embodiment, and corresponds to FIG. 12. Therefore, in this semiconductor device 1, n - Layer (n-type first semiconductor region) 11, p - Layer (p-type second semiconductor region in region I, p-type fifth semiconductor region in region II) 12, n + Layer (third semiconductor region) 14, p + Layer ((collector layer: fourth semiconductor region)) 16, n + A semiconductor substrate 10 on which a layer (sixth semiconductor region) 17 is formed is used, and a trench T, an oxide film (gate insulating film) 13, and an interlayer insulating layer 15 are similarly formed, and a gate electrode 21, an emitter electrode 22, and a collector electrode 23 are similarly electrically connected. Therefore, an IGBT is formed in region I (IGBT region), and a diode is formed in region II.

[0019] where n - In the layer 11, in the region I, p + On the layer 16 side, in region II, p - layer A first crystal defect layer (crystal defect layer) D1 and a second crystal defect layer (crystal defect layer) D2 are locally formed on the side of the first crystal defect layer D1 and the second crystal defect layer D2. - The layer 11 is a layer into which many crystal defects (point defects that shorten the minority carrier lifetime) have been introduced, and is formed, for example, by ion implantation of light ions such as protons or He ions into the semiconductor substrate 10 from the rear surface side (the lower side in FIG. 1). In this case, the energy of ions when forming the second crystal defect layer D2 is set to be larger than the energy of ions when forming the first crystal defect layer D1. As with the techniques described in Patent Documents 1 to 3, in the first crystal defect layer D1 and the second crystal defect layer D2, the lifetime of minority carriers (holes) is increased by 100% compared to the n-type crystal defect layer around them. - It will be shorter than layer 11.

[0020] In this way, the first crystal defect layer D1 and the second crystal defect layer D2 are n -Since the first crystal defect layer D1 is formed in the layer 11, the crystal defect density actually has a distribution as shown on the left and right in FIG. - Layer 11 p + The peak of the crystal defect density in the second crystal defect layer D2 is set near the layer 16. - Layer 11 p - In this case, the second crystal defect layer D2 is set to be substantially p - It is not formed in layer 12 and is substantially n - The first crystal defect layer D1 is formed only in the layer 11. Such a setting is performed by adjusting the energy of the ion implantation. + It is not formed in layer 16 and is substantially n - It is provided only in the layer 11. Such setting is achieved by adjusting the energy of the ion implantation.

[0021] Generally, when an IGBT is turned from on to off, n - The layer 11 is depleted, and at this time, the collector layer (p + If a large number of minority carriers (holes) remain in the region near the collector layer (p + By forming the first crystal defect layer D1 in the region near the layer 16) and shortening the life of minority carriers in this region, the speed of the IGBT's on-to-off operation can be increased.

[0022] On the other hand, when the IGBT is in an on state, the first crystal defect layer D1 is - The layer 12 is provided in a region away from the p - n on layer 12 side - Since sufficient minority carriers (holes) can be accumulated in layer 11, VCEsat can be reduced by the effect of conductivity modulation.

[0023] Also, when the diode changes from forward to reverse, p in region II - n on layer 12 side -Since the second crystal defect layer D2 is formed near the pn junction of the layer 11, p - n on layer 12 side - Minority carriers (holes) near the pn junction of the layer 11 are captured in the second crystal defect layer D2 and can be quickly eliminated, improving the recovery characteristics of the diode. - Layer 11 to p - Since it is not formed on the layer 12 side, the leakage current does not increase.

[0024] On the other hand, when the diode is in a steady state, carriers (holes) accumulate near the back surface, resulting in a low forward voltage. - Layer 11 n + By providing no (or fewer) crystal defects on the layer 17 side, a low forward voltage can be maintained.

[0025] In order to reduce the forward voltage VF of the diode, it is desirable to set the conductivity modulation when the diode in region II is turned on higher than the conductivity modulation when the IGBT in region I is turned on. On the other hand, when the diode in region II is switched from on to off, many residual carriers remain in region II, which deteriorates the characteristics of the diode in region II when it is turned off. Therefore, it is desirable to set the concentration of crystal defects in the second crystal defect layer D2 (peak value in FIG. 1) higher than the concentration (peak value) of crystal defects in the first crystal defect layer D1. This can improve the characteristics of the diode in region II when it is turned off.

[0026] In the above example, the first crystal defect layer D1 is formed in the region I, and the second crystal defect layer D2 is formed in the region II, but these may be extended to the outside of the region. The above modified example having such a configuration will be described below.

[0027] Figure 2 shows the configuration of a semiconductor device 1A (first variant) in which the second crystal defect layer D2 is extended into region I, and Figure 3 shows the configuration of a semiconductor device 1B (second variant) in which the first crystal defect layer D1 is extended into region II.

[0028] When the IGBT is off in region I, the diode is in the forward direction in region II. In this case, n - Layer 11 has p - Many minority carriers (holes) are injected from layer 12, and these holes diffuse not only vertically but also horizontally in the figure, reaching region I. These holes become residual carriers and adversely affect the off-state characteristics of the IGBT. Therefore, it is preferable to eliminate these holes in region I. In the semiconductor device 1A shown in FIG. 2, the portion of the second crystal defect layer D2 in region I (the first-region-side second crystal defect layer D21) can capture and eliminate these holes. As a result, the intrusion of holes into region I and the adverse effect on the off-state characteristics of the IGBT are suppressed. On the other hand, in the semiconductor device 1A shown in FIG. 2, the second crystal defect layer D2 is provided only at the end of region I on the region II side. Therefore, the adverse effect on the conductivity modulation during the on-state of the IGBT and the adverse effect on VCEsat are small.

[0029] When the IGBT is on in region I, n - Holes in layer 11 diffuse from collector layer 16 not only vertically but also horizontally in the figure, reaching region II. These holes become residual carriers in region II and adversely affect the recovery characteristics of the diode. Therefore, it is preferable to eliminate the residual carriers in region II. In semiconductor device 1B shown in FIG. 3, the portion of first crystal defect layer D1 in region II (second-region-side first crystal defect layer D12) can eliminate these holes. On the other hand, since this first crystal defect layer D1 is provided only at the end of region II on the region I side, adverse effects such as an increase in leakage current in the diode due to this are small.

[0030] In this way, the second crystal defect layer D2 can be extended into the region I, or the first crystal defect layer D1 can be extended into the region II. This setting can also be easily achieved when these crystal defect layers are formed by light ion implantation.

[0031] In this case, in order to reduce the adverse effect of the first-region-side second crystal defect layer D21 on the operation of the IGBT, it is preferable that the crystal defect concentration (peak value) of the first-region-side second crystal defect layer D21 is lower than the crystal defect concentration (peak value) of the second crystal defect layer D2 in region II. Also, it is preferable that the crystal defect concentration of the second-region-side first crystal defect layer D12 is lower than the crystal defect concentration of the first crystal defect layer D1 in region I.

[0032] However, structures equivalent to the second crystal defect layer D2 and the first crystal defect layer D1 can also be formed without extending them outside the region. For example, in FIG. 2, the second crystal defect layer D2 can be formed only in region II, and a crystal defect layer with a locally increased crystal defect concentration can be formed on the region II side of region I in a separated state, at the same position in the thickness direction as the second crystal defect layer D2. This corresponds to forming the first-region-side second crystal defect layer D21 in FIG. 2 separated from the second crystal defect layer D2 in region II. It is clear that the same effect can be achieved in this case as well. Similarly, the second-region-side first crystal defect layer D12 in FIG. 3 can also be formed separated from the first crystal defect layer D1 in region I. When forming the crystal defect layer separated in this way, it is particularly easy to make the crystal defect concentration different for each region as described above.

[0033] Conversely, it is also possible to configure the semiconductor device 1C (third modified example) in which the second crystal defect layer D2 does not extend to the boundary between region I and region II, or the second crystal defect layer D2 does not extend to this boundary. Figure 4 shows the configuration of a semiconductor device 1C (third modified example) in which the second crystal defect layer D2 does not extend to this boundary, and Figure 5 shows the configuration of a semiconductor device 1D (fourth modified example) in which the first crystal defect layer D1 does not extend to this boundary.

[0034] In the semiconductor device 1C (FIG. 4), a portion in region II where the second crystal defect layer D2 is not formed on the boundary side with region I is provided, thereby enabling a lower diode forward voltage VF than in the semiconductor device 1 (FIG. 1). In the semiconductor device 1D (FIG. 5), a portion in region I where the first crystal defect layer D1 is not formed is provided, thereby enabling a lower IGBT VCEsat than in the semiconductor device 1 (FIG. 1). Note that the configuration of FIG. 4 can be combined with the configuration of FIG. 3, i.e., the second crystal defect layer D2 is not extended to the boundary side between region I and region II, while the first crystal defect layer D1 is extended into region II. Alternatively, the configuration of FIG. 5 can be combined with the configuration of FIG. 2, i.e., the first crystal defect layer D1 is not extended to the boundary side, while the second crystal defect layer D2 is extended into region I.

[0035] 1 to 5 or the above combination, the first crystal defect layer D1 and the second crystal defect layer D2 can be provided in accordance with the usage conditions (usage voltage, switching speed, etc.) of the RC-IGBT. In any case, the manufacturing process and conditions can be common except for the mask used in ion implantation to form the first crystal defect layer D1 and the second crystal defect layer D2.

[0036] (Second embodiment) In the semiconductor device according to the second embodiment, as described in, for example, Japanese Patent Application Laid-Open No. 2018-125326, a drift layer (n - Layer 11) and p + Between the n-type layer 16 (collector region) and the n-type layer 17 (field stop layer: FS layer) with a locally high impurity concentration is formed. This prevents the depletion layer from being blocked by the collector region (p + The breakdown voltage of the IGBT increases because the FS layer is difficult to reach the side of the layer 16. Even when the FS layer is used in this way, the crystal defect layer as described above can be formed in the same way.

[0037] 6 is a diagram showing the configuration of such a semiconductor device 2 in correspondence with FIG. 1. In the semiconductor substrate 30 used here, n- Layer 11 and p + Layer (collector layer) 16, n + Between layer 17, n - n-type with a higher impurity concentration than layer 11 + A layer (FS layer: seventh semiconductor region) 31 is provided as the FS layer.

[0038] In this case, n - Layers 11 to n + The n-type region is formed thickly toward the layer 31, but for the reasons mentioned above, it is preferable to provide the crystal defect layer D1 only in the portion that functions as the drift layer in the IGBT. - Layer 11 n + Layer 31 side (p + It is clear that the same effect can be achieved by providing the FS layer. That is, even when the FS layer is provided, the same crystal defect layer as described above can be used. + The crystal defect concentration of the crystal defect layer D1 may be at a peak in the layer 31. + It is desirable that it is not present in layer 16. This allows for a relatively small leakage current.

[0039] (Third embodiment) In the semiconductor device according to the third embodiment, as described in, for example, Japanese Patent Application Laid-Open No. 2002-353456, - layer 11) and the base region (p - Between layers 12), locally - An n-type layer (carrier accumulation layer) having a higher impurity concentration than the layer 11 is formed. This allows the collector region (p + Layer 16) to n - The holes injected into the layer 11 are - Since it becomes easy to stay in layer 11, n - This allows the conductivity modulation in layer 11 to occur more efficiently, reducing the on-voltage of the IGBT.

[0040] 7 is a diagram showing the configuration of such a semiconductor device 3 in correspondence with FIGS. 1 and 6. In the semiconductor substrate 40 used here, n - Layer 11 and p - Between layers 12 + A layer (carrier accumulation layer: eighth semiconductor region) 41 is formed.

[0041] In this case, it is also preferable that the crystal defect layer D1 is provided only in the portion that functions as the drift layer in the IGBT. - p in layer 11 + It is provided on the side of the layer 16. It is clear that the same effect can be achieved by this. That is, even when a carrier accumulation layer is provided, the same crystal defect layer as described above can be used in the same way.

[0042] In this case, however, it is possible to set various positional relationships between the carrier accumulation layer and the crystal defect layer, etc. Modifications that take this into consideration will be described below.

[0043] Figure 8 shows the + The structure of the semiconductor device 3A (first modification) is shown, which uses a semiconductor substrate 45 in which the layer 41 is extended to the region II side. + By widening the layer 41, the effect of lowering the on-state voltage of the IGBT as described above can be particularly enhanced.

[0044] Figure 9 shows the reverse of n + 1 shows the configuration of a semiconductor device 3B (second modified example) that uses a semiconductor substrate 46 in which the layer 41 does not extend to the boundary between regions I and II, and the second crystal defect layer D2 extends into region I. In this case, by extending the second crystal defect layer D2 to region I, the recovery characteristics of the diode can be particularly improved.

[0045] Figure 10 shows the - p in layer 11 - Layer 12 side structure (n +7, and the semiconductor substrate 47 in which the first crystal defect layer D1 does not extend to the boundary between the region I and the region II is used. In this structure, when the IGBT is turned on, the collector region (p + Layer 16) to n - It becomes easier to inject many holes into the layer 11, and these holes are - Since the layer 12 side is difficult to reach, the on-voltage of the IGBT in particular can be reduced.

[0046] Figure 11 shows the + 9, the semiconductor device 3D (fourth modified example) uses a semiconductor substrate 48 in which the layer 41 and the second crystal defect layer D2 are the same as those of the semiconductor device 3B in Fig. 9, and the first crystal defect layer D1 is extended into the region II. In this structure, like the semiconductor device 3B, the recovery characteristics of the diode can be particularly improved, and by extending the first crystal defect layer D1, holes flowing from region I to region II can be easily eliminated when the IGBT is on (when the diode is reverse biased), like the semiconductor device 1B, thereby particularly improving the recovery characteristics of the diode.

[0047] The positions of the first and second crystal defect layers in the second and third embodiments can be easily set by using a mask during ion implantation. The same applies to the carrier accumulation layer. The FS layer and the carrier accumulation layer may be used simultaneously.

[0048] Although a trench-gate IGBT was used in the semiconductor device (RC-IGBT) described above, it is clear that a similar configuration can be applied to a planar IGBT. Furthermore, in addition to the FS layer and carrier accumulation layer described above, other layers can be added as appropriate. Furthermore, in the above example, a similar configuration can be applied even if the p-type and n-type in the semiconductor substrate are all reversed. [Explanation of symbols]

[0049] 1, 1A, 1B, 1C, 1D, 2, 3, 3A, 3B, 3C, 3D 900 Semiconductor equipment 10, 30, 40, 45-48, 90 Semiconductor substrate 11, 91 n - layer (first semiconductor region) 12, 92 p. - Layer (second semiconductor region, fifth semiconductor region) 13, 93 Oxide film (gate insulating film) 14, 94 n + layer (third semiconductor region) 15, 95 Interlayer insulation layer 16, 96 p. + layer (fourth semiconductor region) 17, 97 n + layer (sixth semiconductor region) 21, 81 Gate electrode 21 22, 82 Emitter electrode 23, 83 Collector electrode 31n + Layer (seventh semiconductor region) 41n + Layer (eighth semiconductor region) D1 First crystal defect layer (crystal defect layer) D12: First crystal defect layer on the second region side D2 Second crystal defect layer (crystal defect layer) D21: Second crystal defect layer on the first region side T-groove (trench)

Claims

1. a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type opposite to the first conductivity type formed on the first semiconductor region; a third semiconductor region of the first conductivity type formed on a surface side of the second semiconductor region; a fourth semiconductor region of the second conductivity type formed under the first semiconductor region; an emitter electrode electrically connected to the second semiconductor region and the third semiconductor region; a collector electrode electrically connected to the fourth semiconductor region; Equipped with an insulated gate field effect transistor is formed in the first region in a plan view, in which a current between the emitter electrode and the collector electrode is controlled by a gate electrode formed on a surface side of the second semiconductor region; the first semiconductor region; a fifth semiconductor region of the second conductivity type formed on the first semiconductor region; a sixth semiconductor region of the first conductivity type formed under the first semiconductor region; a trench penetrating the fifth semiconductor region in a thickness direction; Equipped with a diode formed by electrically connecting the emitter electrode to the fifth semiconductor region and electrically connecting the collector electrode to the sixth semiconductor region, is formed in a second region adjacent to the first region in a plan view; The first semiconductor region a first crystal defect layer formed in the first region in a plan view, in which a peak of the crystal defect concentration is set on the fourth semiconductor region side in a thickness direction and the crystal defect concentration is locally increased so that the crystal defect concentration is decreased on the second semiconductor region side; a second crystal defect layer formed in the second region in a plan view, the crystal defect concentration of which peak is located closer to the fifth semiconductor region than the first crystal defect layer and shallower than the bottom of the trench in the thickness direction, and the crystal defect concentration is locally increased so that the crystal defect concentration is reduced on the sixth semiconductor region side; is formed, a first region-side second crystal defect layer, the peak of the crystal defect concentration being located closer to the second semiconductor region than the first crystal defect layer and shallower than the bottom of the trench, and the peak value of the crystal defect concentration being lower than the peak value of the crystal defect concentration in the second crystal defect layer in the second region, in a plan view on the second region side of the first region; a first crystal defect layer formed under the first region-side second crystal defect layer;

2. a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type opposite to the first conductivity type formed on the first semiconductor region; a third semiconductor region of the first conductivity type formed on a surface side of the second semiconductor region; a fourth semiconductor region of the second conductivity type formed under the first semiconductor region; an emitter electrode electrically connected to the second semiconductor region and the third semiconductor region; a collector electrode electrically connected to the fourth semiconductor region; Equipped with an insulated gate field effect transistor is formed in the first region in a plan view, in which a current between the emitter electrode and the collector electrode is controlled by a gate electrode formed on a surface side of the second semiconductor region; the first semiconductor region; a fifth semiconductor region of the second conductivity type formed on the first semiconductor region; a sixth semiconductor region of the first conductivity type formed below the first semiconductor region and adjacent to the fourth semiconductor region in a plan view; Equipped with a diode formed by electrically connecting the emitter electrode to the fifth semiconductor region and electrically connecting the collector electrode to the sixth semiconductor region, is formed in a second region adjacent to the first region in a plan view; The first semiconductor region a first crystal defect layer formed in the first region in a plan view, in which a peak of the crystal defect concentration is set on the fourth semiconductor region side in a thickness direction and the crystal defect concentration is locally increased so that the crystal defect concentration is decreased on the second semiconductor region side; a second crystal defect layer formed in the second region in a plan view, the crystal defect concentration being locally increased so that a peak of the crystal defect concentration is set closer to the fifth semiconductor region than the first crystal defect layer in a thickness direction and the crystal defect concentration is lowered closer to the sixth semiconductor region; is formed, The semiconductor device according to claim 1, wherein the second crystal defect layer does not extend to a boundary between the fourth semiconductor region and the sixth semiconductor region in a plan view.

3. A first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type opposite to the first conductivity type formed on the first semiconductor region; a third semiconductor region of the first conductivity type formed on a surface side of the second semiconductor region; a fourth semiconductor region of the second conductivity type formed under the first semiconductor region; an emitter electrode electrically connected to the second semiconductor region and the third semiconductor region; a collector electrode electrically connected to the fourth semiconductor region; Equipped with an insulated gate field effect transistor is formed in the first region in a plan view, in which a current between the emitter electrode and the collector electrode is controlled by a gate electrode formed on a surface side of the second semiconductor region; the first semiconductor region; a fifth semiconductor region of the second conductivity type formed on the first semiconductor region; a sixth semiconductor region of the first conductivity type formed below the first semiconductor region and adjacent to the fourth semiconductor region in a plan view; Equipped with a diode formed by electrically connecting the emitter electrode to the fifth semiconductor region and electrically connecting the collector electrode to the sixth semiconductor region, is formed in a second region adjacent to the first region in a plan view; The first semiconductor region a first crystal defect layer formed in the first region in a plan view, in which a peak of the crystal defect concentration is set on the fourth semiconductor region side in a thickness direction and the crystal defect concentration is locally increased so that the crystal defect concentration is decreased on the second semiconductor region side; a second crystal defect layer formed in the second region in a plan view, the crystal defect concentration being locally increased so that a peak of the crystal defect concentration is set closer to the fifth semiconductor region than the first crystal defect layer in a thickness direction and the crystal defect concentration is lowered closer to the sixth semiconductor region; is formed, 10. A semiconductor device according to claim 9, wherein the first crystal defect layer and the second crystal defect layer do not extend to a boundary between the fourth semiconductor region and the sixth semiconductor region in a plan view.

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