DML Driver

Abstract

This DML driver (2) is configured from a PMOS transistor (M1p), an NMOS transistor (M1n), an inductor (L1), a resistor (Rin), and an optical waveform compensation function unit (20) connected between a source and a ground of the NMOS transistor (M1n). The optical waveform compensation function unit (20) is configured from an NMOS transistor (Mcon), an inductor (Lx), capacitors (Cy, Cx), and a resistor (Rx).

Description

[Technical Field]

[0001] The present invention relates to a technology for driving a directly modulated laser (DML), and more particularly to a DML driver having a frequency peaking function and an optical waveform compensation function. [Background technology]

[0002] In recent years, the remarkable development of social networking services (SNS) has led to an increase in global communication traffic every year. Further increases in traffic are expected in the future due to the development of the Internet of Things (IoT) and cloud computing technologies, and in order to support this massive traffic volume, there is a demand for increased communication capacity both inside and outside data centers.

[0003] With the trend toward larger capacity, the Ethernet (registered trademark) standard, a key element of network specifications, has now completed standardization for 100GbE, and discussions are underway to standardize 400GbE, which aims for even larger capacity. Aiming for application to 400GbE, drivers using DML are attracting attention from the perspective of low power consumption (see Non-Patent Document 1).

[0004] 11 is a circuit diagram showing the configuration of a conventional DML driver. The DML driver includes a PMOS transistor M1 having a gate connected to a bias voltage V2, a source connected to a power supply voltage V1, and a drain connected to the anode of a laser diode (LD) 1. 1p and modulating signal V in is input, and the source of the NMOS transistor M 1n The gate is connected to the bias voltage V3 and the drain is connected to the PMOS transistor M 1p and the anode of LD1, and the source of the NMOS transistor M 1n NMOS transistor M connected to the drain of 2nOne end is connected to a bias voltage V4, and the other end is connected to an NMOS transistor M 1n Resistor R connected to the gate of in It consists of:

[0005] NMOS transistor M 1n and M 2n are cascode-connected, and by this cascode connection, the NMOS transistor M 1n The frequency characteristics are improved compared to when using only one NMOS transistor. Also, even if the operating voltage of LD1 exceeds the withstand voltage of the NMOS transistor alone, the voltage is divided by the cascode connection, so the NMOS transistor M 1n ,M 2n Resistance R in is the impedance matching resistor.

[0006] As shown in Figure 11, in the conventional driver circuit configuration, the driver section did not have the function to compensate for the optical output waveform of the LD, which caused the problem that the optical waveform output from the transmission front end consisting of the DML driver and LD depended on the optical output waveform of the LD itself. [Prior art documents] [Non-patent literature]

[0007] [Non-Patent Document 1] T. Kishi et al., “A 137-mW,4 ch x 25-Gbps low-power compact transmitter flip-chip-bonded 1.3-μm LD-array-on-Si”, In Proceedings of the Optical Fiber Communication Conference and Exhibition, 2018, Paper M2D.2. Summary of the Invention [Problem to be solved by the invention]

[0008] The present invention has been made to solve the above problems, and has an object to provide a DML driver capable of shaping an optical output waveform. [Means for solving the problem]

[0009] The DML driver of the present invention comprises a first transistor having a gate or base connected to a first bias voltage, a source or emitter connected to a first power supply voltage, and a drain or collector connected to an anode of a laser diode; a second transistor having a drain or collector connected to the anode of the laser diode; a first inductor having one end to which a modulation signal is input and the other end connected to the gate or base of the second transistor; a first resistor having one end connected to a second bias voltage and the other end connected to one end of the first inductor; and an optical waveform compensation function unit connected between the source or emitter of the second transistor and a second power supply voltage, a third transistor having a gate or base to which a control voltage is input, a drain or collector connected to the source or emitter of the second transistor, and a source or emitter connected to the second power supply voltage; a second inductor having one end connected to the drain or collector of the third transistor and the other end connected to the second power supply voltage; a first capacitor having one end connected to the drain or collector of the third transistor; a second capacitor having one end connected to the drain or collector of the third transistor and the other end connected to the second power supply voltage; and a second resistor having one end connected to the other end of the first capacitor and the other end connected to the second power supply voltage. The first transistor is a PMOS transistor or a PNP transistor, each of the second and third transistors is an NMOS transistor or an NPN transistor, the first power supply voltage and each of the first and second bias voltages are positive voltages, and the second power supply voltage is ground. It is characterized by the following.

[0010] In addition, one configuration example of the DML driver of the present invention further includes a fourth transistor whose gate or base is connected to a third bias voltage and cascode-connected between the anode of the laser diode and the drain or collector of the second transistor. the fourth transistor is an NMOS transistor or an NPN transistor, and the third bias voltage is a positive voltage; It is characterized by the following. In addition, one configuration example of the DML driver of the present invention further includes a fifth transistor whose gate or base is connected to a fourth bias voltage and which is cascode-connected between the drain or collector of the first transistor and the anode of the laser diode. the fifth transistor is a PMOS transistor or a PNP transistor, and the fourth bias voltage is a positive voltage; It is characterized by the following.

[0011] Furthermore, the DML driver of the present invention includes a first transistor having a gate or base connected to a first bias voltage, a source or emitter connected to a first power supply voltage, and a drain or collector connected to an anode of a laser diode; a second transistor having a gate or base connected to a second bias voltage; a third transistor cascode-connected between the anode of the laser diode and the drain or collector of the second transistor; a first inductor having one end to which a modulation signal is input and the other end connected to the gate or base of the third transistor; a first resistor having one end connected to a third bias voltage and the other end connected to one end of the first inductor; and an optical waveform compensation function unit connected to the first end of the fourth transistor, the optical waveform compensation function unit comprising: a fourth transistor having a gate or a base to which a control voltage is input, a drain or a collector connected to the source or the emitter of the second transistor, and a source or an emitter connected to the second power supply voltage; a second inductor having one end connected to the drain or the collector of the fourth transistor and the other end connected to the second power supply voltage; a first capacitor having one end connected to the drain or the collector of the fourth transistor; a second capacitor having one end connected to the drain or the collector of the fourth transistor and the other end connected to the second power supply voltage; and a second resistor having one end connected to the other end of the first capacitor and the other end connected to the second power supply voltage. The first transistor is a PMOS transistor or a PNP transistor, each of the second, third, and fourth transistors is an NMOS transistor or an NPN transistor, the first power supply voltage and each of the first, second, and third bias voltages are positive voltages, and the second power supply voltage is ground. It is characterized by the following.

[0012] In addition, one configuration example of the DML driver of the present invention further includes a fifth transistor whose gate or base is connected to a fourth bias voltage and which is cascode-connected between the drain or collector of the first transistor and the anode of the laser diode. the fifth transistor is a PMOS transistor or a PNP transistor, and the fourth bias voltage is a positive voltage; It is characterized by the following. Furthermore, one configuration example of the DML driver of the present invention is characterized in that it further comprises a third capacitor having one end connected to the first power supply voltage, and a third resistor having one end connected to the other end of the third capacitor and the other end connected to the drain or collector of the first transistor. Furthermore, one configuration example of the DML driver of the present invention is characterized in that it further comprises a third resistor inserted between the source or emitter of the second transistor and the optical waveform compensation function unit. Moreover, one configuration example of the DML driver of the present invention is characterized in that it further comprises a third capacitor connected in parallel with the third resistor. [Effects of the Invention]

[0013] According to the present invention, a frequency peaking function can be realized by connecting a first inductor in series to the gate of a transistor to which a modulation signal is input, making it possible to compensate for the LD bandwidth. Furthermore, in this invention, by providing an optical waveform compensation function unit, it is possible to improve the EO (Electrical-to-Optical) frequency characteristics and group delay characteristics of the transmission front-end consisting of a DML driver and an LD, making it possible to shape the optical output waveform. [Brief explanation of the drawings]

[0014] [Figure 1] FIG. 1 is a circuit diagram showing the configuration of a DML driver according to a first embodiment of the present invention. [Figure 2] FIG. 2 is a diagram showing the results of simulating the EO response characteristics of the DML driver and LD for the conventional configuration and the first embodiment of the present invention. [Figure 3] FIG. 3 is a diagram showing the results of simulating the group delay characteristics of the DML driver and LD for the conventional configuration and the first embodiment of the present invention. [Figure 4A-4B] 4A and 4B are diagrams showing optical output waveforms of LDs in a conventional configuration and in the first embodiment of the present invention. [Figure 5] FIG. 5 is a circuit diagram showing the configuration of a DML driver according to a second embodiment of the present invention. [Figure 6] FIG. 6 is a circuit diagram showing the configuration of a DML driver according to a third embodiment of the present invention. [Figure 7] FIG. 7 is a circuit diagram showing the configuration of a DML driver according to a fourth embodiment of the present invention. [Figure 8] FIG. 8 is a circuit diagram showing another configuration of the DML driver according to the fourth embodiment of the present invention. [Figure 9] FIG. 9 is a circuit diagram showing the configuration of a DML driver according to a fifth embodiment of the present invention. [Figure 10] FIG. 10 is a circuit diagram showing the configuration of a DML driver according to a sixth embodiment of the present invention. [Figure 11] FIG. 11 is a circuit diagram showing the configuration of a conventional DML driver. DETAILED DESCRIPTION OF THE INVENTION

[0015] [First Example] Hereinafter, embodiments of the present invention will be described with reference to the drawings. Fig. 1 is a circuit diagram showing the configuration of a DML driver according to a first embodiment of the present invention. A DML driver 2 of this embodiment includes a PMOS transistor M1 having a gate connected to a bias voltage V2 (first bias voltage), a source connected to a power supply voltage V1 (first power supply voltage), and a drain connected to the anode of LD1. 1p and NMOS transistor M 1n The gate is connected to a bias voltage V3 (third bias voltage) and the drain is connected to a PMOS transistor M 1p and the anode of LD1, and the source of the NMOS transistor M1n NMOS transistor M connected to the drain of 2n and modulated signal V in is input, and the other end is connected to an NMOS transistor M 1n and a resistor R whose one end is connected to a bias voltage V4 (second bias voltage) and whose other end is connected to one end of the inductor L1. in and NMOS transistor M 1n and an optical waveform compensation function unit 20 connected between the source of the optical amplifier and ground (second power supply voltage).

[0016] The magnitude relationship of each voltage is V1>V2>V3>V4>GND (ground). In this embodiment, the modulation signal V in and NMOS transistor M 1n An inductor L1 is inserted between the gates of the NMOS transistor M 1n An optical waveform compensation function section 20 is inserted between the source and ground.

[0017] The optical waveform compensation function unit 20 applies a control voltage V con is input, and the drain is connected to the NMOS transistor M 1n and an NMOS transistor M con and one end is an NMOS transistor M con The inductor L is connected to the drain of x and one end is an NMOS transistor M con The capacitor C connected to the drain of y and one end is an NMOS transistor M con The other end of the capacitor C is connected to the drain of x and one end is capacitor C y The other end of the gain adjustment resistor R is connected to the ground. x It consists of:

[0018] Inductor L x attenuates the gain of the DML driver 2 at high frequencies.y ,C x increases the gain of DML driver 2 at high frequencies. con Depending on the NMOS transistor M con Since the impedance of the inductor L1 changes, the impedance of the optical waveform compensation function unit 20 changes, making it possible to adjust the amount of frequency peaking by the inductor L1. As a result, in this embodiment, it is possible to improve the group delay characteristics while improving the frequency characteristics of the transmission front end composed of the DML driver 2 and the LD 1.

[0019] The EO (Electrical-to-Optical) response characteristics of the DML driver and LD1 for the conventional configuration and this embodiment were determined by simulation and the results are shown in Figure 2. In Figure 2, 100 indicates the EO response characteristics of the conventional configuration shown in Figure 11, and 101 indicates the EO response characteristics of this embodiment. As can be seen from Figure 2, in the configuration of this embodiment, the frequency peaking effect of inductor L1 improves the band of the EO response characteristics compared to the conventional circuit configuration.

[0020] In this embodiment, the control voltage V con The amount of frequency peaking by the inductor L1 can be adjusted by increasing or decreasing the control voltage V. con Increasing V increases the amount of frequency peaking, con Lowering reduces the amount of frequency peaking.

[0021] Next, the group delay characteristics of the DML driver and LD 1 for the conventional configuration and this embodiment are obtained by simulation and shown in Figure 3. In Figure 3, 102 indicates the group delay characteristics of the conventional configuration, and 103 indicates the group delay characteristics of this embodiment. In the conventional circuit configuration, the group delay value peaks around 16 GHz. In contrast, in the circuit configuration of this embodiment, the optical waveform compensation function unit 20 reduces the group delay value around 16 GHz to less than half of the conventional peak value. Furthermore, when the group delay values ​​at each frequency are compared between the conventional circuit configuration and the circuit configuration of this embodiment, it is clear that the group delay value can be reduced in this embodiment, which uses the optical waveform compensation function unit 20.

[0022] Next, Fig. 4A shows the results of a simulation of the optical output waveform of the LD 1 for a conventional configuration, and Fig. 4B shows the results of a simulation of the optical output waveform of the LD 1 for the configuration of this embodiment. The examples in Fig. 4A and Fig. 4B show the case where a 32 Gbps non-return-to-zero (NRZ) signal light is output from the LD 1. The amplitude scale on the vertical axis is 200 μW / div, and the time scale on the horizontal axis is 20 ps / div. Comparing Fig. 4A and Fig. 4B, it can be seen that the eye opening is improved in both the horizontal axis (time) and vertical axis (amplitude) directions in the circuit configuration of this embodiment due to the frequency peaking function of inductor L1 and the optical waveform compensation function unit 20.

[0023] [Second Example] Next, a second embodiment of the present invention will be described. Fig. 5 is a circuit diagram showing the configuration of a DML driver according to the second embodiment of the present invention. A DML driver 2a of this embodiment differs from the circuit configuration of the first embodiment in that a PMOS transistor M 1p Between the source and drain of f and resistance R f The above elements are connected in series.

[0024] Capacitor C f and resistance R f functions as a high-frequency filter. If excessive overshoot or undershoot is observed in the optical output waveform of LD1,f and resistance R f By providing this, it is possible to suppress overshoot and undershoot of the optical output waveform and shape the optical output waveform. As a result, in this embodiment, it is expected that the eye opening will be improved in both the horizontal axis (time) direction and the vertical axis (amplitude) direction.

[0025] [Third Example] Next, a third embodiment of the present invention will be described. Fig. 6 is a circuit diagram showing the configuration of a DML driver according to the third embodiment of the present invention. A DML driver 2b of this embodiment includes a PMOS transistor M 1p and NMOS transistor M 1n The gates of the PMOS transistors M are connected to the bias voltages V5-1 to V5-x (fourth bias voltages). 1p and one or more PMOS transistors M1 and M2 connected in cascode between the drain of 2p -1~M 2p -x, and the gate is connected to bias voltages V3-1 to V3-y (third bias voltages), and the anode of LD1 and the NMOS transistor M 1n One or more NMOS transistors M cascode-connected between the drain of 2n -1~M 2n -y, inductor L1, and resistor R in and an optical waveform compensation function unit 20.

[0026] The magnitude relationship of each voltage is V1>V2>V5-1>···>V5-x>V3-y>···>V3-1>V4>GND (ground). To cascode connect PMOS transistors, simply connect the source to the drain of the upper PMOS transistor, and the drain to the source of the lower PMOS transistor or the anode of LD1. To cascode connect NMOS transistors, simply connect the source to the drain of the lower NMOS transistor, and the drain to the source of the upper NMOS transistor or the anode of LD1.

[0027] In this way, a multi-stage circuit configuration can be used to prevent breakdown in both PMOS and NMOS transistors. This is effective because the breakdown voltage per transistor decreases at the most advanced nodes. Here, we will look at the PMOS transistor M 1p PMOS transistor M 2p -1~M 2p -x for x stage, NMOS transistor M 1n NMOS transistor M 2n -1~M 2n -y is set to y stages. Both x and y must be 1 or greater.

[0028] [Fourth Example] Next, a fourth embodiment of the present invention will be described. Fig. 7 is a circuit diagram showing the configuration of a DML driver according to the fourth embodiment of the present invention. A DML driver 2c of this embodiment includes a PMOS transistor M1 whose gate is connected to a bias voltage V2, whose source is connected to a power supply voltage V1, and whose drain is connected to the anode of LD1. 1p and an NMOS transistor M whose gate is connected to a bias voltage V4. 1n and the drain is a PMOS transistor M 1p and the anode of LD1, and the source of the NMOS transistor M 1n NMOS transistor M connected to the drain of 2n and modulated signal V in is input, and the other end is connected to an NMOS transistor M 2n and a resistor R whose one end is connected to a bias voltage V3 and whose other end is connected to one end of the inductor L1. in and NMOS transistor M 1n and an optical waveform compensation function section 20 connected between the source of the optical amplifier and ground.

[0029] In the first embodiment, the NMOS transistor M 1n The modulation signal V in In this embodiment, the NMOS transistor M 2nThe gate of the modulation signal V in As a result, in this embodiment, the NMOS transistor M 1n By adjusting the bias voltage V4 applied to the gate of the PMOS transistor M 1p from NMOS transistor M 2n ,M 1n The current flowing to the side can be adjusted.

[0030] As in the third embodiment, the PMOS transistor M 1p PMOS transistor M 2p -1~M 2p -x may be provided in x stages (x is an integer equal to or greater than 1). The configuration in this case is shown in FIG.

[0031] In this embodiment, the NMOS transistor M 1n NMOS transistor M 2n However, as explained in the third embodiment, multiple stages of NMOS transistors M 2n -1~M 2n -y may be connected (y≧2). In this case, multiple stages of NMOS transistors M 2n -1~M 2n Any one of the NMOS transistors M 2n -k (k is 1 to y) gate and modulation signal V in An inductor L1 is connected between 2n -k, a resistor R is placed between the bias voltage V3-k and the inductor L1. in Also, the capacitor C f and resistance R f may be applied to this embodiment.

[0032] [Fifth Example] Next, a fifth embodiment of the present invention will be described. Fig. 9 is a circuit diagram showing the configuration of a DML driver according to the fifth embodiment of the present invention. A DML driver 2d of this embodiment differs from the DML driver 2a of the second embodiment in that it has an NMOS transistor M 1nand the source of the NMOS transistor M con Resistor R between the drain and s As a result, in this embodiment, the linearity of the DML driver 2d can be improved, and the modulation signal V in This allows the DML driver 2d to operate more linearly. In FIG. 9, the resistor R s is applied, but the first, third and fourth examples use resistor R s may be applied.

[0033] [Sixth Example] Next, a sixth embodiment of the present invention will be described. Fig. 10 is a circuit diagram showing the configuration of a DML driver according to the sixth embodiment of the present invention. A DML driver 2e of this embodiment differs from the DML driver 2d of the fifth embodiment in that it has a resistor R s In parallel with capacitor C s As a result, in this embodiment, the high frequency band of the transmission front end formed by the DML driver 2e and the LD1 can be improved compared to the fifth embodiment. In FIG. 10, the resistor R s and capacitor C s is applied, but the first, third and fourth examples use resistor R s and capacitor C s may be applied.

[0034] In addition, if there is no problem with the breakdown voltage of the NMOS transistor, the NMOS transistor M 2n ,M 2n -1~M 2n -y is omitted, and the NMOS transistor M 1n The drain of LD1 may be connected to the anode of LD1, in which case the bias voltages V3, V3-1 to V3-y are not required.

[0035] In the third embodiment, if there is no problem with the breakdown voltage of the PMOS transistor, the PMOS transistor M 2p -1~M 2p-x is omitted, and the PMOS transistor M 1p The drain of LD1 may be connected to the anode of LD1, in which case the bias voltages V5-1 to V5-x are not required.

[0036] In the first to sixth embodiments, the transistor M 1p ,M 2p -1~M 2p -x,M 1n ,M 2n ,M 2n -1~M 2n -y,M con Although an example using a MOS transistor as a 1p ,M 2p -1~M 2p -x is a PNP bipolar transistor, and transistor M 1n ,M 2n ,M 2n -1~M 2n -y,M con An NPN bipolar transistor may be used as the transistor. When a bipolar transistor is used, the gate may be replaced with the base, the drain with the collector, and the source with the emitter in the explanations of the first to sixth embodiments. [Industrial Applicability]

[0037] The present invention can be applied to a technique for directly modulating the optical output of an LD. [Explanation of symbols]

[0038] 1...LD, 2,2a~2e...DML driver, 20...light waveform compensation function section, M 1p ,M 2p -1~M 2p -x...PMOS transistor, M 1n ,M 2n ,M 2n -1~M 2n -y,M con …NMOS transistor, L1,L x …inductor, R in ,Rx ,R f ,R s …Resistance, C y ,C x ,C f ,C s ...Capacitor.

Claims

1. a first transistor having a gate or base connected to a first bias voltage, a source or emitter connected to a first power supply voltage, and a drain or collector connected to an anode of the laser diode; a second transistor having a drain or collector connected to the anode of the laser diode; a first inductor having one end to which a modulation signal is input and the other end connected to the gate or base of the second transistor; a first resistor having one end connected to a second bias voltage and the other end connected to one end of the first inductor; an optical waveform compensation function unit connected between the source or emitter of the second transistor and a second power supply voltage; The optical waveform compensation function unit includes: a third transistor having a gate or a base to which a control voltage is input, a drain or a collector connected to the source or the emitter of the second transistor, and a source or an emitter connected to the second power supply voltage; a second inductor having one end connected to the drain or collector of the third transistor and the other end connected to the second power supply voltage; a first capacitor having one end connected to the drain or collector of the third transistor; a second capacitor having one end connected to the drain or collector of the third transistor and the other end connected to the second power supply voltage; a second resistor having one end connected to the other end of the first capacitor and the other end connected to the second power supply voltage; the first transistor is a PMOS transistor or a PNP transistor; each of the second and third transistors is an NMOS transistor or an NPN transistor; the first power supply voltage and the first and second bias voltages are each a positive voltage; The DML driver, wherein the second power supply voltage is ground.

2. 2. The DML driver of claim 1, a fourth transistor, the gate or base of which is connected to a third bias voltage, cascode-connected between the anode of the laser diode and the drain or collector of the second transistor; the fourth transistor is an NMOS transistor or an NPN transistor, The DML driver is characterized in that the third bias voltage is a positive voltage.

3. 3. The DML driver according to claim 2, a fifth transistor, the gate or base of which is connected to a fourth bias voltage, cascode-connected between the drain or collector of the first transistor and the anode of the laser diode; the fifth transistor is a PMOS transistor or a PNP transistor, The DML driver, wherein the fourth bias voltage is a positive voltage.

4. a first transistor having a gate or base connected to a first bias voltage, a source or emitter connected to a first power supply voltage, and a drain or collector connected to an anode of the laser diode; a second transistor having a gate or a base connected to a second bias voltage; a third transistor cascoded between the anode of the laser diode and the drain or collector of the second transistor; a first inductor having one end to which a modulation signal is input and the other end connected to the gate or base of the third transistor; a first resistor having one end connected to a third bias voltage and the other end connected to one end of the first inductor; an optical waveform compensation function unit connected between the source or emitter of the second transistor and a second power supply voltage; The optical waveform compensation function unit includes: a fourth transistor having a gate or a base to which a control voltage is input, a drain or a collector connected to the source or the emitter of the second transistor, and a source or an emitter connected to the second power supply voltage; a second inductor having one end connected to the drain or collector of the fourth transistor and the other end connected to the second power supply voltage; a first capacitor having one end connected to the drain or collector of the fourth transistor; a second capacitor having one end connected to the drain or collector of the fourth transistor and the other end connected to the second power supply voltage; a second resistor having one end connected to the other end of the first capacitor and the other end connected to the second power supply voltage; the first transistor is a PMOS transistor or a PNP transistor; each of the second, third, and fourth transistors is an NMOS transistor or an NPN transistor; the first power supply voltage and the first, second, and third bias voltages are each a positive voltage; The DML driver, wherein the second power supply voltage is ground.

5. 5. The DML driver according to claim 4, a fifth transistor, the gate or base of which is connected to a fourth bias voltage, cascode-connected between the drain or collector of the first transistor and the anode of the laser diode; the fifth transistor is a PMOS transistor or a PNP transistor, The DML driver, wherein the fourth bias voltage is a positive voltage.

6. 6. The DML driver according to claim 1, a third capacitor having one end connected to the first power supply voltage; a third resistor having one end connected to the other end of the third capacitor and the other end connected to the drain or collector of the first transistor.

7. 6. The DML driver according to claim 1, The DML driver further comprises a third resistor inserted between the source or emitter of the second transistor and the optical waveform compensation function unit.

8. 8. The DML driver according to claim 7, The DML driver further comprising a third capacitor connected in parallel with the third resistor.

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