Semiconductor element manufacturing method and semiconductor wafer processing device

Abstract

To cut a semiconductor wafer properly in a wider region than before, when a modified layer non-formed region is present.SOLUTION: A method of manufacturing a semiconductor element includes the steps of: forming a modified layer inside a semiconductor wafer by irradiating the semiconductor wafer with a laser, the modified layer extending along a surface of the semiconductor wafer; detecting a modified layer non-formed region where the modified layer is not formed in a peripheral portion on the surface of the semiconductor wafer; and cutting the semiconductor wafer at the modified layer starting from a region other than the modified layer non-formed region in the peripheral portion.SELECTED DRAWING: Figure 18

Description

[Technical Field]

[0001] The technology disclosed in this specification relates to a method for manufacturing a semiconductor device and a semiconductor wafer processing apparatus.

[0002] Patent Document 1 discloses a technique for obtaining thin semiconductor wafers by dividing the semiconductor wafer along its surface. In this manufacturing method, a laser is first irradiated onto the semiconductor wafer to form an affected layer extending along the surface inside the semiconductor wafer. The affected layer reduces the strength of the semiconductor wafer. Next, a force is applied to the top surface of the semiconductor wafer in a direction away from the bottom surface, thereby dividing the semiconductor wafer at the affected layer. In the process of dividing the semiconductor wafer, the semiconductor wafer is divided starting from the outer periphery of the semiconductor wafer. That is, the semiconductor wafer is divided by generating a crack (i.e., a dividing surface) starting from the outer periphery of the semiconductor wafer. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2019 / 044588 Summary of the Invention [Problem to be solved by the invention]

[0004] In a process of irradiating a semiconductor wafer with a laser, an altered layer may not be formed over the entire target area. For example, an equipment malfunction in the laser irradiation device may prevent the formation of an altered layer in part of the target area. Furthermore, a foreign object present on the surface of the semiconductor wafer may block the laser, preventing the formation of an altered layer in part of the target area. Thus, if an area where an altered layer is not formed (hereinafter, sometimes referred to as an "altered layer-free area") exists, the semiconductor wafer may not be properly divided in the "altered layer-free area." Furthermore, if an "altered layer-free area" exists at the starting point of division, the semiconductor wafer may not be properly divided not only in the "altered layer-free area" but also in areas adjacent to the "altered layer-free area" (i.e., areas where an altered layer exists). This specification proposes a technology that allows the semiconductor wafer to be properly divided over a wider area than conventional technology when an "altered layer-free area" exists. [Means for solving the problem]

[0005] The method for manufacturing a semiconductor element disclosed in this specification includes the steps of: forming an altered layer extending along the surface of a semiconductor wafer inside the semiconductor wafer by irradiating the semiconductor wafer with a laser; detecting an area of ​​the outer periphery of the surface of the semiconductor wafer where the altered layer has not been formed; and dividing the semiconductor wafer at the altered layer, starting from an area of ​​the outer periphery other than the area where the altered layer has not been formed.

[0006] The "periphery of the surface of the semiconductor wafer" refers to the edge of the outer periphery of the flat surface of the semiconductor wafer. Therefore, the bevel portion near the side surface of the semiconductor wafer is not included in the "periphery of the surface of the semiconductor wafer."

[0007] In this manufacturing method, the semiconductor wafer is divided at the affected layer, starting from a region other than the affected layer-free region in the outer periphery of the surface of the semiconductor wafer. When the affected layer-free region in the outer periphery is located at a position other than the dividing starting point, it is possible to prevent the semiconductor wafer from being divided improperly in the region adjacent to the affected layer-free region. Therefore, this manufacturing method allows the semiconductor wafer to be divided appropriately over a wider region than conventional methods.

[0008] This specification also proposes a semiconductor wafer processing apparatus for processing a semiconductor wafer having an internal deteriorated layer extending along the surface of the semiconductor wafer. The semiconductor wafer processing apparatus includes a deteriorated-layer-free region detection mechanism, a position adjustment mechanism, and a dividing mechanism. The deteriorated-layer-free region detection mechanism performs a step of detecting an deteriorated-layer-free region in the outer periphery of the surface of the semiconductor wafer, where the deteriorated layer is not formed. The position adjustment device performs a step of setting the semiconductor wafer in the dividing apparatus so that an area in the outer periphery other than the deteriorated-layer-free region is positioned at a dividing start point of the dividing apparatus. The dividing apparatus performs a step of dividing the semiconductor wafer at the deteriorated layer, starting from the dividing start point.

[0009] This semiconductor wafer processing apparatus can appropriately divide the semiconductor wafer over a wider area than conventionally possible. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. [Figure 2] FIG. 2 is a cross-sectional view of a portion near a side surface of a semiconductor wafer. [Figure 3] 10A to 10C are cross-sectional views showing a laser irradiation step. [Figure 4] FIG. [Figure 5] FIG. 10 is a side view of the dividing mechanism in a closed state. [Figure 6] FIG. 10 is a side view of the splitter mechanism in an open state. [Figure 7] FIG. 4 is a cross-sectional view showing an area where an altered layer is formed and an area where an altered layer is not formed. [Figure 8] 10 is a cross-sectional view showing an affected layer formed region and an affected layer not formed region after division. FIG. [Figure 9] FIG. 10 is a plan view showing the arrangement of a semiconductor wafer on a stage 52 in a dividing step of a comparative example. [Figure 10] FIG. 10 is a plan view showing an example of the distribution of defective division portions 98 in a division step of a comparative example. [Figure 11] FIG. 1 is a block diagram of a semiconductor wafer processing device. [Figure 12] 10A and 10B are diagrams showing images of a semiconductor wafer captured by an affected layer-free region detection mechanism. [Figure 13] 10A and 10B are diagrams showing images of an area where an altered layer has been formed and an area where an altered layer has not been formed. [Figure 14] FIG. 14 is a diagram showing a binarized image of the image in FIG. 13. [Figure 15] FIG. 15 is a diagram showing an image obtained by performing noise removal processing on the image of FIG. 14. [Figure 16] FIG. [Figure 17] 10 is a plan view showing the arrangement of the semiconductor wafer on the stage 52 when the first end 88a is the starting point for division in the division step of the embodiment. FIG. [Figure 18] 10 is a plan view showing the arrangement of the semiconductor wafer on the stage 52 when the second end 88b is the starting point for division in the division step of the embodiment. FIG. [Figure 19] 10 is a plan view showing the arrangement of the semiconductor wafer on the stage 52 when the third end 89a is the starting point for division in the division step of the embodiment. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0011] In the above-described manufacturing method, the semiconductor wafer may be made of a III-V group semiconductor or gallium oxide.

[0012] According to this configuration, since the semiconductor wafer is optically transparent, it is easy to detect the region where the altered layer is not formed.

[0013] In the above-described manufacturing method, prior to the step of dividing the semiconductor wafer, a peeling line may be identified on the surface of the semiconductor wafer, the peeling line passing through the center of an outline circle of the semiconductor wafer and extending along a specific crystal direction. In the step of dividing the semiconductor wafer, if a first end of the peeling line is not in the region where the affected layer is not formed, the semiconductor wafer may be divided at the affected layer using the first end as the starting point, and if the first end of the peeling line is in the region where the affected layer is not formed, the semiconductor wafer may be divided at the affected layer using a second end of the peeling line opposite to the first end as the starting point.

[0014] This configuration allows the crack to propagate in the direction of the peel line during the dividing process, regardless of whether the crack originates from the first end or the second end. By propagating the crack in a specific crystal direction in this way, a flat dividing surface can sometimes be obtained.

[0015] In the manufacturing method described above, in the step of dividing the semiconductor wafer, if both the first end and the second end of the peeling line are in the region where the altered layer is not formed, the semiconductor wafer may be divided at the altered layer using as the starting point an end of a line that passes through the center on the surface of the semiconductor wafer and extends along a direction different from the specific crystal direction.

[0016] According to this configuration, even when both the first end and the second end are regions where no affected layer is formed, the semiconductor wafer can be divided starting from the region where the affected layer is present.

[0017] In the semiconductor wafer processing apparatus described above, the position adjustment mechanism may identify a peeling line on the surface of the semiconductor wafer that passes through the center of the outer circle of the semiconductor wafer and extends along a specific crystal direction, and set the semiconductor wafer in the dividing mechanism so that a first end of the peeling line is located at the splitting start point if the first end is not in the region where an altered layer is not formed, and set the semiconductor wafer in the dividing mechanism so that a second end of the peeling line opposite to the first end is located at the splitting start point if the first end is in the region where an altered layer is not formed.

[0018] In the semiconductor wafer processing apparatus described above, when both the first end and the second end of the peeling line are in the region where the altered layer is not formed, the position adjustment mechanism may set the semiconductor wafer in the dividing mechanism so that the end of a line that passes through the center on the surface of the semiconductor wafer and extends along a direction different from the specific crystal direction is positioned at the dividing starting point.

[0019] A semiconductor device manufacturing method will be described below, comparing the manufacturing method of the embodiment with a manufacturing method of a comparative example. FIG. 1 shows a semiconductor wafer 12 to be processed. The semiconductor wafer 12 is made of a single crystal of gallium nitride. The semiconductor wafer 12 is optically transparent. The top surface 12a of the semiconductor wafer 12 is formed of a specific crystal plane (e.g., an m-plane). Two orientation flats 12n-1 and 12n-2 indicating specific crystal directions are provided on a side surface 12d of the semiconductor wafer 12. FIG. 2 shows a cross section of a portion of the semiconductor wafer 12 near the side surface 12d. A bevel portion 22 having an inclined surface is provided near the side surface 12d. The surface of the bevel portion 22 is inclined so that the thickness of the semiconductor wafer 12 becomes thinner as it approaches the side surface 12d. The main portion 20 in FIG. 2 is the portion having the flat top surface 12a. Therefore, the boundary between the main portion 20 and the bevel portion 22 is the outer periphery 24 of the top surface 12a.

[0020] In both the manufacturing method of the embodiment and the manufacturing method of the comparative example, a laser irradiation step and a semiconductor wafer dividing step are sequentially performed on the semiconductor wafer 12. Note that a semiconductor element structure or a part thereof may be formed on the semiconductor wafer 12 at a stage before the laser irradiation step is performed.

[0021] The manufacturing method of the embodiment and the manufacturing method of the comparative example share a common laser irradiation step. In the laser irradiation step, as shown in FIG. 3, a laser beam L is irradiated onto the semiconductor wafer 12 so that a focal point S is formed inside the semiconductor wafer 12. While FIG. 3 shows the semiconductor wafer 12 being irradiated with the laser beam L from the upper surface 12a, the semiconductor wafer 12 may also be irradiated with the laser beam L from the lower surface 12b. At the position of the focal point S, the semiconductor wafer 12 is heated and decomposed, forming an affected layer 90. That is, the affected layer 90 is a crystalline defect layer composed of gallium and other elements precipitated by the decomposition of gallium nitride. Here, as shown by arrow 100, the focal point S is moved parallel to the upper surface 12a of the semiconductor wafer 12. This forms an affected layer 90 inside the semiconductor wafer 12, extending parallel to the upper surface 12a. Furthermore, as shown by the dashed arrow in FIG. 4, the focal point S is moved so as to scan the entire semiconductor wafer 12, thereby forming the affected layer 90 across almost the entire lateral area of ​​the semiconductor wafer 12. The strength of the semiconductor wafer 12 is lower in the affected layer 90 than in the other portions of the semiconductor wafer 12 (ie, the crystalline region) other than the affected layer 90.

[0022] In the laser irradiation process, the laser beam L may be reflected or refracted on the surface of the bevel portion 22, preventing the formation of the affected layer 90 in the bevel portion 22. Furthermore, in the laser irradiation process, the affected layer 90 is formed across the entire lateral area of ​​the main portion 20. However, if an abnormality occurs in the laser irradiation process, the affected layer 90 may not be formed in part of the main portion 20. For example, an equipment abnormality in the laser irradiation device may prevent the affected layer 90 from being formed in part of the main portion 20. Furthermore, for example, if foreign matter adhering to the semiconductor wafer 12 blocks the laser beam L, the affected layer 90 may not be formed in part of the main portion 20. Hereinafter, when the semiconductor wafer 12 is viewed from above, the region where the affected layer 90 is formed will be referred to as an affected-layer-formed region 92, and the region where the affected layer 90 is not formed will be referred to as an affected-layer-unformed region 94.

[0023] (Comparative Example Semiconductor Wafer Dividing Process) Next, a semiconductor wafer dividing process of the comparative example will be described. The semiconductor wafer dividing process is performed using a dividing mechanism 50 shown in FIGS. 5 and 6. The dividing mechanism 50 has a stage 52 and a rotating plate 54. The rotating plate 54 can rotate around a rotation axis 56. The rotating plate 54 is rotated by a motor (not shown). The rotation of the rotating plate 54 opens and closes the dividing mechanism 50. In the semiconductor wafer dividing process of the comparative example, first, the dividing mechanism 50 is opened, and the semiconductor wafer 12 is placed on the stage 52. Here, the lower surface 12b of the semiconductor wafer 12 is fixed to the stage 52. For example, the lower surface 12b can be fixed to the stage 52 by vacuum suction. Alternatively, the lower surface 12b can be fixed to the stage 52 by adhesive tape, adhesive, or the like. Next, the rotating plate 54 is rotated to close the dividing mechanism 50, and the lower surface of the rotating plate 54 is fixed to the upper surface 12a of the semiconductor wafer 12. For example, the upper surface 12a can be fixed to the rotating plate 54 by vacuum suction. Alternatively, the upper surface 12a may be fixed to the rotating plate 54 with adhesive tape, glue, or the like. Next, as shown in FIG. 6, the rotating plate 54 is rotated to open the dividing mechanism 50. This causes the upper portion 12U of the semiconductor wafer 12 to be pulled in a direction away from the lower portion 12L of the semiconductor wafer 12. This causes a crack to form in the affected layer 90, dividing the semiconductor wafer 12. In other words, the upper portion 12U is peeled off from the lower portion 12L. As a result, the thinner upper portion 12U is obtained.

[0024] (Problems with the Semiconductor Wafer Dividing Process in the Comparative Example) As shown in FIG. 7, the degraded layer 90 is not present in the degraded layer unformed region 94. Therefore, the semiconductor wafer 12 cannot be divided into the intended shape in the degraded layer unformed region 94. For example, as shown in FIG. 8, cracks are formed in the degraded layer unformed region 94 at a depth that is shifted from the depth of the degraded layer 90. Therefore, in FIG. 8, the thickness of the upper portion 12U is thinner in the degraded layer unformed region 94 than in the degraded layer formed region 92. Also, the thickness of the upper portion 12U may be thicker in the degraded layer unformed region 94 than in the degraded layer formed region 92. Furthermore, unevenness occurs on the dividing surface in the degraded layer unformed region 94. Hereinafter, a region where the dividing surface (i.e., the crack) does not have the intended shape is referred to as a dividing defect portion 98.

[0025] 5 and 6, side surface 52a indicates the side surface of stage 52 farther from rotation axis 56, and side surface 52b indicates the side surface of stage 52 closer to rotation axis 56. When rotating rotary plate 54 to divide semiconductor wafer 12, the amount of lift of rotary plate 54 is greater near side surface 52a than near side surface 52b. Therefore, as indicated by arrow 102 in FIG. 6, cracks in semiconductor wafer 12 propagate from side surface 52a toward side surface 52b. Therefore, as shown in FIG. 9, the portion of outer periphery 24 of semiconductor wafer 12 closest to side surface 52a becomes the effective division starting point 12s of semiconductor wafer 12. In other words, division starting point 12s is a point on outer periphery 24 determined by the positional relationship between stage 52 and semiconductor wafer 12. In the semiconductor wafer dividing process of the comparative example, as shown in FIG. 9, an affected layer-free region 94 may exist at division starting point 12s. When the semiconductor wafer 12 is divided in a state in which a degraded layer unformed region 94 exists at the division starting point 12s, as shown in FIG. 10, a division defect 98 (i.e., the shaded portion in FIG. 10) occurs not only in the degraded layer unformed region 94 but also in a region 96 where a crack occurs after the degraded layer unformed region 94 (i.e., the degraded layer formed region 92 adjacent to the degraded layer unformed region 94 on the side surface 52b side). That is, in the region 96 in which the degraded layer 70 exists, the semiconductor wafer 12 is divided at a position shifted from the degraded layer 70. Thus, in the semiconductor wafer dividing process of the comparative example, when a degraded layer unformed region 94 exists at the division starting point 12s, a problem occurs in that the semiconductor wafer 12 cannot be divided properly not only in the degraded layer unformed region 94 but also in the region 96 adjacent thereto.

[0026] (Manufacturing method of the embodiment) In the manufacturing method of the embodiment, the affected layer-free region detection step, the division starting point calculation step, and the angle adjustment step are performed before the semiconductor wafer dividing step. That is, in the manufacturing method of the embodiment, the affected layer-free region detection step, the division starting point calculation step, the angle adjustment step, and the semiconductor wafer dividing step are performed in this order.

[0027] 11 shows a semiconductor wafer processing apparatus 30 that performs the affected layer-free region detection step, the division starting point calculation step, the angle adjustment step, and the semiconductor wafer dividing step. The semiconductor wafer processing apparatus 30 has a wafer loading section 32, an affected layer-free region detection mechanism 34, a wafer angle adjustment mechanism 36, a dividing mechanism 50, a control device 40, and a dividing starting point determination device 42. The control device 40 and the dividing starting point determination device 42 are configured with arithmetic circuits. The dividing mechanism 50 of the semiconductor wafer processing apparatus 30 is the same as the dividing mechanism 50 shown in FIGS. 5 and 6. Although not shown, the semiconductor wafer processing apparatus 30 also has a transport mechanism that transports the semiconductor wafer 12 within the semiconductor wafer processing apparatus 30.

[0028] The wafer loading section 32 is a section where the semiconductor wafer 12 is loaded into and unloaded from the semiconductor wafer processing apparatus 30. The semiconductor wafer 12 loaded into the wafer loading section 32 is transported to the affected layer free region detection mechanism .

[0029] The degraded layer-free region detection mechanism 34 performs the degraded layer-free region detection step. The degraded layer-free region detection mechanism 34 has a camera and photographs the semiconductor wafer 12 from the top surface 12a side. FIG. 12 is an image of the semiconductor wafer 12 photographed by the degraded layer-free region detection mechanism 34. As described above, the semiconductor wafer 12 is optically transparent, and the degraded layer 90 can be observed from the appearance of the semiconductor wafer 12. For example, in the image of FIG. 12, the gray region is the degraded layer 90 (i.e., the degraded layer-formed region 92), and the white region is the degraded layer-free region 94. The degraded layer-free region detection mechanism 34 identifies the degraded layer-formed region 92 and the degraded layer-free region 94 based on the photographed image. FIGS. 13 to 15 are enlarged images of the degraded layer-formed region 92 and the degraded layer-free region 94. FIG. 13 is an image photographed by the camera. In FIG. 13, the gray area is the degraded layer-formed area 92, and the white area is the degraded layer-free area 94. The degraded layer-free area detection mechanism 34 calculates an image by binarizing the brightness value of each pixel of the image captured by the camera, using a value between white and gray as a threshold value. For example, the degraded layer-free area detection mechanism 34 calculates the image of FIG. 14 by binarizing the image of FIG. 13. Next, the degraded layer-free area detection mechanism 34 performs noise removal processing on the binarized image. For example, the degraded layer-free area detection mechanism 34 performs noise removal processing on the image of FIG. 14 to calculate the image shown in FIG. 15 (i.e., an image in which minute white and black areas have been removed and the boundaries between the white and black areas have been smoothed). In the image after noise removal processing, the degraded layer-free area detection mechanism 34 identifies the black area as the degraded layer-formed area 92 and the white area as the degraded layer-free area 94. The degraded layer-free region detection mechanism 34 calculates the coordinate range of the degraded layer-free region 94. The coordinate range of the degraded layer-free region 94 is a coordinate range expressed in an xy coordinate system. The degraded layer-free region detection mechanism 34 transmits the calculated coordinate range to the dividing start point determination device 42. When the degraded layer-free region detection process is completed, the semiconductor wafer 12 is transported to the wafer angle adjustment mechanism 36.

[0030] Upon receiving the coordinate range of the affected layer-free region 94, the dividing start point determination device 42 performs a dividing start point calculation process. In the dividing start point calculation process, the dividing start point determination device 42 first detects orientation flats 12n-1 and 12n-2 from an image (e.g., the image of FIG. 12) captured by the affected layer-free region detection mechanism 34. Next, the dividing start point determination device 42 identifies a first peeling line 88 shown in FIG. 16 based on the positions and angles of the orientation flats 12n-1 and 12n-2. The first peeling line 88 is a line that passes through the center 12c of the outline circle of the semiconductor wafer 12 on the upper surface 12a and extends along a specific crystal direction. The outline circle of the semiconductor wafer 12 is a portion of the outline (i.e., the contour) of the semiconductor wafer 12 that has an arc shape. The specific crystal direction is a predetermined crystal direction that is stored in the dividing start point determination device 42. The specific crystal direction can be a crystal direction that tends to flatten the split surface when a crack propagates in that crystal direction. After identifying the first peel line 88, the splitting start point determination device 42 identifies one end of the first peel line 88 as a first end 88a and the other end of the first peel line 88 as a second end 88b. The first end 88a and the second end 88b are intersections of the first peel line 88 and the outer periphery 24. Next, the splitting start point determination device 42 determines whether the first end 88a and the second end 88b are in the affected-layer-free region 94 based on the coordinate range of the affected-layer-free region 94 calculated by the affected-layer-free region detection mechanism 34. If the first end 88a is not in the affected-layer-free region 94, the splitting start point determination device 42 determines the first end 88a as the splitting start point. When the first end 88a is in the affected layer unformed region 94 and the second end 88b is not in the affected layer unformed region 94, the splitting starting point determination device 42 determines the second end 88b as the splitting starting point. When both the first end 88a and the second end 88b are in the affected layer unformed region 94, the splitting starting point determination device 42 identifies a second peeling line 89 different from the first peeling line 88 as shown in FIG. 16, and identifies one end of the second peeling line 89 (hereinafter referred to as the third end 89a) as the splitting starting point. The second peeling line 89 is a line that passes through the center 12c and extends along a crystal direction different from that of the first peeling line 88.

[0031] After the dividing starting point determination process is completed, the angle adjustment process is performed. In the angle adjustment process, the angle of the semiconductor wafer 12 is adjusted by the wafer angle adjustment mechanism 36, and then the semiconductor wafer 12 is transferred onto the stage 52 of the dividing mechanism 50. The wafer angle adjustment mechanism 36 and the dividing mechanism 50 are controlled by the control device 40. The wafer angle adjustment mechanism 36 has a rotatable stage. In the angle adjustment process, the semiconductor wafer 12 is first placed on the stage of the wafer angle adjustment mechanism 36. Then, the control device 40 rotates the semiconductor wafer 12 around the center 12c using the stage of the wafer angle adjustment mechanism 36. This adjusts the angle of the semiconductor wafer 12 relative to the dividing mechanism 50. After the angle adjustment, the semiconductor wafer 12 is transferred onto the stage 52 of the dividing mechanism 50. As shown in FIG. 17 , if the first end 88a is determined as the dividing starting point, the control device 40 adjusts the angle of the semiconductor wafer 12 on the stage 52 of the dividing mechanism 50 so that the first end 88a becomes the dividing starting point 12s. That is, the angle of the semiconductor wafer 12 is adjusted so that the first end 88a is located closest to the side surface 52a within the outer periphery 24. Also, as shown in FIG. 18 , when the second end 88b is determined as the division starting point (i.e., when the first end 88a is the affected layer unformed region 94), the control device 40 adjusts the angle of the semiconductor wafer 12 so that the second end 88b becomes the division starting point 12s on the stage 52 of the dividing mechanism 50. Also, as shown in FIG. 19 , when the third end 89a is determined as the division starting point (i.e., when the first end 88a and the second end 88b are the affected layer unformed region 94), the control device 40 adjusts the angle of the semiconductor wafer 12 so that the third end 89a becomes the division starting point 12s on the stage 52 of the dividing mechanism 50. In this way, in the angle adjustment process, the angle of the semiconductor wafer 12 is adjusted so that the affected layer unformed region 94 is not located at the division starting point 12s.

[0032] When the angle adjustment step is completed, the control device 40 controls the dividing mechanism 50 to perform the semiconductor wafer dividing step. In the semiconductor wafer dividing step of the embodiment, similar to the semiconductor wafer dividing step of the comparative example, the semiconductor wafer 12 is divided at the affected layer 90, starting from the dividing starting point 12s. That is, with the lower surface 12b of the semiconductor wafer 12 fixed to the stage 52 and the upper surface 12a of the semiconductor wafer 12 fixed to the rotating plate 54, the control device 40 drives the motor of the dividing mechanism 50 to rotate the rotating plate 54. As a result, the semiconductor wafer 12 is divided as shown in FIG. 6.

[0033] As described above, in the manufacturing method of the embodiment, the semiconductor wafer 12 is placed on the stage 52 so that the degraded-layer-free region 94 is not located at the dividing starting point 12s. Therefore, in the semiconductor wafer dividing step, the occurrence of a dividing defect 98 from the degraded-layer-free region 94 located at the dividing starting point 12s to the adjacent region 96 is prevented, as shown in Fig. 10. For example, when the degraded-layer-free region 94 is located at a position other than the dividing starting point 12s as shown in Figs. 18 and 19, although a dividing defect occurs in the degraded-layer-free region 94, the occurrence of a dividing defect in the degraded-layer-free region 92 adjacent to the degraded-layer-free region 94 can be suppressed.

[0034] As described above, by dividing the semiconductor wafer 12 into the upper portion 12U and the lower portion 12L, the upper portion 12U having a smaller thickness can be obtained. Therefore, by performing electrode formation, dicing, etc. on the upper portion 12U, a thin semiconductor element can be manufactured. In addition, the lower portion 12L can be reused in manufacturing the semiconductor element.

[0035] In the above-described embodiment, the semiconductor wafer 12 is made of gallium nitride. However, the semiconductor wafer 12 may be made of a III-V group semiconductor other than gallium nitride, or gallium oxide. These materials are transparent, so it is easy to identify the region where an altered layer has not been formed and the region where an altered layer has been formed from the appearance of the semiconductor wafer.

[0036] Furthermore, in the above-described embodiment, the control device 40 and the division starting point determination device 42 are configured by separate arithmetic circuits, but the control device 40 and the division starting point determination device 42 may also be configured by a single arithmetic circuit.

[0037] In the above-described embodiment, the wafer angle adjustment mechanism 36 is provided separately from the dividing mechanism 50. However, the wafer angle adjustment mechanism 36 and the dividing mechanism 50 may be realized by the same device. For example, the stage 52 of the dividing mechanism 50 may have a wafer angle adjustment function.

[0038] In the above-described embodiment, the division starting point determination device 42 calculates the peeling lines 88, 89 and determines the ends of the peeling lines 88, 89 as the division starting points. However, as long as the affected layer-free region is not located at the division starting points, the division starting points may be determined by any method.

[0039] Furthermore, in the above-described embodiment, the region where no affected layer is formed is detected based on an image captured by a camera, but the region where no affected layer is formed may also be detected by a transmission type laser sensor or the like.

[0040] The wafer angle adjusting mechanism 36 and the transport mechanism that transports the semiconductor wafer to the dividing mechanism 50 in the embodiment are an example of a position adjusting mechanism.

[0041] Although the embodiments have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and variations of the specific examples exemplified above. The technical elements described in this specification or drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technology exemplified in this specification or drawings simultaneously achieves multiple objectives, and achieving one of these objectives itself has technical utility. [Explanation of symbols]

[0042] 12: semiconductor wafer, 12s: division starting point, 24: outer periphery, 88: first peeling line, 88a: first end, 88b: second end, 89: second peeling line, 89a: third end, 90: degraded layer, 92: degraded layer formed region, 94: degraded layer not formed region

Claims

1. A method for manufacturing a semiconductor device, comprising: forming an affected layer extending along a surface of the semiconductor wafer inside the semiconductor wafer by irradiating the semiconductor wafer with a laser; detecting an area where the deteriorated layer is not formed in the outer periphery of the surface of the semiconductor wafer; setting the semiconductor wafer in a dividing mechanism; dividing the semiconductor wafer at the affected layer by the dividing mechanism; and If the affected layer unformed region exists in the outer periphery, in the step of setting the semiconductor wafer in the dividing mechanism, an angle of the semiconductor wafer is adjusted so that a region other than the affected layer unformed region is positioned as a dividing start point of the dividing mechanism; If the region where the altered layer is not formed exists in the outer periphery, in the step of dividing the semiconductor wafer, the dividing mechanism divides the semiconductor wafer at the altered layer, starting from the division starting point. Manufacturing method.

2. If the region where the altered layer is not formed exists in the outer periphery, in the step of dividing the semiconductor wafer, the dividing mechanism divides the semiconductor wafer at the altered layer, with the dividing starting point as the dividing starting point, while the region where the altered layer is not formed and the region where the altered layer is formed exist in the outer periphery. The method of claim 1.

3. Before the step of dividing the semiconductor wafer, a peeling line is identified on the surface of the semiconductor wafer, the peeling line passing through the center of the outline circle of the semiconductor wafer and extending along a specific crystal direction; In the step of dividing the semiconductor wafer, If the first end of the peeling line is not in the region where the deteriorated layer is not formed, the semiconductor wafer is divided at the deteriorated layer, with the first end as the starting point; When the first end of the peeling line is in the region where the deteriorated layer is not formed, the semiconductor wafer is divided at the deteriorated layer, with a second end of the peeling line opposite to the first end as the starting point. The method according to claim 1 or 2.

4. 4. The manufacturing method according to claim 3, wherein in the step of dividing the semiconductor wafer, if both the first end and the second end of the peeling line are in the region where the altered layer is not formed, the semiconductor wafer is divided at the altered layer, starting from an end of a line that passes through the center on the surface of the semiconductor wafer and extends along a direction different from the specific crystal direction.

5. 1. A semiconductor wafer processing apparatus for processing a semiconductor wafer having an affected layer extending along a surface of the semiconductor wafer therein, a mechanism for detecting an area where an altered layer has not yet formed; a position adjustment mechanism; splitting mechanism, and the affected layer-free region detection mechanism performs a step of detecting an affected layer-free region in the outer periphery of the surface of the semiconductor wafer, where the affected layer is not formed; the position adjusting mechanism performs a step of setting the semiconductor wafer on the dividing mechanism so that a region of the outer periphery other than the region where the affected layer is not formed is positioned as a dividing start point of the dividing mechanism; the dividing mechanism performs a step of dividing the semiconductor wafer at the affected layer, starting from the dividing starting point. Semiconductor wafer processing equipment.

6. The position adjustment mechanism Identifying a peeling line on the surface of the semiconductor wafer, the peeling line passing through the center of the outline circle of the semiconductor wafer and extending along a specific crystal direction; If the first end of the peeling line is not in the affected layer-free region, the semiconductor wafer is set in the dividing mechanism so that the first end is located at the dividing start point; When the first end of the peeling line is in the region where the affected layer is not formed, the semiconductor wafer is set in the dividing mechanism so that a second end of the peeling line opposite to the first end is positioned at the dividing start point.

6. The semiconductor wafer processing apparatus according to claim 5.

7. 7. The semiconductor wafer processing apparatus according to claim 6, wherein when both the first end and the second end of the peeling line are in the region where the altered layer is not formed, the position adjustment mechanism sets the semiconductor wafer in the dividing mechanism so that an end of a line that passes through the center on the surface of the semiconductor wafer and extends along a direction different from the specific crystal direction is positioned at the dividing starting point.

Images