Silicon carbide semiconductor device and method for manufacturing silicon carbide semiconductor device

Abstract

To provide a silicon carbide semiconductor device capable of suppressing a channel leak by increasing channel mobility with a threshold held high, and a method of manufacturing the silicon carbide semiconductor device.SOLUTION: A silicon carbide semiconductor device comprises: a silicon carbide semiconductor substrate 1 of a first conductivity type; a first semiconductor layer 2 of the first conductivity type; a first semiconductor region 3 of a second conductivity type; a second semiconductor region 4 of the first conductivity type; a trench 5; a gate insulating film 7; a gate electrode 8; a third semiconductor region 19 of the first conductivity type provided between a gate insulating film 7 on a side wall of the trench 5 and the first semiconductor region 3; and a fourth semiconductor region 17 of the second conductivity type provided between the first semiconductor region 3 and third semiconductor region 19 and having higher impurity density than the first semiconductor region 3.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device. [Background technology]

[0002] Silicon carbide (SiC) is expected to be a next-generation semiconductor material that will replace silicon (Si). Compared to conventional semiconductor devices that use silicon carbide as the semiconductor material, semiconductor devices that use silicon carbide as the semiconductor material (hereinafter referred to as silicon carbide semiconductor devices) have various advantages, such as the ability to reduce the resistance of the device in the on-state to one-hundredth of that of conventional semiconductor devices that use silicon as the semiconductor material, and the ability to be used in higher temperature environments (over 200°C). This is due to the characteristics of the material itself, namely, that the band gap of silicon is about three times larger than that of silicon, and that the dielectric breakdown field strength is nearly one order of magnitude greater than that of silicon.

[0003] To date, commercially available silicon carbide semiconductor devices include Schottky barrier diodes (SBDs) and vertical MOSFETs (metal oxide semiconductor field effect transistors) with planar gate structures or trench gate structures.

[0004] The planar gate structure is a MOS gate structure in which a flat MOS gate is provided on the front surface of a semiconductor substrate. The trench gate structure is a MOS gate structure in which a MOS gate is embedded in a trench formed on the front surface of a semiconductor substrate (semiconductor chip), and a channel (inversion layer) is formed along the sidewall of the trench in a direction perpendicular to the front surface of the semiconductor substrate. This allows for a higher density of unit cells (element constituent units) per unit area compared to a planar gate structure in which a channel is formed along the front surface of the semiconductor substrate, thereby increasing the current density per unit area, and is therefore advantageous in terms of cost.

[0005] The structure of a conventional silicon carbide semiconductor device will be described using a trench-type SiC-MOSFET as an example. FIG. 8 is a cross-sectional view showing the structure of a conventional silicon carbide semiconductor device. FIG. 8 shows the structure of a unit cell (functional unit of an element) arranged in an active region through which current flows in an on-state. As shown in FIG. 8, a conventional semiconductor device 200 has n + An n-type drift layer 102 is deposited on the front surface of a silicon carbide semiconductor substrate 101. A MOS gate structure is provided on the first main surface side of the n-type drift layer 102. The MOS gate structure includes a p-type base region 103, an n-type base region 104, a n-type base region 105, a n-type base region 106, a n-type base region 107, a n-type base region 108, a n-type base region 109 ... + type source region 104, p + The gate electrode 108 is made up of a contact region 114, a trench 105, a gate insulating film 107, and a gate electrode 108. + type source region 104 and p + The p-type contact region 114 is selectively provided inside the p-type base region 103 .

[0006] The trench 105 has a depth of n + The gate electrode 108 penetrates the p-type source region 104 and the p-type base region 103 to reach the n-type drift layer 102. The gate electrode 108 is provided inside the trench 105. The gate electrode 108 is connected to the p-type base region 103 and the n-type drift layer 102, with a gate insulating film 107 provided on the bottom and sidewalls of the trench 105 in between. + The n-type drift layer 102 has a first p-type region 115 formed between the trenches 105 and facing the n-type source region 104. A first p-type region 115 is selectively formed in the surface layer of the n-type drift layer 102 between the trenches 105. A second p-type base region 116 is selectively formed in the n-type drift layer 102 so as to cover the entire bottom surface of the trench 105.

[0007] In the conventional semiconductor device 200, source-drain leakage during forward bias and reverse bias is suppressed by either increasing the concentration of the p-type base region 103 to a certain extent or by performing full-surface channel implantation. Furthermore, in order to suppress an increase in leakage current and an increase in saturation current due to the short channel effect when the drain voltage is high, a p-type channel implantation layer 117 with a higher concentration than the p-type base region 103 is provided near the channel. Furthermore, by forming the high-concentration p-type channel implantation layer 117 near the channel by full-surface channel implantation before opening the trench 105, the channel threshold can be adjusted and channel leakage penetrating the p-type base region 103 can be suppressed.

[0008] 9 is a cross-sectional view showing another structure of a conventional silicon carbide semiconductor device. As shown in FIG. 9, in a conventional semiconductor device 210, it is known to provide a high-concentration p-type region 118 near the trench 105 in order to suppress a high electric field at the bottom of the trench 105 when the drain voltage becomes high (see, for example, Patent Document 1 listed below). By forming the high-concentration p-type region 118 near the trench 105 by oblique implantation separately from the p-type base region 103, it is possible to suppress a high electric field at the gate insulating film 107.

[0009] In addition, a p-type region is provided adjacent to the gate insulating film, and the p-type region + A silicon carbide semiconductor device is known in which the n-type source region does not contact the gate insulating film, thereby reducing the contact area between the n-type source resistance region and the gate insulating film (see, for example, Patent Document 2 below). Also, a third p-type source region is provided in the p-type base region away from and parallel to the trench sidewall. + A semiconductor device is known in which, by providing a p-type region, the p-type impurity concentration can be increased in the portion of the p-type base region facing the sidewall of the trench across the channel region, thereby suppressing the extension of depletion layers from the drain side and source side into the p-type base region when the MOSFET is on (see, for example, Patent Document 3 below). [Prior art documents] [Patent documents]

[0010] [Patent Document 1] Patent No. 6416143 [Patent Document 2] Patent Publication No. 2021-150405 [Patent Document 3] Japanese Patent Application Publication No. 2019-050352 Summary of the Invention [Problem to be solved by the invention]

[0011] However, in conventional silicon carbide semiconductor devices, source-drain leakage during reverse bias cannot be suppressed unless the p-type base region 103 has a certain high concentration. Also, as shown in Figure 9, in order to place the high-concentration p-type region 118 very close to the channel, oblique implantation is required for the trench 105. However, with oblique implantation, the implanted impurities remain near the channel, making it impossible to make the entire p-type base region 103 a high-concentration p-type region.

[0012] In order to solve the above-mentioned problems associated with the conventional techniques, an object of the present invention is to provide a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device that can increase channel mobility and suppress channel leakage while maintaining a high threshold voltage. [Means for solving the problem]

[0013] In order to solve the above-mentioned problems and achieve the object of the present invention, a silicon carbide semiconductor device according to the present invention has the following features. A first semiconductor layer of a first conductivity type, having a lower impurity concentration than the silicon carbide semiconductor substrate, is provided on a front surface of a silicon carbide semiconductor substrate of a first conductivity type. A first semiconductor region of a second conductivity type is provided on a surface of the first semiconductor layer opposite to the silicon carbide semiconductor substrate. A second semiconductor region of a first conductivity type is selectively provided in a surface layer of the first semiconductor region opposite to the silicon carbide semiconductor substrate. A trench is provided that penetrates the first semiconductor region and the second semiconductor region and reaches the first semiconductor layer. A gate insulating film is provided inside the trench along a bottom and sidewalls of the trench. A gate electrode is provided inside the trench, inside the gate insulating film. A third semiconductor region of a first conductivity type is provided on the sidewalls of the trench between the gate insulating film and the first semiconductor region. A fourth semiconductor region of the second conductivity type having a higher impurity concentration than the first semiconductor region is provided between the first semiconductor region and the third semiconductor region. The fourth semiconductor region is thinner than the first semiconductor region, and a part of the bottom surface thereof is in contact with the first semiconductor layer.

[0014] Furthermore, the silicon carbide semiconductor device according to the present invention is characterized in that, in the above-described invention, the width of the third semiconductor region in the direction in which the trenches are arranged is greater than 0 nm and not greater than 50 nm, the width of the fourth semiconductor region in the direction in which the trenches are arranged is greater than 10 nm and not greater than 200 nm, and the first semiconductor region is separated from the gate insulating film on the sidewall of the trench by 100 nm or more.

[0015] Further, in the silicon carbide semiconductor device according to the present invention, in the above-mentioned invention, the impurity concentration of the fourth semiconductor region is 1×10 18 / cm 3 or more, and the impurity concentration of the first semiconductor region is 5×10 16 / cm 3 The present invention is characterized in that: Moreover, in the silicon carbide semiconductor device according to the present invention, the third semiconductor region has the same impurity concentration as the first semiconductor layer.

[0016] In order to solve the above-mentioned problems and achieve the object of the present invention, a method for manufacturing a silicon carbide semiconductor device according to the present invention has the following features. First, a first step is performed in which a first semiconductor layer of a first conductivity type having a lower impurity concentration than the silicon carbide semiconductor substrate is formed on a front surface of the silicon carbide semiconductor substrate. Next, a second step is performed in which a first semiconductor region of a second conductivity type and a third semiconductor region of the first conductivity type are formed on a surface of the first semiconductor layer opposite to the silicon carbide semiconductor substrate. Next, a third step is performed in which a second semiconductor region of a first conductivity type is selectively formed on a surface layer of the first semiconductor region opposite to the silicon carbide semiconductor substrate. Next, a fourth step is performed in which a trench is formed that penetrates the first semiconductor region and the second semiconductor region and reaches the first semiconductor layer. Next, a fifth step is performed in which an impurity is obliquely implanted from a sidewall of the trench to form a fourth semiconductor region of a second conductivity type having a higher impurity concentration than the first semiconductor region. Next, a sixth step is performed in which a gate insulating film is formed inside the trench along the bottom and sidewall of the trench. Next, a seventh step is performed in which a gate electrode is formed inside the gate insulating film inside the trench. In the second step, impurities are implanted so that the third semiconductor region is formed between the gate insulating film on the sidewall of the trench and the first semiconductor region. In the fifth step, the fourth semiconductor region is formed between the first semiconductor region and the third semiconductor region.

[0017] According to the above-described invention, the area immediately adjacent to the gate insulating film on the sidewall of the trench is an n-type region, and the area adjacent to the gate insulating film on the sidewall of the trench is a p-type region with a higher impurity concentration than the p-type base region. The p-type base region is located at a distance of about 100 nm or more from the gate insulating film on the sidewall of the trench, making the p-type base region highly p-type. This allows the threshold voltage to be increased and leakage to be suppressed without reducing the electron mobility of the channel. Therefore, by increasing the channel mobility while maintaining a high threshold voltage, low on-resistance can be achieved, and conduction loss can be reduced while suppressing switching malfunctions due to a decrease in threshold voltage. [Effects of the Invention]

[0018] The silicon carbide semiconductor device and the method for manufacturing the silicon carbide semiconductor device according to the present invention have the effect of increasing channel mobility and suppressing channel leakage while maintaining a high threshold voltage. [Brief explanation of the drawings]

[0019] [Figure 1] 1 is a cross-sectional view showing a structure of a silicon carbide semiconductor device according to an embodiment; [Figure 2] 1 is a graph showing a breakdown voltage waveform of a silicon carbide semiconductor device according to an embodiment. [Figure 3] 1 is a graph showing on-resistance versus threshold voltage for a silicon carbide semiconductor device according to an embodiment and a conventional silicon carbide semiconductor device. [Figure 4] 1A to 1C are cross-sectional views showing a state during the manufacture of a silicon carbide semiconductor device according to an embodiment (part 1). [Figure 5] 10 is a cross-sectional view (part 2) showing a state during the manufacture of the silicon carbide semiconductor device according to the embodiment. FIG. [Figure 6] 10 is a cross-sectional view (part 3) showing a state during the manufacture of the silicon carbide semiconductor device according to the embodiment. FIG. [Figure 7] 10 is a cross-sectional view (part 4) showing a state during the manufacture of a silicon carbide semiconductor device according to an embodiment. FIG. [Figure 8] FIG. 1 is a cross-sectional view showing the structure of a conventional silicon carbide semiconductor device. [Figure 9] FIG. 10 is a cross-sectional view showing another structure of a conventional silicon carbide semiconductor device. DETAILED DESCRIPTION OF THE INVENTION

[0020] Preferred embodiments of a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device according to the present invention will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, layers and regions prefixed with n or p indicate that electrons or holes are the majority carriers, respectively. The + and - symbols attached to n or p indicate higher and lower impurity concentrations than layers and regions not prefixed with these symbols, respectively. In the following description of the embodiments and the accompanying drawings, similar components are designated by the same reference symbols, and redundant explanations will be omitted. In this specification, in the notation of Miller indices, "-" refers to a bar attached to the index immediately following it, and adding "-" before an index indicates a negative index. It is preferable that the terms "same" or "equivalent" be used to include variations within 5% in consideration of variations in manufacturing.

[0021] (Embodiment) The semiconductor device according to the present invention is configured using a wide bandgap semiconductor. In the embodiment, a trench MOSFET 100 will be described as an example of a silicon carbide semiconductor device fabricated (manufactured) using silicon carbide (SiC) as a wide bandgap semiconductor.

[0022] 1 is a cross-sectional view showing the structure of a silicon carbide semiconductor device according to an embodiment. As shown in FIG. 1, in the silicon carbide semiconductor device according to the embodiment, n + An n-type drift layer (first semiconductor layer of the first conductivity type) 2 is provided on a first main surface side (front surface) of a silicon carbide semiconductor substrate (silicon carbide semiconductor substrate of the first conductivity type) 1. + A MOS gate structure having a trench gate structure is provided on the opposite side of the silicon carbide semiconductor substrate 1. The MOS gate structure includes a p-type base region (a first semiconductor region of a second conductivity type) 3, an n-type base region (a first semiconductor region of a second conductivity type) 4, a n-type base region (a second semiconductor region of a second conductivity type) 5, a n-type base region (a first semiconductor region of a second conductivity type) 6, a n-type base region (a second semiconductor region of a second + The p-type source region (second semiconductor region of the first conductivity type) 4, the trench 5, the gate insulating film 7, and the gate electrode 8. +A trench contact region 5 may be provided. The trench 5 has, for example, a stripe shape as shown in Fig. 1. Fig. 1 shows only the active region of the trench MOSFET 100, through which the main current flows.

[0023] A second p-type region 16 is selectively provided within the n-type drift layer 2, spaced apart from the p-type base region 3. The second p-type region 16 may be embedded within the n-type drift layer 2 so as to surround the bottom of the trench 5, and faces the gate electrode 8 with the gate insulating film 7 interposed therebetween. In other words, the bottom of the trench 5 may be located within the second p-type region 16. The second p-type region 16 is wider than the trench 5. The second p-type region 16 has the function of alleviating the electric field applied to the n-type drift layer 2. The second p-type region 16 may be a diffusion region formed by, for example, ion implantation.

[0024] A first p-type region 15 is provided in the surface layer of the n-type drift layer 2 between the trenches 5. The first p-type region 15 is provided to the same depth as the second p-type region 16 and has the same potential as the p-type base region 3. Like the second p-type region 16, the first p-type region 15 has the function of alleviating the electric field applied to the n-type drift layer 2.

[0025] In order to set the first p-type region 15 and the second p-type region 16 at the same potential, a portion of the first p-type region 15 may be extended to connect the first p-type region 15 and the second p-type region 16. The p-type base region 3 is provided on the n-type drift layer 2. The p-type base region 3 is a diffusion region formed in the surface layer of the n-type drift layer 2 by, for example, ion implantation.

[0026] In this embodiment, the p-type base region 3 and the channel implantation layer 17 are provided away from the gate insulating film 7 on the sidewall of the trench 5. An n-type region (third semiconductor region of the first conductivity type) 19 having the same impurity concentration as the n-type drift layer 2 is provided between the gate insulating film 7 on the sidewall of the trench 5 and the p-type base region 3, in close proximity to the gate insulating film 7. The width W1 of the n-type region 19 in the direction in which the trenches 5 are aligned is greater than 0 nm and approximately 50 nm or less. Therefore, the area W1 on the sidewall of the trench 5 in close proximity to the gate insulating film 7 is an n-type region. This prevents electrons from traveling only at the interface with the gate insulating film 7, thereby preventing a decrease in channel mobility. Because the sidewall of the trench 5 is n-type and electrons can travel through that portion, it becomes a (accumulation layer) channel when the device is on. Furthermore, a channel is more easily induced than in a p-type region at the same gate positive bias. Furthermore, the gate potential and the high-concentration channel implantation layer 17 near the interface deplete the n-type near the interface, so no channel is formed and the threshold does not fall below 0V (no depletion) even if it is n-type.

[0027] Furthermore, a channel implantation layer 17 (fourth semiconductor region of the second conductivity type) having a higher impurity concentration than the p-type base region 3 is provided between the n-type region 19 and the p-type base region 3, near the gate insulating film 7. The width W2 of the channel implantation layer 17 in the direction in which the trenches 5 are aligned is greater than 10 nm and approximately 200 nm or less. Therefore, the range W2 near the gate insulating film 7 on the sidewall of the trench 5 is a p-type region having a higher impurity concentration than the p-type base region 3. This makes it possible to increase the threshold voltage of the semiconductor device. Furthermore, the impurity concentration of the channel implantation layer 17 is, for example, 1×10 18 / cm 3 That's all.

[0028] The p-type base region 3 is provided in a region at least W3 (approximately 100 nm) away from the gate insulating film 7 on the sidewall of the trench 5, and the p-type base region 3 is made of a high-concentration p-type. This makes it possible to suppress leakage in the p-type base region 3. The impurity concentration of the p-type base region 3 is, for example, 5×10 16 / cm 3 That's all.

[0029] By adopting such a structure, in the embodiment, it is possible to increase the threshold voltage and suppress leakage without reducing the electron mobility in the channel. Therefore, by increasing the channel mobility while keeping the threshold voltage high, it is possible to achieve a low on-resistance, and it is possible to reduce conduction loss while suppressing malfunctions during switching due to a decrease in the threshold voltage.

[0030] n + The n-type source region 4 is selectively provided inside the p-type base region 3. + The source region 4 may be an epitaxial layer or a diffusion region formed by, for example, ion implantation. + A p-type contact region 14 may be selectively provided inside the p-type base region 3. + The p-type source region 4 is in contact with the gate insulating film 7. + The contact region 14 is provided at a position away from the gate insulating film 7. The trench 5 is + The p-type source region 4 and the p-type base region 3 are penetrated to reach the n-type drift layer 2 .

[0031] The gate electrode 8 is connected to the second p-type region 16, the p-type base region 3, and the n-type region 4, with the gate insulating film 7 provided on the bottom and sidewall of the trench 5 interposed therebetween. + The gate electrode 8 faces the p-type source region 4, the channel implantation layer 17, and the n-type drift layer 2. The drain side end of the gate electrode 8 is located closer to the drain than the pn junction between the p-type base region 3 and the n-type drift layer 2.

[0032] The source electrode (not shown) is connected to the p-type base region 3 and the n + The p-type source region 4 is in contact with the p-type source region 4 and is electrically insulated from the gate electrode 8 by an interlayer insulating film (not shown). + When the contact region 14 is provided, the source electrode 10 is + type contact region 14 and n + The source region 4 is in contact with the source region 4 .

[0033] n +A drain electrode serving as a back surface electrode (not shown) is provided on the second main surface (back surface) of the silicon carbide semiconductor substrate 1. A drain electrode pad (not shown) is provided on the surface of the back surface electrode.

[0034] 2 is a graph showing a breakdown voltage waveform of the silicon carbide semiconductor device according to the embodiment. In FIG. 2, the horizontal axis represents the drain voltage in V, and the vertical axis represents the drain current in A. In FIG. 2, the impurity concentration of p-type base region 3 is set to 2×10 16 / cm 3 ~6×10 16 / cm 3 As shown in Figure 2, the breakdown voltage is shown when the impurity concentration is changed from 4×10 16 / cm 3 Above this, a high breakdown voltage can be maintained.

[0035] 3 is a graph showing on-resistance versus threshold voltage for a silicon carbide semiconductor device according to an embodiment and a conventional silicon carbide semiconductor device. In Fig. 3, the horizontal axis represents threshold (Vth) in V, and the vertical axis represents on-resistance (RonA) in mΩ / cm. 2 3, in the silicon carbide semiconductor device according to the embodiment, the on-resistance can be reduced while maintaining a higher threshold voltage than in the conventional silicon carbide semiconductor device.

[0036] (Method for manufacturing silicon carbide semiconductor device according to embodiment) Next, a method for manufacturing a silicon carbide semiconductor device according to an embodiment will be described. Figures 4 to 7 are cross-sectional views showing states during the manufacturing process of a silicon carbide semiconductor device according to an embodiment.

[0037] First, n-type silicon carbide + A silicon carbide substrate 1 is prepared. + A first n-type drift layer (not shown) made of silicon carbide is epitaxially grown on the front surface (first main surface) of silicon carbide substrate 1 while doping with n-type impurities, for example, nitrogen atoms (N).

[0038] Next, a mask (not shown) having desired openings is formed on the surface of the first n-type drift layer using photolithography, for example, using an oxide film. Then, p-type impurities such as aluminum are ion-implanted into the openings in the oxide film to form a lower first p-type base region (not shown) and a second p-type base region 16. Next, the mask used for ion implantation is removed. Next, a second n-type drift layer (not shown) doped with n-type impurities such as nitrogen is formed on the surface of the first n-type drift layer.

[0039] Next, an ion implantation mask having predetermined openings is formed on the surface of the second n-type drift layer by photolithography, using, for example, an oxide film. Then, p-type impurities such as aluminum are ion-implanted into the openings in the oxide film to form a first upper p-type base region (not shown) that overlaps the first lower p-type base region. The upper and lower first p-type base regions form a continuous region, which becomes first p-type base region 15. Next, the ion implantation mask is removed. The state up to this point is shown in Figure 4.

[0040] Next, a third n-type drift layer (not shown) doped with n-type impurities such as nitrogen is formed on the surface of the second n-type drift layer. The first n-type drift layer, the second n-type drift layer, and the third n-type drift layer are then combined to form the n-type drift layer 2.

[0041] Next, an ion implantation mask having predetermined openings is formed on the surface of the third n-type drift layer using photolithography, using, for example, an oxide film. Then, p-type impurities such as aluminum are ion-implanted into the openings in the oxide film to selectively form p-type base regions 3 in parts of the surface of the third n-type drift layer. Here, the impurities are implanted so that an n-type region remains between the gate insulating film 7 on the sidewall of the trench 5 and the p-type base region 3. Next, the ion implantation mask is removed. The state up to this point is shown in Figure 5.

[0042] Next, a trench-forming mask having a predetermined opening is formed on the surface of the p-type base region 3 by photolithography, using, for example, an oxide film. Next, trenches 5 are formed by dry etching, penetrating the p-type base region 3 and reaching the n-type drift layer 2. The bottom of the trench 5 may reach the second p-type base region 16 formed in the n-type drift layer 2. Next, the trench-forming mask is removed. The n-type region on the sidewall of the trench 5 becomes the n-type region 19. The state up to this point is shown in FIG. 6.

[0043] Next, p-type impurities such as aluminum are ion-implanted obliquely into the p-type base region 3 from the sidewall of the trench 5 to form a channel implantation layer 17. The state up to this point is shown in FIG.

[0044] Next, an ion implantation mask having a predetermined opening is formed by photolithography on the surface of the p-type base region 3. N-type impurities such as nitrogen (N) and phosphorus (P) are ion-implanted into the opening, forming n-type impurities in a part of the surface of the p-type base region 3. + Next, the n-type source region 4 is formed. + The ion implantation mask used for forming the p-type source region 4 is removed, and a new ion implantation mask having a predetermined opening is formed in the same manner. P-type impurities such as boron are ion-implanted into a portion of the surface of the p-type base region 3, forming a p + The p-type contact region 14 is formed. + The impurity concentration of the p-type contact region 14 is set to be higher than the impurity concentration of the p-type base region 3.

[0045] Next, a heat treatment (activation annealing) is performed to activate all the regions formed by ion implantation. For example, the heat treatment (annealing) is performed in an inert gas atmosphere at about 1700° C., and the p-type base region 3, the first p-type base region 15, the second p-type base region 16, and the n + Type source region 4, p +An activation process is performed on the mold contact region 14 and the channel implantation layer 17. As described above, the ion implantation regions may be activated all at once by a single heat treatment, or the heat treatment may be performed each time an ion implantation is performed.

[0046] Next, n + A gate insulating film 7 is formed on the surface of the source region 4 and along the bottom and sidewalls of the trench 5. First, an oxide film is deposited in the trench by a chemical reaction (chemical vapor deposition) such as thermal oxidation or high temperature oxidation (HTO) at a temperature of about 1000°C in an oxygen atmosphere.

[0047] Next, sacrificial oxidation may be performed to round the corners of the bottom and opening of the trench 5. Next, the oxide film is subjected to annealing treatment, thereby forming the gate insulating film 7.

[0048] Next, a polycrystalline silicon layer doped with, for example, phosphorus atoms is provided on the gate insulating film 7. This polycrystalline silicon layer may be formed so as to fill the trench 5. This polycrystalline silicon layer is patterned by photolithography and left inside the trench 5 to form the gate electrode 8.

[0049] Next, an interlayer insulating film such as a BPSG film is deposited so as to cover the gate electrode 8. Next, the interlayer insulating film is patterned to form contact holes, and n + Type source region 4 and p + The n-type contact region 14 is exposed. Next, an n-type contact region 14 is deposited inside the contact hole by, for example, sputtering. + Type source region 4 and p + A source electrode (not shown) is formed so as to contact the mold contact region 14 .

[0050] Next, a back electrode (not shown) is formed over the entire back surface of the semiconductor substrate. Thereafter, the semiconductor wafer is cut (diced) into individual chips, thereby completing the trench MOSFET 100 shown in FIG.

[0051] As described above, according to the embodiment, the area immediately adjacent to the gate insulating film on the sidewall of the trench is an n-type region, and the area adjacent to the gate insulating film on the sidewall of the trench is a p-type region with a higher impurity concentration than the p-type base region. The p-type base region is located at a distance of about 100 nm or more from the gate insulating film on the sidewall of the trench, making the p-type base region highly p-type. This allows the threshold voltage to be increased and leakage to be suppressed without reducing the electron mobility of the channel. Therefore, by increasing the channel mobility while maintaining a high threshold voltage, low on-resistance can be achieved, and conduction loss can be reduced while suppressing malfunctions during switching due to a decrease in threshold voltage.

[0052] The present invention can be modified in various ways without departing from the spirit of the present invention, and in each of the above-described embodiments, for example, the dimensions of each part and the impurity concentration are variously set according to the required specifications, etc. Furthermore, although each of the embodiments has been described in terms of an n-type as the first conductivity type and a p-type as the second conductivity type, the present invention is equally valid even if the first conductivity type is a p-type and the second conductivity type is an n-type. [Industrial Applicability]

[0053] INDUSTRIAL APPLICABILITY As described above, the silicon carbide semiconductor device and method for manufacturing a silicon carbide semiconductor device according to the present invention are useful for power semiconductor devices used in power conversion devices such as inverters, power supply devices for various industrial machines, automobile igniters, and the like. [Explanation of symbols]

[0054] 1, 101 n + Silicon carbide semiconductor substrate 2, 102 n-type drift layer 3, 103 p-type base region 4, 104 n + Type Source Area 5, 105 Trench 7, 107 Gate insulating film 8, 108 gate electrode 14, 114 p. +Mold contact area 15, 115 1st p-type region 16, 116 2nd p-type region 17, 117 Channel implantation layer 19 n-type region 100 Trench MOSFET 118 High concentration p-type region 200, 210 Semiconductor device

Claims

1. a silicon carbide semiconductor substrate of a first conductivity type; a first semiconductor layer of a first conductivity type provided on a front surface of the silicon carbide semiconductor substrate and having a lower impurity concentration than the silicon carbide semiconductor substrate; a first semiconductor region of a second conductivity type provided on a surface of the first semiconductor layer opposite to the silicon carbide semiconductor substrate; a second semiconductor region of a first conductivity type selectively provided in a surface layer of the first semiconductor region on the opposite side to the silicon carbide semiconductor substrate; a trench that penetrates the first semiconductor region and the second semiconductor region and reaches the first semiconductor layer; a gate insulating film provided inside the trench along the bottom and sidewalls of the trench; a gate electrode provided inside the trench and on the inner side of the gate insulating film; a third semiconductor region of the first conductivity type provided between the gate insulating film and the first semiconductor region on a sidewall of the trench; a fourth semiconductor region of a second conductivity type provided between the first semiconductor region and the third semiconductor region and having a higher impurity concentration than the first semiconductor region; Equipped with a fourth semiconductor region having a thickness smaller than that of the first semiconductor region, the fourth semiconductor region having a bottom surface that is in contact with the first semiconductor layer;

2. a width of the third semiconductor region in a direction in which the trenches are arranged is greater than 0 nm and not more than 50 nm; a width of the fourth semiconductor region in a direction in which the trenches are arranged is greater than 10 nm and not more than 200 nm; 2 . The silicon carbide semiconductor device according to claim 1 , wherein the first semiconductor region is spaced 100 nm or more from the gate insulating film on the sidewall of the trench.

3. The impurity concentration of the fourth semiconductor region is 1×10 18 / cm 3 That's all, The impurity concentration of the first semiconductor region is 5×10 16 / cm 3 3. The silicon carbide semiconductor device according to claim 1, wherein the silicon carbide semiconductor device is a silicon carbide semiconductor device.

4. A silicon carbide semiconductor device according to claim 1, wherein the third semiconductor region has the same impurity concentration as the first semiconductor layer.

5. A method of manufacturing a semiconductor device comprising: a first step of forming a first semiconductor layer of a first conductivity type on a front surface of a silicon carbide semiconductor substrate having an impurity concentration lower than that of the silicon carbide semiconductor substrate; a second step of forming a first semiconductor region of a second conductivity type and a third semiconductor region of the first conductivity type on a surface of the first semiconductor layer opposite to the silicon carbide semiconductor substrate; a third step of selectively forming a second semiconductor region of a first conductivity type in a surface layer of the first semiconductor region on an opposite side to the silicon carbide semiconductor substrate; a fourth step of forming a trench that penetrates the first semiconductor region and the second semiconductor region and reaches the first semiconductor layer; a fifth step of forming a fourth semiconductor region of the second conductivity type having a higher impurity concentration than the first semiconductor region by injecting impurities obliquely from a sidewall of the trench; a sixth step of forming a gate insulating film inside the trench along the bottom and sidewalls of the trench; a seventh step of forming a gate electrode inside the trench and on the inner side of the gate insulating film; Including, In the second step, an impurity is implanted so that the third semiconductor region is formed between the gate insulating film on the sidewall of the trench and the first semiconductor region; a fifth step of forming the fourth semiconductor region between the first semiconductor region and the third semiconductor region;

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