Circuit-embedded packaging substrate with exposed side edges and method for manufacturing same

Abstract

To provide a side-exposed embedded trace packaging substrate and a manufacturing method thereof.SOLUTION: The side-exposed embedded trace substrate includes a medium layer, a first circuit layer, and a first circuit layer embedded in the medium layer. An outer surface of the first circuit layer is not higher than a surface of the medium layer, and the first circuit layer includes a pad, where the pad has a cavity to increase a side-exposed area of the pad. An area of contact between the substrate and solder during package welding is increased so that: the welding reliability is enhanced; the problem of poor welding or poor reliability caused by embedding of circuits is avoided; and the problem of poor filling of a packaging material due to an insufficient "gap" between a component and the pad during packaging is resolved.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to the technical field of semiconductor packaging, and more particularly to a circuit-embedded packaging substrate with exposed sides and a method for fabricating the same. [Background technology]

[0002] With the trend of electronic products becoming lighter, thinner, shorter and smaller, traditional wire bonding technology is increasingly unable to meet the demand for more I / O pins, and the application of flip-chip technology, which is compatible with a higher I / O pin count, is becoming more widespread.As an advanced packaging technology, it requires a higher degree of integration of the packaging substrate, and circuit-embedded packaging substrate technology is well suited to this demand. Summary of the Invention [Problem to be solved by the invention]

[0003] In view of this, an object of the present disclosure is to propose a circuit-embedded packaging substrate with exposed sides and a method for manufacturing the same. [Means for solving the problem]

[0004] In accordance with the above objectives, in a first aspect, the present disclosure provides: providing an exposed-side, embedded-circuit packaging substrate including a medium layer and a first circuit layer embedded in the medium layer; The height of the outer surface of the first circuit layer does not exceed the surface of the medium layer, and the first circuit layer includes a pad, the pad having a cavity to increase the exposed area of ​​a side of the pad.

[0005] In some embodiments, the cavity is located at the edge or in the center of the pad.

[0006] In some embodiments, the depth of the cavity is less than the thickness of the first circuit layer, and the pads are used to mount components.

[0007] In some embodiments, the depth of the cavity is equal to the thickness of the first circuit layer, and the pad is used for welding components.

[0008] In some embodiments, the first circuit layer includes a first sublayer and a second sublayer below the first sublayer, the top surface of the first sublayer is flush with the surface of the medium layer, and the cavity exposes the medium layer surrounded by the first sublayer and the second sublayer.

[0009] In a second aspect, an embodiment of the present disclosure includes: (a) providing a substrate, the substrate including a media layer and a first circuit layer embedded in the media layer; (b) applying a first resist layer to the substrate and forming a first window by exposure and development, the first window exposing at least a partial region of a pad of the first circuit layer; (c) etching the first circuit layer exposed by the first window to form a cavity in a portion of the pad; and (d) removing the first resist layer to obtain the circuit-embedded packaging substrate with the exposed side edges.

[0010] In some embodiments, the etching process is selected from an acid etch or an alkaline etch.

[0011] In some embodiments, the first window is located at the edge of the pad or in the center of the pad.

[0012] In some embodiments, the depth of the cavity is less than the thickness of the first circuit layer, and the pad is used to mount a component; or The depth of the cavity is equal to the thickness of the first circuit layer, and the pad is used for welding components.

[0013] In some embodiments, step (a) comprises: (a1) providing a mounting plate; (a2) applying a first anti-coating layer to the support plate, and forming a second window by exposure and development; (a3) electroplating the second window area to form a first sub-layer of the first circuit layer; (a4) applying a second anti-coating layer to the first anti-coating layer and the first sub-layer, and forming a third window by exposure and development, while maintaining the second anti-coating layer corresponding to the exposed side edge of the pad; (a5) electroplating the third window area to form a second sub-layer of the first circuit layer; (a6) removing the first anti-coating layer and the second anti-coating layer; (a7) forming a third anti-coating layer on the support plate and the first circuit layer, and forming a fourth window by exposure and development; (a8) electroplating the fourth window area to form a metal pillar; (a9) removing the third anti-coating layer; (a10) laminating a medium layer and thinning the medium layer until the metal pillars are exposed; (a11) forming a second circuit layer on the medium layer; (a12) removing the placing plate.

[0014] In some embodiments, the projections of the first window area and the third window area on the substrate do not overlap.

[0015] In some embodiments, step (a11) comprises: applying a seed layer to the medium layer; applying a fourth anti-coating layer to the seed layer, and forming a second circuit layer pattern by exposure and development; and electroplating to form the second circuit layer.

[0016] In some embodiments, the support plate includes a first metal layer and a second metal layer, and step (a12) includes: The method includes the step of separating the first metal layer and the second metal layer, and etching the second metal layer that contacts the medium layer. [Effects of the Invention]

[0017] As can be seen from the above description, the circuit-embedded packaging substrate with exposed sides and the method for fabricating the same provided by the present disclosure provides cavities in the pad areas embedded in the first circuit layer of the medium layer, increasing the exposed area of ​​the pad sides, thereby increasing the contact area with the solder of the substrate during packaging welding, improving the reliability of welding, avoiding the problem of poor welding or unreliable welding due to embedded circuits, and solving the problem of insufficient "gap" between the component and the pad during packaging, resulting in poor filling of the packaging material. [Brief explanation of the drawings]

[0018] In order to more clearly explain the technical solutions in the present disclosure or related art, the following briefly introduces drawings used in the description of the embodiments or related art. Needless to say, the drawings described below are merely embodiments of the present disclosure, and those skilled in the art can obtain other drawings from these drawings without performing any novel work. In the drawings, the thickness and shape of some layers and regions may be exaggerated for better understanding and ease of description. [Figure 1]FIG. 1 is a structural schematic diagram of a circuit-embedded packaging substrate with exposed sides provided according to one embodiment of the present disclosure. [Figure 2] FIG. 2 is a structural schematic diagram of a circuit-embedded packaging substrate with exposed sides provided according to another embodiment of the present disclosure. [Figure 3(a)] FIG. 3(a) is a schematic cross-sectional view of an intermediate structure at each step of a method for fabricating a circuit-embedded packaging substrate with an exposed side according to one embodiment of the present disclosure. [Figure 3(b)] FIG. 3(b) is a schematic cross-sectional view of an intermediate structure in each step of a method for fabricating a circuit-embedded packaging substrate with an exposed side according to one embodiment of the present disclosure. [Figure 3(c)] FIG. 3(c) is a schematic cross-sectional view of an intermediate structure in each step of a method for fabricating a circuit-embedded packaging substrate with an exposed side according to an embodiment of the present disclosure. [Figure 3(d)] FIG. 3(d) is a schematic cross-sectional view of an intermediate structure in each step of a method for fabricating a circuit-embedded packaging substrate with an exposed side according to one embodiment of the present disclosure. [Figure 3(e)] FIG. 3(e) is a schematic cross-sectional view of an intermediate structure in each step of a method for fabricating a circuit-embedded packaging substrate with an exposed side according to one embodiment of the present disclosure. [Figure 3(f)] FIG. 3(f) is a schematic cross-sectional view of an intermediate structure in each step of a method for fabricating a circuit-embedded packaging substrate with an exposed side according to one embodiment of the present disclosure. [Figure 4(a)] FIG. 4(a) is a schematic cross-sectional view of an intermediate structure at each step of a method for fabricating a circuit-embedded packaging substrate with exposed sides according to another embodiment of the present disclosure. [Figure 4(b)] FIG. 4(b) is a schematic cross-sectional view of an intermediate structure in each step of a method for fabricating a circuit-embedded packaging substrate with exposed sides according to another embodiment of the present disclosure. [Figure 4(c)] FIG. 4(c) is a schematic cross-sectional view of an intermediate structure in each step of a method for fabricating a circuit-embedded packaging substrate with exposed sides according to another embodiment of the present disclosure. [Figure 4(d)]FIG. 4(d) is a schematic cross-sectional view of an intermediate structure in each step of a method for fabricating a circuit-embedded packaging substrate with exposed sides according to another embodiment of the present disclosure. [Figure 4(e)] FIG. 4(e) is a schematic cross-sectional view of an intermediate structure in each step of a method for fabricating a circuit-embedded packaging substrate with exposed sides according to another embodiment of the present disclosure. [Figure 4(f)] FIG. 4(f) is a schematic cross-sectional view of an intermediate structure in each step of a method for fabricating a circuit-embedded packaging substrate with exposed sides according to another embodiment of the present disclosure. [Figure 4(g)] FIG. 4(g) is a schematic cross-sectional view of an intermediate structure in each step of a method for fabricating a circuit-embedded packaging substrate with exposed sides according to another embodiment of the present disclosure. [Figure 4(h)] FIG. 4(h) is a schematic cross-sectional view of an intermediate structure in each step of a method for fabricating a circuit-embedded packaging substrate with exposed sides according to another embodiment of the present disclosure. [Figure 4(i)] FIG. 4(i) is a schematic cross-sectional view of an intermediate structure at each step in a method for fabricating a circuit-embedded packaging substrate with exposed sides according to another embodiment of the present disclosure. [Figure 4(j)] FIG. 4(j) is a schematic cross-sectional view of an intermediate structure in each step of a method for fabricating a circuit-embedded packaging substrate with exposed sides according to another embodiment of the present disclosure. [Figure 4(k)] FIG. 4( k ) is a schematic cross-sectional view of an intermediate structure in each step of a method for fabricating a circuit-embedded packaging substrate with exposed sides according to another embodiment of the present disclosure. [Figure 4(l)] FIG. 4(l) is a schematic cross-sectional view of an intermediate structure in each step of a method for fabricating a circuit-embedded packaging substrate with exposed sides according to another embodiment of the present disclosure. [Figure 4(m)] FIG. 4(m) is a schematic cross-sectional view of an intermediate structure in each step of a method for fabricating a circuit-embedded packaging substrate with exposed sides according to another embodiment of the present disclosure. [Figure 4(n)]FIG. 4(n) is a schematic cross-sectional view of an intermediate structure in each step of a method for fabricating a circuit-embedded packaging substrate with exposed sides according to another embodiment of the present disclosure. [Figure 4(o)] FIG. 4(o) is a schematic cross-sectional view of an intermediate structure in each step of a method for fabricating a circuit-embedded packaging substrate with exposed sides according to another embodiment of the present disclosure. [Figure 4(p)] FIG. 4(p) is a schematic cross-sectional view of an intermediate structure in each step of a method for fabricating a circuit-embedded packaging substrate with exposed sides according to another embodiment of the present disclosure. [Figure 4(q)] FIG. 4(q) is a schematic cross-sectional view of an intermediate structure in each step of a method for fabricating a circuit-embedded packaging substrate with exposed sides according to another embodiment of the present disclosure. [Figure 4(r)] FIG. 4(r) is a schematic cross-sectional view of an intermediate structure in each step of a method for fabricating a circuit-embedded packaging substrate with exposed sides according to another embodiment of the present disclosure. [Figure 4(s)] FIG. 4(s) is a schematic cross-sectional view of an intermediate structure at each step in a method for fabricating a circuit-embedded packaging substrate with exposed sides according to another embodiment of the present disclosure. [Figure 4(t)] FIG. 4(t) is a schematic cross-sectional view of an intermediate structure at each step of a method for fabricating a circuit-embedded packaging substrate with exposed sides according to another embodiment of the present disclosure. [Figure 4(u)] FIG. 4(u) is a schematic cross-sectional view of an intermediate structure in each step of a method for fabricating a circuit-embedded packaging substrate with exposed sides according to another embodiment of the present disclosure. [Figure 4(v)] FIG. 4(v) is a schematic cross-sectional view of an intermediate structure in each step of a method for fabricating a circuit-embedded packaging substrate with exposed sides according to another embodiment of the present disclosure. [Figure 4(w)] FIG. 4(w) is a schematic cross-sectional view of an intermediate structure in each step of a method for fabricating a circuit-embedded packaging substrate with exposed sides according to another embodiment of the present disclosure. [Figure 4(x)]FIG. 4(x) is a schematic cross-sectional view of an intermediate structure in each step of a method for fabricating a circuit-embedded packaging substrate with exposed sides according to another embodiment of the present disclosure. [Figure 4(y)] FIG. 4(y) is a schematic cross-sectional view of an intermediate structure in each step of a method for fabricating a circuit-embedded packaging substrate with exposed sides according to another embodiment of the present disclosure. [Figure 4(z)] FIG. 4(z) is a schematic cross-sectional view of an intermediate structure at each step of a method for fabricating a circuit-embedded packaging substrate with exposed sides according to another embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0019] Hereinafter, the present disclosure will be described in more detail using specific embodiments and with reference to drawings, so that the objectives, technical solutions and advantages of the present disclosure will be more apparent.

[0020] Unless otherwise defined, technical or scientific terms used in the embodiments of the present disclosure have common meanings understood by those skilled in the art. The terms "first," "second," and similar terms used in the embodiments of the present disclosure do not denote any order, quantity, or importance, but are used to distinguish different components. The term "comprises" or similar terms means that the element or object appearing before the term covers the element or object listed after the term and its equivalents, but does not exclude other elements or objects. Terms such as "top," "bottom," "left," and "right" are used to express only relative positional relationships, and if the absolute position of the object being described changes, the relative positional relationships may change accordingly.

[0021] Embedded trace substrate (ETS) is a packaging substrate that is manufactured based on coreless substrate technology.

[0022] By using Coreless technology, the circuitry on either the outermost side (front or back) is embedded in the media layer, which avoids etching the sidewalls of the circuitry when etching the seed layer later, improving circuit performance. The circuitry also has better flatness than the conventional MSAP and SAP processes, and since the circuitry is embedded in the media layer, it helps reduce the thickness of the substrate.

[0023] However, in conventional embedded circuit boards, all five sides except the front of the circuit on a specific side are embedded in a medium layer. During the packaging welding process, while conventional non-embedded circuits have five sides in contact with the welding material, embedded circuits only have one side in contact with the welding material, which leads to a lack of reliability and a tendency for welding defects to occur due to the influence of shear stress when contacting one side. Furthermore, when passive components must be mounted on pads using surface mounted technology (SMT), insufficient "gap" between the components and pads often prevents the packaging material from flowing through the small gap, resulting in packaging voids.

[0024] In view of this, an exemplary embodiment of the present disclosure provides a circuit-embedded packaging substrate with exposed sides, which combines the advantages of conventional non-embedded circuit boards and embedded circuit boards, and solves the problem of poor welding or unreliability caused by embedding circuits during packaging welding, which is common with conventional coreless embedded circuit packaging technology, and also solves the problem of poor filling of packaging material due to insufficient "gap" between components and pads during packaging.

[0025] Specifically, as shown in FIGS. 1 and 2, the circuit-embedded packaging substrate with exposed sides is The substrate includes a medium layer 301, 412 and a first circuit layer 302, 406 embedded in the medium layer 301, 412, the first circuit layer 302, 406 including a pad (not shown in the figure), the pad including a cavity 305, 420 to increase the exposed area of ​​the side of the pad.

[0026] In the embodiments of the present disclosure, the side of the pad refers to the side perpendicular to the surface direction of the substrate, and does not refer to the outer periphery of the pad.

[0027] In this technical solution, the cavity is used to expose the side of the pad, increasing the contact area between the solder 306 and the pad, thereby avoiding the problem of poor welding or unreliability; the cavity also widens the gap between the pad and the component 307, 421, which allows the packaging material to be fully filled, improving the packaging quality.

[0028] In some embodiments, the cavity is located at the edge (left side of FIG. 1) or the center (right side of FIG. 1, FIG. 2) of the pad. However, the cavity may be located on one side of the pad or on multiple sides of the pad (see FIG. 3(d)), and the present disclosure is not limited in this regard.

[0029] The width and depth of the cavity may be set based on design requirements. In the present disclosure, an example will be described as follows.

[0030] In some embodiments, the depth of the cavity 420 is less than the thickness of the first circuit layer 406, and the pads are used to mount the components 421. Providing the cavity 420 in this manner not only ensures the mounting stability of the mounted components 421, but also meets the need for filling the packaging material and avoids waste of packaging material.

[0031] In some embodiments, as shown in FIG. 1, the depth of cavity 305 is equal to the thickness of first circuit layer 302, and the pads are used to weld components.

[0032] In some embodiments, the first circuit layer 406 includes a first sublayer 4061 and a second sublayer 4062, the surface of the first sublayer 4061 is flush with the surface of the medium layer 412, and the cavity 420 is located in the first sublayer 4061 and its bottom is the medium layer 412.

[0033] An exemplary embodiment of the present disclosure also provides a method for fabricating a circuit-embedded packaging substrate with exposed sides. Figures 3(a) to 3(e) are schematic cross-sectional views of intermediate structures in each step of the method for fabricating a circuit-embedded packaging substrate with exposed sides according to one embodiment of the present disclosure.

[0034] The fabrication method includes the following steps: As shown in Figure 3(a), a substrate 300 is provided (step (a)), where the substrate 300 includes a medium layer 301 and a first circuit layer 302, whose surfaces are flush with each other.

[0035] The number of medium layers included in the substrate 300 is not limited to one, but in the following process, only a substrate including one medium layer will be shown. The present disclosure does not limit the number of layers of the substrate, the thickness of each layer, or the type of material of each layer.

[0036] The substrate 300 may be fabricated using a coreless technique or a conventional CCL build-up technique to form multiple media layers, and methods for interlayer conduction include conduction through copper pillars, conduction through laser drilling, and conduction through machine drilling, but are not limited to these.

[0037] Next, as shown in Figures 3(b) and 3(c), a first resist layer 303 is applied to the substrate, and a first window 304 is formed by exposure and development (step (b)). The first window 304 at least partially overlaps the pad region of the first circuit layer 302. Setting the position of the first window 304 helps ensure that a cavity formed later by etching is located in the pad region, increasing the exposed area of ​​the side of the pad.

[0038] Optionally, the first window 304 is located at the edge of the pad or in the center of the pad.

[0039] Optionally, the process of applying the first resist layer 303 may be to laminate a dry resist film or to apply a resist material, for example, a photoresist material.

[0040] Generally, a resist film layer is applied to both sides of the substrate, and only the circuit-embedded surface is shown in the figures. The resist film layer is applied to the non-embedded surface only to protect the circuit from etching, and no special etching process is performed. This is not a key focus of the examples of this disclosure, so it is not shown.

[0041] Next, as shown in Figure 3(d), the first circuit layer in the first window area is etched to form a cavity 305 (step (c)), where the location of the cavity 305 is the location to be etched. Optionally, the etching process is selected from acid etching or alkaline etching.

[0042] 3(d), the structure at the top right is a plan view of the pad area. Note that the location of the cavity is merely exemplary, and the cavity 305 may be located on one, two, three, or four horizontal sides of the pad depending on design requirements. Of course, the cavity 305 may also be located in the center of the pad.

[0043] Finally, as shown in FIG. 3(e), the first resist layer 303 is removed to obtain a circuit-embedded packaging substrate with exposed sides (step (d)). Those skilled in the art will understand that if resist film layers are applied to both sides of the substrate, the resist film layers on both sides are removed simultaneously. Those skilled in the art may select an appropriate film peeling process according to their needs, and the present disclosure is not limited thereto.

[0044] In some embodiments, the depth of cavity 305 is equal to the thickness of first circuit layer 302, and the pad is used to weld components. As shown in Figure 3(f), the cavity can expose the sides of the pad, and welding at the exposed sides of the pad increases the contact area between the solder 306 and the substrate, while also allowing the solder to vertically encase the substrate circuitry, improving its ability to withstand horizontal shear stress without fracture, i.e., improving the reliability of the weld.

[0045] In addition, by welding the passive component 307 to such a pad, after the component is welded, a "void" will be formed at the bottom of the component, which will be helpful for the packaging resin material to flow and fill in the subsequent packaging process of the substrate, and avoid the technical problem that the "void" is too small, resulting in poor adhesive flow at the bottom of the component.

[0046] 4(a) to 4(y) show schematic cross-sectional views of intermediate structures at each step of a method for fabricating a circuit-embedded packaging substrate with exposed sides according to another embodiment of the present disclosure, and the illustrative embodiment includes a specific method for fabricating the substrate (see FIGS. 4(a) to 4(u)).

[0047] The manufacturing method includes the following steps: As shown in Fig. 4(a), a mounting plate is provided (step (a1)). Note that the mounting plate may have a symmetrical structure on both sides, and Fig. 4(a) shows only the structure on one side.

[0048] The mounting plate includes a mounting plate 401, a first metal layer 402, and a second metal layer 403, where the first metal layer 402 is attached to the mounting plate 401. Optionally, both the first metal layer 402 and the second metal layer 403 can be separated in a physical manner.

[0049] Optionally, the first metal layer 402 is a copper foil having a thickness of 16-20 μm, for example 18 μm, and the second metal layer 403 is a copper foil having a thickness of 2-3 μm.

[0050] Next, as shown in Figures 4(b) and 4(c), a first anti-coating layer 404 is applied to the support substrate, and a second window 405 is formed by exposure and development (step (a2)). Here, the second window 405 exposes the area of ​​the circuit to be electroplated.

[0051] Next, as shown in Figure 4(d), the area of ​​the second window 405 is electroplated to form a first sub-layer 4061 of the first circuit layer (step (a3)). For example, the thickness of the first sub-layer 4061 may be half the thickness of the first circuit layer, or the thickness of the electroplating may be specifically set according to actual needs, and the present disclosure is not limited thereto.

[0052] Next, as shown in Figures 4(e) and 4(f), a second anti-coating layer 407 is applied to the first anti-coating layer 404 and the first sub-layer 4061, and a third window 408 is formed by exposure and development (step (a4)).

[0053] The second anti-coating layer 407 corresponding to the region where the side of the pad is exposed is maintained, so that the second anti-coating layer at that position can be used as an etching barrier layer, thereby accurately controlling the etching depth of the cavity.

[0054] As will be appreciated by those skilled in the art, the third window 408 exposes locations to be subsequently electroplated, meaning that the third window area is smaller than the second window area.

[0055] Next, as shown in FIG. 4(g), the third window area is electroplated to form the second sub-layer 4062 of the first circuit layer (step (a5)).

[0056] Subsequently, as shown in FIG. 4(h), the first anti-coating layer 404 and the second anti-coating layer 407 are removed (step (a6)).

[0057] Next, as shown in Figures 4(i) and 4(j), a third anti-coating layer 409 is formed on the support plate and the first circuit layer, and a fourth window 410 is formed by exposure and development (step (a7)).

[0058] Subsequently, as shown in FIG. 4(k), the fourth window area is electroplated to form metal pillars 411 (step (a8)).

[0059] Next, as shown in FIG. 4(l), the third anti-coating layer 409 is removed (step (a9)).

[0060] Next, as shown in FIGS. 4(m) and 4(n), medium layer 412 is laminated and thinned until metal pillars 411 are exposed (step (a10)).

[0061] The material of the medium layer 412 may be resin coated copper (RCC), resin coated film (RCF), or a resin material that does not contain glass fiber, such as one selected from the group consisting of liquid crystal polymer, bismaleimide triazine (BT) resin, prepreg, Ajinomoto Build-up (ABF) film, epoxy resin, and polyimide resin, but the present invention is not limited thereto.

[0062] Optionally, the process for thinning the media layer 412 is selected from grinding, plasma etching, or sandblasting.

[0063] Next, as shown in FIGS. 4(o) to 4(r), a second circuit layer 416 is formed on the medium layer 412 (step (a11)).

[0064] The surface mounting process has limitations on the thickness of the circuit layer, and if the cavity is too deep or large, it is easy to cause uneven filling. In the embodiment of two-layer electroplating, two anti-coating layers are provided and electroplated twice, so that the medium layer that later replaces the second anti-coating layer can be used as an etching stop layer, thereby allowing the cavity depth to be adjusted through active control according to the flowability requirements of the packaging material.

[0065] In some embodiments, step (a11) includes: As shown in FIG. 4(o), a seed layer 413 is applied to the medium layer 412, where the seed layer 413 can be fabricated by sputtering or chemical vapor deposition. Optionally, the material of the seed layer 413 can be copper or copper+titanium. As shown in FIG. 4(p), a fourth anti-coating layer 414 is then applied to the seed layer 413, and a second circuit layer pattern 415 is formed by exposure and development. Finally, as shown in FIG. 4(r), a second circuit layer 416 is formed by electroplating.

[0066] As can be understood by those skilled in the art, the formation process of each anti-coating layer can be a dry film lamination or a coating, and the present disclosure does not limit the same. The material of each anti-coating layer can be a photoresist material or other organic material, and the present disclosure does not limit the same.

[0067] Illustratively, in the embodiments of the present disclosure, the material of the first circuit layer, the second circuit layer and the metal pillars may be copper.

[0068] Finally, as shown in Figures 4(s) to 4(u), the mounting plate is removed (step (a12)). Now, referring to Figure 4(s), the first metal layer 40 and the second metal layer 403 are separated, and as shown in Figure 4(u), the second metal layer 403 in contact with the medium layer 412 is etched.

[0069] Optionally, the method may further include a step of removing the fourth anti-coating layer 414 before etching the second metal layer 403 in contact with the medium layer 412 (FIG. 4(t)). As will be understood by those skilled in the art, this step may be completed before separating the first metal layer 40 and the second metal layer 403, or may be completed after separating the first metal layer 40 and the second metal layer 403, and the present disclosure is not limited thereto.

[0070] Note that the seed layer 413 is etched at the same time as etching the second metal layer 403. Note that the second metal layer 403 is also used as a seed layer for forming the first circuit layer.

[0071] This results in a substrate 400 after removing the mounting plate, which may be used to fabricate a circuit-embedded packaging substrate with exposed sides.

[0072] Next, referring to the above-mentioned steps (b) to (d), a circuit-embedded packaging substrate with exposed sides is fabricated.

[0073] First, as shown in Figures 4(v) and 4(w), first resist layers 417 and 418 are applied to a substrate 400, and a first window 419 is formed by exposure and development. The first resist layer 418 is used to protect the second circuit layer. Here, the projections of the first window region and the third window region on the substrate do not overlap. By setting this up, the medium layer replacing the second anti-coating layer can be used as an etching barrier layer to control the etching depth of the first window region, thereby achieving effective control of the cavity depth.

[0074] Subsequently, as shown in FIG. 4(x), the first circuit layer in the first window area is etched to form a cavity 420.

[0075] Finally, as shown in FIG. 4(y), the first resist layers 417 and 418 are removed to obtain a circuit-embedded packaging substrate with exposed sides.

[0076] Here, as shown in FIG. 4(z), the depth of the cavity is smaller than the thickness of the first circuit layer, and the pad may be used to mount the component 421, forming a “void” at the bottom of the component, which is helpful for the packaging resin material to flow and fill in the later packaging process of the substrate, and avoids the technical problem that the “void” is too small, resulting in poor adhesive flow at the bottom of the component.

[0077] Those skilled in the art will understand that the description of any of the above embodiments is merely illustrative and does not suggest that the scope of the present disclosure (including claims) is limited to these examples. Within the spirit of the present disclosure, the technical features of the above embodiments or different embodiments can be combined with each other, steps can be performed in any order, and there can be many other variations of different aspects of the above embodiments of the present disclosure, which are not provided in the detailed description for the sake of simplicity.

[0078] The embodiments of the present disclosure are intended to include all such replacements, amendments, and variations that fall within the broad scope of the claims, and therefore, any omissions, amendments, equivalent replacements, improvements, etc. that fall within the spirit and principles of the embodiments of the present disclosure are intended to be included within the scope of the claims of the present disclosure. [Explanation of symbols]

[0079] 40 First metal layer, 300 Substrate, 301 Medium layer, 302 First circuit layer, 303 First resist layer, 304 First window, 305 Cavity, 306 Solder, 307 Passive components, 400 Substrate, 401 Support plate, 402 First metal layer, 403 Second metal layer, 404 First anti-coating layer, 405 Second window, 406 First circuit layer, 407 Second anti-coating layer, 408 Third window, 409 Third anti-coating layer, 410 Fourth window, 411 Metal pillar, 412 Medium layer, 413 Seed layer, 414 Fourth anti-coating layer, 415 Second circuit layer pattern, 416 Second circuit layer, 417 First resist layer, 418 First resist layer, 419 First window, 420 Cavity, 421 Mounted components, 4061 1st sub-layer, 4062 2nd sub-layer

Claims

1. a media layer and a first circuit layer embedded in the media layer; a height of an outer surface of the first circuit layer does not exceed a surface of the medium layer, the first circuit layer includes a pad, and the pad has a cavity to increase an exposed area of ​​a side edge of the pad; A packaging substrate with an exposed side and an embedded circuit, characterized in that the first circuit layer includes a first sublayer and a second sublayer below the first sublayer, the top surface of the first sublayer is flush with the surface of the medium layer, and the cavity exposes the medium layer surrounded by the first sublayer and the second sublayer.

2. The circuit-embedded packaging substrate according to claim 1 , wherein the cavity is located at the edge or the center of the pad.

3. 2. The circuit-embedded packaging substrate according to claim 1, wherein the depth of the cavity is smaller than the thickness of the first circuit layer, and the pads are used to mount components.

4. 2. The circuit-embedded packaging substrate according to claim 1, wherein the depth of the cavity is equal to the thickness of the first circuit layer, and the pad is used for welding components.

5. (a) providing a substrate, the substrate including a media layer and a first circuit layer embedded in the media layer; (b) applying a first resist layer to the substrate and forming a first window by exposure and development, the first window exposing at least a partial region of a pad of the first circuit layer; (c) etching the first circuit layer exposed by the first window to form a cavity in a portion of the pad; and (d) removing the first resist layer to obtain a circuit-embedded packaging substrate having exposed sides.

6. 6. The method of claim 5, wherein the etching process is selected from acid etching and alkaline etching.

7. The method of claim 5 , wherein the first window is located at the edge of the pad or at the center of the pad.

8. the depth of the cavity is less than the thickness of the first circuit layer; or 6. The method of claim 5, wherein the depth of the cavity is equal to the thickness of the first circuit layer.

9. Step (a) (a1) providing a mounting plate; (a2) applying a first anti-coating layer to the support plate, and forming a second window by exposure and development; (a3) electroplating the second window area to form a first sub-layer of the first circuit layer; (a4) applying a second anti-coating layer to the first anti-coating layer and the first sub-layer, and forming a third window by exposure and development, while maintaining the second anti-coating layer corresponding to the exposed side edge of the pad; (a5) electroplating the third window area to form a second sub-layer of the first circuit layer; (a6) removing the first anti-coating layer and the second anti-coating layer; (a7) forming a third anti-coating layer on the support plate and the first circuit layer, and forming a fourth window by exposure and development; (a8) electroplating the fourth window area to form a metal pillar; (a9) removing the third anti-coating layer; (a10) laminating a medium layer and thinning the medium layer until the metal pillars are exposed; (a11) forming a second circuit layer on the medium layer; The method of claim 5, further comprising the step of: (a12) removing the support plate.

10. 10. The method of claim 9, wherein the projections of the first window area and the third window area on the substrate do not overlap.

11. Step (a11) applying a seed layer to the medium layer; applying a fourth anti-coating layer to the seed layer, and forming a second circuit layer pattern by exposure and development; 10. The method of claim 9, further comprising the step of electroplating to form the second circuit layer.

12. The support plate includes a first metal layer and a second metal layer, and step (a12) includes:

10. The method of claim 9, further comprising the step of separating the first metal layer and the second metal layer and etching the second metal layer in contact with the medium layer.

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