Fine-tuned capacitance with fin capacitor design

Abstract

The device includes a main capacitor comprised of a first plate of a first interconnect line (BEOL) metallization layer, a main insulator layer on the first plate, and a second plate on the main insulator layer. The second plate is comprised of a second BEOL metallization layer. The device includes a first tuning capacitor on a first portion of a first BEOL interconnect trace coupled to the first plate of the main capacitor via a first BEOL sideline trace. The first tuning capacitor is comprised of a first insulator layer on a surface and sidewalls of the first portion of the first BEOL interconnect trace. The first tuning capacitor includes a second BEOL interconnect trace on a surface and sidewalls of the first insulator layer. The device includes a first via capture pad coupled by the second BEOL interconnect trace of the first tuning capacitor.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to U.S. Patent Application No. 17 / 149,006, filed January 14, 2021, entitled "CAPACITANCE FINE TUNING BY FIN CAPACITOR DESIGN," the disclosure of which is incorporated herein by reference in its entirety.

[0002] Aspects of the present disclosure relate to semiconductor devices, and more particularly to capacitance tuning using a fin capacitor design. [Background technology]

[0003] Mobile radio frequency (RF) chips (e.g., mobile RF transceivers) are migrating to deep submicron process nodes due to cost and power consumption issues. Mobile RF transceiver designs are further complicated by added circuit functionality to support communication enhancements, such as fifth-generation (5G) new radio (NR) communication systems. Additional design challenges for mobile RF transceivers include the use of passive devices, which directly impacts analog / RF performance issues, including mismatch, noise, and other performance issues.

[0004] Passive devices may include high performance capacitor components. For example, analog integrated circuits use various types of passive devices, such as integrated capacitors. For example, the passive device may be an integrated passive device (IPD). Such integrated capacitors may include metal-oxide-semiconductor (MOS) capacitors, pn-junction capacitors, metal-insulator-metal (MIM) capacitors, poly-poly capacitors, metal-oxide-metal (MOM) capacitors, and other similar capacitor structures.

[0005] Mobile radio frequency (RF) transceiver designs may include metal-insulator-metal (MIM) capacitors. Unfortunately, during operation, the capacitance value of MIM capacitors can vary within RF products such as RF transceivers. There is a need for tuning capacitors that support reduced capacitance adjustment intervals for high-precision applications. Summary of the Invention [Means for solving the problem]

[0006] The device includes a main capacitor comprised of a first plate in a back-end interconnect (BEOL) metallization layer, a main insulator layer on the first plate, and a second plate on the main insulator layer. The second plate is comprised of a second back-end metallization layer. The device includes a first tuning capacitor in a first portion of a first back-end interconnect trace coupled to the first plate of the main capacitor via a first back-end sideline trace. The first tuning capacitor is comprised of a first insulator layer on a surface and sidewalls of the first portion of the first back-end interconnect trace. The first tuning capacitor includes a second back-end interconnect trace on a surface and sidewalls of the first insulator layer. The device includes a first via capture pad coupled by the second back-end interconnect trace of the first tuning capacitor.

[0007] A method for fabricating a main capacitor coupled to a tuning capacitor is described. The method includes forming a first plate of the main capacitor comprised of a first back-end (BEOL) metallization layer. The method also includes depositing a first back-end (BEOL) interconnect trace coupled to the first plate of the main capacitor via a first back-end (BEOL) sideline trace to form the first plate of the tuning capacitor. The method further includes depositing an insulator layer over the first plate of the main capacitor and the first plate of the tuning capacitor. The method also includes depositing a second back-end (BEOL) metallization layer over the insulator layer to form the second plate of the main capacitor, and depositing a second back-end (BEOL) interconnect trace over the insulator layer to form the second plate of the tuning capacitor. The method further includes forming a first via coupled to the second plate of the main capacitor and a via capture pad coupled to the second back-end (BEOL) interconnect trace.

[0008] The foregoing has outlined rather broadly the features and technical advantages of the present disclosure in order that the detailed description that follows may be better understood. Additional features and advantages of the present disclosure are described below. Those skilled in the art will appreciate that this disclosure may readily be utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present disclosure. Those skilled in the art will also realize that such equivalent constructions do not depart from the teachings of the present disclosure as set forth in the appended claims. The novel features believed characteristic of the present disclosure, both as to its organization and method of operation, together with further objects and advantages, will be better understood when the following description is considered in conjunction with the accompanying drawings. It is to be expressly understood, however, that each of the figures is provided for the purpose of illustration and description only and is not intended as a definition of the limits of the present disclosure.

[0009] For a more complete understanding of the present disclosure, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a schematic diagram of a radio frequency front-end (RFFE) module using passive devices. [Figure 2] FIG. 1 is a schematic diagram of a radio frequency front-end (RFFE) module using passive devices in a chipset. [Figure 3] FIG. 1 is a block diagram illustrating a cross-sectional view of an integrated circuit (IC) device including a main capacitor and a tuning capacitor, according to an aspect of the present disclosure. [Figure 4A] FIG. 1 is a block diagram illustrating a radio frequency integrated circuit (RFIC) chip having fin-type tuning capacitors, according to an aspect of the present disclosure. [Figure 4B] FIG. 1 is a block diagram illustrating a radio frequency integrated circuit (RFIC) chip having fin-type tuning capacitors, according to an aspect of the present disclosure. [Figure 4C] FIG. 1 is a block diagram illustrating a radio frequency integrated circuit (RFIC) chip having fin-type tuning capacitors, according to an aspect of the present disclosure. [Figure 5A] FIG. 1 is a plan view illustrating a radio frequency integrated circuit (RFIC) chip having fin-type tuning capacitors according to an embodiment of the present disclosure. [Figure 5B] FIG. 1 is a plan view illustrating a radio frequency integrated circuit (RFIC) chip having fin-type tuning capacitors according to an embodiment of the present disclosure. [Figure 6A] FIG. 1 is a plan view illustrating a radio frequency integrated circuit (RFIC) chip having fin-type tuning capacitors according to an embodiment of the present disclosure. [Figure 6B] FIG. 1 is a plan view illustrating a radio frequency integrated circuit (RFIC) chip having fin-type tuning capacitors according to an embodiment of the present disclosure. [Figure 7A] 4A-4C, which illustrate a process for fabricating the radio frequency integrated circuit (RFIC) chip of FIGS. 4A-4C, including a main capacitor and a fin-type tuning capacitor that is enabled to adjust the tuning capacitance of the main capacitor using via formation, according to an embodiment of the present disclosure. [Figure 7B]4A-4C, which illustrate a process for fabricating the radio frequency integrated circuit (RFIC) chip of FIGS. 4A-4C, including a main capacitor and a fin-type tuning capacitor that is enabled to adjust the tuning capacitance of the main capacitor using via formation, according to an embodiment of the present disclosure. [Figure 7C] 4A-4C, which illustrate a process for fabricating the radio frequency integrated circuit (RFIC) chip of FIGS. 4A-4C, including a main capacitor and a fin-type tuning capacitor that is enabled to adjust the tuning capacitance of the main capacitor using via formation, according to an embodiment of the present disclosure. [Figure 7D] 4A-4C, which illustrate a process for fabricating the radio frequency integrated circuit (RFIC) chip of FIGS. 4A-4C, including a main capacitor and a fin-type tuning capacitor that is enabled to adjust the tuning capacitance of the main capacitor using via formation, according to an embodiment of the present disclosure. [Figure 7E] 4A-4C, which illustrate a process for fabricating the radio frequency integrated circuit (RFIC) chip of FIGS. 4A-4C, including a main capacitor and a fin-type tuning capacitor that is enabled to adjust the tuning capacitance of the main capacitor using via formation, according to an embodiment of the present disclosure. [Figure 7F] 4A-4C, which illustrate a process for fabricating the radio frequency integrated circuit (RFIC) chip of FIGS. 4A-4C, including a main capacitor and a fin-type tuning capacitor that is enabled to adjust the tuning capacitance of the main capacitor using via formation, according to an embodiment of the present disclosure. [Figure 8] FIG. 1 is a process flow diagram illustrating a method for fabricating a main capacitor coupled to a tuning capacitor according to one aspect of the present disclosure. [Figure 9] FIG. 1 is a block diagram illustrating an example wireless communication system in which the configurations of the present disclosure may be advantageously utilized. [Figure 10] 1 is a block diagram illustrating a design workstation used for circuit, layout, and logic design of semiconductor components according to one configuration. DETAILED DESCRIPTION OF THE INVENTION

[0011] The detailed description set forth below with reference to the accompanying drawings is intended as a description of various configurations and does not represent the only configuration in which the concepts described herein may be practiced. The detailed description includes specific details to provide a thorough understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form to avoid obscuring such concepts.

[0012] As described herein, the use of the term "and / or" is intended to mean an "inclusive or," and the use of the term "or" is intended to mean an "exclusive or." As described herein, the term "exemplary" as used throughout this description means "serving as an example, instance, or illustration" and should not necessarily be construed as preferred or advantageous over other exemplary configurations. As described herein, the term "coupled" as used throughout this description means "connected directly or indirectly through an intervening electrical, mechanical, or other connection (e.g., a switch)" and is not necessarily limited to a physical connection. Additionally, a connection may be one in which objects are permanently connected or releasably connected. The connection may be through a switch. As described herein, the term "adjacent" as used throughout this description means "adjacent, in close proximity, next to, or nearby." As described herein, the term "on" as used throughout this description means "directly on" in some configurations and "indirectly on" in other configurations.

[0013] Mobile radio frequency (RF) chips (e.g., mobile RF transceivers) are migrating to deep submicron process nodes due to cost and power consumption issues. Mobile RF transceiver designs are further complicated by added circuit functionality to support communication enhancements, such as fifth-generation (5G) new radio (NR) communication systems. Additional design challenges for mobile RF transceivers include the use of passive devices, which directly impacts analog / RF performance issues, including mismatch, noise, and other performance issues.

[0014] Passive devices in mobile radio frequency (RF) transceivers may include high performance capacitor components. For example, analog integrated circuits use various types of passive devices, such as integrated capacitors. Such integrated capacitors may include metal-oxide-semiconductor (MOS) capacitors, pn-junction capacitors, metal-insulator-metal (MIM) capacitors, poly-poly capacitors, metal-oxide-metal (MOM) capacitors, and other similar capacitor structures. Capacitors are generally passive elements used within integrated circuits to store charge. For example, parallel plate capacitors are often constructed using conductive plates or structures with an insulating material between the plates.

[0015] The amount of storage, or capacitance, for a given capacitor depends on the materials used to make its plates and insulators, the area of ​​the plates, and the spacing between the plates. The insulator material is often a dielectric material. By tailoring the plates and dielectric material, a parallel plate capacitor can be manufactured to exhibit a specified capacitance level. This parallel plate capacitor is fabricated on a semiconductor chip, and many designs place the capacitor on the chip's substrate. Parallel plate capacitors, such as metal-insulator-metal (MIM) capacitors, may be fabricated within active devices or passive devices, such as integrated passive devices (IPDs). Unfortunately, capacitance variations can occur during the integrated circuit (IC) or passive component radio frequency (RF) filter manufacturing process.

[0016] Capacitance variation during an IC or passive component RF filter manufacturing process occurs due to the characteristics of the RF process. That is, due to the RF filter manufacturing process, the actual capacitance value varies between a certain numerical range (e.g., production lot-to-lot variation and / or intra-wafer variation). A tuning capacitor may compensate for the capacitance variation to match a value closer to a specified capacitance value. When this tuning capacitor is manufactured using a via capture pad, the minimum adjustment of the metal-insulator-metal (MIM) capacitance is limited by the minimum capture pad size, which is dictated by the via formation process (e.g., a photo process), which can be very rough.

[0017] Various aspects of the present disclosure use fin capacitor designs to provide metal-insulator-metal (MIM) capacitance tuning. The process flow for fabricating the fin capacitor designs may include substrate-on-line (FEOL) processes, middle-of-line (MOL) processes, and back-of-line (BEOL) processes. It will be understood that the term "layer" includes films and is not to be construed as indicating vertical or horizontal thickness unless otherwise stated. As explained, the term "substrate" may refer to the substrate of a diced wafer or the substrate of an undiced wafer. Similarly, the terms chip and die may be used interchangeably.

[0018] As described, a wiring process interconnect layer may refer to a conductive interconnect layer (e.g., first interconnect layer (M1) or metal 1 (M1), metal 2 (M2), metal 3 (M3), metal 4 (M4), etc.) for electrically coupling to substrate process active devices of an integrated circuit. Various BEOL interconnect layers are formed in corresponding BEOL interconnect layers, with lower BEOL interconnect layers using thinner metal layers relative to upper BEOL interconnect layers. BEOL interconnect layers may be electrically coupled to middle of process (MOL) interconnect layers, for example, connecting M1 to an oxide diffusion (OD) layer of the integrated circuit. The MOL interconnect layers may include a zero interconnect layer (M0) for connecting M1 to an active device layer of the integrated circuit. A BEOL first via (V2) may connect M2 to M3 or another BEOL interconnect layer.

[0019] According to aspects of the present disclosure, an integrated circuit includes a tuning capacitor configured according to a fin-type capacitor design. In one configuration, the integrated circuit includes a metal-insulator-metal (MIM) capacitor. The MIM capacitor includes a first plate configured from a first back-end interconnect (BEOL) metallization layer, an MIM dielectric layer on the first plate, and a second plate configured from a second back-end metallization layer on the MIM dielectric layer. The integrated circuit also includes a first tuning capacitor.

[0020] In one configuration, the tuning capacitor is comprised of a first back-end interconnect (BEOL) layer coupled to a first plate of a metal-insulator-metal (MIM) capacitor. The tuning capacitor includes a first dielectric layer on a first portion of the first BEOL interconnect trace and a sidewall of the first portion of the first BEOL interconnect trace. The tuning capacitor further includes a second BEOL interconnect trace on a surface and a sidewall of the first dielectric layer. The integrated circuit further includes a first via capture pad coupled to the second BEOL interconnect trace. The first via capture pad is located outside a first capacitor region of the first tuning capacitor and the MIM capacitor. The target capacitance is determined by coupling the first via capture pad to a third BEOL metallization layer through a via.

[0021] According to aspects of the present disclosure, the fin-type capacitor design of the tuning capacitor can reduce the effective capacitance area, thereby enabling fine capacitance tuning. The effective capacitance area is defined by the fin width on the first back-end of line (BEOL) metallization layer (M1), the second back-end of line (BEOL) metallization layer (M2), and the minimum fin width is determined by the redistribution layer (RDL) features of the integrated circuit device. In one configuration, the tuning capacitor is configured to support a tuning capacitance step provided by a 5 micrometer (μm) design, with the tuning capacitance step being approximately 0.0078 picofarads (pF) (e.g., 0.3% assuming a 2.58 pF target capacitance).

[0022] FIG. 1 is a schematic diagram of a radio frequency front-end (RFFE) module 100 that uses passive devices including a capacitor 116 (e.g., a fin-type metal-insulator-metal (MIM) tuning capacitor). The RFFE module 100 includes a power amplifier 102, a duplexer / filter 104, and a radio frequency (RF) switch module 106. The power amplifier 102 amplifies a signal to a particular power level for transmission. The duplexer / filter 104 filters the input and output signals according to a variety of different parameters, including frequency, insertion loss, rejection, or other similar parameters. Additionally, the RF switch module 106 may select a particular portion of the input signal to pass to the remainder of the RFFE module 100.

[0023] The radio frequency front-end (RFFE) module 100 also includes tuner circuits 112 (e.g., first tuner circuit 112A and second tuner circuit 112B), a diplexer 190, a capacitor 116, an inductor 118, a ground terminal 115, and an antenna 114. The tuner circuits 112 (e.g., first tuner circuit 112A and second tuner circuit 112B) include components such as a tuner, a portable data entry terminal (PDET), and a housekeeping analog-to-digital converter (HKADC). The tuner circuits 112 may perform impedance tuning (e.g., voltage standing wave ratio (VSWR) optimization) for the antenna 114. The RFFE module 100 also includes a passive combiner 108 coupled to a wireless transceiver (WTR) 120. The passive combiner 108 combines the detected power from the first tuner circuit 112A and the second tuner circuit 112B. The wireless transceiver 120 processes the information from the passive combiner 108 and provides this information to a modem 130 (e.g., a mobile station modem (MSM)). The modem 130 provides a digital signal to an application processor (AP) 140.

[0024] As shown in FIG. 1 , the diplexer 190 is located between the tuner components of the tuner circuit 112 and the capacitor 116 (e.g., a fin-type metal-insulator-metal (MIM) tuning capacitor), the inductor 118, and the antenna 114. The diplexer 190 is disposed between the antenna 114 and the tuner circuit 112 and can provide high system performance from the radio frequency front-end (RFFE) module 100 to a chipset including the wireless transceiver 120, the modem 130, and the application processor 140. The diplexer 190 also performs frequency domain multiplexing for both high-band and low-band frequencies. After the diplexer 190 performs its frequency multiplexing function on the input signal, the output of the diplexer 190 is sent to an optional inductor / capacitor (LC) network including the capacitor 116 and the inductor 118. The LC network may provide additional impedance matching components for the antenna 114, if desired. In that case, a signal having a particular frequency is transmitted or received by antenna 114. Although a single capacitor and inductor are shown, multiple components are also contemplated.

[0025] 2 is a schematic diagram of a radio frequency integrated circuit (RFIC) chip 200 having a wireless local area network (WLAN) (e.g., Wi-Fi) module 170 including a first diplexer 190-1 and a radio frequency front end (RFFE) module 150 including a second diplexer 190-2, including a fin-type metal-insulator-metal (MIM) tuning capacitor, for a chipset 160. The Wi-Fi module 170 includes a first diplexer 190-1 that communicatively couples an antenna 192 to the wireless local area network module (e.g., WLAN module 172). The RFFE module 150 includes a second diplexer 190-2 that communicatively couples an antenna 194 to a wireless transceiver (WTR) 120 via a duplexer 180. Wireless transceiver 120 and WLAN module 172 of Wi-Fi module 170 are coupled to modem (mobile station modem (MSM), e.g., baseband modem) 130, which is powered by power supply 152 via power management integrated circuit (PMIC) 156. Chipset 160 also includes capacitors 162 and 164 and inductor 166 to achieve signal integrity.

[0026] Each of the power management integrated circuit (PMIC) 156, modem 130, wireless transceiver 120, and wireless local area network (WLAN) module 172 includes a capacitor (e.g., 158, 132, 122, and 174) and operates according to a clock 154. Additionally, an inductor 166 couples the modem 130 to the PMIC 156. The design of the radio frequency integrated circuit (RFIC) chip 200 includes a metal-insulator-metal (MIM) capacitor comprising a fin-type MIM tuning capacitor according to an aspect of the present disclosure.

[0027] 3 is a block diagram illustrating a cross-sectional view of an integrated circuit (IC) device 300 including a main capacitor 310 and a tuning capacitor 320 according to an embodiment of the present disclosure. In one configuration, the main capacitor 310 and the tuning capacitor 320 are formed from an interconnect stack of the IC device 300 including multiple back-end (BEOL) metallization layers (M1, M2, M3, ..., Mn) on a semiconductor substrate (e.g., a diced silicon wafer). For example, the main capacitor 310 and the tuning capacitor 320 are metal-insulator-metal (MIM) capacitors. In this example, the main capacitor 310 and the tuning capacitor 320 are formed using plates of the M1 and M2 metallization layers below the metallization layer M3.

[0028] In one configuration, main capacitor 310 includes a first plate 312, an insulator 314 on first plate 312, and a second plate 316 on insulator 314. First plate 312 is formed from metallization layer M1, and second plate 316 is formed from metallization layer M2. Tuning capacitor 320 includes a first plate 322, an insulator 324 on first plate 322, and a second plate 326 on insulator 324. Similar to main capacitor 310, first plate 322 is formed from metallization layer M1, and second plate 326 is formed from metallization layer M2. In particular, the main capacitor 310 and the tuning capacitor 320 share the metallization layer M1 as a first plate (e.g., 312 / 322) and are coupled to the metallization layer M3 350 via the first via 302 and the second via 340, respectively.

[0029] According to an embodiment of the present disclosure, the second plate 326 of the tuning capacitor 320 is configured and sized to operate as a via capture pad. Unfortunately, the minimum size of the second plate 326 configured as a via capture pad in the metallization layer M2 is approximately 30 microns per side of a rectangular pad. In this configuration, the 5 micron width between the via edge and the pad edge of the second plate 326 limits the minimum via size to approximately 20 microns (e.g., using a photo process). Based on this configuration of the second plate 326 (e.g., a 30 x 30 micron pad), the minimum tuning capacitance available from the tuning capacitor 320 is predetermined (e.g., 0.28 picofarads (pF)). Furthermore, the main capacitor 310 is fabricated with a predetermined target capacitance (e.g., 2.69 gigahertz (GHz): 2.58 pF). Based on this predetermined target capacitance of the main capacitor 310, the predetermined minimum tuning capacitance of the tuning capacitor 320 is approximately 11%, which may be too coarse and insufficient for a radio frequency (RF) product such as the radio frequency integrated circuit (RFIC) chip 200 of FIG. 2.

[0030] 4A, 4B, and 4C are block diagrams illustrating a radio frequency integrated circuit (RFIC) chip 400 having a fin-type tuning capacitor according to an embodiment of the present disclosure. Typically, the RFIC chip 400 includes a main capacitor 410 and a tuning capacitor 420 that are selectively enabled to adjust the tuning capacitance of the main capacitor 410 using via formation. For example, the main capacitor 410 and the tuning capacitor 420 are metal-insulator-metal (MIM) capacitors. In this example, the main capacitor 410 and the tuning capacitor 420 are formed using plates of M1 and M2 metallization layers below the metallization layer M3.

[0031] In an embodiment of the present disclosure, tuning capacitor 420 is configured as a fin-type tuning capacitor comprised of a first BEOL interconnect trace 418 coupled to a first plate 412 of main capacitor 410 via a first BEOL sideline trace 428. FIG. 4B shows an exploded view of first tuning capacitor 420-1 of FIG. 4A , including a first insulator layer 424 on a first portion of first BEOL interconnect trace 418. First tuning capacitor 420-1 further includes a second BEOL interconnect trace 432-1 on first insulator layer 424. In this configuration, a cross-sectional view of first tuning capacitor 420-1 includes first plate 422, first insulator layer 424 on first plate 422, and a sidewall of first plate 422. The first tuning capacitor 420-1 further includes a second plate 426 (highlighted) formed from a second BEOL interconnect trace 432-1 on the surface and sidewalls of the first insulator layer 424, completing the formation of the first tuning capacitor 420-1.

[0032] 4A, the radio frequency integrated circuit (RFIC) chip 400 further includes a first via capture pad 430-1 coupled to a second BEOL interconnect trace 432-1. The first via capture pad 430-1 is disposed outside the first capacitor region of the first tuning capacitor 420-1 and the main capacitor 410.

[0033] Referring again to FIG. 4B , the fin-type capacitor design of the first tuning capacitor 420-1 can increase the effective capacitance area, thereby enabling fine capacitance tuning. In one configuration, the effective capacitance area is defined by the fin width 460 (e.g., 2 microns) of the first BEOL interconnect trace 418 and the second BEOL interconnect trace 432-1. Furthermore, the minimum fin width is determined by the redistribution layer (RDL) function of the radio frequency integrated circuit (RFIC) chip 400. In this configuration, the first width W1 of the first insulator layer 424 (e.g., a passivation (silicon nitride) layer) is larger than the fin width 460 of the first BEOL interconnect trace 418. Furthermore, the second width W2 of the first insulator layer 424 is larger than the fin width 470 of the second BEOL interconnect trace 432-1. In one example, the tuning capacitance step provided by a fin width 460 of 5 micrometers (μm) is approximately 0.0078 picofarads (pF) (e.g., assuming a target capacitance of 2.58 pF, the tuning step is 0.3%). The target capacitance is determined by coupling the first via capture pad 430-1 to the metallization layer M3 450 through the second via 440, as shown in FIG. 4C and Table I.

[0034] [Table 1]

[0035] 3, based on this predetermined target capacitance of the main capacitor 310, the predetermined minimum tuning capacitance of the tuning capacitor 320 is approximately 11%, which may be too coarse and insufficient for a radio frequency (RF) product such as the radio frequency integrated circuit (RFIC) chip 200 of FIG. 2. A tuning capacitance step (e.g., 0.28 picofarads (pF)) with an 11% tuning capacitance versus a target capacitance (e.g., 2.58 pF) for a via capture pad (e.g., 30×30 micrometers (μm)) is shown in column 1. Column 2 shows a tuning capacitance step (e.g., 0.031 pF) with a 1.2% tuning capacitance versus a target capacitance for a fin-type tuning capacitor (e.g., 10×10 microns). Column 3 shows the target capacitance for a tuning capacitance step (e.g., 0.0078 pF) with 0.3% tuning capacitance versus a fin-type tuning capacitor (e.g., 5×5 micrometers (μm)). Column 4 shows the target capacitance for a tuning capacitance step (e.g., 0.0012 pF) with 0.05% tuning capacitance versus a fin-type tuning capacitor (e.g., 2×2 μm).

[0036] 4C is a cross-sectional view showing a main capacitor 410 coupled to a first tuning capacitor 420-1 through a metallization layer M3 450. In this configuration, the main capacitor 410 includes a first plate 412, an insulator layer 414 on the first plate 412, and a second plate 416 on the insulator 414. The first plate 412 is formed from metallization layer M1, and the second plate 416 is formed from metallization layer M2. The first tuning capacitor 420-1 includes a first plate 422, a first insulator layer 424 on the first plate 422, and a second plate 426 formed from a second BEOL interconnect trace 432-1 on the first insulator layer 424. Similar to the main capacitor 410, the first plate 422 is formed from metallization layer M1 and the second plate 426 is formed from metallization layer M2. Specifically, the main capacitor 410 and the tuning capacitor 420 share metallization layer M1 as their first plates (e.g., 412 / 422) and are coupled to metallization layer M3 450 via first via 402 and second via 440, respectively. Selective placement of the first via 402 and second via 440 results in a target capacitance level.

[0037] 5A and 5B are plan views illustrating radio frequency integrated circuit (RFIC) chips 500 and 550, respectively, having fin-type tuning capacitors according to an embodiment of the present disclosure. The RFIC chip 500 shown in FIG. 5A is similar to the RFIC chip 400 shown in FIG. 4A and includes the main capacitor 410 and tuning capacitor 420 of FIG. 4A. In this embodiment of the present disclosure, the tuning capacitor 420 is formed on one side of the main capacitor 410 according to a single-side fin configuration. This configuration is beneficial for reducing the footprint of the RFIC chip 500.

[0038] The radio frequency integrated circuit (RFIC) chip 550 shown in FIG. 5B is similar to the RFIC chip 500 shown in FIG. 5A and includes the main capacitor 410 and the tuning capacitor 420. In this aspect of the disclosure, the tuning capacitor 420 is also formed on one side of the main capacitor 410 according to a single-side fin configuration. This configuration provides mixed fin widths along with the single-side fin configuration of FIG. 5A. For example, the widths of the first BEOL interconnect trace 418 and the second BEOL interconnect trace 432 are formed as different widths (e.g., 5 microns or 10 microns). This configuration may be beneficial in enabling various tuning capacitance spacings by using different fin widths, as shown in Table II.

[0039] [Table 2]

[0040] 6A and 6B are plan views illustrating radio frequency integrated circuit (RFIC) chips 600 and 650 having fin-type tuning capacitors, respectively, according to an embodiment of the present disclosure. The RFIC chip 600 shown in FIG. 6A is similar to the RFIC chip 500 shown in FIG. 5A and including the main capacitor 410 and tuning capacitor 420 of FIG. 4A. In this embodiment of the present disclosure, the tuning capacitor 420 is also formed on one side of the main capacitor 410 according to a single-side fin configuration. This configuration may be beneficial for reducing the footprint of the RFIC chip 500 by positioning the via capture pad 430 and the second BEOL interconnect trace 432 orthogonal to the first BEOL sideline trace 428. In particular, this configuration rotates the via capture pad 430 and the second BEOL interconnect trace 432, resulting in a saved area 602 relative to the configuration shown in FIG. 5A.

[0041] The radio frequency integrated circuit (RFIC) chip 650 shown in FIG. 6B is similar to the RFIC chip 550 shown in FIG. 5B and including the main capacitor 410 and tuning capacitor 420 of FIG. 4A. In this embodiment of the disclosure, the tuning capacitor 420 is also formed on one side of the main capacitor 410 according to a single-side fin configuration. In this example, mixed fin widths are also provided to modify the single-side fin configuration of FIG. 5B. Specifically, the widths of the first BEOL interconnect trace 418 and the second BEOL interconnect trace 432 are formed as different widths (e.g., 5 microns or 10 microns). In this configuration, the desired tuning capacitance is configured by fusing the second BEOL interconnect traces 432-1 and 432-2 rather than selectively forming vias as shown in FIG. 5B.

[0042] 7A-7F illustrate a process for fabricating the radio frequency integrated circuit (RFIC) chip of FIGS. 4A-4C including a main capacitor 410 and a tuning capacitor 420 that is selectively enabled to adjust the tuning capacitance of the main capacitor 410 using via formation, according to an embodiment of the present disclosure.

[0043] 7A is a plan view of the first plate 412 of the main capacitor 410 and the first BEOL sideline trace 428 and first BEOL interconnect trace 418 of the tuning capacitor 420 of FIGS. 4A-4C according to an embodiment of the present disclosure. In this configuration, in step 700, the first BEOL interconnect trace 418, first BEOL sideline trace 428, and first plate 412 of the main capacitor 410 are formed from metallization layer M1, for example, as shown in FIG.

[0044] 7B further illustrates fabrication of the main capacitor 410 and tuning capacitor 420 of FIGS. 4A-4C according to an embodiment of the present disclosure. In step 710, as shown in FIGS. 4B and 4C, an insulator layer 414 (e.g., a main insulator layer) is deposited on the first plate 412, and an insulator layer (e.g., a first insulator layer 424) is deposited on predetermined portions of the first BEOL interconnect trace 418 of the tuning capacitor 420. For example, FIG. 4B illustrates an exploded view of the first tuning capacitor 420-1 of FIG. 4A, including the first insulator layer 424 on the first plate 422 and the sidewalls of the first plate 422. In one configuration, the first insulator layer 424 is an insulator layer (e.g., silicon nitride (SiN)).

[0045] 4A-4C in accordance with an embodiment of the present disclosure. In step 720, a metallization layer M2 is deposited on the insulator layer 414 to form the second plate 416 of the main capacitor 410. Further, the metallization layer M2 is deposited on a predetermined portion of the first BEOL interconnect trace 418 on the insulator layer 414 to form the second plate 426 of the tuning capacitor 420.

[0046] For example, FIG. 4B shows an exploded view of the first tuning capacitor 420-1 of FIG. 4A, including a first insulator layer 424 on the first plate 422 and a sidewall of the first plate 422 of the first tuning capacitor 420-1. The first tuning capacitor 420-1 further includes a second plate 426 on the surface and sidewall of the first insulator layer 424. As shown in FIG. 4A, the radio frequency integrated circuit (RFIC) chip 400 further includes a first via capture pad 430-1 coupled to a second BEOL interconnect trace 432. The first via capture pad 430-1, the second BEOL interconnect trace 432, and the second plate 416 of the tuning capacitor 420 may be formed by copper (CU) deposition or CU plating. Although CU deposition is described, other conductive materials are also contemplated for the metallization layer M2.

[0047] 7D further illustrates fabrication of the main capacitor 410 and tuning capacitor 420 of FIGS. 4A-4C in accordance with an embodiment of the present disclosure. In step 730, the main capacitor 410 and tuning capacitor 420 of FIGS. 4A-4C undergo capacitance measurements to determine via locations on the second plate 416 and selected ones of the via capture pads 430.

[0048] 7E further illustrates fabrication of the main capacitor 410 and tuning capacitor 420 of FIGS. 4A-4C according to an embodiment of the present disclosure. In step 740, the first via 402 and the second via 440 are formed at the selected via locations determined in FIG. 7D.

[0049] 7F further illustrates fabrication of the main capacitor 410 and tuning capacitor 420 of FIGS. 4A-4C according to an embodiment of the present disclosure. In step 750, a metallization layer M3 is deposited over the first via 402 and second via 440 formed in FIG. 7E. For example, FIG. 4C shows the main capacitor 410 and tuning capacitor 420-1 sharing metallization layer M1 as a first plate (e.g., 412 / 422) and coupled to metallization layer M3 450 via the first via 402 and second via 440, respectively. Selective placement of the first via 402 and second via 440 results in a target capacitance level, as shown, for example, in FIG.

[0050] FIG. 8 is a process flow diagram illustrating a method for fabricating a main capacitor coupled to a tuning capacitor according to one embodiment of the present disclosure. Method 800 begins at block 802, where a first plate of the main capacitor is formed from a first back-end (BEOL) metallization layer. For example, as shown in FIG. 7A, in step 700, the first plate 412 of the main capacitor 410 is formed from the M1 metallization layer, for example, as also shown in FIG. 4A. In block 804, a first BEOL interconnect trace is deposited and coupled to the first plate of the main capacitor via the first BEOL sideline trace to form the first plate of the tuning capacitor. For example, as shown in FIG. 7A, in step 700, the first BEOL interconnect trace 418 and the first BEOL sideline trace 428 are formed from the M1 metallization layer, for example, as also shown in FIG. 4A.

[0051] In block 806, an insulator layer is deposited on the first plate of the main capacitor and the first plate of the tuning capacitor. As shown in FIG. 7B, in step 710, an insulator layer 414 is deposited on the first plate 412, and a first insulator layer 424 is deposited on a predetermined portion of the first BEOL interconnect trace 418 of the tuning capacitor 420, as also shown in FIGS. 4B and 4C. In block 808, a second BEOL metallization layer is deposited on the insulator layer to form the second plate of the main capacitor, and a second BEOL interconnect trace is deposited on the first plate on the insulator layer to form the second plate of the tuning capacitor. As shown in FIG. 7C, in step 720, an M2 metallization layer is deposited on the insulator layer 414 to form the second plate 416 of the main capacitor 410. Additionally, an M2 metallization layer is deposited on the insulator layer 414 over a predetermined portion of the first BEOL interconnect trace 418 to form the second plate 426 of the tuning capacitor 420 .

[0052] 8, in block 810, a first via is formed and coupled to the second plate of the main capacitor, and a second via is coupled to a via capture pad coupled to a second BEOL interconnect trace. For example, as shown in FIG. 7D, in step 730, the main capacitor 410 and tuning capacitor 420 of FIGS. 4A-4C undergo capacitance measurements to determine via locations on the second plate 416 and selected ones of the via capture pads 430. Further, as shown in FIG. 7E, in step 740, a first via 402 and a second via 440 are formed at the selected via locations determined in FIG. 7D.

[0053] The method 800 may also include forming a second tuning capacitor comprised of the first BEOL interconnect trace coupled to the main capacitor and a second insulator layer on a second portion of the first BEOL interconnect trace and a sidewall of the second portion of the first BEOL interconnect trace. The second tuning capacitor includes the second BEOL interconnect trace on a surface and a sidewall of the second insulator layer. The method 800 may further include forming a second via capture pad coupled to a second capacitor region of the second tuning capacitor and the second BEOL interconnect trace outside the main capacitor.

[0054] According to a further aspect of the present disclosure, an integrated circuit (IC) includes a main capacitor. In one configuration, the IC has means for tuning the main capacitor. In one configuration, the tuning means may be a tuning capacitor 420, as also shown in FIGS. 4B and 4C. In another aspect, the means may be any structure or any material configured to perform the functions recited by the means.

[0055] FIG. 9 is a block diagram illustrating an example wireless communication system 900 in which an aspect of the present disclosure may be advantageously employed. For illustrative purposes, FIG. 9 shows three remote units 920, 930, and 950 and two base stations 940. It will be appreciated that a wireless communication system may have more remote units and base stations. The remote units 920, 930, and 950 include integrated circuit (IC) devices 925A, 925C, and 925B that include the disclosed fin-type tuning capacitors. It will be appreciated that other devices, such as base stations, switching devices, and network equipment, may also include the disclosed fin-type tuning capacitors. FIG. 9 illustrates a forward link signal 980 from the base station 940 to the remote units 920, 930, and 950, and a reverse link signal 990 from the remote units 920, 930, and 950 to the base station 940.

[0056] In FIG. 9 , remote unit 920 is shown as a mobile phone, remote unit 930 is shown as a portable computer, and remote unit 950 is shown as a fixed-location remote unit in a wireless local loop system. For example, the remote units may be portable data units such as mobile phones, handheld personal communications system (PCS) units, personal digital assistants, or other fixed-location data units such as GPS-enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, meter reading equipment, or other devices that store or retrieve data or computer instructions, or combinations thereof. While FIG. 9 illustrates remote units according to embodiments of the present disclosure, the present disclosure is not limited to these exemplary units. Embodiments of the present disclosure may be suitably used in many devices that include the disclosed fin-type tuned capacitors.

[0057] FIG. 10 is a block diagram illustrating a design workstation used for circuit design, layout design, and logic design of semiconductor components, such as the capacitors disclosed above. The design workstation 1000 includes a hard disk 1001 containing operating system software, support files, and design software such as Cadence or OrCAD. The design workstation 1000 also includes a display 1002 to facilitate design of a circuit 1010 or a radio frequency (RF) component 1012, such as a fin-type tuning capacitor. A storage medium 1004 is provided for tangibly storing the design of the circuit 1010 or RF component 1012 (e.g., a fin-type MIM tuning capacitor). The design of the circuit 1010 or RF component 1012 may be stored on the storage medium 1004 in a file format such as GDSII or GERBER. The storage medium 1004 may be a compact disc read-only memory (CD-ROM), a digital versatile disc (DVD), a hard disk, a flash memory, or other suitable device. Additionally, design workstation 1000 includes a drive 1003 for accepting input from or writing output to storage medium 1004 .

[0058] The data recorded on the storage medium 1004 may specify logic circuit configurations, pattern data for photolithography masks, or mask pattern data for continuous write tools such as electron beam lithography. The data may also include logic verification data such as timing diagrams and net circuits associated with logic simulations. Providing the data on the storage medium 1004 facilitates the design of the circuit 1010 or radio frequency (RF) component 1012 by reducing the number of processes for designing a semiconductor wafer.

[0059] The following numbered clauses describe example implementations. 1. A device comprising: a main capacitor having a first plate comprised of a first back-end interconnect (BEOL) metallization layer, a main insulator layer on the first plate, and a second plate on the main insulator layer comprised of a second BEOL metallization layer; a first tuning capacitor having a first portion of a first BEOL interconnect trace coupled to the first plate of the main capacitor via a first BEOL sideline trace; a first insulator layer on a surface and sidewalls of the first portion of the first BEOL interconnect trace; and a second BEOL interconnect trace on a surface and sidewalls of the first insulator layer; and a first via capture pad coupled to the second BEOL interconnect trace of the first tuning capacitor. 2. The device of clause 1, wherein the first BEOL interconnect trace is orthogonal to the second BEOL interconnect trace. 3. A device described in any one of clauses 1 to 2, wherein the first BEOL interconnect trace is coupled to one side of the first plate of the main capacitor via a first BEOL sideline trace. 4. A device described in any one of clauses 1 to 3, further comprising a second tuning capacitor comprising a second portion of the first BEOL interconnect trace, a second insulator layer on the surface and sidewalls of the second portion of the first BEOL interconnect trace, and a third BEOL interconnect trace on the surface and sidewalls of the second insulator layer, and a second via capture pad coupled to the third BEOL interconnect trace of the second tuning capacitor. 5. The device of clause 4, wherein the width of the third BEOL interconnect trace of the second tuning capacitor is greater than the width of the second BEOL interconnect trace of the first tuning capacitor. 6. A device described in any one of clauses 4 to 5, wherein the width of the second portion of the first BEOL interconnect trace of the second tuning capacitor is greater than the width of the first portion of the first BEOL interconnect trace of the first tuning capacitor. 7. The device of any one of clauses 4 to 6, further comprising: a first via coupled to a second plate of the main capacitor; a second via coupled to the second via capture pad; and a third BEOL metallization layer over the first via and the second via. 8. The device described in any one of clauses 1 to 6, further comprising: a first via coupled to a second plate of the main capacitor; a second via coupled to the first via capture pad; and a third BEOL metallization layer over the first via and the second via. 9. A device described in any one of clauses 1 to 8, wherein the first width of the first insulator layer is greater than the width of a first portion of a first BEOL interconnect trace of the first tuning capacitor, and the second width of the first insulator layer is greater than the width of a second BEOL interconnect trace of the first tuning capacitor. 10. A device according to any one of clauses 1 to 9, wherein the device comprises an integrated circuit (IC). 11. A device according to any one of clauses 1 to 9, wherein the device comprises an integrated passive device (IPD). 12. The device of clause 11, wherein the IPD comprises a radio frequency (RF) filter. 13. A device according to any one of clauses 11 to 12, wherein the IPD is integrated into a radio frequency (RF) module. 14. A method for fabricating a main capacitor coupled to a tuning capacitor, the method comprising: forming a first plate of the main capacitor comprised of a first back-end (BEOL) metallization layer; depositing a first BEOL interconnect trace coupled to the first plate of the main capacitor via a first BEOL sideline trace to form the first plate of the tuning capacitor; depositing an insulator layer on the first plate of the main capacitor and the first plate of the tuning capacitor; depositing a second BEOL metallization layer on the insulator layer to form the second plate of the main capacitor; and depositing a second BEOL interconnect trace on the insulator layer to form the second plate of the tuning capacitor; and forming a first via coupled to the second plate of the main capacitor and a via capture pad coupled to the second BEOL interconnect trace. 15. The method of clause 14, wherein the tuning capacitor comprises: a first tuning capacitor comprising a first portion of a first BEOL interconnect trace, a first insulator layer on a surface and sidewalls of the first portion of the first BEOL interconnect trace, and a second BEOL interconnect trace on a surface and sidewalls of the first insulator layer; a first via capture pad coupled to the second BEOL interconnect trace of the first tuning capacitor; a second tuning capacitor comprising a second portion of the first BEOL interconnect trace, a second insulator layer on a surface and sidewalls of the second portion of the first BEOL interconnect trace, and a third BEOL interconnect trace on a surface and sidewalls of the second insulator layer; and a second via capture pad coupled by the third BEOL interconnect trace of the second tuning capacitor. 16. The method of clause 15, wherein a width of the third BEOL interconnect trace of the second tuning capacitor is greater than a width of the second BEOL interconnect trace of the first tuning capacitor. 17. The method of any one of clauses 15 to 16, wherein the width of the second portion of the first BEOL interconnect trace of the second tuning capacitor is greater than the width of the first portion of the first BEOL interconnect trace of the first tuning capacitor. 18. The method of any one of clauses 15 to 17, further comprising forming a first via coupled to a second plate of the main capacitor, forming a second via coupled to the first via capture pad, and forming a third BEOL metallization layer over the first via and the second via. 19. The method of any one of clauses 15 to 17, further comprising forming a first via coupled to a second plate of the main capacitor, forming a second via coupled to a second via capture pad, and forming a third BEOL metallization layer over the first via and the second via. 20. The method of any one of clauses 15 to 19, wherein the first width of the first insulator layer is greater than the width of a first portion of a first BEOL interconnect trace of the first tuning capacitor, and the second width of the first insulator layer is greater than the width of a second BEOL interconnect trace of the first tuning capacitor.

[0060] For a firmware and / or software implementation, methods may be implemented with modules (e.g., procedures, functions, etc.) that perform the functions described herein. Machine-readable media tangibly embodying instructions may be used in implementing the methods described herein. For example, software code may be stored in a memory and executed by a processor unit. The memory may be implemented within the processor unit or external to the processor unit. The term "memory," as used herein, may refer to long-term memory, short-term memory, volatile memory, non-volatile memory, or other types of memory, and is not limited to a specific type or number of memories or the type of medium on which the memory is stored.

[0061] When implemented in firmware and / or software, the functions may be stored as one or more instructions or code on a computer-readable storage medium. Examples include computer-readable storage media encoded with data structures and computer-readable storage media encoded with a computer program. A computer-readable storage medium includes a physical computer storage medium. A storage medium may be any available medium that can be accessed by a computer. By way of example, and not limitation, such computer-readable storage media may include random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD-ROM) or other optical disk storage, magnetic disk storage or other magnetic storage devices, or other medium that can be used to store desired program code in the form of instructions or data structures and that can be accessed by a computer. As used herein, disk and disc include compact discs (CDs), laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray® discs, where disks typically reproduce data magnetically and discs reproduce data optically using lasers. Combinations of the above should also be included within the scope of computer-readable recording media.

[0062] In addition to storage on a computer-readable recording medium, the instructions and / or data may be provided as signals on a transmission medium included in a communications device. For example, a communications device may include a transceiver having signals representing the instructions and data. The instructions and data are configured to cause one or more processors to perform the functions outlined in the claims.

[0063] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alterations can be made therein without departing from the technology of the present disclosure, as defined by the appended claims. For example, relative terms such as "top" and "bottom" are used in reference to a substrate or an electronic device. Of course, if the substrate or electronic device is inverted, top becomes bottom and bottom becomes top. Additionally, if in a landscape orientation, top and bottom may refer to the sides of the substrate or electronic device. Moreover, the scope of the present application is not intended to be limited to the particular configurations of processes, machines, manufacture, compositions of matter, means, methods, and steps described herein. As one skilled in the art will readily appreciate from this disclosure, any existing or later-developed processes, machines, manufacture, compositions of matter, means, methods, or steps that perform substantially the same function or achieve substantially the same results as the corresponding configurations described herein may be utilized in accordance with the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.

[0064] Those skilled in the art will further appreciate that the various illustrative logic blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability between hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends on the particular application and design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

[0065] The various illustrative logic blocks, modules, and circuits described in connection with the disclosure herein may be implemented or performed using a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof, designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but alternatively, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

[0066] The steps of a method or algorithm described in connection with the present disclosure may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in random access memory (RAM), flash memory, read-only memory (ROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, a hard disk, a removable disk, a compact disk read-only memory (CD-ROM), or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. Alternatively, the storage medium may be integral to the processor. The processor and the storage medium may reside in an application-specific integrated circuit (ASIC). The ASIC may reside in a user terminal. Alternatively, the processor and the storage medium may reside as discrete components in a user terminal.

[0067] In one or more exemplary designs, the functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted via a computer-readable medium as one or more instructions or code. Computer-readable media includes both computer storage media and communication media, including any medium that facilitates transfer of a computer program from one place to another. Storage media may be any available medium that can be accessed by a general-purpose computer or a special-purpose computer. By way of example, and not limitation, such computer-readable media may include random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD-ROM) or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium used to carry or store program code means specified in the form of instructions or data structures and that can be accessed by a general-purpose computer or a special-purpose computer or a general-purpose or special-purpose processor. Additionally, any connection may be properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium.As used herein, disk and disc include compact discs (CDs), laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray® discs, where disks typically reproduce data magnetically and discs reproduce data optically using lasers. Combinations of the above should also be included within the scope of computer-readable recording media.

[0068] The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications of the disclosure will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein. [Explanation of symbols]

[0069] 100 Radio Frequency Front End (RFFE) Modules 102 Power Amplifier 104 Duplexer / Filter 106 Radio Frequency (RF) Switch Module 108 Passive Combiner 112 Tuner circuit 112A First Tuner Circuit 112B Second Tuner Circuit 114 Antenna 115 Ground terminal 116 Capacitor 118 Inductor 120 Wireless Transceiver 122 Capacitor 130 Modem 132 Capacitor 140 Application Processor (AP) 150 Radio Frequency Front End (RFFE) Modules 152 Power supply 154 Clock 156 Power Management Integrated Circuit (PMIC) 158 Capacitor 160 chipset 162, 164 Capacitor 166 Inductor 170 Wireless Local Area Network (WLAN) Module, Wi-Fi Module 172 WLAN Module 174 Capacitor 180 Duplexer 190 Diplexer 190-1 First diplexer 190-2 Second diplexer 192 Antenna 194 Antenna 200 Radio Frequency Integrated Circuit (RFIC) Chips, Diplexers 300 Integrated Circuit (IC) Devices 310 Main Capacitor 312 First Plate 314 Insulators 316 Second Plate 320 Tuning Capacitor 322 First Plate 324 Insulators 326 Second Plate 340 Second Via 350 metallization layers 400 Radio Frequency Integrated Circuit (RFIC) Chips 402 First Via 410 Main Capacitor 412 First Plate 414 Insulator Layer 416 Second Plate 418 interconnection traces 420 Tuning Capacitor 420-1 First tuning capacitor 422 First Plate 424 First Insulator Layer 426 Second Plate 428 First BEOL Interconnect Trace 430 Via Capture Pad 430-1 First via capture pad 432, 432-1, 432-2 Second BEOL interconnect traces 440 Second Via 450 metallization layers 460 fin width 470 fin width 500, 550 Radio Frequency Integrated Circuit (RFIC) Chips 600, 650 Radio Frequency Integrated Circuit (RFIC) Chips 602 Reserved Area 900 Wireless Communication System 920, 930, 950 Remote Units 925A, 925B, 925C Integrated Circuit (IC) Devices 940 base station 980 forward link signal 990 reverse link signal 1000 Design Workstations 1001 Hard Disk 1002 Display 1003 Drive unit 1004 Storage medium 1010 Circuit 1012 RF Components M0 Zero Interconnect Layer M1 First interconnect layer, metal 1 M2 metal 2 M3 metal 3 M4 metal 4 V2 BEOL 1st via

Claims

1. a main capacitor comprising a first plate constructed from a first wiring step, BEOL, metallization layer, a main insulator layer on the first plate, and a second plate constructed from a second BEOL metallization layer on the main insulator layer; a first tuning capacitor comprising: first portions of first BEOL interconnect traces coupled to the first plate of the main capacitor via first BEOL sideline traces, each of the first BEOL sideline traces extending perpendicularly in the plane of the first plate to the first portions of the first BEOL interconnect traces; a first insulator layer on a surface and sidewalls of the first portions of the first BEOL interconnect traces; and a second BEOL interconnect trace on a surface and sidewalls of the first insulator layer; a first via capture pad coupled to the second BEOL interconnect trace of the first tuning capacitor.

2. The device of claim 1 , wherein the first BEOL interconnect trace is orthogonal to the second BEOL interconnect trace.

3. The device of claim 1 , wherein the first BEOL interconnect trace is coupled to one side of the first plate of the main capacitor via the first BEOL sideline trace.

4. a second tuning capacitor comprising a second portion of the first BEOL interconnect trace, a second insulator layer on a surface and sidewalls of the second portion of the first BEOL interconnect trace, and a third BEOL interconnect trace on a surface and sidewalls of the second insulator layer; a second via capture pad coupled to the third BEOL interconnect trace of the second tuning capacitor.

5. 5. The device of claim 4, wherein a width of the third BEOL interconnect trace of the second tuning capacitor is greater than a width of the second BEOL interconnect trace of the first tuning capacitor.

6. a width of the second portion of the first BEOL interconnect trace of the second tuning capacitor is greater than a width of the first portion of the first BEOL interconnect trace of the first tuning capacitor; or a first via coupled to the second plate of the main capacitor; a second via coupled to the second via capture pad; 5. The device of claim 4, further comprising a third BEOL metallization layer over the first via and the second via.

7. a first via coupled to the second plate of the main capacitor; a second via coupled to the first via capture pad; 10. The device of claim 1, further comprising: a third BEOL metallization layer over the first via and the second via.

8. 2. The device of claim 1, wherein a first width of the first insulator layer is greater than a width of the first portion of the first BEOL interconnect trace of the first tuning capacitor, and a second width of the first insulator layer is greater than a width of the second BEOL interconnect trace of the first tuning capacitor.

9. The device of claim 1 , wherein the device comprises an integrated circuit (IC).

10. The device of claim 1 , wherein the device comprises an integrated passive device (IPD).

11. The device of claim 10 , wherein the integrated passive device (IPD) comprises a radio frequency (RF) filter or the IPD is integrated into a radio frequency (RF) module.

12. 1. A method for manufacturing a main capacitor coupled to a tuning capacitor, comprising: forming a first plate of the main capacitor comprised of a first interconnect step, back-end-of-line (BEOL), and metallization layer; depositing first BEOL interconnect traces to form first plates of the tuning capacitors coupled to the first plates of the main capacitors via first BEOL sideline traces, each of the first BEOL sideline traces extending perpendicular to the first plates of the tuning capacitors in the plane of the first plates; depositing an insulator layer on the first plate of the main capacitor and the first plate of the tuning capacitor; depositing a second BEOL metallization layer on the insulator layer to form a second plate of the main capacitor, and depositing a second BEOL interconnect trace on the insulator layer to form a second plate of the tuning capacitor; forming a first via coupled to the second plate of the main capacitor, and forming a second via coupled to a via capture pad coupled to the second BEOL interconnect trace.

13. The tuning capacitor is a first tuning capacitor comprising a first portion of the first BEOL interconnect trace, a first insulator layer on a surface and sidewalls of the first portion of the first BEOL interconnect trace, and a second BEOL interconnect trace on a surface and sidewalls of the first insulator layer; a first via capture pad coupled to the second BEOL interconnect trace of the first tuning capacitor; a second tuning capacitor comprising a second portion of the first BEOL interconnect trace, a second insulator layer on a surface and sidewalls of the second portion of the first BEOL interconnect trace, and a third BEOL interconnect trace on a surface and sidewalls of the second insulator layer; a second via capture pad coupled to the third BEOL interconnect trace of the second tuning capacitor.

14. 14. The method of claim 13, wherein a width of the third BEOL interconnect trace of the second tuning capacitor is greater than a width of the second BEOL interconnect trace of the first tuning capacitor.

15. a width of the second portion of the first BEOL interconnect trace of the second tuning capacitor is greater than a width of the first portion of the first BEOL interconnect trace of the first tuning capacitor; or forming a second via coupled to the first via capture pad; forming a third BEOL metallization layer on the first via and the second via, or forming a second via coupled to the second via capture pad; forming a third BEOL metallization layer on the first via and the second via, or 14. The method of claim 13, wherein a first width of the first insulator layer is greater than a width of the first portion of the first BEOL interconnect trace of the first tuning capacitor, and a second width of the first insulator layer is greater than a width of the second BEOL interconnect trace of the first tuning capacitor.

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