Nonvolatile memory device and method of operating the same

Abstract

To provide a non-volatile memory device and an operating method thereof having improved performance and improved reliability by minimizing noise effects due to a common source line.SOLUTION: A non-volatile memory device according to the present invention includes: a plurality of bit lines connected to a plurality of cell strings; a common source line connected to the plurality of cell strings; at least one dummy bit line provided between the plurality of bit lines and the common source line; a control logic circuit configured to generate at least one dummy bit line drive signal in response to a command from an external device; and a dummy bit line driver configured to selectively provide a first voltage to the at least one dummy bit line in response to the at least one dummy bit line drive signal.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to semiconductor memories, and more particularly to non-volatile memory devices and methods of operating the same. [Background technology]

[0002] Semiconductor memories can be divided into volatile memory devices such as SRAM and DRAM, in which stored data disappears when the power supply is cut off, and non-volatile memory devices such as flash memory, PRAM, MRAM, ReRAM, and FeRAM, in which stored data is retained even when the power supply is cut off.

[0003] During a read operation, a flash memory device reads data stored in a memory cell by sensing a voltage change on a bit line connected to the memory cell. At this time, a current flows through a common source line connected to the memory cell, and noise due to the current on the common source line flows into the bit line. In this case, the voltage on the bit line is affected by the noise due to the current on the common source line, thereby reducing the reliability of the flash memory device. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Korean Patent Registration No. 10-1374338 [Patent Document 2] U.S. Patent No. 9,634,023 [Patent Document 3] U.S. Patent No. 9,035,371 [Patent Document 4] U.S. Patent No. 10,573,659 [Patent Document 5] U.S. Patent No. 10,546,814 [Patent Document 6] U.S. Patent No. 9,431,415 [Patent Document 7] US Patent Application Publication No. 2009 / 0124072 [Patent Document 8] US Patent Application Publication No. 2019 / 0267333 [Patent Document 9] US Patent Application Publication No. 2020 / 0219898 Summary of the Invention [Problem to be solved by the invention]

[0005] The present invention has been made in consideration of the above-mentioned conventional problems, and an object of the present invention is to provide a nonvolatile memory device and an operating method thereof that minimize the influence of noise due to a common source line. [Means for solving the problem]

[0006] In order to achieve the above object, according to one aspect of the present invention, a nonvolatile memory device includes a plurality of bit lines connected to a plurality of cell strings, a common source line connected to the plurality of cell strings, at least one dummy bit line provided between the plurality of bit lines and the common source line, a control logic circuit configured to generate at least one dummy bit line driving signal in response to a command from an external device, and a dummy bit line driver configured to selectively provide a first voltage to the at least one dummy bit line in response to the at least one dummy bit line driving signal.

[0007] According to another aspect of the present invention, which has been made to achieve the above object, a nonvolatile memory device includes a peripheral circuit formed on a semiconductor substrate, a memory cell array formed on the peripheral circuit and including a plurality of cell strings, and a metal layer formed on the memory cell array, the metal layer including a plurality of bit lines connected to the plurality of cell strings, a common source line connected to the plurality of cell strings, and at least one dummy bit line provided between the plurality of bit lines and the common source line, and the peripheral circuit includes a control logic circuit configured to generate at least one dummy bit line driving signal in response to a command from an external circuit, and a dummy bit line driver configured to selectively provide a first voltage to the at least one dummy bit line in response to the at least one dummy bit line driving signal.

[0008] In order to achieve the above object, according to one aspect of the present invention, a method for operating a nonvolatile memory device includes receiving a read command from an external device; applying a first voltage to at least one dummy bit line located between a plurality of bit lines and a common source line in response to the read command; performing a read operation in response to the read command; receiving an erase command from the external device; floating the at least one dummy bit line, electrically connecting the at least one dummy bit line to the common source line, or applying an erase voltage to the at least one dummy bit line in response to the erase command; and performing an erase operation in response to the erase command. [Effects of the Invention]

[0009] According to the nonvolatile memory device of the present invention, by controlling the voltage of the dummy bit line adjacent to the common source line, noise due to the current of the common source line can be prevented from flowing into the bit line, and the time required for the common source line or the bit line to reach the erase voltage during an erase operation can be shortened. Therefore, a nonvolatile memory device and an operating method thereof having improved performance and reliability can be provided. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a block diagram illustrating a nonvolatile memory device according to an embodiment of the present invention; [Figure 2] 2 is a circuit diagram showing an example of one memory block BLK among a plurality of memory blocks included in the memory cell array of FIG. 1. FIG. [Figure 3] FIG. 2 is a perspective view schematically illustrating the nonvolatile memory device of FIG. [Figure 4] 4 is a cross-sectional view showing the nonvolatile memory device taken along line B in FIG. 3. [Figure 5] 4 is a cross-sectional view showing the nonvolatile memory device taken along line A in FIG. 3. [Figure 6] 4 is a plan view showing a cell core region in the metal layer of FIG. 3. FIG. [Figure 7] 6 is a plan view showing a third contact region in the metal layer of FIG. 5. FIG. [Figure 8] FIG. 2 is a circuit diagram showing a dummy bit line driver of FIG. [Figure 9] 9 is a timing diagram illustrating a first dummy bit line driving signal provided to the dummy bit line driver of FIG. 8; [Figure 10A] 10 is a diagram for explaining the levels of the bit lines, dummy bit lines, and common source line CSL according to the timing diagram of FIG. 9. FIG. [Figure 10B] 10 is a diagram for explaining the levels of the bit lines, dummy bit lines, and common source line CSL according to the timing diagram of FIG. 9. FIG. [Figure 10C]10 is a diagram for explaining the levels of the bit lines, dummy bit lines, and common source line CSL according to the timing diagram of FIG. 9. FIG. [Figure 11A] FIG. 2 is a diagram illustrating a dummy bit line driver of FIG. [Figure 11B] FIG. 2 is a diagram illustrating a dummy bit line driver of FIG. [Figure 12] 11C is a timing diagram illustrating the first and second dummy bit line driving signals of FIG. 11A or FIG. 11B. [Figure 13A] 13 is a diagram for explaining the levels of the bit line, the dummy bit line, and the common source line according to the timing diagram of FIG. 12. FIG. [Figure 13B] 13 is a diagram for explaining the levels of the bit line, the dummy bit line, and the common source line according to the timing diagram of FIG. 12. FIG. [Figure 13C] 13 is a diagram for explaining the levels of the bit line, the dummy bit line, and the common source line according to the timing diagram of FIG. 12. FIG. [Figure 14] 11C is a timing diagram illustrating the first and second dummy bit line driving signals of FIG. 11A or FIG. 11B. [Figure 15A] 10A and 10B are diagrams illustrating a method of controlling a dummy bit line according to an embodiment of the present invention; [Figure 15B] 10A and 10B are diagrams illustrating a method of controlling a dummy bit line according to an embodiment of the present invention; [Figure 16] 1 illustrates an example of a nonvolatile memory device including a plurality of dummy bit line drivers according to an embodiment of the present invention; [Figure 17] 2 is a flowchart showing the operation of the nonvolatile memory device of FIG. [Figure 18A] 1 is a timing diagram illustrating an operation of a nonvolatile memory device according to an embodiment of the present invention; [Figure 18B] 1 is a timing diagram illustrating an operation of a nonvolatile memory device according to an embodiment of the present invention; [Figure 19]14 illustrates an example of a memory device 1400 according to an embodiment of the present invention. [Figure 20] 1A to 1C are diagrams illustrating various stacked structures of a nonvolatile memory device according to an embodiment of the present invention; [Figure 21] 1A to 1C are diagrams illustrating various stacked structures of a nonvolatile memory device according to an embodiment of the present invention; [Figure 22] 1A to 1C are diagrams illustrating various stacked structures of a nonvolatile memory device according to an embodiment of the present invention; [Figure 23] 1 is a block diagram illustrating a memory system according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, specific examples of embodiments of the present invention will be described in detail with reference to the drawings.

[0012] 1 is a block diagram illustrating a nonvolatile memory device according to an embodiment of the present invention. Referring to FIG. 1, the nonvolatile memory device 100 includes a memory cell array 110, an address decoder 120, a page buffer circuit 130, an input / output (I / O) circuit 140, a control logic and voltage generation circuit (control logic circuit) 150, and a dummy bit line (DBL) driver 160. In one embodiment, components other than the memory cell array 110, such as the address decoder 120, the page buffer circuit 130, the input / output (I / O) circuit 140, the control logic and voltage generation circuit 150, and the dummy bit line driver 160, are included in a peripheral circuit PERI. In one embodiment, the nonvolatile memory device 100 has a cell-on-peripheral (COP) or CMOS-under-array (CUA) structure in which the memory cell array 110, a memory cell structure, or a memory cell region is stacked on top of the peripheral circuit PERI (or peripheral circuit region).

[0013] The memory cell array 110 includes a plurality of memory blocks. Each of the memory blocks includes a plurality of cell strings, each of which is connected to a plurality of bit lines BL. Each of the cell strings includes a plurality of serially connected cell transistors. The cell transistors are connected to a string select line SSL, a word line WL, and a ground select line GSL.

[0014] The address decoder 120 is connected to the memory cell array 110 via string select lines SSL, word lines WL, and ground select lines GSL. The address decoder 120 receives an address ADDR from an external device (e.g., a memory controller) and decodes the received address ADDR. The address decoder 120 controls or drives the string select lines SSL, word lines WL, and ground select lines GSL based on the decoded address ADDR.

[0015] The page buffer circuit 130 is connected to the memory cell array 110 via bit lines BL. The page buffer circuit 130 senses voltage changes on the bit lines BL to read data stored in memory cells of the memory cell array 110. The page buffer circuit 130 provides the read data to the input / output circuit 140. The page buffer circuit 130 is configured to temporarily store data DATA received via the input / output circuit 140. The page buffer circuit 130 controls or drives the bit lines BL based on the temporarily stored data DATA.

[0016] The input / output circuit 140 exchanges data DATA with an external device (e.g., a memory controller). The input / output circuit 140 transfers data DATA received from the external device to the page buffer circuit 130, or transfers data DATA received from the page buffer circuit 130 to the external device.

[0017] The control logic and voltage generation circuit 150 (hereinafter referred to as the "control logic circuit") is configured to generate various voltages required for the nonvolatile memory device 100 to operate, such as multiple program voltages, multiple program verify voltages, multiple pass voltages, multiple read voltages, and multiple erase voltages.

[0018] The control logic circuit 150 controls the operation of the nonvolatile memory device 100 in response to a command CMD and a control signal CTRL from an external device. For example, in response to the command CMD, the control logic circuit 150 controls the address decoder 120, the page buffer circuit 130, the input / output circuit 140, and the dummy bit line driver 160 so that an operation corresponding to the command CMD (e.g., a program operation, a read operation, an erase operation, etc.) is performed.

[0019] The dummy bit line driver 160 is connected to the dummy bit lines DBL of the memory cell array 110. The dummy bit line driver 160 is configured to control the voltage of the dummy bit lines DBL or provide a bias under the control of the control logic circuit 150. For example, the memory cell array 110 includes the dummy bit lines DBL. The dummy bit lines DBL refer to bit lines formed in a similar pattern to the bit lines BL of the memory cell array 110 (e.g., an upper metal layer of the memory cell array 110) but are not electrically connected to the cell transistors or the page buffer circuit 130. Alternatively, the dummy bit lines DBL refer to bit lines formed in the same shape or structure as the bit lines BL but are not used in operations (e.g., read operations, program operations, or erase operations) of the nonvolatile memory device 100.

[0020] The dummy bit line driver 160 controls the voltage of the dummy bit line DBL under the control of the control logic circuit 150. When the dummy bit line DBL is controlled by the dummy bit line driver 160, noise generated by the common source line CSL of the memory cell array 110 does not flow into the bit line BL, thereby improving the reliability of the operation of the nonvolatile memory device 100. The operation and structure of the dummy bit line driver 160 will be described in more detail with reference to the following drawings.

[0021] 2 is a circuit diagram showing an example of one memory block BLK among the plurality of memory blocks included in the memory cell array of FIG. 1. While one memory block BLK will be described with reference to FIG. 2, the scope of the present invention is not limited thereto. The plurality of memory blocks included in the memory cell array 110 have the same or similar structure as the memory block BLK of FIG. 2. Referring to FIGS. 1 and 2, the memory block BLK includes a plurality of cell strings (CS11, CS12, CS21, CS22). Each of the plurality of cell strings (CS11, CS12, CS21, CS22) is arranged in a row direction and a column direction.

[0022] Among the plurality of cell strings (CS11, CS12, CS21, CS22), cell strings located in the same column are connected to the same bit line. For example, the cell strings (CS11, CS21) are connected to a first bit line BL1, and the cell strings (CS12, CS22) are connected to a second bit line BL2. Each of the plurality of cell strings (CS11, CS12, CS21, CS22) includes a plurality of cell transistors. Each of the plurality of cell transistors is a charge trap flash (CTF) memory cell, although the scope of the present invention is not limited thereto. The plurality of cell transistors are stacked in a height direction, which is a direction perpendicular to a plane formed by the row and column directions (e.g., a semiconductor substrate (not shown) or a peripheral circuit PERI).

[0023] A plurality of cell transistors are connected in series between corresponding bit lines (e.g., BL1 or BL2) and a common source line CSL. For example, the plurality of cell transistors include string select transistors (SSTb, SSTa), dummy memory cells (DMC1, DMC2), memory cells (MC1 to MC8), and ground select transistors (GSTa, GSTb). The serially connected string select transistors (SSTb, SSTa) are provided or connected between the serially connected memory cells (MC1 to MC8) and the corresponding bit lines (e.g., BL1 or BL2). The serially connected ground select transistors (GSTa, GSTb) are provided or connected between the serially connected memory cells (MC1 to MC8) and the common source line CSL. In one embodiment, a second dummy memory cell DMC2 is provided between the serially connected string selection transistors (SSTb, SSTa) and the serially connected memory cells (MC1 to MC8), and a first dummy memory cell DMC1 is provided between the serially connected memory cells (MC1 to MC8) and the serially connected ground selection transistors (GSTb, GSTa).

[0024] Among the memory cells (MC1 to MC8) of each of the plurality of cell strings (CS11, CS12, CS21, CS22), memory cells located at the same height share the same word line. For example, the first memory cell MC1 of each of the plurality of cell strings (CS11, CS12, CS21, CS22) is located at the same height from the substrate (not shown) and shares the first word line WL1. The second memory cell MC2 of each of the plurality of cell strings (CS11, CS12, CS21, CS22) is located at the same height from the substrate (not shown) and shares the second word line WL2. Similarly, the third to eighth memory cells (MC3 to MC8) of each of the plurality of cell strings (CS11, CS12, CS21, CS22) are located at the same height from the substrate (not shown) and share the third to eighth word lines (WL3 to WL8), respectively.

[0025] Dummy memory cells (DMC1, DMC2) located at the same height among the dummy memory cells of each of the plurality of cell strings (CS11, CS12, CS21, CS22) share the same dummy word line. For example, the first dummy memory cell DMC1 of each of the plurality of cell strings (CS11, CS12, CS21, CS22) shares the first dummy word line DWL1, and the second dummy memory cell DMC2 of each of the plurality of cell strings (CS11, CS12, CS21, CS22) shares the second dummy word line DWL2. In one embodiment, the dummy word lines are added for a multi-stacked structure. For example, a dummy word line is added between word lines (e.g., WL4, WL5) and connected to the dummy memory cells added between the memory cells (e.g., MC4, MC5). However, the scope of the present invention is not limited thereto.

[0026] The string select transistors (SSTa, SSTb) of each of the cell strings (CS11, CS12, CS21, CS22) located in the same row and at the same height are connected to the same string select line. For example, the string select transistors SSTb of the cell strings (CS11, CS12) are connected to the string select line SSL1b, and the string select transistors SSTa of the cell strings (CS11, CS12) are connected to the string select line SSL1a. The string select transistors SSTb of the cell strings (CS21, CS22) are connected to the string select line SSL2b, and the string select transistors SSTa of the cell strings (CS21, CS22) are connected to the string select line SSL2a.

[0027] Although not shown, the string select transistors (SSTb, SSTa) located in the same row of each of the cell strings (CS11, CS12, CS21, CS22) share the same string select line. For example, the string select transistors (SSTb, SSTa) of the cell strings (CS11, CS12) share a first string select line, and the string select transistors (SSTb, SSTa) of the cell strings (CS21, CS22) share both the first string select line and a second string select line.

[0028] Among the ground selection transistors (GSTb, GSTa) of each of the plurality of cell strings (CS11, CS12, CS21, CS22), the ground selection transistors located in the same row and at the same height are connected to the same ground selection line. For example, the ground selection transistor GSTb of the cell strings (CS11, CS12) is connected to the ground selection line GSL1b, and the ground selection transistor GSLa of the cell strings (CS11, CS12) is connected to the ground selection line GST1a. The ground selection transistor GSTb of the cell strings (CS21, CS22) is connected to the ground selection line GSL2b, and the ground selection transistor GSLa of the cell strings (CS21, CS22) is connected to the ground selection line GST2a.

[0029] Although not shown, the ground selection transistors (GST1b, GST1a) of each of the plurality of cell strings (CS11, CS12, CS21, CS22) share the same ground selection line. Alternatively, the ground selection transistors (GSTb, GSTa) of each of the plurality of cell strings (CS11, CS12, CS21, CS22) at the same height share the same ground selection line. Alternatively, the ground selection transistors (GSTb, GSTa) of each of the plurality of cell strings (CS11, CS12, CS21, CS22) located in the same row share the same ground selection line.

[0030] In one embodiment, although not shown, each of the plurality of cell strings (CS11, CS12, CS21, CS22) of the memory block BLK further includes an erase control transistor ECT. The erase control transistors ECT of each of the plurality of cell strings (CS11, CS12, CS21, CS22) are located at the same height from the substrate and connected to the same erase control line ECL. For example, the erase control transistor ECT is located between the common source line CSL and the ground selection transistor GSTa in each of the plurality of cell strings (CS11, CS12, CS21, CS22). Alternatively, the erase control transistor ECT is located between the bit line (BL1, BL2) and the string selection transistor SSTb. However, the scope of the present invention is not limited thereto.

[0031] 2 is an example, and the number of cell strings may be increased or decreased, and the number of rows and columns constituting the cell strings may be increased or decreased depending on the number of cell strings. The number of cell transistors (GST, MC, DMC, SST) of the memory block BLK may be increased or decreased, and the height of the memory block BLK may be increased or decreased depending on the number of cell transistors. The number of lines (GSL, WL, DWL, SSL) connected to the cell transistors may be increased or decreased depending on the number of cell transistors.

[0032] 3 is a perspective view schematically illustrating the nonvolatile memory device of FIG. 1. Hereinafter, for convenience of explanation, a schematic structure of the nonvolatile memory device 100 will be described based on one memory block BLK, but the scope of the present invention is not limited thereto. For simplicity of the drawings and convenience of explanation, only the configuration related to the technical concept of the present invention will be described, but the scope of the present invention is not limited thereto.

[0033] 1 to 3, the peripheral circuit PERI of the nonvolatile memory device 100 is formed on a plane (e.g., a semiconductor substrate) defined by row and column directions. The memory block BLK having a three-dimensional structure is formed above the peripheral circuit PERI or in a direction perpendicular to the peripheral circuit PERI, i.e., in the height direction. That is, the nonvolatile memory device 100 has a COP structure.

[0034] Various signal lines (e.g., bit lines BL, word lines WL, string select lines SSL, ground select lines GSL, common source lines CSL, etc.) of the memory blocks BLK are connected to the peripheral circuit PERI via conductive lines included in the metal layer ML. In one embodiment, the bit lines BL of the memory blocks BLK are connected to the peripheral circuit PERI through contact regions CT. For example, the bit lines BL of the memory blocks BLK are electrically connected to the conductive lines of the metal layer ML. Dummy memory blocks dBLK having a structure similar to that of the memory blocks BLK are formed in the contact regions CT, and the peripheral circuit PERI (particularly, the page buffer circuit 130) is electrically connected to the conductive lines of the metal layer ML through via plugs that penetrate the dummy memory blocks dBLK in the height direction. In one embodiment, the page buffer circuit 130 is formed in the contact regions CT of the peripheral circuit PERI.

[0035] 4 is a cross-sectional view of a nonvolatile memory device taken along line B in FIG. 3. FIG. 5 is a cross-sectional view of a nonvolatile memory device taken along line A in FIG. 3. For the sake of brevity and convenience of explanation, components not necessary for explaining embodiments of the present invention and their detailed description will be omitted. For example, some string selection lines, some word lines, dummy word lines, some ground selection lines, etc. of a memory block BLK are omitted in the following drawings, but the scope of the present invention is not limited thereto.

[0036] 1, 3, 4, and 5, a peripheral circuit PERI is formed on a semiconductor substrate SUB. A cell region CELL is formed above the peripheral circuit PERI or along the height direction from the peripheral circuit PERI. The cell region CELL refers to an area where a memory block BLK is formed. In the cell region CELL, a common source line CSL, a ground selection line GSL, word lines (WL1 to WL6), and a string selection line SSL are stacked vertically in the height direction from the peripheral circuit PERI.

[0037] In the first contact region CNR1, the common source line CSL, the ground selection line GSL, the word lines (WL1 to WL6), and the string selection line SSL are formed in a stepped shape. For example, in the first contact region CNR1, the lengths of the common source line CSL, the ground selection line GSL, the word lines (WL1 to WL6), and the string selection line SSL in the row direction become shorter as they are farther from the peripheral circuit PERI.

[0038] In the first contact region CNR1, the ground selection line GSL, the word lines WL1 to WL6, and the string selection line SSL are connected to the first contact plug CT1 through the first via plug TP1. The first contact plug CT1 is connected to the first conductive line CL1 of the metal layer ML. The first via plug TP1 is formed in the cell region CELL along a height direction (i.e., a direction perpendicular to the peripheral circuit PERI). In one embodiment, the first via plug TP1 or a via plug described below refers to a vertical through structure such as a TSV (Through Silicon Via) or a THV (Through Hole Via). In one embodiment, the metal layer ML includes multiple layers for providing various wirings or patterns of the conductive line CL1.

[0039] The first conductive line CL1 of the metal layer ML is connected to the second contact plug CT2 in the second contact region CNR2. The second contact plug CT2 is electrically connected to the peripheral circuit PERI via the second through plug TP2. In one embodiment, as shown in FIG. 4, the first word line WL1 is electrically connected to the peripheral circuit PERI, particularly the address decoder 120, via the first through plug TP1, the first contact plug CT1, the first conductive line CL1, the second contact plug CT2, and the second through plug TP2. The connection structure of the word lines WL1 to WL6 of the memory block BLK described above is merely an example, and the scope of the present invention is not limited thereto.

[0040] The channel CH is provided in the cell core region CAR. The channel CH penetrates the vertically stacked common source line CSL, ground selection line GSL, word lines WL1 to WL6, and string selection line SSL. The channel CH is connected to the bit line BL via the third contact CT3.

[0041] In one embodiment, the metal layer ML includes a conductive line corresponding to the common source line CSL. The conductive line corresponding to the common source line CSL is connected to the common source line CSL in the cell region CELL via a fourth contact plug CT4 and a fourth through plug TP4. In one embodiment, the common source line CSL in the metal layer ML is commonly connected to all or a portion of the memory cell array via a mesh structure or a ring structure. In one embodiment, in the cell region CELL, the common source line CSL is commonly connected to all or a portion of the memory cell array via a mesh structure or a ring structure.

[0042] 5, bit lines BL electrically connected to the channels CH and the third contact plugs CT3 extend in the column direction. The bit lines BL extending in the column direction from the metal layer ML are electrically connected to the page buffer circuit 130 of the peripheral circuit PERI through fifth contact plugs CT5 and fifth through plugs TP5 in the third contact region CNR3. In one embodiment, the third contact region CNR3 corresponds to the contact region CT or the dummy block dBLK described with reference to FIG. 3. That is, the third contact region CNR3 refers to a region (e.g., a bit line contact region) in which through plugs electrically connecting the bit lines BL and the page buffer circuit 130 are formed. In the third contact region CNR3, regions corresponding to the ground selection line GSL, the word lines WL1 to WL6, and the string selection line SSL are provided as mold patterns MP.

[0043] In one embodiment, the dummy bit line DBL extends in the row direction in the cell core region CAR and is electrically connected to the dummy bit line driver 160 of the peripheral circuit PERI through the sixth contact plug CT6 and the sixth through plug TP6 in the third contact region CNR3. In one embodiment, the dummy bit line DBL refers to a bit line formed in the same pattern as the bit line BL using a metal layer but not electrically connected to the channel CH. Alternatively, the dummy bit line DBL is electrically connected to the channel connected to the bit line BL, but the channel connected to the dummy bit line DBL has a different structure from the channel CH connected to the bit line BL.

[0044] In one embodiment, the page buffer circuit 130 is provided in the third contact region CNR3 of the peripheral circuit PERI, and the dummy bit line driver 160 is provided at a position different from the third contact region CNR3 of the peripheral circuit PERI. That is, the dummy bit line DBL is connected to the peripheral circuit PERI through the sixth through plug TP6 formed in a region (i.e., the third contact region CNR3) where the fifth through plug for electrically connecting the bit line BL and the page buffer circuit 130 of the peripheral circuit PERI is provided, but the dummy bit line driver 160 electrically connected to the dummy bit line DBL is provided at a position different from the third contact region CNR3 or a position different from the page buffer circuit 130.

[0045] 6 is a plan view showing a cell core region in the metal layer of FIG. 3. Referring to FIG. 3 and FIG. 6, in the cell core region of the metal layer ML of the nonvolatile memory device 100, the common source line CSL, the dummy bit lines (DBLa, DBLb), and the bit lines (BLa, BLb) extend along the column direction. The common source line CSL, the dummy bit lines (DBLa, DBLb), and the bit lines (BLa, BLb) are arranged along the row direction.

[0046] The bit lines (BLa, BLb) are electrically connected to channels or memory cells of a plurality of memory blocks. The dummy bit lines (DBLa, DBLb) are disposed between the common source line CSL and the bit lines (BLa, BLb) on the metal layer ML. For example, the dummy bit line DBLa is disposed between the common source line CSL and the bit line BLa, and the dummy bit line DBLb is disposed between the common source line CSL and the bit line BLb.

[0047] In one embodiment, when the level of the common source line CSL changes, noise flows into the bit lines (BLa, BLb) due to the common source line CSL. For example, when the nonvolatile memory device 100 performs a read operation or a program verify operation, a large current flows through the common source line CSL. The large current flowing through the common source line CSL may cause noise in the bit lines (BLa, BLb), which may reduce the reliability of read data.

[0048] In one embodiment, the dummy bit line driver 160 according to the present invention is configured to control the levels of the dummy bit lines DBLa and DBLb according to the operation of the nonvolatile memory device 100. In this case, it is possible to block or prevent noise generated from the common source line CSL from flowing into the bit lines BLa and BLb.

[0049] 7 is a plan view showing a third contact region in the metal layer of FIG. 5. Referring to FIG. 5 and FIG. 7, a plurality of bit lines BL and dummy bit lines DBL are provided in the third contact region CNR3 of the metal layer ML. In one embodiment, the plurality of bit lines BL and dummy bit lines DBL provided in the third contact region CNR3 of the metal layer ML are electrically connected to the bit lines (BLa, BLb) and dummy bit lines (DBLa, DBLb) described with reference to FIG. 6 through various conductive lines of the metal layer ML.

[0050] In the third contact region CNR3 of the metal layer ML, the bit lines BL are electrically connected to the page buffer circuit 130 of the peripheral circuit PERI through through plugs TP formed in the through plug region TPA. The through plug regions TPA connected to the bit lines BL are arranged at a regular interval or pitch. For example, the distance between the first through plug region TPA1 and the second through plug region TPA2 adjacent to the first through plug region TPA1 in the row direction is a first length L1. The distance between the through plug region TPA1 and the third through plug region TPA3 adjacent to the first through plug region TPA1 in the column direction is a second length L2. That is, the through plug regions TPA configured to connect the bit lines BL are formed in a regular or uniform pattern in the third contact region CNR3.

[0051] The dummy bit lines DBL are electrically connected to the dummy bit line driver 160 of the peripheral circuit PERI through the dummy through plug regions DTPA. The dummy through plug regions DTPA are formed in an irregular pattern or at irregular positions in the third contact region CNR3 compared to the through plug regions TPA. For example, the distance between the dummy through plug region DTPA and the second through plug region TPA2 adjacent to the dummy through plug region DTPA in the row direction is a third distance L3. Here, the third distance L3 is shorter than the first distance L1. That is, the dummy through plug regions DTPA electrically connected to the dummy bit lines DBL are formed between the through plug regions TPA formed in a regular pattern. The dummy through plug regions DTPA are irregular compared to the arrangement of the through plug regions TPA.

[0052] 7 shows one dummy via plug area DTPA, the scope of the present invention is not limited thereto, and the number of dummy via plug areas DTPA may vary. In one embodiment, the dummy via plug areas DTPA are commonly connected to a dummy bit line driver 160 through a ring structure or a mesh structure in a metal layer (not shown) of the peripheral circuit PERI.

[0053] 8 is a circuit diagram illustrating the dummy bit line driver of FIG. 1. Hereinafter, for convenience of explanation, it is assumed that the dummy bit lines driven or controlled by the dummy bit line driver 160 are dummy bit lines adjacent to the common source line in the cell core region CAR. That is, in FIG. 6, it is assumed that one dummy bit line among the dummy bit lines DBLa closest to the common source line CSL and one dummy bit line among the dummy bit lines DBLb closest to the common source line CSL are driven or controlled by the dummy bit line driver 160. However, the scope of the present invention is not limited thereto. For example, the dummy bit lines driven or controlled by the dummy bit line driver 160 may be at least one dummy bit line among the dummy bit lines DBLa closest to the common source line CSL, one dummy bit line closest to the bit line BLa, or at least one dummy bit line among the dummy bit lines DBLa. That is, the dummy bit lines driven or controlled by the dummy bit line driver 160 may vary.

[0054] 1 and 8, the dummy bit line driver 160 includes a first switch SW1 connected between the dummy bit line DBL and a zeroth voltage V0. The first switch SW1 operates in response to a first dummy bit line driving signal DBL_DRV1. The first switch SW1 provides or blocks the zeroth voltage V0 to the dummy bit line DBL in response to the first dummy bit line driving signal DBL_DRV1. In one embodiment, the first switch SW1 is implemented with an NMOS transistor device, although the scope of the present invention is not limited thereto.

[0055] In one embodiment, the zeroth voltage V0 is a ground voltage GND or VSS, but the scope of the present invention is not limited thereto, and the zeroth voltage V0 may be a predetermined positive voltage or a predetermined negative voltage.

[0056] When the zeroth voltage V0 is applied to the dummy bit line DBL, the dummy bit line DBL maintains the zeroth voltage V0, thereby preventing noise generated by a large current in the common source line CSL from flowing into other bit lines BL.

[0057] 9 is a timing diagram illustrating a first dummy bit line driving signal DBL_DRV1 provided to the dummy bit line driver of FIG 8. Referring to FIG 1, FIG 8, and FIG 9, the control logic circuit 150 controls the first dummy bit line driving signal DBL_DRV1 according to the operation of the nonvolatile memory device 100. For example, the nonvolatile memory device 100 performs a read operation RD, a program operation PGM, and an erase operation ERS.

[0058] The control logic circuit 150 generates a first dummy bit line driving signal DBL_DRV1 so that the first switch SW1 of the dummy bit line driver 160 is turned on while the nonvolatile memory device 100 is performing a read operation RD or a program operation PGM, and the first switch SW1 of the dummy bit line driver 160 is turned off while the nonvolatile memory device 100 is performing an erase operation ERS.

[0059] For example, while the nonvolatile memory device 100 is performing a read operation RD, a current may flow through the common source line CSL, which may cause noise to flow into the adjacent bit line BL. In this case, the dummy bit line driver 160 operates to apply a zeroth voltage V0 to the dummy bit line DBL located between the common source line CSL and the bit line BL. This prevents noise caused by the current in the common source line CSL from flowing into the bit line BL. In one embodiment, the program verify step of the program operation PGM of the nonvolatile memory device 100 is performed using a mechanism similar to that of the read operation, and noise caused by the current in the common source line CSL is prevented by the same operation as described above.

[0060] In one embodiment, the nonvolatile memory device 100 performs an erase operation ERS through a gate induced drain leakage (GIDL) erase operation. That is, an erase voltage is applied to a common source line CSL of the nonvolatile memory device 100. At this time, if the voltage of the dummy bit line DBL adjacent to the common source line CSL is maintained or biased at the zeroth voltage V0, the time it takes for the common source line CSL to rise to the erase voltage is delayed.

[0061] The dummy bit line driver 160 turns off the first switch SW1 in response to the first dummy bit line driving signal DBL_DRV1 from the control logic circuit 150. In this case, during the erase operation ERS of the nonvolatile memory device 100, the dummy bit line DBL is in a floating state, thereby shortening the time it takes for the common source line CSL to rise to the erase voltage.

[0062] 10A to 10C are diagrams illustrating the levels of the bit lines, dummy bit lines, and common source line CSL according to the timing diagram of FIG. 9. For convenience of explanation, FIGS. 10A to 10C illustrate only some of the various lines included in the cell core region CAR of the metal layer ML, and it is assumed that the dummy bit lines controlled by the dummy bit line driver 160 are first and second dummy bit lines DBL1 and DBL2 adjacent to the common source line CSL. However, the scope of the present invention is not limited thereto, and the number and positions of the dummy bit lines or the number and positions of the dummy bit lines controlled by the dummy bit line driver 160 may be variously changed.

[0063] First, referring to Figures 9 and 10A, when the nonvolatile memory device 100 performs a read operation RD or a program operation PGM (particularly a program verify operation), the first to fourth bit lines (BL1, BL2, BL3, BL4) have first to fourth bit line voltages (VBL1, VBL2, VBL3, VBL4) depending on the state of the corresponding memory cell.

[0064] When the nonvolatile memory device 100 performs a read operation RD or a program operation PGM (particularly, a program verify operation), applying a ground voltage GND to the common source line CSL causes a current to flow according to the state of a memory cell targeted by the read operation RD or the program operation PGM (particularly, a program verify operation). Noise caused by the current flowing through the common source line CSL may affect adjacent bit lines (e.g., BL2, BL3). In this case, the dummy bit line driver 160 according to the present invention applies a zeroth voltage V0 to the first and second dummy bit lines DBL1, DBL2. That is, the first and second dummy bit lines DBL1, DBL2 are maintained at the zeroth voltage V0 by the dummy bit line driver 160. In one embodiment, the zeroth voltage V0 is provided from a power supply or voltage terminal physically separated from the common source line CSL. The zeroth voltage V0 is a ground voltage GND or VSS. Alternatively, the zeroth voltage V0 is a predetermined positive voltage or a predetermined negative voltage.

[0065] When the first and second dummy bit lines (DBL1, DBL2) are biased to the zeroth voltage V0, noise generated by the current of the common source line CSL can be prevented from flowing into adjacent bit lines (e.g., BL2, BL3). That is, since the adjacent bit lines (e.g., BL2, BL3) are not affected by noise due to the current of the common source line CSL, the states of the memory cells connected to the adjacent bit lines (e.g., BL2, BL3) or the data stored in the memory cells can be accurately sensed.

[0066] 9 and 10B, while the nonvolatile memory device 100 performs an erase operation ERS, an erase voltage VERS is applied to the common source line CSL. The erase voltage VERS is a positive high voltage. If the first and second dummy bit lines DBL1 and DBL2 maintain the zero voltage V0 or another bias voltage while the erase voltage VERS is applied to the common source line CSL, the time required for the common source line CSL to rise to the erase voltage VERS increases.

[0067] The dummy bit line driver 160 according to this embodiment floats the first and second dummy bit lines DBL1 and DBL2 adjacent to the common source line CSL while the nonvolatile memory device 100 performs the erase operation ERS. In this case, if the common source line CSL and the adjacent first and second dummy bit lines DBL1 and DBL2 are coupled while the level of the common source line CSL rises to the erase voltage VERS, the time it takes for the common source line CSL to reach the erase voltage VERS can be shortened.

[0068] 9 and 10C, the dummy bit line driver 160 floats the first and second dummy bit lines DBL1 and DBL2 adjacent to the common source line CSL and the bit lines BL2 and BL3 while the nonvolatile memory device 100 is performing the erase operation ERS. For example, the nonvolatile memory device 100 applies an erase voltage VERS to the common source line CSL and the bit lines BL1 to BL4 during the erase operation ERS. That is, unlike the embodiment of FIG. 10B, the nonvolatile memory device 100 further applies the erase voltage VERS to the bit lines BL1 to BL4. In this case, the dummy bit line driver 160 floats the first and second dummy bit lines DBL1 and DBL2 adjacent to the common source line CSL and the bit lines BL2 and BL3, thereby shortening the time it takes for the common source line CSL and the bit lines BL2 and BL3 to reach the erase voltage VERS.

[0069] 10C shows one dummy bit line DBL1 between the common source line CSL and the bit line BL2, but the scope of the present invention is not limited thereto. For example, as described with reference to FIG. 6, multiple dummy bit lines DBLa may be present between the common source line CSL and the bit line BLa. In this case, the dummy bit line driver 160 is configured to float at least one dummy bit line adjacent to the common source line CSL and at least one dummy bit line adjacent to the bit line BLa, among the multiple dummy bit lines DBLa.

[0070] As described above, according to an embodiment of the present invention, the dummy bit line driver 160 is configured to apply the zeroth voltage V0 to at least one dummy bit line adjacent to the common source line CSL and to float the at least one dummy bit line adjacent to the common source line CSL while the nonvolatile memory device 100 is performing an erase operation ERS. This prevents noise due to the current of the common source line CSL from flowing into the bit line during a sensing operation (e.g., a read operation or a program verify operation) of the nonvolatile memory device 100, thereby improving the reliability of the sensing operation. Furthermore, during an erase operation ERS of the nonvolatile memory device 100, the time it takes for the common source line CSL or the bit line BL to rise to the erase voltage VERS can be shortened. Therefore, a nonvolatile memory device with improved reliability and performance is provided.

[0071] Figures 11A and 11B are diagrams illustrating the dummy bit line driver of Figure 1. The dummy bit line driver 160 of Figure 1 is replaced with dummy bit line drivers 160a and 160b of Figures 11A and 11B.

[0072] 1 and 11A, the dummy bit line driver 160a includes first and second switches SW1 and SW2. The first switch SW1 is connected between the dummy bit line DBL and the zeroth voltage V0 and operates in response to a first dummy bit line driving signal DBL_DRV1. The first switch SW1 and the first dummy bit line driving signal DBL_DRV1 are the same as those described above, and therefore a detailed description thereof will be omitted.

[0073] The second switch SW2 is connected between the common source line CSL and the dummy bit line DBL and operates in response to a second dummy bit line driving signal DBL_DRV2. For example, during an erase operation ERS of the nonvolatile memory device 100, the common source line CSL receives an erase voltage VERS from the erase voltage generator 10. In one embodiment, the erase voltage generator 10 is included in the control logic and voltage generation circuit 150 of FIG. 1 or is substituted for the control logic and voltage generation circuit 150 of FIG. 1.

[0074] During the erase operation ERS of the nonvolatile memory device 100, the second switch SW2 of the dummy bit line driver 160a electrically connects the common source line CSL and the dummy bit line DBL in response to the second dummy bit line driving signal DBL_DRV2. That is, during the erase operation ERS of the nonvolatile memory device 100, the second switch SW2 of the dummy bit line driver 160a applies the erase voltage VERS to both the dummy bit line DBL and the common source line CSL. In this case, the dummy bit line DBL rises to the erase voltage VERS together with the common source line CSL, thereby shortening the time it takes for the common source line CSL to reach the erase voltage VERS.

[0075] 1 and 11B, the dummy bit line driver 160b includes first and second switches SW1 and SW2. The first switch SW1 is connected between the dummy bit line DBL and the zeroth voltage V0 and operates in response to a first dummy bit line driving signal DBL_DRV1. The first switch SW1 and the first dummy bit line driving signal DBL_DRV1 are the same as those described above, and therefore a detailed description thereof will be omitted.

[0076] 11B is connected between the dummy bit line DBL and the erase voltage generator 11 and operates in response to a second dummy bit line driving signal DBL_DRV2. For example, the erase voltage generator 11 is configured to provide an erase voltage VERS to the common source line CSL, the bit line BL, or the common source line and bit line CSL / BL during an erase operation ERS of the nonvolatile memory device 100. That is, during an erase operation of the nonvolatile memory device 100, the time it takes for the common source line CSL, the bit line BL, or the common source line and bit line CSL / BL to reach the erase voltage VERS can be shortened.

[0077] 11A or 11B. For ease of explanation, detailed descriptions of the above-mentioned components will be omitted. Referring to FIGS. 1, 11A, 11B, and 12, the control logic circuit 150 generates the first and second dummy bit line driving signals DBL_DRV1 and DBL_DVR2 in response to the operation of the nonvolatile memory device 100.

[0078] For example, the control logic circuit 150 generates the first dummy bit line driving signal DBL_DRV1 such that the first switch SW1 of the dummy bit line driver (160a or 160b) is turned on during a read operation RD and a program operation PGM of the nonvolatile memory device 100 and the first switch SW1 of the dummy bit line driver (160a or 160b) is turned off during an erase operation ERS of the nonvolatile memory device 100. The control logic circuit 150 generates the second dummy bit line driving signal DBL_DRV2 such that the second switch SW2 of the dummy bit line driver (160a or 160b) is turned off during a read operation RD and a program operation PGM of the nonvolatile memory device 100 and the second switch SW2 of the dummy bit line driver (160a or 160b) is turned on during an erase operation ERS of the nonvolatile memory device 100.

[0079] The operation of the dummy bit line driver 160a or 160b according to the first and second dummy bit line driving signals DBL_DRV1 and DBL_DRV2 in the timing diagram of FIG. 12 has been described above, so a detailed description thereof will be omitted.

[0080] 13A to 13C are diagrams illustrating the levels of the bit lines, dummy bit lines, and common source lines according to the timing diagram of FIG. 12. For convenience of explanation, detailed descriptions of the above-mentioned components will be omitted. In one embodiment, the levels of the bit lines, dummy bit lines, and common source lines during a read operation or a program operation of the nonvolatile memory device 100 are the same as those described with reference to FIG. 10A, and therefore detailed descriptions thereof will be omitted.

[0081] 1 and 13A, during an erase operation ERS of the nonvolatile memory device 100, an erase voltage VERS is applied to both the common source line CSL and the dummy bit lines (DBL1, DBL2). In this case, the dummy bit lines (DBL1, DBL2) adjacent to the common source line CSL rise to the erase voltage VERS together, thereby shortening the time it takes for the common source line CSL to reach the erase voltage VERS. In one embodiment, the erase voltage VERS is applied to the dummy bit lines (DBL1, DBL2) of the nonvolatile memory device 100 by electrically connecting the dummy bit line DBL to the common source line CSL via a second switch SW2 as shown in FIG. 11A, or by providing the erase voltage VERS from the erase voltage generator 11 to the dummy bit line DBL via the second switch SW2 as shown in FIG. 11B.

[0082] 1 and 13B, during an erase operation ERS of the nonvolatile memory device 100, an erase voltage VERS is applied to both the bit lines (BL1 to BL4) and the dummy bit lines (DBL1 and DBL2). In this case, the dummy bit lines (DBL1 and DBL2) adjacent to the bit lines (BL2 and BL3) rise to the erase voltage VERS simultaneously, thereby shortening the time it takes for the bit lines (BL2 and BL3) to rise to the erase voltage VERS. In one embodiment, the erase voltage VERS is applied to the dummy bit lines (DBL1 and DBL2) of the nonvolatile memory device 100 by providing the erase voltage VERS from the erase voltage generator 11 to the dummy bit line DBL via the second switch SW2, as shown in FIG. 11B.

[0083] 1 and 13C, during an erase operation ERS of the nonvolatile memory device 100, an erase voltage VERS is applied to the common source line CSL, the bit lines BL1 to BL4, and the dummy bit lines DBL1 and DBL2. In this case, the common source line CSL and the dummy bit lines DBL1 and DBL2 adjacent to the bit lines BL3 and BL4 rise to the erase voltage VERS simultaneously, thereby shortening the time it takes for the common source line CSL and the bit lines BL3 and BL4 to reach the erase voltage VERS. In one embodiment, the erase voltage VERS is applied to the dummy bit lines DBL1 and DBL2 of the nonvolatile memory device 100 by electrically connecting the dummy bit line DBL to the common source line CSL via a second switch SW2 as shown in FIG. 11A, or by providing the erase voltage VERS from the erase voltage generator 11 to the dummy bit line DBL via a second switch SW2 as shown in FIG. 11B.

[0084] 11A or 11B. For ease of explanation, detailed descriptions of the above-mentioned components will be omitted. Referring to FIGS. 1, 11A, 11B, and 14, the control logic circuit 150 generates the first and second dummy bit line driving signals DBL_DRV1 and DBL_DVR2 in response to the operation of the nonvolatile memory device 100.

[0085] For example, the control logic circuit 150 generates the first dummy bit line driving signal DBL_DRV1 as described with reference to FIG. 12 during the read operation RD and the program operation PGM of the nonvolatile memory device 100. The control logic circuit 150 generates the second dummy bit line driving signal DBL_DRV2 so that the second switch SW2 of the dummy bit line driver 160a or 160b is turned off. According to the timing diagram of FIG. 14, the dummy bit line driver 160a or 160b operates as described with reference to FIGS. 8 to 10B, and a detailed description thereof will be omitted.

[0086] In one embodiment, the dummy bit line driver is implemented as shown in Figure 11A. When the nonvolatile memory device 100 performs an erase operation by applying an erase voltage VERS to the bit line BL, the control logic circuit 150 floats the dummy bit line DBL during the erase operation by generating first and second dummy bit line drive signals DBL_DRV1 and DBL_DRV2 as shown in the timing diagram of Figure 14. This reduces the time it takes for the bit line BL to rise to the erase voltage VERS.

[0087] 15A and 15B are diagrams illustrating a method of controlling a dummy bit line according to an embodiment of the present invention. In the above embodiment, a configuration in which one dummy bit line DBL is controlled between a common source line CSL and a bit line BL has been described, but the scope of the present invention is not limited thereto.

[0088] 15A, a plurality of dummy bit lines (DBL1a, DBL2a, DBL3a, DBL1b, DBL2b, and DBL3b) are present between the bit line BL and the common source line CSL. The dummy bit line driver 160c controls the dummy bit lines (DBL1a, DBL2a, DBL3a, DBL1b, DBL2b, and DBL3b) adjacent to the common source line CSL based on the driving method described above. Among the plurality of dummy bit lines (DBL1a, DBL2a, DBL3a, DBL1b, DBL2b, and DBL3b), some dummy bit lines (DBL2a and DBL2b) are biased to the zeroth voltage V0 or a predetermined voltage, and other dummy bit lines (DBL3a and DBL3b) are floating. At this time, some dummy bit lines (DBL2a, DBL2b) and other dummy bit lines (DBL3a, DBL3b) maintain a bias state or a floating state regardless of the operation of the nonvolatile memory device 100.

[0089] In one embodiment, the positions of the dummy bit lines biased to the zeroth voltage V0 or to a floating state may be varied in various ways. For example, as shown in FIG. 15B, some dummy bit lines DBL2a and DBL2b may be floated, and other dummy bit lines DBL3a and DBL3b may be biased to the zeroth voltage V0 or a predetermined voltage.

[0090] 15A and 15B are merely examples, and the scope of the present invention is not limited thereto. For example, the positions of the dummy bit lines controlled by the dummy bit line driver 160 or the positions of the dummy bit lines biased to a predetermined state may be varied in various ways depending on the operation of the nonvolatile memory device 100.

[0091] 16 is a diagram illustrating an example of a nonvolatile memory device including a plurality of dummy bit line drivers according to an embodiment of the present invention. For the sake of clarity and convenience, unnecessary components are omitted. For the sake of clarity, the dummy bit lines are indicated by dashed lines in FIG. 16.

[0092] 1 and 16, each of the first to third bit line groups BL_G1 to BL_G3 includes a plurality of bit lines and is connected to a first to third page buffer circuit 130-1 to 130-3, respectively. The number of bit lines included in each of the first to third bit line groups BL_G1 to BL_G3 is the same, but the scope of the present invention is not limited thereto.

[0093] The first to third bit line groups (BL_G1 to BL_G3) are separated by common source lines CSL. For example, the first bit line group BL_G1 is located between the first common source line CSL_1 and the second common source line CSL_2, the second bit line group BL_G2 is located between the second common source line CSL_2 and the third common source line CSL_3, and the third bit line group BL_G3 is located between the third common source line CSL_3 and the fourth common source line CSL_4. In the embodiment of FIG. 16, the first to fourth common source lines (CSL_1 to CSL_4) are shown separated from one another, but the scope of the present invention is not limited thereto. For example, the first to fourth common source lines (CSL_1 to CSL_4) are connected to one common source line CSL through a mesh structure or a ring structure.

[0094] Each of the dummy bit line drivers 160-1 to 160-4 is connected to or controls a dummy bit line adjacent to a common source line CSL_1 to CSL_4. For example, the first dummy bit line driver 160-1 is configured to control a dummy bit line adjacent to the first common source line CSL_1, the second dummy bit line driver 160-2 is configured to control a dummy bit line adjacent to the second common source line CSL_2, the third dummy bit line driver 160-3 is configured to control a dummy bit line adjacent to the third common source line CSL_3, and the fourth dummy bit line driver 160-4 is configured to control a dummy bit line adjacent to the fourth common source line CSL_4.

[0095] Each of the plurality of dummy bit line drivers 160-1 to 160-4 operates independently according to the operating state of the nonvolatile memory device 100 and the operating state of the bit line group BL_G1. For example, when a read operation is performed on the second bit line group BL_G2, the second and third dummy bit line drivers 160-2 and 160-3 corresponding to the second and third common source lines CSL_2 and CSL_3 adjacent to the second bit line group BL_G2 operate according to the above-described operating method. In one embodiment, the remaining dummy bit line drivers 160-1 and 160-4 are inactivated or maintain the corresponding dummy bit lines at a specific voltage or float.

[0096] 17 is a flowchart illustrating the operation of the nonvolatile memory device of FIG 1. Referring to FIG 1 and FIG 17, in step S110, the nonvolatile memory device 100 receives a command CMD. For example, the nonvolatile memory device 100 receives the command CMD from an external device (e.g., a memory controller).

[0097] In step S120, the nonvolatile memory device 100 determines whether the received command CMD is an erase command (ERS CMD). If the command CMD is not an erase command (ERS CMD), the nonvolatile memory device 100 provides the zeroth voltage V0 to the dummy bit line DBL in step S130. For example, the control logic circuit 100 of the nonvolatile memory device 100 generates a first dummy bit line drive signal DBL_DRV1 or a second dummy bit line drive signal DBL_DRV2 in response to the command CMD so that the zeroth voltage V0 is provided to the dummy bit line DBL. In one embodiment, the control logic circuit 100 maintains the first dummy bit line drive signal DBL_DRV1 or the second dummy bit line drive signal DBL_DRV2 so that the zeroth voltage V0 is provided to the first dummy bit line.

[0098] The dummy bit line driver (at least one of 160, 160a, 160b, or 160-1 to 160-4) provides the zeroth voltage V0 to the dummy bit line DBL in response to the first dummy bit line driving signal DBL_DRV1 or the second dummy bit line driving signal DBL_DRV2.

[0099] In the case of the erase command (ERS CMD), the nonvolatile memory device 100 applies an erase voltage VERS to the dummy bit line DBL or floats the dummy bit line DBL in operation S140. For example, the control logic circuit 100 generates a first dummy bit line driving signal DBL_DRV1 or a second dummy bit line driving signal DBL_DRV2 so that the erase voltage VERS is provided to the dummy bit line DBL or the dummy bit line DBL is floated in response to the erase command (ERS CMD). The dummy bit line driver (at least one of 160, 160a, 160b, or 160-1 to 160-4) provides the erase voltage VERS to the dummy bit line DBL or floats the dummy bit line DBL in response to the first dummy bit line driving signal DBL_DRV1 or the second dummy bit line driving signal DBL_DRV2. In one embodiment, the dummy bit line driver (160a or at least one of 160-1 to 160-4) electrically connects the dummy bit line DBL to the common source line CSL in response to the first dummy bit line driving signal DBL_DRV1 or the second dummy bit line driving signal DBL_DRV2.

[0100] In step S150, the nonvolatile memory device 100 performs an operation corresponding to the command CMD. For example, if the command CMD is a read command, the nonvolatile memory device 100 performs a read operation. In this case, since the dummy bit line DBL is biased to the zeroth voltage V0 in step S130, noise due to the current of the common source line CSL does not flow into the bit line. If the command CMD is an erase command, the nonvolatile memory device 100 performs an erase operation. In this case, since the erase voltage VERS is applied to the dummy bit line DBL or the dummy bit line DBL is in a floating state in step S140, the speed at which the common source line CSL or the bit line BL reaches the erase voltage VERS is reduced.

[0101] 18A and 18B are timing diagrams illustrating the operation of a nonvolatile memory device according to an embodiment of the present invention. For the sake of simplicity and ease of explanation, the read and program operations of the nonvolatile memory device 100 are illustrated in a simplified manner. However, the scope of the present invention is not limited thereto. The horizontal axis of the timing diagrams of FIGS. 18A and 18B indicates time.

[0102] In the above embodiment, when the nonvolatile memory device 100 is not performing an erase operation (i.e., when a read operation or a program operation is being performed), the dummy bit line DBL maintains the zeroth voltage V0. However, the scope of the present invention is not limited thereto, and the voltage of the dummy bit line DBL may be variously controlled while the nonvolatile memory device 100 is performing a read operation or a program operation.

[0103] 1 and 18A, the nonvolatile memory device 100 performs a read operation, which includes a bit line precharge operation (BL_PRECH), a word line setup operation (WL_SETUP), a selected read voltage application operation (VRD), and a sensing operation (SENSING).

[0104] 18A, during a read operation of the nonvolatile memory device 100, a first voltage V1 is applied to the dummy bit line DBL during a bit line precharge operation BL_PRECH, and a zeroth voltage V0 is applied to the dummy bit line DBL during the remaining operations (WL_SETUP, VRD, SENSING). When the first voltage V1 is applied to the dummy bit line DBL during the bit line precharge operation BL_PRECH, the precharge speed of the bit line BL is improved.

[0105] For example, the precharge operation BL_PRECH of the bit line BL is an operation of charging the bit line BL to a precharge voltage. In this case, if the dummy bit line DBL maintains the zeroth voltage V0, the precharge speed of the dummy bit line DBL and the adjacent bit line BL may decrease. On the other hand, if a first voltage V1 is applied to the dummy bit line DBL during the precharge operation BL_PRECH of the bit line BL, the precharge speed of the bit line BL adjacent to the dummy bit line DBL increases. In one embodiment, the first voltage V1 is provided to the dummy bit line DBL at the same level or in the same form as the bit line precharge voltage.

[0106] In one embodiment, during the sensing operation SENSING of the read operation, the voltage of the dummy bit line DBL is maintained at the zeroth voltage V0, which can prevent noise caused by the current flowing through the common source line CSL from flowing into the bit line BL, as described above.

[0107] 1 and 18B, the nonvolatile memory device 100 performs a program operation. The program operation includes a bit line inhibit operation BL_INH, a word line setup operation WL_SETUP, a program voltage application operation VPGM, and a verify operation VERI. In one embodiment, the verify operation VERI is similar to the read operation described above. That is, the verify operation VERI includes multiple sub-operations as described with reference to FIG. 18A, and provides a first voltage V1 to the dummy bit line DBL during any one of the multiple sub-operations (e.g., a bit line precharge operation).

[0108] 18B, during a bit line inhibit operation BL_INH during a program operation of the nonvolatile memory device 100, a second voltage V2 is applied to the dummy bit line DBL, and a zeroth voltage V0 is applied to the dummy bit line DBL during the remaining operations (WL_SETUP, VPGM, VERI). When a first voltage V1 is applied to the dummy bit line DBL during the bit line inhibit operation BL_INH, the precharge speed of the bit line BL is improved. For example, the bit line inhibit operation BL_INH refers to an operation of charging a bit line corresponding to a memory cell to be program-inhibited to the power supply voltage VCC. At this time, as described above, when the second voltage V2 is applied to the dummy bit line DBL, the bit line adjacent to the dummy bit line DBL is rapidly charged to the power supply voltage VCC.

[0109] 18A and 18B are merely examples, and the scope of the present invention is not limited thereto. The nonvolatile memory device 100 according to an embodiment of the present invention may control the dummy bit lines DBL in various ways other than the control method of the dummy bit lines DBL shown in FIG.

[0110] For example, the read operation may include multiple read sub-operations. In at least one first read sub-operation of the multiple read sub-operations, the nonvolatile memory device 100 provides a first voltage V1 to the dummy bit line DBL. At this time, the at least one first read sub-operation includes a bit line precharge operation (i.e., an operation of directly controlling the bit line voltage). In at least one second read sub-operation of the multiple read sub-operations, the nonvolatile memory device 100 provides a zeroth voltage V0 to the dummy bit line DBL. At least one second read sub-operation includes a sensing operation (i.e., an operation of generating noise due to a current in a common source line).

[0111] Similarly, the program operation includes a plurality of program sub-operations, and in at least one first program sub-operation of the plurality of program sub-operations, the nonvolatile memory device 100 provides a second voltage V2 to the dummy bit line DBL. At this time, the at least one first program sub-operation includes a bit line inhibit operation (i.e., an operation of directly controlling the bit line voltage). At least one second program sub-operation of the plurality of program sub-operations, the nonvolatile memory device 100 provides a zeroth voltage V0 to the dummy bit line DBL. At this time, the at least one second program sub-operation includes a verify operation or a bit line precharge operation included in the verify operation.

[0112] As described above, the nonvolatile memory device 100 according to an embodiment of the present invention can prevent noise caused by current flowing through the common source line CSL from entering the bit line BL by maintaining the voltage of the dummy bit line DBL at the zeroth voltage V0 during a program or read operation. In one embodiment, the nonvolatile memory device 100 controls the voltage of the dummy bit line DBL to a predetermined voltage (e.g., V1, V2, etc.) during a sub-operation that directly controls the voltage of the bit line BL during a program or read operation, or during an operation that charges the voltage of the bit line BL to a specific voltage (e.g., a pre-charge voltage, a power supply voltage, etc.). In this case, the time required to charge the bit line to a specific voltage is shortened, thereby improving the performance of the nonvolatile memory device 100.

[0113] FIG. 19 illustrates an example of a memory device 1400 according to an embodiment of the present invention. Referring to FIG. 19, the memory device 1400 has a chip-to-chip (C2C) structure. The C2C structure refers to fabricating an upper chip including a cell region CELL on a first wafer, fabricating a lower chip including a peripheral circuit region PERI on a second wafer separated from the first wafer, and then bonding the upper and lower chips together. Here, the bonding process refers to a method of electrically connecting a bonding metal formed on the top metal layer of the upper chip to a bonding metal formed on the top metal layer of the lower chip. For example, the bonding metal may be copper (Cu) using Cu-to-Cu bonding. However, the embodiment is not limited thereto. For example, the bonding metal may be aluminum (Al) or tungsten (W).

[0114] Each of the peripheral circuit region PERI and the cell region CELL of the memory device 1400 includes an external pad bonding region PA, a word line bonding region WLBA, and a bit line bonding region BLBA.

[0115] The peripheral circuit region PERI includes a first substrate 1210, an interlayer insulating layer 1215, a plurality of circuit elements (1220a, 1220b, 1220c) formed on the first substrate 1210, first metal layers (1230a, 1230b, 1230c) connected to each of the plurality of circuit elements (1220a, 1220b, 1220c), and second metal layers (1240a, 1240b, 1240c) formed on the first metal layers (1230a, 1230b, 1230c). In one embodiment, the first metal layers (1230a, 1230b, 1230c) are formed of tungsten, which has a relatively high electrical resistance, and the second metal layers (1240a, 1240b, 1240c) are formed of copper, which has a relatively low electrical resistance.

[0116] Although only the first metal layers (1230a, 1230b, 1230c) and the second metal layers (1240a, 1240b, 1240c) are illustrated and described herein, this is not limiting, and in one embodiment, at least one or more additional metal layers are further formed on the second metal layers (1240a, 1240b, 1240c). At least a portion of the one or more additional metal layers formed on the second metal layers (1240a, 1240b, 1240c) is formed of aluminum or the like, which has lower electrical resistance than copper, which forms the second metal layers (1240a, 1240b, 1240c).

[0117] The interlayer insulating layer 1215 is disposed on the first substrate 210 to cover the plurality of circuit elements (1220a, 1220b, 1220c), the first metal layer (1230a, 1230b, 1230c), and the second metal layer (1240a, 1240b, 1240c), and includes an insulating material such as silicon oxide, silicon nitride, etc.

[0118] Lower bonding metals (1271b, 1272b) are formed on the second metal layer 1240b in the word line bonding region WLBA. In the word line bonding region WLBA, the lower bonding metals (1271b, 1272b) in the peripheral circuit region PERI are electrically coupled to the upper bonding metals (1371b, 1372b) in the cell region CELL by bonding. The lower bonding metals (1271b, 1272b) and the upper bonding metals (1371b, 1372b) are formed of aluminum, copper, tungsten, or the like.

[0119] The upper bonding metals (1371b, 1372b) in the cell area CELL are referred to as first metal pads, and the lower bonding metals (1271b, 1272b) in the peripheral circuit area PERI are referred to as second metal pads.

[0120] The cell region CELL provides at least one memory block. The cell region CELL includes a second substrate 1310, an interlayer insulating film 1315, and a common source line 1320. A plurality of word lines (1331 to 1338: 1330) are stacked on the second substrate 1310 along a direction (Z-axis direction) perpendicular to the top surface of the second substrate 1310. A string selection line and a ground selection line are respectively arranged above and below the word lines 1330, and a plurality of word lines 1330 are arranged between the string selection line and the ground selection line.

[0121] The word lines 1330 have different widths along the X direction. As the distance from the first substrate 1210 in the peripheral circuit region PERI to a corresponding one of the word lines 1330 increases, the width of the corresponding one of the word lines 1330 increases. Similarly, as the distance from the second substrate 1310 in the cell region CELL to a corresponding one of the word lines 1330 increases, the width of the corresponding one of the word lines 1330 decreases.

[0122] In the bit line bonding region BLBA, the channel structure CH extends in a direction (Z-direction) perpendicular to the top surface of the second substrate 1310 and penetrates the word lines 1330, the string select lines, and the ground select lines. The channel structure CH includes a data storage layer, a channel layer, and a buried insulating layer, and the channel layer is electrically connected to a first metal layer 1350c and a second metal layer 1360c. For example, the first metal layer 1350c is a bit line contact, and the second metal layer 1360c is a bit line. In one embodiment, the bit line 1360c extends along a first direction (Y-axis direction) parallel to the top surface of the second substrate 1310.

[0123] The interlayer insulating layer 1315 is disposed on the second substrate 310 to cover the common source line 1320, the plurality of word lines 1330, the plurality of cell contact plugs 1340, the first metal layer (1350a, 1350b, 1350c), and the second metal layer (1360a, 1360b, 1360c), and includes an insulating material such as silicon oxide, silicon nitride, etc.

[0124] 19, the region where the channel structure CH, the bit line 1360c, etc. are arranged is defined as a bit line bonding region BLBA. The bit line 1360c is electrically connected to circuit elements 1220c that provide a page buffer 1393 in the peripheral circuit region PERI of the bit line bonding region BLBA. The bit line 1360c is connected to upper bonding metals (1371c, 1372c) in the peripheral circuit region PERI, and the upper bonding metals (1371c, 1372c) are connected to lower bonding metals (1271c, 1272c) that are connected to the circuit elements 1220c of the page buffer 1393.

[0125] In the word line bonding region WLBA, the word lines 1330 extend in a second direction (X-axis direction) perpendicular to the first direction and parallel to the top surface of the second substrate 1310, and are connected to a plurality of cell contact plugs (1341-1347: 1340). The word lines 1330 and the cell contact plugs 1340 are connected to each other through pads formed by extending at least some of the word lines 1330 to different lengths in the second direction. A first metal layer 1350b and a second metal layer 1360b are sequentially connected to the top of the cell contact plug 1340 connected to the word line 1330. In the word line bonding region WLBA, the cell contact plug 1340 is connected to the peripheral circuit region PERI via upper bonding metals (1371b, 1372b) of the cell region CELL and lower bonding metals (1271b, 1272b) of the peripheral circuit region PERI.

[0126] The cell contact plug 1340 is electrically coupled in the peripheral circuit region PERI to a circuit element 1220b that forms a row decoder 1394. In one embodiment, the operating voltage of the circuit element 1220b of the row decoder 1394 is different from the operating voltage of the circuit element 1220c that forms the page buffer 1393. As an example, the operating voltage of the circuit element 1220c that forms the page buffer 1393 is higher than the operating voltage of the circuit element 1220b that forms the row decoder 1394.

[0127] A common source line contact plug 1380 is disposed in the external pad bonding area PA. The common source line contact plug 1380 is formed of a conductive material such as metal, metal compound, or polysilicon, and is electrically connected to the common source line 1320. A first metal layer 1350a and a second metal layer 1360a are sequentially stacked on the common source line contact plug 1380. For example, the area where the common source line contact plug 1380, the first metal layer 1350a, and the second metal layer 1360a are disposed is defined as the external pad bonding area PA.

[0128] 19, a lower insulating film 1201 is formed under a first substrate 1210 to cover the lower surface of the first substrate 1210, and a first I / O pad 1205 is formed on the lower insulating film 1201. The first I / O pad 1205 is connected to at least one of a plurality of circuit elements (1220a, 1220b, 1220c) disposed in the peripheral circuit region PERI via a first I / O contact plug 1203 and is separated from the first substrate 1210 by the lower insulating film 1201. A side insulating film is disposed between the first I / O contact plug 1203 and the first substrate 1210 to electrically separate the first I / O contact plug 1203 from the first substrate 1210.

[0129] 19, an upper insulating film 1301 covering the upper surface of the second substrate 1310 is formed on the upper side of the second substrate 1310, and a second I / O pad 1305 is disposed on the upper insulating film 1301. The second I / O pad 1305 is connected to at least one of the plurality of circuit elements (1220a, 1220b, 1220c) disposed in the peripheral circuit region PERI via a second I / O contact plug 1303 and lower bonding metals (1271a, 1272a) of the peripheral circuit region PERI. In one embodiment, the second I / O pad 1305 is electrically connected to the circuit element 1220a.

[0130] According to an embodiment, the second substrate 1310 and the common source line 1320 are not disposed in the region where the second I / O contact plug 1303 is disposed. In addition, the second I / O pad 1305 does not overlap the word line 1330 in the third direction (Z-axis direction). Referring to FIG. 19, the second I / O contact plug 1303 is separated from the second substrate 1310 in a direction parallel to the top surface of the second substrate 1310 and is connected to the second I / O pad 1305 through the interlayer insulating layer 1315 of the cell region CELL.

[0131] Depending on the embodiment, the first I / O pads 1205 and the second I / O pads 1305 may be selectively formed. For example, the memory device 1400 may include only the first I / O pads 1205 disposed on the top of the first substrate 1210, or may include only the second I / O pads 1305 disposed on the top of the second substrate 1310. Alternatively, the memory device 1400 may include both the first I / O pads 1205 and the second I / O pads 1305.

[0132] In each of the external pad bonding area PA and bit line bonding area BLBA included in each of the cell area CELL and the peripheral circuit area PERI, a metal pattern provided in the uppermost metal layer exists as a dummy pattern, or the uppermost metal layer is empty.

[0133] In the memory device 1400, a lower metal pattern 1273a having the same cross-sectional shape as the upper metal pattern 1372a of the interconnected cell region CELL is formed in the uppermost metal layer of the peripheral circuit region PERI in the external pad bonding region PA, corresponding to the upper metal pattern 1372a formed in the uppermost metal layer of the cell region CELL. The lower metal pattern 1273a formed in the uppermost metal layer of the peripheral circuit region PERI is not connected to a separate contact in the peripheral circuit region PERI. Similarly, in the external pad bonding region PA, an upper metal pattern 1372a having the same shape as the lower metal pattern 1273a of the peripheral circuit region PERI may be formed in the upper metal layer of the cell region CELL in the external pad bonding region PA, corresponding to the lower metal pattern 1273a formed in the uppermost metal layer of the peripheral circuit region PERI.

[0134] Lower bonding metals 1271b and 1272b are formed on the second metal layer 1240b of the word line bonding region WLBA. In the word line bonding region WLBA, the lower bonding metals 1271b and 1272b of the peripheral circuit region PERI are electrically connected to the upper bonding metals 1371b and 1372b of the cell region CELL by Cu-to-Cu bonding.

[0135] In the bit line bonding region BLBA, an upper metal pattern 1392 having the same cross-sectional shape as the lower metal pattern 1252 in the peripheral circuit region PERI is formed in the uppermost metal layer of the cell region CELL, corresponding to the lower metal pattern 1252 formed in the uppermost metal layer of the peripheral circuit region PERI. No contact is formed on the upper metal pattern 1392 formed in the uppermost metal layer of the cell region CELL.

[0136] In one embodiment, a reinforcement metal pattern having the same cross-sectional shape as a metal pattern formed in a top metal layer of one of the cell region CELL and the peripheral circuit region PERI is formed in a top metal layer of the other of the cell region CELL and the peripheral circuit region PERI, and no contact pattern is formed in the reinforcement metal pattern.

[0137] In one embodiment, the memory device 1400 of FIG. 19 includes the nonvolatile memory device 100 described with reference to FIGS. 1 to 17. The cell region CELL and peripheral circuit region PERI of the nonvolatile memory device 100 described with reference to FIGS. 1 to 17 correspond to the cell region CELL and peripheral circuit region PERI of the memory device 1400 of FIG. 19. The bit line bonding region BLBA of FIG. 19 further includes bonding pads for dummy bit lines, and the dummy bit lines are electrically connected to dummy bit line drivers in the peripheral circuit region PERI through the additional bonding pads. The dummy bit line drivers in the peripheral circuit region PERI control the dummy bit lines according to the method described with reference to FIGS. 1 to 19. In one embodiment, the dummy bit line drivers are formed in the peripheral circuit region PERI so as to be physically separated or physically isolated from the page buffer 1393.

[0138] 20-22 are diagrams illustrating various stacked structures of a nonvolatile memory device according to an embodiment of the present invention. In one embodiment, the various memory structures described with reference to FIGS. 20-22 are the nonvolatile memory devices described with reference to FIGS. 1-19 or operate according to the methods described with reference to FIGS. 1-19. The number of memory structures described with reference to FIGS. 20-22 is merely an example, and the number of memory structures may be variously changed.

[0139] 20, a memory device 2000 includes a plurality of memory structures (2100-2400). The plurality of memory structures (2100-2400) are stacked in a direction perpendicular to a substrate. For example, a first memory structure 2100 is formed on a lower substrate (not shown), and a second memory structure 2200 is formed on top of the first memory structure 2100. A third memory structure 2300 is formed on top of the second memory structure 2200, and a fourth memory structure 2400 is formed on top of the third memory structure 2300.

[0140] Each of the plurality of memory structures (2100-2400) has a COP structure. For example, the first memory structure 2100 includes a first peripheral circuit 2110 and a first cell array 2120 formed above the first peripheral circuit 2110. Similarly, each of the second to fourth memory structures (2200-2400) includes second to fourth peripheral circuits (2210-2410) and second to fourth cell arrays (2220-2420) formed above the second to fourth peripheral circuits (2210-2410), respectively.

[0141] In one embodiment, each of the first to fourth cell arrays (2120 to 2420) includes dummy bit lines, and each dummy bit line is connected to a dummy bit line driver of a corresponding peripheral circuit. For example, the dummy bit lines of the first cell array 2120 are connected to the dummy bit line driver of the first peripheral circuit 2110, the dummy bit lines of the second cell array 2220 are connected to the dummy bit line driver of the second peripheral circuit 2210, the dummy bit lines of the third cell array 2320 are connected to the dummy bit line driver of the third peripheral circuit 2310, and the dummy bit lines of the fourth cell array 2420 are connected to the dummy bit line driver of the fourth peripheral circuit 2410. The dummy bit line drivers control the dummy bit lines according to the methods described with reference to FIGS. 1 to 19.

[0142] 21, a memory device 3000 includes a peripheral circuit 3001 and a plurality of cell arrays (3120-3420). Compared to the memory device 2000 of FIG. 10, the memory device 3000 of FIG. 21 does not have peripheral circuits between the plurality of cell arrays (3120-3420). For example, a peripheral circuit 3001 is formed on a lower substrate (not shown), a first cell array 3120 is formed above the peripheral circuit 3001, a second cell array is formed above the first cell array 3120, a third cell array 3320 is formed above the second cell array 3220, and a fourth cell array 3420 is formed above the third cell array 3320.

[0143] Each of the cell arrays 3120 to 3420 includes a metal layer for a word line, a bit line, or a dummy bit line. The dummy bit line of each of the cell arrays 3120 to 3420 is connected to a dummy bit line driver of the peripheral circuit 3001.

[0144] In one embodiment, a channel of a plurality of cell arrays (3120 to 3420) is shared by one channel, and in this case, cell strings sharing the same channel in a plurality of cell arrays (3120 to 3420) constitute one memory block.

[0145] 22, a memory device 4000 includes a plurality of memory structures 4100 to 4400. The memory structures 4100 to 4400 are stacked in a direction perpendicular to a substrate. Each of the memory structures 4100 to 4400 includes a peripheral circuit and a cell array bonded together using a bonding method, as described with reference to FIG. 19. For example, a first memory structure 4100 includes a first peripheral circuit 4110 and a first cell array 4120 formed on the first peripheral circuit 4110. The first peripheral circuit 4110 and the first cell array 4120 are electrically connected to each other using a bonding method, as described with reference to FIG. 19. Similarly, each of the second to fourth memory structures (4200 to 4400) includes second to fourth peripheral circuits (4210 to 4410) and second to fourth cell arrays (4220 to 4420) bonded to the upper portions of the second to fourth peripheral circuits (4210 to 4410) through a bonding method.

[0146] As described above, the nonvolatile memory device according to the present invention has various stacked structures. The nonvolatile memory device controls the dummy bit lines according to an operating state. Therefore, a nonvolatile memory device having improved reliability and performance can be provided.

[0147] Fig. 23 is a block diagram showing a memory system 5000 according to one embodiment of the present invention. Referring to Fig. 23, the memory system 5000 includes a memory controller 5100 and a memory device 5200. The memory device 5200 includes first to eighth pins (P11 to P18), a memory interface circuit 5210, a control logic circuit 5220, and a memory cell array 5230. The memory device 5200 is the non-volatile memory device described with reference to Figs. 1 to 22.

[0148] The memory interface circuit 5210 receives a chip enable signal nCE from the memory controller 5100 via the first pin P11. The memory interface circuit 5210 transmits and receives signals to and from the memory controller 5100 via the second to eighth pins (P12 to P18) in accordance with the chip enable signal nCE. For example, when the chip enable signal nCE is in an enabled state (for example, low level), the memory interface circuit 5210 transmits and receives signals to and from the memory controller 5100 via the second to eighth pins (P12 to P18).

[0149] The memory interface circuit 5210 receives a command latch enable signal CLE, an address latch enable signal ALE, and a write enable signal nWE from the memory controller 5100 via the second to fourth pins (P12 to P14). The memory interface circuit 5210 receives a data signal DQ from the memory controller 5100 via the seventh pin P17, and transfers the data signal DQ to the memory controller 5100. The memory interface circuit 5210 transmits a command CMD, an address ADDR, and data DATA via the data signal DQ. For example, the data signal DQ is transmitted via a plurality of data signal lines. In this case, the seventh pin P17 includes a plurality of pins corresponding to the plurality of data signals DQ.

[0150] The memory interface circuit 5210 acquires a command CMD from a data signal DQ received during an enable period (e.g., a high-level state) of the command latch enable signal CLE based on the toggle timing of the write enable signal nWE, and an address ADDR from a data signal DQ received during an enable period (e.g., a high-level state) of the address latch enable signal ALE based on the toggle timing of the write enable signal nWE.

[0151] In one embodiment, the write enable signal nWE toggles between a high level and a low level from a static state (e.g., a high level or a low level). For example, the write enable signal nWE toggles during the interval in which the command CMD or the address ADDR is transferred. Therefore, the memory interface circuit 5210 obtains the command CMD or the address ADDR based on the toggle timing of the write enable signal nWE.

[0152] The memory interface circuit 5210 receives a read enable signal nRE from the memory controller 5100 via a fifth pin P15. The memory interface circuit 5210 receives a data strobe signal DQS from the memory controller 5100 or sends a data strobe signal DQS to the memory controller 5100 via a sixth pin P16.

[0153] In a data DATA output operation of the memory device 5200, the memory interface circuit 5210 receives a read enable signal nRE that toggles via the fifth pin P15 before outputting the data DATA. The memory interface circuit 5210 generates a data strobe signal DQS that toggles based on the toggling of the read enable signal nRE. For example, the memory interface circuit 5210 generates a data strobe signal DQS that starts toggling after a predetermined delay (e.g., tDQSRE) based on the toggle start time of the read enable signal nRE. The memory interface circuit 5210 sends a data signal DQ containing data DATA based on the toggle timing of the data strobe signal DQS. This allows the data DATA to be transferred to the memory controller 5100 in accordance with the toggle timing of the data strobe signal DQS.

[0154] In a data DATA input operation of the memory device 5200, when a data signal DQ containing data DATA is received from the memory controller 5100, the memory interface circuit 5210 receives a data strobe signal DQS that toggles together with the data DATA from the memory controller 5100. The memory interface circuit 5210 acquires the data DATA from the data signal DQ based on the toggle timing of the data strobe signal DQS. For example, the memory interface circuit 5210 acquires the data DATA by sampling the data signal DQ at the rising and falling edges of the data strobe signal DQS.

[0155] The memory interface circuit 5210 transfers a ready / busy output signal nR / B to the memory controller 5100 via the eighth pin P18. The memory interface circuit 5210 transfers status information of the memory device 5200 to the memory controller 5100 through the ready / busy output signal nR / B. When the memory device 5200 is busy (i.e., when an internal operation of the memory device 5200 is being performed), the memory interface circuit 5210 sends a ready / busy output signal nR / B indicating the busy status to the memory controller 5100. When the memory device 5200 is ready (i.e., when an internal operation of the memory device 5200 is not being performed or has been completed), the memory interface circuit 5210 transfers a ready / busy output signal nR / B indicating the ready status to the memory controller 5100. For example, while the memory device 5200 is reading data DATA from the memory cell array 5230 in response to a page read command, the memory interface circuit 5210 sends a ready / busy output signal nR / B indicating a busy state (e.g., low level) to the memory controller 5100. For example, while the memory device 5200 is programming data DATA into the memory cell array 5230 in response to a program command, the memory interface circuit 5210 transfers a ready / busy output signal nR / B indicating a busy state to the memory controller 5100.

[0156] The control logic circuit 5220 controls various overall operations of the memory device 5200. The control logic circuit 5220 receives commands / addresses CMD / ADDR obtained from the memory interface circuit 5210. The control logic circuit 5220 generates control signals for controlling other components of the memory device 5200 according to the received commands / addresses CMD / ADDR. For example, the control logic circuit 5220 generates various control signals for programming data DATA to the memory cell array 5230 or reading data DATA from the memory cell array 5230.

[0157] The memory cell array 5230 stores the data DATA obtained from the memory interface circuit 5210 under the control of the control logic circuit 5220. The memory cell array 5230 outputs the stored data DATA to the memory interface circuit 5210 under the control of the control logic circuit 5220.

[0158] The memory cell array 5230 includes a plurality of memory cells. For example, the plurality of memory cells are flash memory cells. However, the present invention is not limited thereto, and the memory cells may be Resistive Random Access Memory (ReRAM) cells, Ferroelectric Random Access Memory (FeRAM) cells, Phase Change Random Access Memory (PRAM) cells, Thyristor Random Access Memory (TRAM) cells, or Magnetic Random Access Memory (MRAM) cells. The following describes embodiments of the present invention, focusing on an embodiment in which the memory cells are NAND flash memory cells.

[0159] The memory controller 5100 includes first to eighth pins (P21 to P28) and a controller interface circuit 5110. The first to eighth pins (P21 to P28) correspond to the first to eighth pins (P11 to P18) of the memory device 5200.

[0160] The controller interface circuit 5110 sends a chip enable signal nCE to the memory device 5200 via the first pin P21. The controller interface circuit 5110 transmits and receives signals to and from the memory device 5200 selected by the chip enable signal nCE via the second to eighth pins (P22 to P28).

[0161] The controller interface circuit 5110 transfers a command latch enable signal CLE, an address latch enable signal ALE, and a write enable signal nWE to the memory device 5200 via the second to fourth pins (P22 to P24). The controller interface circuit 5110 sends a data signal DQ to the memory device 5200 or receives a data signal DQ from the memory device 5200 via the seventh pin P27.

[0162] The controller interface circuit 5110 sends a data signal DQ including a command CMD or an address ADDR along with a toggling write enable signal nWE to the memory device 5200. The controller interface circuit 5110 transfers the data signal DQ including the command CMD to the memory device 5200 by sending a command latch enable signal CLE having an enable state, and transfers the data signal DQ including the address ADDR to the memory device 5200 by sending an address latch enable signal ALE having an enable state.

[0163] The controller interface circuit 5110 transfers a read enable signal nRE to the memory device 5200 via a fifth pin P25. The controller interface circuit 5110 receives a data strobe signal DQS from the memory device 5200 or transfers a data strobe signal DQS to the memory device 5200 via a sixth pin P26.

[0164] In a data DATA output operation of the memory device 5200, the controller interface circuit 5110 generates a toggling read enable signal nRE and transfers the read enable signal nRE to the memory device 5200. For example, the controller interface circuit 5110 generates a read enable signal nRE that is changed from a static state (e.g., high or low) to a toggle state before the data DATA is output. This causes the memory device 5200 to generate a data strobe signal DQS that toggles based on the read enable signal nRE. The controller interface circuit 5110 receives a data signal DQ containing data DATA together with the toggling data strobe signal DQS from the memory device 5200. The controller interface circuit 5110 obtains the data DATA from the data signal DQ based on the toggle timing of the data strobe signal DQS.

[0165] In a data DATA input operation of the memory device 5200, the controller interface circuit 5110 generates a toggling data strobe signal DQS. For example, the controller interface circuit 5110 generates a data strobe signal DQS that is changed from a static state (e.g., a high level or a low level) to a toggle state before transferring data DATA. The controller interface circuit 5110 transfers a data signal DQ containing data DATA to the memory device 5200 based on the toggle timing of the data strobe signal DQS.

[0166] The controller interface circuit 5110 receives a ready / busy output signal nR / B from the memory device 5200 via the eighth pin P28. The controller interface circuit 5110 determines the status information of the memory device 5200 based on the ready / busy output signal nR / B.

[0167] Although the embodiments of the present invention have been described in detail above with reference to the drawings, the present invention is not limited to the above-described embodiments and can be modified in various ways without departing from the technical concept of the present invention. [Explanation of symbols]

[0168] 10, 11 Erase voltage (VERS) generator 100 Non-volatile memory device 110 memory cell array 120 Address Decoder 130 Page buffer circuit 130-1 to 130-4 1st to 4th page buffer circuits 140 Input / Output (I / O) Circuit 150 Control logic and voltage generation circuit (control logic circuit) 160, 160a, 160b, 160c Dummy Bit Line (DBL) Drivers 160-1 to 160-4 1st to 4th dummy bit line drivers 1201, 1301 Lower and upper insulating films 1203, 1303 First and second input / output contact plugs 1205, 1305 1st and 2nd input / output pads 1210, 1310 1st and 2nd boards 1215, 1315 Interlayer insulation layer 1220a, 1220b, 1220c circuit elements 1230a, 1230b, 1230c First metal layer 1240a, 1240b, 1240c Second metal layer 1252, 1273a Lower metal pattern 1271a, 1272a Lower bonding metal 1271b, 1272b Lower bonding metal (second metal pad) 1271c, 1272c Lower bonding metal 1320 Common Source Line 1330, 1331-1338 Word Line 1340, 1341~1347 Cell Contact Plug 1350a, 1350b, 1350c First metal layer (bit line contact) 1360a, 1360b, 1360c Second metal layer (bit line) 1371a, 1372a Upper bonding metal (upper metal pattern) 1371b, 1372b Upper bonding metal (first metal pad) 1371c, 1372c Upper bonding metal 1380 Contact Plug 1392 Upper metal pattern 1393 page buffer 1394 Line Decoder 1400, 2000, 3000, 4000, 5200 memory devices 2100, 2200, 2300, 2400 1st to 4th memory structures 2110, 2210, 2310, 2410 1st to 4th peripheral circuits 2120, 2220, 2320, 2420 1st to 4th cell arrays 3001 Peripheral circuit 3120, 3220, 3320, 3420 1st to 4th cell arrays 4100, 4200, 4300, 4400 1st to 4th memory structures 4110, 4210, 4310, 4410 1st to 4th peripheral circuits 4120, 4220, 4320, 4420 1st to 4th cell arrays 5000 Memory System 5100 Memory Controller 5110 Controller Interface Circuit 5210 Memory Interface Circuit 5220 Control Logic Circuit 5230 Memory Cell Array ADDR Address ALE Address latch enable signal BL Bit Line BL_G1~BL_G3 1st~3rd bit line group BL_INH Bit line inhibit operation BL_PRECH Bit line precharge operation BL1~BL4 1st to 4th bit lines BLa, BLb bit lines BLBA Bit Line Bonding Area BLK Memory Block CAR Cell Core Region CELL Cell area CH Channel (structure) CL1 First conductive line CLE Command latch enable signal CMD command CNR1 to CNR3: First to third contact regions CS11, CS12, CS21, CS22 cell strings CSL Common Source Line CSL_1~CSL_4 1st~4th common source lines CT contact area CT1~CT6 1st~6th contact plugs CTRL control signal DATA DBL, DBL1, DBL2, DBL1a to DBL3a, DBL1b to DBL3b, DBLa, DBLb dummy bit lines DBL_DRV1, DBL_DRV2 First and second dummy bit line drive signals dBLK dummy memory block DMC1, DMC2 First and second dummy memory cells DQ data signal DQS data strobe signal DTPA dummy through plug area DWL1, DWL2 First and second dummy word lines ECT Erase Control Transistor ERS Erase Operation GND Ground voltage GSL Ground Select Line GSTa, GSTb ground selection transistor MC1 to MC8 1st to 8th memory cells ML Metal Layer MP mold pattern nCE Chip enable signal nR / B Ready / Busy output signal nRE enable signal nWE Write enable signal P11~P18 1st to 8th pins P21~P28 1st to 8th pins PA External Pad Bonding Area PERI Peripheral circuit (area) PGM Program operation RD Read operation SENSING Sensing operation SSL, SSL1a, SSL1b, SSL2a, SSL2b string selection lines SSTa, SSTb string select transistors SUB Semiconductor substrate SW1, SW2 First and second switches TP1, TP2, TP4 to TP6 1st, 2nd, 4th to 6th through plugs TPA1 to TPA3 First to third through plug areas V0~V2 0th~2nd voltage VBL1~VBL4 1st~4th bit line voltage VERI verification operation VERS Erase voltage VPGM Program voltage application operation VRD selection read voltage application operation WL Word Line WL1~WL8 1st to 8th word lines WL_SETUP Word line setup operation WLBA Word Line Bonding Area

Claims

1. 1. A non-volatile memory device, comprising: a plurality of bit lines connected to a plurality of cell strings; a common source line connected to the plurality of cell strings; at least one dummy bit line disposed between the plurality of bit lines and the common source line; a control logic circuit configured to generate at least one dummy bit line drive signal in response to a command from an external device; a dummy bit line driver configured to selectively provide a first voltage to the at least one dummy bit line in response to the at least one dummy bit line driving signal.

2. 2. The nonvolatile memory device of claim 1, wherein the dummy bit line driver comprises a first switch connected between the at least one dummy bit line and a first terminal receiving the first voltage and configured to operate in response to a first dummy bit line driving signal among the at least one dummy bit line driving signal.

3. The control logic circuit generating the first dummy bit line driving signal to turn on the first switch in response to the command not being an erase command; 3. The nonvolatile memory device of claim 2, configured to generate the first dummy bit line driving signal such that the first switch is turned off in response to the command being the erase command.

4. The dummy bit line driver a first switch connected between the at least one dummy bit line and a first terminal receiving the first voltage, the first switch configured to operate in response to a first dummy bit line driving signal among the at least one dummy bit line driving signal; 2. The nonvolatile memory device of claim 1, further comprising: a second switch connected between the at least one dummy bit line and the common source line and configured to operate in response to a second dummy bit line driving signal among the at least one dummy bit line driving signal.

5. The control logic circuit generating the first and second dummy bit line driving signals such that the first switch is turned on and the second switch is turned off in response to the command not being an erase command; 5. The nonvolatile memory device of claim 4, configured to generate the first and second dummy bit line drive signals such that the first switch is turned off and the second switch is turned on in response to the command being the erase command.

6. 10. The nonvolatile memory device of claim 1, further comprising: an erase voltage generator configured to generate an erase voltage during an erase operation and provide the erase voltage to the common source line, the bit line, or the common source line and the bit line.

7. The dummy bit line driver a first switch connected between the at least one dummy bit line and a first terminal receiving the first voltage, the first switch configured to operate in response to a first dummy bit line driving signal among the at least one dummy bit line driving signal; 7. The nonvolatile memory device of claim 6, further comprising: a second switch connected between the at least one dummy bit line and the erase voltage generator and configured to selectively provide the erase voltage from the erase voltage generator to the dummy bit line in response to a second dummy bit line driving signal among the at least one dummy bit line driving signal.

8. 2. The nonvolatile memory device of claim 1, wherein the first voltage is a ground voltage.

9. the dummy bit line driver is configured to apply a second voltage to the at least one dummy bit line while a precharge operation for the plurality of bit lines is being performed, and to provide the first voltage to the at least one dummy bit line while a sensing operation for the plurality of bit lines is being performed, when the command is a read command; 9. The nonvolatile memory device of claim 8, wherein the second voltage is a precharge voltage for the plurality of bit lines.

10. further comprising a page buffer circuit electrically connected to the plurality of bit lines; the page buffer circuit and the dummy bit line driver are formed in a peripheral circuit region on a semiconductor substrate; 2. The nonvolatile memory device of claim 1, wherein the plurality of cell strings, the plurality of bit lines, the common source line, and the at least one dummy bit line are formed in a memory cell region above the peripheral circuit region.

11. Each of the plurality of bit lines is electrically connected to the page buffer circuit via a first through plug that penetrates the memory cell region; 11. The nonvolatile memory device of claim 10, wherein the at least one dummy bit line is connected to the dummy bit line driver through at least one second via plug that penetrates the memory cell region.

12. the first through plug and the at least one second through plug are provided on a plane on which the page buffer circuit is formed; The first through plugs are formed at first intervals along a first direction, 12. The nonvolatile memory device of claim 11, wherein a distance between one of the first through plugs adjacent to the at least one second through plug along the first direction and the at least one second through plug is a second distance narrower than the first distance.

13. 1. A non-volatile memory device, comprising: a peripheral circuit formed on a semiconductor substrate; a memory cell array formed above the peripheral circuit and including a plurality of cell strings; a metal layer formed on the memory cell array; The metal layer is a plurality of bit lines connected to the plurality of cell strings; a common source line connected to the plurality of cell strings; at least one dummy bit line provided between the plurality of bit lines and the common source line; The peripheral circuit includes: a control logic circuit configured to generate at least one dummy bit line drive signal in response to a command from an external device; a dummy bit line driver configured to selectively provide a first voltage to the at least one dummy bit line in response to the at least one dummy bit line driving signal.

14. 14. The nonvolatile memory device of claim 13, wherein the peripheral circuits further comprise a page buffer circuit electrically connected to the plurality of bit lines.

15. The memory cell array a plurality of first through plugs formed in a direction perpendicular to the semiconductor substrate, the first through plugs being configured to electrically connect the plurality of bit lines and the page buffer circuit; 15. The nonvolatile memory device of claim 14, further comprising: at least one second through plug formed in a direction perpendicular to the semiconductor substrate, the second through plug being configured to electrically connect the at least one dummy bit line and the dummy bit line driver.

16. 16. The nonvolatile memory device of claim 15, wherein the plurality of first via plugs and the at least one second via plug are formed in a bit line contact region.

17. The control logic circuit In response to the command not being an erase command, generating the at least one dummy bit line drive signal to provide the first voltage to the at least one dummy bit line; 14. The nonvolatile memory device of claim 13, wherein the nonvolatile memory device is configured to generate the at least one dummy bit line drive signal such that, in response to the command being the erase command, the at least one dummy bit line is floated, the at least one dummy bit line is connected to the common source line, or an erase voltage is applied to the at least one dummy bit line.

18. 1. A method of operating a non-volatile memory device, comprising: receiving a read command from an external device; applying a first voltage to at least one dummy bit line located between a plurality of bit lines and a common source line in response to the read command; performing a read operation in response to the read command; receiving an erase command from the external device; floating the at least one dummy bit line, electrically connecting the at least one dummy bit line to the common source line, or applying an erase voltage to the at least one dummy bit line in response to the erase command; and performing an erase operation in response to the erase command.

19. the plurality of bit lines are connected to a page buffer circuit; 20. The method of claim 18, wherein the at least one dummy bit line is connected to a dummy bit line driver.

20. 20. The method of claim 18, wherein the erase operation includes applying the erase voltage to the common source line, the plurality of bit lines, or the common source line and the plurality of bit lines.

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