Split-gate flash memory cell with improved control gate capacitive coupling and method for fabricating same

Abstract

A method of forming a memory device includes forming a first insulating layer, a first conductive layer, and a second insulating layer in a semiconductor substrate, forming a trench in the second insulating layer to expose a top surface of the first conductive layer, performing an oxidation process and a sloped etch process to reshape the top surface into a concave shape, forming a third insulating layer on the reshaped top surface, forming a conductive spacer in the third insulating layer, removing a portion of the first conductive layer to leave a floating gate below the conductive spacer, where the reshaped top surface terminates at a sharp edge on a side, and forming a word line gate laterally adjacent to and insulated from the floating gate. The conductive spacer includes a bottom surface that faces and conforms to the reshaped top surface.

Description

[Technical Field]

[0001] (Priority Claim) This application claims priority to Chinese Patent Application No. 202110266241.0, filed March 11, 2021, entitled "Split-Gate Flash Memory Cell With Improved Control Gate Capacitive Coupling, And Method Of Making Same," and U.S. Patent Application No. 17 / 346,524, filed June 14, 2021, entitled "Split-Gate Flash Memory Cell With Improved Control Gate Capacitive Coupling, And Method Of Making Same."

[0002] FIELD OF THE INVENTION The present invention relates to non-volatile memory arrays. [Background technology]

[0003] Split-gate nonvolatile memory cells and arrays of such cells are well known. For example, U.S. Pat. No. 5,029,130 ​​(the "'130 patent") discloses an array of split-gate nonvolatile memory cells and is incorporated herein by reference for all purposes. Such memory cells are shown in FIG. 1. Each memory cell 10 includes a source region 14 / drain region 16 formed in a semiconductor substrate 12, with a channel region 18 therebetween. A floating gate 20 is formed above a first portion of the channel region 18 and is insulated from (and controls the conductivity of) the first portion of the channel region 18, and is also formed above a portion of the drain region 16. A control gate 22 has a first portion 22a disposed above (and insulated from) (and controls the conductivity of) the second portion of the channel region 18, and a second portion 22b extending above the floating gate 20. The floating gate 20 and control gate 22 are insulated from (and controls the conductivity of) the second portion of the channel region 18 by a gate oxide 26.

[0004] The memory cell is erased (electrons are removed from the floating gate 20) by applying a high positive voltage to the control gate 22, which causes electrons in the floating gate 20 to tunnel through the intermediate insulator 24 from the floating gate 20 to the control gate 22 by Fowler-Nordheim tunneling.

[0005] The memory cell is programmed by applying a positive voltage to the control gate 22 and a positive voltage to the drain region 16 (electrons are applied to the floating gate 20). An electron current flows from the source region 14 toward the drain region 16. When the electrons reach the gap between the control gate 22 and the floating gate 20, they accelerate and heat up. Some of the heated electrons are injected into the floating gate 20 through the gate oxide 26 due to electrostatic attraction from the floating gate 20.

[0006] A memory cell is read by applying a positive read voltage to the drain region 16 and control gate 22 (turning on the portion of the channel region 18 under the control gate 22). If the floating gate 20 is positively charged (i.e., erased of electrons and capacitively coupled with a positive voltage from the drain region 16), then the portion of the channel region 18 under the floating gate 20 will also be turned on and current will flow through the channel region 18, which is sensed as an erased state, or "1" state. If the floating gate 20 is negatively charged (i.e., programmed with electrons), the portion of the channel region 18 under the floating gate 20 will be mostly or completely off and no (or very little) current will flow through the channel region 18, which is sensed as a programmed state, or "0" state. Those skilled in the art will understand that the source and drain may be interchangeable, where the floating gate may extend partially above the source region 14 instead of the drain region 16, as shown in FIG. 2. Also shown in FIG. 2 is the floating gate 20 formed with a concave upper surface that terminates in sharp edges facing the control gate 22 at the sides of the floating gate 20 for better erase tunneling efficiency.

[0007] Split-gate memory cells having three or more gates are also known. For example, U.S. Patent No. 8,711,636 ("the '636 patent") (incorporated herein by reference for all purposes) discloses a memory cell having an additional coupling gate disposed above and insulated from the source region for better capacitive coupling to the floating gate. See, for example, FIG. 3, which shows a coupling gate 24 disposed above a source region 14.

[0008] A four-gate memory is disclosed in U.S. Patent No. 6,747,310 (the "'310 patent"), which is incorporated herein by reference for all purposes. For example, as shown in FIG. 4, a memory cell 10 has a source region 14 and a drain region 16 separated by a channel region 18, a floating gate 20 disposed above and insulated from a first portion of the channel region 18, a select gate 28 disposed above and insulated from a second portion of the channel region 18, a control gate 22 disposed above and insulated from the floating gate 20, and an erase gate 30 disposed above and insulated from the source region 14. Programming is indicated by heated electrons from the channel region 18 injecting themselves into the floating gate 20. Erasing is indicated by electrons tunneling from the floating gate 20 to the erase gate 30.

[0009] The memory cells of Figures 1 and 2 have been used successfully as flash memory in several technology nodes. They are relatively easy to implement in low-cost processes and exhibit excellent performance. The memory cell of Figure 4 has been used successfully as embedded flash in several advanced technology nodes. It has very good quality and a competitive cell size. The memory cell of Figure 3 is less complex than the memory cell of Figure 4 because it has one less gate in each cell.

[0010] As the size of memory cells 10 shrinks, it becomes more difficult to achieve the desired capacitive coupling between the floating gate and the control gate while avoiding undesirable capacitive coupling between the floating gate and other gates, which can adversely affect performance. A need exists for improved performance at a reasonable cost. Summary of the Invention

[0011] The aforementioned need is addressed by a semiconductor device that includes the steps of forming a first insulating layer on a top surface of a semiconductor substrate, forming a first conductive layer on the first insulating layer, forming a second insulating layer on the first conductive layer, forming a trench in the second insulating layer exposing a top surface portion of the first conductive layer, performing an oxidation process and a sloped etching process to reform the top surface portion of the first conductive layer at a bottom of the trench from a planar shape to a concave shape, forming a third insulating layer on the reformed top surface portion of the first conductive layer at the bottom of the trench, forming conductive spacers in the trench and on the third insulating layer, and removing a portion of the first conductive layer to leave a floating gate of the first conductive layer below the conductive layer spacers, the floating gate including a top surface portion having a concave shape that terminates at a sharp edge at a side of the floating gate, the conductive spacers facing the top surface portion of the floating gate. forming a word line laterally adjacent to and insulated from the floating gate; and forming spaced apart source and drain regions in the semiconductor substrate, with a channel region in the semiconductor substrate extending between the source and drain regions, wherein the floating gate is disposed above and insulated from a first portion of the channel region to control a conductivity of the first portion of the channel region, and the word line gate is disposed above and insulated from a second portion of the channel region to control a conductivity of the second portion of the channel region.

[0012] The memory cell includes: spaced-apart source and drain regions in a semiconductor substrate, with a channel region of the semiconductor substrate extending between the source and drain regions; a floating gate disposed above and insulated from a first portion of the channel region to control the conductivity of the first portion of the channel region, the floating gate including an upper surface portion having a concave shape terminating in a sharp edge at a side of the floating gate; a word line gate including a first portion disposed above and insulated from a second portion of the channel region to control the conductivity of a second portion of the channel region, the second portion disposed at least partially above the floating gate, and a notch facing the sharp edge of the floating gate; and a coupling gate disposed above and insulated from the floating gate, the coupling gate including a lower surface facing the upper surface of the floating gate, the lower surface having a shape corresponding to the concave shape of the upper surface of the floating gate, and insulated from the upper surface of the floating gate by an insulating layer of uniform thickness.

[0013] The memory cell includes: spaced-apart source and drain regions in a semiconductor substrate, with a channel region of the semiconductor substrate extending between the source and drain regions; a floating gate disposed above and insulated from a first portion of the channel region to control the conductivity of the first portion of the channel region, the floating gate including an upper surface portion having a concave shape terminating in sharp edges at sides of the floating gate; a word line gate disposed above and insulated from a second portion of the channel region to control the conductivity of a second portion of the channel region; a coupling gate disposed above and insulated from the floating gate, the coupling gate including a lower surface facing the upper surface of the floating gate, the lower surface having a shape matching the concave shape of the upper surface of the floating gate and insulated from the upper surface of the floating gate by an insulating layer of uniform thickness; and an erase gate disposed above and insulated from the floating gate and the coupling gate, the erase gate including a notch facing the sharp edges of the floating gate.

[0014] Other objects and features of the present invention will become apparent from a review of the specification, claims, and accompanying drawings.

[0015]

[0016]

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[0018]

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[0020]

[0021]

[0022]

[0023] [Brief explanation of the drawings]

[0024] [Figure 1] FIG. 1 is a cross-sectional view of a conventional two-gate memory cell. [Figure 2] FIG. 1 is a cross-sectional view of a conventional two-gate memory cell. [Figure 3] FIG. 1 is a cross-sectional view of a conventional three-gate memory cell. [Figure 4] FIG. 1 is a cross-sectional view of a conventional four-gate memory cell. [Figure 5] 10A to 10C are cross-sectional views illustrating steps for forming memory cell pairs. [Figure 6] 10A to 10C are cross-sectional views illustrating steps for forming memory cell pairs. [Figure 7] 10A to 10C are cross-sectional views illustrating steps for forming memory cell pairs. [Figure 8] 10A to 10C are cross-sectional views illustrating steps for forming memory cell pairs. [Figure 9] 10A to 10C are cross-sectional views illustrating steps for forming memory cell pairs. [Figure 10] 10A to 10C are cross-sectional views illustrating steps for forming memory cell pairs. [Figure 11] 10A to 10C are cross-sectional views illustrating steps for forming memory cell pairs. [Figure 12] 10A to 10C are cross-sectional views illustrating steps for forming memory cell pairs. [Figure 13] 10A to 10C are cross-sectional views illustrating steps for forming memory cell pairs. [Figure 14] 10A to 10C are cross-sectional views illustrating steps for forming memory cell pairs. [Figure 15] 10A to 10C are cross-sectional views illustrating steps for forming memory cell pairs. [Figure 16] FIG. 2 is a schematic diagram showing the configuration of an array of memory cell pairs. [Figure 17] 1 is a table of exemplary, non-limiting operating voltages and currents for memory cell pairs. [Figure 18] 10A-10C are cross-sectional views illustrating steps for forming memory cell pairs according to an alternative embodiment. [Figure 19] 10A-10C are cross-sectional views illustrating steps for forming memory cell pairs according to an alternative embodiment. [Figure 20]10A-10C are cross-sectional views illustrating steps for forming memory cell pairs according to an alternative embodiment. [Figure 21] 10A-10C are cross-sectional views illustrating steps for forming memory cell pairs according to an alternative embodiment. [Figure 22] FIG. 10 is a schematic diagram illustrating the configuration of an array of memory cell pairs according to an alternative embodiment. [Figure 23] 10 is a table of exemplary non-limiting operating voltages and currents for memory cell pairs according to an alternative embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0025] The present embodiment provides a novel memory cell design and method for fabricating the same. FIGS. 5-15 illustrate the formation of memory cells on a semiconductor substrate. While the formation of a pair of memory cells is shown in the figures and described below, it should be understood that simultaneous formation of multiple pairs of such memory cells may be performed. The process begins with the formation of a (first) insulating layer 42, such as silicon dioxide (referred to herein as "oxide"), on a top surface 40a of a semiconductor substrate 40, such as silicon. A (first) conductive layer 44, such as polysilicon, is formed on the insulating layer 42. As shown in FIG. 5, a (second) insulating layer 46, such as silicon nitride (referred to herein as "nitride"), is formed on the conductive layer 44.

[0026] As shown in FIG. 6 , a masking step is performed (i.e., photoresist 48 is deposited, portions of the photoresist 48 are selectively exposed, and then removed), followed by etching to form trenches 50 in the insulating layer 46 and expose the top surface portion 45 of the conductive layer 44 at the bottom of the trenches 50. The top surface portion 45 of the conductive layer 44 is planar. At this point, appropriate implants can be performed on the conductive layer 44. As shown in FIG. 7 , after removing the photoresist 48, multiple processes are performed to reshape the top surface portion 45 of the conductive layer 44 at the bottom of the trenches 50 from a planar shape to a curved, concave shape. Specifically, an oxidation process (e.g., thermal oxidation) is performed to oxidize the top surface portion 45 of the conductive layer 44 at the bottom of the trenches 50, with the oxidation consuming more of the conductive layer 44 at the center of the trenches 50 than near the sides of the trenches 50. An oxide etch is then performed to remove the oxidized portions of the oxide layer 44. A sloped etch process is then performed to remove material from conductive layer 44 at a faster rate in the center of trench 50 than near the sides of trench 50. The combination of the oxidation and sloped etch processes results in a large curvature in the top surface portion 45 of conductive layer 44 at the bottom of trench 50. It should be understood that the order of the processes can be reversed, whereby the sloped etch process is performed first, followed by the oxidation process.

[0027] Insulating spacers 52, also referred to as first insulating spacers 52, such as oxide, are formed on the sides of trench 50 by insulating deposition and insulating etching. Forming the spacers involves depositing material above the contours of the structure, followed by an anisotropic etching process, whereby material is removed from horizontal surfaces of the structure while material remains largely intact on vertically oriented surfaces of the structure (which often have rounded top surfaces). A (third) insulating layer 54, such as oxide, is formed on the structure by depositing insulating material, which also thickens spacers 52. At least a portion of insulating layer 54 on top surface portion 45 of conductive layer 44 has a uniform thickness. As shown in FIG. 8 , conductive spacers 56, such as polysilicon, are formed in trench 50 by deposition and etching. One or more etches are then performed to remove exposed portions of insulating layer 54, conductive layer 44, and insulating layer 42 from the bottom of trench 50 (i.e., between conductive spacers 56) to expose top surface 40 a of semiconductor substrate 40. The height of conductive spacers 56 is also reduced by these etches, in one example, so that the top surfaces of conductive spacers 56 are substantially level with the top surface of the portion of conductive layer 44 below insulating layer 46. An optional insulating layer may be formed on exposed top surface 40a of semiconductor substrate 40. An implant is then performed to form drain region 58 in semiconductor substrate 40 below trench 50, as shown in FIG.

[0028] Next, the trench 50 is filled with an insulating material 60, such as an oxide, by deposition, followed by etch-back or CMP (chemical mechanical polishing) to expose the insulating layer 46. Optionally, further etch-back is performed to lower the top surface of the insulating material 60 below the height defined by the insulating layer 46. Then, as shown in FIG. 10, an etch is performed to remove the insulating layer 46. Then, an anisotropic etch is performed to remove the exposed portions of the conductive layer 44. Optionally, a non-selective etch is performed to remove both the insulating material 60 and the conductive layer 44. In this case, the height of the insulating material 60 is reduced. An implant into the semiconductor substrate 40 can then be performed through the exposed portions of the insulating layer 42 to form word line channel implants. Then, as shown in FIG. 11, an etch is performed to remove the exposed portions of the insulating layer 42 and lower the top surface of the insulating material 60 (in one non-limiting example, to expose the conductive spacers 56, i.e., so that the top surface of the insulating material 60 is substantially flush with the top surfaces of the conductive spacers 56).

[0029] Insulating spacers 62, also referred to as second insulating spacers 62, such as oxide, are formed on the sides of the structure by deposition and etching. A (fourth) insulating layer 64, such as oxide, is formed on the structure (e.g., by depositing an insulating material), which also thickens the insulating spacers 62. As shown in FIG. 12, a (second) conductive layer 66, such as polysilicon, is formed on the insulating layer 64 and the insulating spacers 62. Photoresist 68 is formed above the conductive layer 66, and the photoresist 68 is removed except for blocks of the photoresist 68 positioned vertically above one of the sidewalls of the conductive layer 44. Etching is then performed to remove portions of the conductive layer 66 that are indirectly laterally adjacent to the conductive layer 44 and are not located under the photoresist 68, as shown in FIG. 13. After removal of the photoresist 68, an implant is performed to form a drain region 70 in the semiconductor substrate 40 adjacent to the remainder of the conductive layer 66. 14, the structure is coated with an insulating material 72, such as an interlayer dielectric (ILD) oxide, and contacts 74 extending through the insulating material 72 to the drain regions 70 are formed by masking steps, etching through the insulating material 72 to create contact holes exposing the drain regions 70, and filling the contact holes with a conductive material. Contacts are similarly formed to each of the conductive layer 66 and the conductive spacers 56, in one embodiment, simultaneously with the formation of the contacts 74.

[0030] The final memory cell structure is shown in Figure 15. A pair of memory cells 76 is formed, each memory cell 76 including a shared source region 58 and a respective drain region 70, a channel region 78 in the semiconductor substrate 40 extending between the shared source region 58 and the respective drain region 70, a floating gate 44a (remnant of conductive layer 44) disposed above a first portion of the channel region 78 and controlling its conductivity (and disposed above a portion of the source region 58), a word line gate 66a (remnant of conductive layer 66) disposed above a second portion of the channel region 78 and controlling its conductivity, and a coupling gate 56a (remnant of conductive spacer 56) disposed above the floating gate 44a. The floating gate 44a has a sloped, concave upper surface 44b (remnant of upper surface portion 45) that terminates at a side surface 44c with a sharp edge 44d. The coupling gate 56a has a lower surface 56b that conforms to the concave shape of the upper surface 44b of the floating gate 44a and is separated from the upper surface 44b by the remainder of the insulating layer 54. The word line gate 66a has a first portion 66b that is indirectly laterally adjacent to the floating gate 44a (and that is above and controls the conductivity of a second portion of the channel region 78), a second portion 66c that is at least partially above the floating gate 44a (i.e., there is at least some vertical overlap between the second portion 66c and the floating gate 44a) and at least partially above the coupling gate 56a (i.e., there is at least some vertical overlap between the second portion 66c and the coupling gate 56a), and a notch 66d (to enhance tunneling during erasure) that faces the sharp edge 44d of the floating gate 44a.

[0031] The architecture of a memory array formed of memory cells 76 is shown in FIG. 16. Pairs of memory cells 76 are arranged in rows and columns, with pairs of memory cells 76 formed end-to-end to form columns. For each row of memory cells 76, the word line gates 66a are formed as a continuous line connecting together all of the word line gates 66a across the entire row of memory cells 76, and the coupling gates 56a are formed as a continuous line connecting together all of the coupling gates 56a across the entire row of memory cells 76. For each row of memory cell pairs, the source regions 58 are formed as a continuous diffusion (or connected to a continuous line) connecting together all of the source regions 58 across the entire row of memory cell pairs 76. Each column of memory cells 76 includes a bit line 80 that electrically connects all of the contacts 74 (and therefore all of the drain regions 70) of all of the memory cells 76 in the column.

[0032] 17 shows illustrative, non-limiting examples of voltages and currents for read, erase, and program operations, respectively, for the various lines of FIG. 16 that are selected for operation and that either include (i.e., labeled "selected") or do not include (i.e., labeled "unselected") a memory cell 76. The selected memory cell 76 is erased (electrons are removed from the floating gate 44a) by applying a positive voltage to the word line gate 66a while maintaining zero voltages on each of the bit line 80, source region 58, and coupling gate 56a, thereby tunneling electrons from the floating gate 44a through the intermediate insulator to the word line gate 66 by Fowler-Nordheim tunneling. The entire row of memory cells 76 is erased simultaneously. The selected memory cell 76 is programmed (electrons are applied to the floating gate 44a) by applying a positive voltage to the word line gate 66a, coupling gate 56a, and source region 58. Electron current will flow from the source region 58 toward the drain region 70, and some of the electrons will be injected into the floating gate 44a through the intermediate insulator provided by the insulating layer 64. The selected memory cell 76 is read by applying a positive read voltage to the drain region 70 (connected to the bit line 80), the word line gate 66a (which turns on the channel region under the word line gate 66a), and the coupling gate 56a, and zero voltage to the source region 58. If the floating gate 44a is positively charged (erased), current will flow through the channel region 78, which is sensed as an erased state, or "1" state. If the floating gate 44a is negatively charged (programmed), no (or very little) current will flow through the channel region 78, which is sensed as a programmed state, or "0" state.

[0033] The memory cell 76 and its formation have many advantages. By conforming the bottom surface 56b of the coupling gate 56a to the top surface 44b of the floating gate 44a (due to the uniform thickness of the insulating layer 54 therebetween), capacitive coupling between the coupling gate 56a and the floating gate 44a is enhanced, improving read and program performance. The insulating spacer 62 can be formed thick enough to reduce capacitive coupling between the floating gate 44a and the word line gate 66a, improving read, program, and erase performance. There is no conductive gate between the floating gate 44a and the coupling gate 56a in the area above the source region 58, which could result in undesirable capacitive coupling between the gates of different memory cells 76 and / or the common source region 58. The use of both an oxidation process and a sloped etch process to form the floating gate 44a results in a more pronounced curved, or concave, shape (and therefore sharper edges 44d) for the top surface 44b of the floating gate 44a, improving erase performance. The sides of the floating gate 44a and the coupling gate 56a (facing away from the word line gate 66a and located above the source region 58) are self-aligned to each other (i.e., the side of the coupling gate 56a defines the location of the etching of the conductive layer 44 that occurs on the side of the floating gate 44a above the source region 58, see Figures 8-9).

[0034] 18-21 illustrate an alternative embodiment for forming a memory cell 76. This embodiment begins with the structure shown in FIG. 12 (after the formation of conductive layer 66). As shown in FIG. 18, an etch is performed to remove conductive layer 66 except for the (third) conductive spacer 66e of conductive layer 66. The etch is performed so that the top surface of conductive spacer 66e is recessed below the portion of insulating layer 64 of conductive spacer 56 by a recess amount "R." This recess amount R will result in an erase gate notch, as described further below. A (fifth) insulating layer 82, such as oxide, is formed on conductive spacer 66e (e.g., by deposition or thermal oxidation). A (third) conductive layer, such as polysilicon, is formed above the structure. Photoresist 86 is formed above the conductive layer, and all but the block of photoresist 86 located vertically above conductive spacer 56 and partially above conductive spacer 66e is removed. 19, an etch is then performed to remove portions of the conductive layer other than the blocks of conductive material 88 under the blocks of photoresist 86. After removal of photoresist 86, an implant is performed to form drain region 70 in substrate 40 adjacent conductive layer 82 of conductive spacer 66e. As shown in FIG. 20, the structure is covered with an insulating material 72, such as an ILD oxide, and a contact 74 extending through insulating material 72 to drain region 70 is formed by a masking step, etching through the insulating material to create a contact hole exposing drain region 70, and filling the contact hole with a conductive material. Contacts are similarly formed to each of conductive spacer 66e and conductive spacer 56, in one embodiment, simultaneously with the formation of contact 74.

[0035] The final memory cell structure of the alternative embodiment is shown in FIG. 21. It is similar to the memory cell structure shown in FIG. 15, except that the word line gate, conductive spacer 66e, is disposed laterally indirectly adjacent to the floating gate 44a (i.e., no portion partially overlies the floating gate 44a). Instead, the block of conductive material 88 is an erase gate that extends over both floating gates 44a of the pair of memory cells 76, over both coupling gates 56a, and at least partially over both word line gates formed with conductive spacer 66e (i.e., there is at least some vertical overlap between the erase gate formed with the block of conductive material 88 and the word line gate formed with conductive spacer 66e). The erase gate formed with the block of conductive material 88 includes a notch 88a facing the sharp edge 44d of the floating gate 44a (to enhance tunneling during erasure). This alternative embodiment is advantageous because it reduces capacitive coupling between the floating gate 44a and the word line gate formed of the conductive spacer 66e (because the word line gate formed of the conductive spacer 66e does not have a portion that extends over and above the floating gate 44a), provides efficient erasure due to the notch 88a facing the sharp edge 44d, and limits capacitive coupling between the floating gate 44a and the erase gate formed of the block of conductive material 88 due to the intervening coupling gate 56a while maintaining increased capacitive coupling between the floating gate 44a and the coupling gate 56a as described above.

[0036] The architecture of a memory array formed with memory cells 76 of an alternative embodiment is shown in Figure 22 and is similar to the architecture described above with respect to Figure 16, except that for each row of memory cell pairs, an erase gate formed of a block of conductive material 88 is formed as a continuous line connecting together all of the erase gates formed of blocks of conductive material 88 for the entire row of memory cell pairs. Figure 23 shows illustrative, non-limiting examples of voltages and currents for read, erase, and program operations, respectively, for various lines in Figure 22 that either include (i.e., labeled "selected") or do not include (i.e., labeled "unselected") memory cells 76 selected for operation. One operational difference in the alternative embodiment is that the positive voltage used to erase memory cells 76 is applied to the erase gate formed of a block of conductive material 88 rather than to the word gate line gate formed of conductive spacer 66e.

[0037] It will be understood that the claims are not limited to the above-described embodiments illustrated herein, but rather encompass all modifications falling within the scope of any claim. For example, references herein to embodiments and examples of the present invention are not intended to limit the scope of the claims or the terminology therein, but instead merely refer to one or more features that may be covered by one or more of the claims. The examples of materials, processes, and values ​​described above are merely examples and should not be construed as limiting the scope of the claims. Furthermore, as will be apparent from the claims and this specification, not all method steps need be performed in the exact order illustrated or claimed, but rather in any order that allows for the proper formation of the memory devices of the present invention. Finally, a single layer of material can be formed as multiple layers of such or similar materials, and vice versa.

[0038] It should be noted that, as used herein, the terms "over" and "on" both encompass "directly on" (with no intermediate material, element, or gap disposed therebetween) and "indirectly on" (with an intermediate material, element, or gap disposed therebetween). Similarly, the term "adjacent" includes "directly adjacent" (with no intermediate material, element, or gap disposed therebetween) and "indirectly adjacent" (with an intermediate material, element, or gap disposed therebetween); "attached" includes "directly attached" (with no intermediate material, element, or gap disposed therebetween) and "indirectly attached to" (with an intermediate material, element, or gap disposed therebetween); and "electrically coupled" includes "directly electrically coupled" (without an intermediate material, element, or gap electrically connecting the elements therebetween) and "indirectly electrically coupled" (with an intermediate material, element, or gap electrically connecting the elements therebetween). For example, forming an element "over a substrate" can include forming the element directly on the substrate without any intermediate materials / elements, or forming the element indirectly on the substrate through one or more intermediate materials / elements.

Claims

1. A method for forming a memory device, comprising: forming a first insulating layer on a top surface of a semiconductor substrate; forming a first conductive layer on the first insulating layer; forming a second insulating layer on the first conductive layer; forming a trench in the second insulating layer exposing a top surface portion of the first conductive layer; performing an oxidation process and a sloped etch process to reform the top surface portion of the first conductive layer from a planar shape to a concave shape at the bottom of the trench; forming a third insulating layer on the top surface portion of the first conductive layer reformed at the bottom of the trench; forming a conductive spacer in the trench and over the third insulating layer; removing a portion of the first conductive layer to leave a floating gate of the first conductive layer below the conductive spacer, the floating gate including the top surface portion with the concave shape terminating in sharp edges at sides of the floating gate; The conductive spacer includes a lower surface, the lower surface comprising: facing the top surface portion of the floating gate; having a shape that matches the concave shape of the top surface portion of the floating gate; insulated from the top surface portion of the floating gate by a portion of the third insulating layer having a uniform thickness; forming a word line gate laterally adjacent to and insulated from said floating gate; forming spaced apart source and drain regions in the semiconductor substrate and extending a channel region in the semiconductor substrate between the source and drain regions, the floating gate being disposed above and insulated from a first portion of the channel region to control a conductivity of the first portion of the channel region, and the word line gate being disposed above and insulated from a second portion of the channel region to control a conductivity of the second portion of the channel region; forming a block of conductive material above and insulated from the floating gate and the conductive spacer, the block of conductive material including a notch facing the sharp edge of the floating gate, and the block of conductive material further disposed at least partially above the word line gate.

2. A memory cell comprising: spaced apart source and drain regions in a semiconductor substrate, a channel region of the semiconductor substrate extending between the source and drain regions; a floating gate disposed above and insulated from a first portion of the channel region to control a conductivity of the first portion of the channel region, the floating gate including a top surface having a concave shape terminating in sharp edges at sides of the floating gate; a word line gate disposed above and insulated from the second portion of the channel region for controlling the conductivity of the second portion of the channel region; a coupling gate disposed above and insulated from the floating gate, the coupling gate including a lower surface, the lower surface comprising: facing the top surface of the floating gate; having a shape that matches the concave shape of the top surface of the floating gate; a coupling gate insulated from the top surface of the floating gate by an insulating layer of uniform thickness; an erase gate disposed above the floating gate and the coupling gate and insulated from the floating gate and the coupling gate, the erase gate including a notch facing the sharp edge of the floating gate, wherein the erase gate is further disposed at least partially above the word line gate.

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