Bias voltage adjustment approach for SiO / SiN layer alternating etching process

Abstract

The embodiments of the present disclosure generally relate to a method for etching a film stack with high selectivity and low etch recipe transition time. In one embodiment, a method for etching a film stack having a stacked pair of oxide and nitride layers is described. The method includes transferring a substrate having a film stack formed thereon into a process chamber, providing a first bias voltage to the substrate, etching an oxide layer of the film stack while providing the first bias voltage to the substrate, providing a second bias voltage to the substrate, the second bias voltage being greater than the first bias voltage, and etching a nitride layer of the film stack while providing the second bias voltage to the substrate.

Description

[Technical Field]

[0001] Embodiments of the present disclosure generally relate to methods for etching film stacks with high selectivity and low etch recipe transition times. [Background technology]

[0002] The fabrication of very large-scale integrated (VLSI) and ultra-large-scale integrated (ULSI) semiconductor devices involves the reliable fabrication of sub-micron features. However, as circuit technology continues to shrink, the size and pitch dimensions of circuit features, such as interconnects, place ever-increasing demands on processing power. To further increase device and interconnect density, the multi-level interconnects at the heart of this technology require precise imaging and placement of high-aspect-ratio features, such as vias and other interconnect structures. Additionally, there is a need to form sub-micron-sized features and interconnects while reducing waste of intermediate materials, such as resist and hard mask materials.

[0003] As feature sizes shrink, the demand for increased aspect ratios (defined as the ratio of feature depth to feature width) has steadily increased, reaching 10:1 and beyond. Achieving film stacks and etch processes capable of reliably forming features with such high aspect ratios presents significant challenges. Inaccurate control or low resolution of the lithographic exposure and development process can degrade the critical dimensions of the various layers utilized to transfer features into the film stack, resulting in unacceptable linewidth roughness (LWR). High linewidth roughness (LWR) and undesirable waviness profiles can lead to inaccurate feature transfer into the film stack and ultimately device failure and yield loss.

[0004] Furthermore, high etch selectivity is required to transfer features into multilayer film stacks. To achieve these high etch selectivities, different etch recipes, including different process gas chemistries and different chamber pressures, must be utilized for each different material layer to enable wide etch tuning. For example, in an alternating oxide-nitride film stack, different process gases flow into the chamber at different pressures to achieve high etch selectivity between layers. However, overall throughput and efficiency depend on long transition periods due to etch recipe changes, such as process gas recipe changes (i.e., flow rates, gas types, pressures, etc.) between the nitride layer etch step and the oxide layer etch step. Therefore, changing the etch recipe between layers reduces the overall throughput and efficiency of the process chamber.

[0005] Therefore, there is a need in the art for improved methods for etching multilayer film stacks. Summary of the Invention

[0006] In one embodiment, a method for etching a film stack having a laminated pair of oxide and nitride layers is described. The method includes transferring a substrate having the film stack formed thereon into a processing chamber, applying a first bias voltage to the substrate, etching the oxide layer of the film stack while applying the first bias voltage to the substrate, applying a second bias voltage to the substrate that is different from the first bias voltage, and etching the nitride layer of the film stack while applying the second bias voltage to the substrate. In one example, the second bias voltage is greater than the first bias voltage.

[0007] In another embodiment, a method for etching a film stack having a laminated pair of oxide and nitride layers is described. The method includes transferring a substrate having the film stack formed thereon into a process chamber, applying a C N F M , C X H Y F Zand an oxygen-containing gas, providing a first bias voltage to the substrate, etching a first oxide layer of the film stack while providing the first bias voltage to the substrate and while providing the process gas mixture to the substrate, providing a second bias voltage to the substrate different from the first bias voltage, etching a nitride layer of the film stack while providing the second bias voltage to the substrate and while providing the process gas mixture to the substrate, providing a third bias voltage to the substrate less than the second bias voltage, and etching a second oxide layer of the film stack while providing the third bias voltage to the substrate and while providing the process gas mixture to the substrate. In one embodiment, the second bias voltage is greater than the first bias voltage.

[0008] In yet another embodiment, a method for etching a film stack having a stacked pair of silicon oxide and silicon nitride layers is provided, the method comprising: transferring a substrate having the film stack formed thereon into a process chamber; N F M , C X H Y F Z and an oxygen-containing gas, wherein the oxygen-containing gas comprises about 25% to about 50% by volume of the process gas mixture; providing a first bias voltage to the substrate; etching a first silicon oxide layer of the film stack while providing the first bias voltage to the substrate and while providing the process gas mixture to the substrate; providing a second bias voltage to the substrate, different from the first bias voltage; etching a silicon nitride layer of the film stack while providing the second bias voltage to the substrate and while providing the process gas mixture to the substrate; providing the first bias voltage to the substrate; and etching a second silicon oxide layer of the film stack while providing the first bias voltage to the substrate and while providing the process gas mixture to the substrate. In one embodiment, the second bias voltage is greater than the first bias voltage.

[0009] So that the above-mentioned features of the present disclosure may be understood in detail, a more particular description of the present disclosure briefly summarized above can be had by reference to embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the accompanying drawings depict only exemplary embodiments and therefore should not be considered as limiting the scope of the present disclosure, which may also admit of other equally effective embodiments. [Brief explanation of the drawings]

[0010] [Figure 1] 1 shows a simplified cutaway schematic view of one example of a plasma processing chamber suitable for etching a film stack disposed on a substrate in accordance with one or more embodiments of the present disclosure. [Figure 2] 3A-3D illustrate a flow diagram of a method for performing an etching process on a film stack, such as that shown in FIGS. 3A-3D, in accordance with one or more embodiments of the present disclosure. [Figure 3A] 3A-3D illustrate various stages of a highly selective etching process for film stack 300 according to the method of FIG. [Figure 3B] 3A-3D illustrate various stages of a highly selective etching process for film stack 300 according to the method of FIG. [Figure 3C] 3A-3D illustrate various stages of a highly selective etching process for film stack 300 according to the method of FIG. [Figure 3D] 3A-3D illustrate various stages of a highly selective etching process for film stack 300 according to the method of FIG. DETAILED DESCRIPTION OF THE INVENTION

[0011] To facilitate understanding, identical elements common to the figures have been designated using identical reference numerals where possible. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.

[0012] The following disclosure describes highly selective membrane stack etching. Specific details are set forth in the following description and in FIGS. 1-4 to provide a thorough understanding of various embodiments of the present disclosure. To avoid unnecessarily obscuring the description of the various embodiments, other details describing well-known structures often associated with highly selective membrane stack etching are not set forth in the following disclosure. Additionally, the descriptions of the apparatus described herein are exemplary and should not be understood or interpreted as limiting the scope of the embodiments described herein.

[0013] Many of the details, steps, dimensions, angles, and other features shown in the drawings are merely illustrative of particular embodiments. Thus, other embodiments may have other details, components, dimensions, angles, and features without departing from the spirit and scope of the present disclosure. Furthermore, further embodiments of the present disclosure may be practiced without some of the details described below.

[0014] Embodiments of the present disclosure generally relate to a method for etching a film stack with high etch selectivity and low transition times when switching between etching different layers of the film stack. During conventional etching of a multilayer film stack, different etch recipes are required to etch each different material layer to achieve high etch selectivity between the different materials comprising the stack. However, the transition times for changing or altering etch recipe conditions reduce efficiency and overall throughput. According to embodiments of the present disclosure, a multilayer etch recipe for etching a multi-material film stack is disclosed. The multilayer etch recipe utilizes different bias voltages to etch the different materials comprising the multilayer film stack without substantially changing the process gas mixture, flow rates, or pressure to selectively etch the different materials in the multilayer film stack, while substantially reducing the time previously required to transition between etching different materials in the multilayer film stack. Because changing the bias voltage consumes less time than changing the pressure or process gas flow rates / chemistries for each different layer during a conventional etch process, the transition time between etching different materials is dramatically reduced, resulting in increased overall efficiency and throughput.

[0015] Although the particular apparatus in which embodiments described herein may be practiced is not limiting, embodiments are described as being practiced in a SYM3® and / or SYM3D® etch system available from Applied Materials, Inc. of Santa Clara, Calif. Alternatively, embodiments described herein may be practiced in other suitable apparatus, including those from other manufacturers.

[0016] 1 is a simplified cutaway schematic diagram of one embodiment of a plasma processing chamber 100 suitable for etching a film stack disposed on a substrate 102. The plasma processing chamber 100 includes a chamber body 105 having a processing space 101 defined therein. The chamber body 105 has sidewalls 112 and a bottom 118, which are electrically grounded 126. The dimensions of the chamber body 105 and associated components of the plasma processing chamber 100 are not limiting and can be larger in proportion to the size of the substrate 102 to be processed therein. Example substrate sizes include 200 mm diameter, 250 mm diameter, 300 mm diameter, and 450 mm diameter, among others.

[0017] The chamber body 105 supports a chamber lid assembly 110 to enclose the processing space 101. A substrate access port 113 is formed through a sidewall 112 of the chamber body 105 to facilitate transfer of the substrate 102 into and out of the plasma processing chamber 100. A pumping port 145 is defined through the chamber body 105 and connects to the processing space 101. A throttle valve 147 can be utilized to control the flow of gas out of the processing space 101 through the pumping port 145. As shown in FIG. 1 , the pumping port 145 is located in the lower chamber 118 below the substrate support pedestal 135 that supports the substrate 103 during processing. A gas panel 160 is coupled to the chamber body 105 by a gas line 167 to supply process gases into the processing space 101. The gas panel 160 includes one or more process gas sources 161, 162, 163, and 164, which may further include inert, non-reactive, and reactive gases. Examples of process gases that may be provided by the gas panel 160 include, but are not limited to, C2F4, C4F8, C3F6, C4F6, C M F N Containing gases, including CHF3, CH2F2, CH3F, C X H Y F ZThe process gas may include an oxygen-containing gas, including O2, H2O, H2O2, O3, N2O, NO2, and a hydrogen-containing gas, such as H2. Additionally, the process gas may include a halogen-containing gas, including Cl2, HCl, HF, F2, Br2, HCl, HBr, SF6, NF3, a passivation gas, including nitrogen (N2), carbonyl sulfide (COS), and sulfur dioxide (SO2), and an inert gas, including argon and helium. In some embodiments, the process gas may include a nitrogen-, chlorine-, fluorine-, oxygen-, and hydrogen-containing gas (e.g., BCl3, NF3, NH3, CO2, SO2, CO, N, among others). 2,、 NO2, N2O, and H2).

[0018] Valves 166 control the flow of process gases from sources 161, 162, 163, and 164 from a gas panel 160 and are managed by a controller 165. The flow of gases supplied from the gas panel 160 to the chamber body 105 may include a combination of gases (i.e., a process gas mixture or process gas). The chamber lid assembly 110 may include a nozzle 114. The nozzle 114 has one or more ports for introducing process gases from the sources 161, 162, 164, and 163 of the gas panel 160 into the processing space 101. After the process gases are introduced into the plasma processing chamber 100, energy is supplied to the gases to generate a plasma. An antenna 148, such as one or more inductor coils, may be provided adjacent to the plasma processing chamber 100, for example, above the lid assembly 110. A source power supply 142 provides source power via a matching network 141 to an antenna 148 to inductively couple energy, such as RF energy, to a process gas disposed in the processing space 101 to maintain a plasma generated from the process gas. Alternatively or in addition to the source power supply 142, process electrodes below and / or above the substrate 102 can be used to capacitively couple RF source power to the process gas to maintain a plasma in the processing space 101. The operation of the source power supply 142 is controlled by a system controller 165, which also controls the operation of other components in the plasma processing chamber 100.

[0019] As briefly mentioned above, a substrate support pedestal 135 is disposed within the process space 101 to support the substrate 102 during processing. As shown in FIG. 1 , the substrate support pedestal 135 is supported from the sidewalls 112 of the process chamber 100. The substrate support pedestal 135 may include an electrostatic chuck (ESC) 122 for holding the substrate 102 during processing. The ESC chuck 122 uses electrostatic attraction to hold the substrate 102 against the substrate support pedestal 135. The ESC 122 is powered by an RF power supply 125 integrated with a matching network 124. The ESC 122 has insulation 128 to reduce plasma attraction to the sidewalls of the ESC 122, thereby extending the maintenance life of the ESC 122. Additionally, the substrate support pedestal 135 may have a cathode liner 136 that protects the sidewalls of the substrate support pedestal 135 from plasma gases and extends the interval between maintenance of the plasma processing chamber 100 .

[0020] The substrate support pedestal 135 or ESC 122 includes an electrode 121 embedded in a dielectric. A bias power supply 150 is coupled to the electrode 121 to provide a bias voltage to the substrate 102. The bias voltage attracts ions present in a plasma generated from the process gas in the processing space 101, anisotropically etching the substrate 102 disposed on the ESC 122. The bias power supply 150 can provide a steady-state bias voltage, cycle the bias voltage on and off, or pulse the bias voltage during processing of the substrate 102. The bias power supply 150 can provide a bias voltage from about 0 kV to about 8 kV, such as from about 2 kV to about 8 kV, or from about 0 kV to about 3 kV.

[0021] A cover ring 130 is disposed on the ESC 122 along the periphery of the substrate support pedestal 135. The cover ring 130 is configured to protect the top surface of the substrate support pedestal 135 from the plasma environment inside the plasma of the processing chamber 100 during processing.

[0022] A system controller 165 can be utilized to control process sequences, regulating gas flow from the gas panel 160 into the plasma processing chamber 100, adjusting bias voltages from the bias power supply 150, and other process parameters. The system controller 165 further includes a processor, such as a CPU, and memory storage. In some embodiments, the memory storage can store, and the processor can execute, the methods described herein. When executed by the CPU, the software routines transform the CPU into a special-purpose computer (controller) that controls the plasma processing chamber 100, thereby performing etching processes as described herein in accordance with the present disclosure. The software routines may also be stored and / or executed by a second controller (not shown) located with the plasma processing chamber 100.

[0023] FIG. 2 is a flow diagram of a method 200 for performing an etching process on a film stack, such as that shown in FIGS. 3A-3D, in accordance with multiple embodiments of the present disclosure. The method 200 may be stored as a software routine in the memory of the system controller 165 or otherwise accessed by the system controller 165, which, in turn, executes the software routine to cause the plasma processing chamber 100 to perform the method. FIGS. 3A-3D illustrate various stages of a highly selective etching process on a film stack 300 in accordance with the method 200. In some embodiments, the film stack 300 has alternating oxide-nitride layers. For example, there may be more than 128 pairs of oxide-nitride layers. The method 200 begins at step 210 by transferring a substrate 102 into an etching processing system, such as the processing chamber 100 described above. The substrate 102 includes the film stack 300 and an etch mask 360. An etch mask 360 is disposed over the film stack 300 to facilitate etching of exposed openings 362 in the film stack 300 formed through the etch mask 360. The etch mask 360 may be a photoresist layer, a hard mask layer, a combination of a photoresist layer and a hard mask layer, or any other layer or layers suitable for masking the film stack 300 for pattern transfer by etching.

[0024] The film stack 300 includes stacked pairs of alternating layers. As shown in FIG. 3A , each pair of alternating layers includes an oxide layer 304 and a nitride layer 306. For convenience, only a total of two pairs of alternating layers 304 and 306 are shown in FIG. 3 . In some embodiments, five or more pairs of alternating layers 304 and 306 are included in the film stack 300. For example, about four or more pairs of alternating layers may be present in the film stack 300, such as about 16 or more pairs of alternating layers, such as about 32 or more pairs, about 64 or more pairs, about 128 or more pairs, or about 256 or more pairs of alternating layers.

[0025] Each layer 304 and 306 may be about 10 nanometers (nm) to about 40 nm thick, for example, about 20 nm to about 30 nm thick. The combined thickness of the alternating layers 304 and 306 of a pair may be about 40 nm to about 16 micrometers (μm). In some embodiments of the alternating pair, the nitride layer 306 may be above the oxide layer 304. In other embodiments of the alternating pair, the oxide layer 304 may be above the nitride layer 306. In one example, the oxide layer 304 is silicon oxide and the nitride layer 306 is silicon nitride.

[0026] In step 220, the process gas mixture flows into the processing chamber 100 at a substantially constant chamber pressure and source power. As used herein, "substantially constant" and "substantially the same" mean within about ±5% of the compared value. In some embodiments, the pressure in the processing chamber 100 is from about 10 mTorr to about 40 mTorr, e.g., from about 15 mTorr to about 35 mTorr, or from about 20 mTorr to 30 mTorr. In some embodiments, the source power from the source power supply 142 can be from about 500 watts (W) to about 3000 W, e.g., from about 1000 W to about 2500 W, or from about 1500 W to about 2000 W. It is contemplated that the source power may be adjusted during the method 200 to assist in selective etching of the film stack 300.

[0027] In some embodiments, a process gas mixture can be selected based on the dissociation energies of selected species at different bias voltages. Gases with specific dissociation energies at different bias voltages can be useful for etching two or more materials depending on the bias voltage applied. In some embodiments, the process gas mixture includes a process gas containing carbon and fluorine, used in combination with a process gas containing carbon, hydrogen, and fluorine, and a process gas containing oxygen. For example, process gas C M F Y and process gas C X H Y F ZThe first gas mixture comprises about 10% to about 50%, for example about 10% to about 40%, for example about 10% to about 30%, for example 20% to about 30% C by volume. M F Y In some embodiments, C M F Y and C X H Y F Z The process gas mixture containing also contains oxygen. M F Y , C X H Y F Z The process gas mixture of nitrogen and oxygen may contain about 10% to about 60% oxygen by volume, for example, about 25% to about 50% oxygen, for example, about 30% to about 45% oxygen, for example, about 35% to about 40% oxygen. The amount of oxygen provided in the process gas mixture depends on the pattern and application of the etching process. Source power energizes the process gas mixture into a plasma. As used herein, "oxygen" may be used to refer to any oxygen-containing gas disclosed herein.

[0028] In step 230, the bias power supply 150 provides a first bias voltage to the electrode 121. The electrode 121 attracts ions in a plasma generated by the process gas in the processing space 101 to the substrate 102 disposed on the ESC 122. In some embodiments, the first bias power is between about 0 kilovolts (kV) and about 3 kV, e.g., between about 1 kV and about 2 kV. In step 240, the oxide layer 304 is etched through the openings 362 formed in the etch mask 360 while providing the first bias from step 230 to the substrate 102 and the process gas from step 220 to create a plurality of features 308 and expose the surface 310 of the nitride layer 306, as shown in FIG. 3B . In some embodiments, the first bias voltage achieves an oxide-to-silicon nitride selectivity of about 2 or greater, e.g., about 3 or greater, e.g., about 3.2 or greater. Step 240 is performed until an endpoint for etching the layer 304 is reached. The endpoint may be determined in any suitable manner, such as by timed etching, optical emission spectroscopy (OES), laser interferometry, or the like.

[0029] In step 250, after the endpoint is detected, the bias power supply 150 provides a second bias voltage to the electrode 121. The second bias voltage is different from the first bias voltage. In one example, the second bias voltage is greater than the first bias voltage. The second bias voltage can be higher if the material layer being etched has a higher binding energy. In some embodiments, the second bias voltage is about 2 kV to about 8 kV, e.g., about 3 kV to about 7 kV, e.g., about 4 kV to about 6 kV, e.g., about 5 kV. In step 260, while providing the second bias from step 250 to the substrate 102 and the process gas from step 220, the exposed surface 310 of the nitride layer 306 is etched through the opening 362 formed in the etch mask 360 to expose the surface 312 of the oxide layer 304, as shown in FIG. 3C . In some embodiments, the second bias voltage achieves a silicon nitride-oxide etch selectivity of about 1 or greater, e.g., about 1.2 or greater, e.g., about 1.4 or greater. In some embodiments, the first or second bias voltage is absolute zero. In other embodiments, the first or second bias voltage is closer to zero relative to a higher voltage. For example, a first bias voltage of less than 1 kV can be considered zero compared to a second bias voltage of about 2 kV or about 4 kV.

[0030] In optional step 270, steps 230 through 260 are repeated, etching oxide layer 304 and nitride layer 306 at the first and second bias voltages, respectively, until surface 314 of substrate 102 is exposed, as shown in FIG. 3D. Alternatively, steps 230 through 260 can be repeated a fixed number of times.

[0031] It is contemplated that nitride-oxide films may be etched in a manner similar to that described herein, in which case the second bias voltage may be less than the first bias voltage.

[0032] According to several embodiments of the present disclosure, a universal etch recipe may be utilized in combination with changes in bias voltage to a substrate upon which a multilayer film stack is disposed to selectively etch the multilayer film stack with reduced etch recipe transition times. Because changing the bias voltage takes less time than changing the pressure or process gas flow / chemistry during etching, shorter etch recipe transition times are required between etch steps, which may improve overall chamber efficiency and throughput. As shown herein, the etch recipe transition time may be reduced by as much as 50%, resulting in a 100% improvement in overall throughput.

[0033] While the foregoing is directed to implementations of the present disclosure, other and further implementations of the present disclosure may be devised without departing from the basic scope thereof, the scope of which is defined by the claims that follow.

Claims

1. 1. A method for etching a film stack having a laminated pair of oxide and nitride layers, comprising: transporting the substrate having the film stack formed thereon into a processing chamber; providing a first bias voltage to the substrate; etching an oxide layer of the film stack with a first process gas recipe while providing the first bias voltage to the substrate; providing a second bias voltage to the substrate that is greater than the first bias voltage; and etching a nitride layer of the film stack with the first process gas recipe while providing the second bias voltage to the substrate.

2. The method of claim 1 , wherein providing the second bias voltage occurs after etching the oxide layer of the film stack.

3. 10. The method of claim 1, wherein the oxide layer of the film stack is silicon oxide (SiO) and the nitride layer of the film stack is silicon nitride (SiN).

4. 4. The method of claim 3, wherein the first bias voltage is from about 0 kV to about 3 kV and the second bias voltage is from about 2 kV to about 8 kV.

5. providing a process gas mixture to the substrate, the process gas mixture comprising: N F M , C X H Y F Z and oxygen.

6. 6. The method of claim 5, wherein the oxygen comprises about 25% to about 50% by volume of the process gas mixture.

7. 6. The method of claim 5, wherein the composition of the process gas mixture remains substantially the same during the etching of the oxide layer and the etching of the nitride layer.

8. Said C N F M Gas is C 2 F 4 , C 4 F 8 , C 3 F 6 , and C 4 F 6 wherein C is selected from the group consisting of X H Y F Z Gas is CHF 3 , C.H. 2 F 2 , and C.H. 3 6. The method of claim 5, wherein the hydroxyl group is selected from the group consisting of:

9. 10. The method of claim 1, wherein the oxide layer and the nitride layer are each about 20 nm to about 30 nm thick.

10. 1. A method for etching a film stack having a laminated pair of oxide and nitride layers, comprising: transporting the substrate having the film stack formed thereon into a process chamber; The substrate is N F M , C X H Y F Z providing a process gas mixture comprising: providing a first bias voltage to the substrate; etching a first oxide layer of the film stack while providing the first bias voltage to the substrate and while providing the process gas mixture to the substrate; providing a second bias voltage to the substrate that is greater than the first bias voltage; etching a nitride layer of the film stack while providing the second bias voltage to the substrate and while providing the process gas mixture to the substrate; providing a third bias voltage to the substrate that is less than the second bias voltage; and etching a second oxide layer of the film stack while providing the third bias voltage to the substrate and while providing the process gas mixture to the substrate.

11. 11. The method of claim 10, wherein the oxide layer of the film stack is silicon oxide (SiO) and the nitride layer of the film stack is silicon nitride (SiN).

12. 12. The method of claim 11, wherein the first bias voltage is from about 0 kV to about 3 kV and the second bias voltage is from about 2 kV to about 8 kV.

13. 13. The method of claim 12, wherein the first bias voltage is about 0 kV and the second bias voltage is about 2 kV.

14. 14. The method of claim 13, wherein etching the oxide layer achieves an oxide-to-silicon nitride etch selectivity of about 3.2 or greater.

15. 14. The method of claim 13, wherein etching the nitride layer achieves a silicon nitride-to-oxide etch selectivity of about 1.4 or greater.

16. Said C N F M Gas is C 2 F 4 , C 4 F 8 , C 3 F 6 , and C 4 F 6 wherein C is selected from the group consisting of X H Y F Z Gas is CHF 3 , C.H. 2 F 2 , and C.H. 3 11. The method of claim 10, wherein the hydroxyl group is selected from the group consisting of: F.

17. The method of claim 10 , wherein the first bias voltage and the second bias voltage increase as the aspect ratio increases.

18. 1. A method for etching a film stack having a laminated pair of silicon oxide and silicon nitride layers, comprising: transporting the substrate having the film stack formed thereon into a process chamber; The substrate is N F M , C X H Y F Z and oxygen, wherein the oxygen comprises about 25% to about 50% by volume of the process gas mixture; providing a first bias voltage to the substrate; etching a first silicon oxide layer of the film stack while providing the first bias voltage to the substrate and while providing the process gas mixture to the substrate; providing a second bias voltage to the substrate that is greater than the first bias voltage; etching a silicon nitride layer of the film stack while providing the second bias voltage to the substrate and while providing the process gas mixture to the substrate; providing the first bias voltage to the substrate; and etching a second silicon oxide layer of the film stack while providing the first bias voltage to the substrate and while providing the process gas mixture to the substrate.

19. 20. The method of claim 18, wherein providing the second bias voltage occurs after etching the first silicon oxide layer of the film stack.

20. 20. The method of claim 18, wherein the first bias voltage and the second bias voltage increase as the aspect ratio increases.

21. The method of claim 1, wherein the first process gas recipe includes an etching gas type, flow rate, and pressure.

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