Semiconductor device and manufacturing method thereof

Abstract

To provide a semiconductor device capable of obtaining stable characteristics and a method for manufacturing the same.SOLUTION: According to one embodiment, a semiconductor device includes first, second, and third electrodes, a semiconductor member, and an insulating member. The semiconductor member includes first, second, third, fourth, fifth, and sixth semiconductor regions. The fifth semiconductor region includes a fourth partial region and a fifth partial region. The fourth partial region is located between a first partial region of the first semiconductor region and the third electrode. The fifth partial region is located between a third partial region of the first semiconductor region and the fourth semiconductor region.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] For example, stable characteristics are desired in semiconductor devices such as transistors. [Prior art documents] [Non-patent literature]

[0003] [Non-Patent Document 1] 2019 IEEE International Electron Devices Meeting, IEDM 2019. Institute of Electrical and Electronics Engineers Inc., 2019. 8993596 (Technical Digest - International Electron Devices Meeting, IEDM; Vol. 2019-December). Summary of the Invention [Problem to be solved by the invention]

[0004] The embodiments of the present invention provide a semiconductor device and a method for manufacturing the same that can provide stable characteristics. [Means for solving the problem]

[0005] According to an embodiment of the present invention, a semiconductor device includes a first electrode, a second electrode, a third electrode, a semiconductor member, and an insulating member. The direction from the first electrode to the second electrode is along a first direction. The third electrode is located between the first electrode and the second electrode. The semiconductor member includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, a fourth semiconductor region of the first conductivity type, a fifth semiconductor region of the second conductivity type, and a sixth semiconductor region of the second conductivity type. The first semiconductor region includes a first partial region, a second partial region, and a third partial region. The first partial region is located between the first electrode and the third electrode in the first direction. A second direction from the first partial region to the second partial region intersects with the first direction. The third partial region is located between the second partial region and the second electrode in the first direction. The second semiconductor region is provided between the third partial region and the second electrode. The second semiconductor region includes a first semiconductor portion. The third semiconductor region is provided between the first semiconductor portion and the second electrode and is electrically connected to the second electrode. The fourth semiconductor region is provided between the third partial region and the second semiconductor region in the first direction. The fifth semiconductor region includes a fourth partial region and a fifth partial region. The fourth partial region is located between the first partial region and the third electrode in the first direction. The fifth partial region is located between the third partial region and the fourth semiconductor region in the first direction. The direction from a portion of the third electrode to the fifth partial region is along the second direction. The fifth partial region is continuous with the fourth partial region. The sixth semiconductor region is provided between the first electrode and the first semiconductor region. The insulating member includes a first insulating region. The first insulating region is provided between the semiconductor member and the third electrode. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a schematic cross-sectional view illustrating the semiconductor device according to the first embodiment. [Figure 2] FIG. 2 is a schematic cross-sectional view illustrating the semiconductor device according to the first embodiment. [Figure 3]3(a) and 3(b) are graphs illustrating the semiconductor device according to the first embodiment. [Figure 4] 4A to 4C are schematic cross-sectional views illustrating the method for manufacturing the semiconductor device according to the second embodiment. [Figure 5] 5A to 5C are schematic cross-sectional views illustrating the method for manufacturing the semiconductor device according to the second embodiment. [Figure 6] 6A to 6C are schematic cross-sectional views illustrating the method for manufacturing the semiconductor device according to the second embodiment. [Figure 7] 7A to 7C are schematic cross-sectional views illustrating the method for manufacturing the semiconductor device according to the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments of the present invention will be described with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the size ratio between parts, etc. are not necessarily the same as those in reality. Even when the same part is shown, the dimensions and ratios may be different depending on the drawing. In this specification and in each drawing, elements similar to those previously described with reference to the previous drawings are designated by the same reference numerals, and detailed descriptions thereof will be omitted where appropriate.

[0008] (First embodiment) FIG. 1 is a schematic cross-sectional view illustrating the semiconductor device according to the first embodiment. As shown in FIG. 1, the semiconductor device 110 according to the embodiment includes a first electrode 51, a second electrode 52, a third electrode 53, a semiconductor member 10M, and an insulating member 40.

[0009] The direction from the first electrode 51 to the second electrode 52 is along the first direction D1. The first direction D1 is defined as the Z-axis direction. The direction perpendicular to the Z-axis direction is defined as the X-axis direction. The direction perpendicular to the Z-axis direction and the X-axis direction is defined as the Y-axis direction.

[0010] The third electrode 53 is located between the first electrode 51 and the second electrode 52 .

[0011] The semiconductor member 10M includes a first semiconductor region 11 of a first conductivity type, a second semiconductor region 12 of a second conductivity type, a third semiconductor region 13 of the first conductivity type, a fourth semiconductor region 14 of the first conductivity type, a fifth semiconductor region 15 of the second conductivity type, and a fifth semiconductor region 15 of the second conductivity type.

[0012] For example, the first conductivity type is n-type and the second conductivity type is p-type. In an embodiment, the first conductivity type may be p-type and the second conductivity type may be n-type. In the following, the first conductivity type is assumed to be n-type and the second conductivity type is assumed to be p-type.

[0013] The first semiconductor region 11 is, for example, n - The first semiconductor region 11 is a base layer. The first semiconductor region 11 includes, for example, a first partial region 11a, a second partial region 11b, and a third partial region 11c. The first partial region 11a is located between the first electrode 51 and the third electrode 53 in the first direction D1. A second direction D2 from the first partial region 11a to the second partial region 11b intersects with the first direction D1. The second direction D2 is, for example, the X-axis direction. The region that overlaps with the third electrode 53 in the first direction D1 corresponds to the first partial region 11a. The second partial region 11b does not overlap with the third electrode 53 in the first direction D1.

[0014] The third partial region 11c is located between the second partial region 11b and the second electrode 52 in the first direction D1. When the first electrode 51 is used as a reference, the height of the third partial region 11c is greater than the height of the second partial region 11b. When the first electrode 51 is used as a reference, the height of the third partial region 11c is greater than the height of the first partial region 11a.

[0015] At least a portion of the second semiconductor region 12 is, for example, a p-base layer. The second semiconductor region 12 is provided between the third partial region 11c and the second electrode 52. The second semiconductor region 12 includes a first semiconductor portion 12a. The first semiconductor portion 12a is, for example, a p-base layer. As shown in FIG. 1, the second semiconductor region 12 may further include a second semiconductor portion 12b.

[0016] The third semiconductor region 13 is, for example, an n-emitter layer. The third semiconductor region 13 is provided between the first semiconductor portion 12a and the second electrode 52 in the first direction D1. The third semiconductor region 13 is electrically connected to the second electrode 52.

[0017] The fourth semiconductor region 14 is, for example, an n-barrier layer. The fourth semiconductor region 14 is provided between the third partial region 11c and the second semiconductor region 12 in the first direction D1.

[0018] The fifth semiconductor region 15 is, for example, a p-barrier layer. The fifth semiconductor region 15 includes a fourth partial region 15d and a fifth partial region 15e. The fourth partial region 15d is located between the first partial region 11a and the third electrode 53 in the first direction D1. The fifth partial region 15e is located between the third partial region 11c and the fourth semiconductor region 14 in the first direction D1. The direction from a part of the third electrode 53 to the fifth partial region 15e is along the second direction D2.

[0019] As shown in FIG. 1 , the third electrode 53 includes an end 53a and another end 53b. The end 53a is located between the first electrode 51 and the second electrode 52 in the first direction D1. The other end 53b is located between the end 53a and the second electrode 52 in the first direction D1. For example, when the height of the first electrode 51 is used as a reference, the height of at least a portion of the fifth partial region 15e may be higher than the height of the end 53a of the third electrode 53. The fifth partial region 15e is continuous with the fourth partial region 15d. For example, the direction from at least a portion of the fourth partial region 15d to at least a portion of the third partial region 11c is along the second direction D2.

[0020] The sixth semiconductor region 16 is, for example, a p-collector layer. The sixth semiconductor region 16 is provided between the first electrode 51 and the first semiconductor region 11. For example, the sixth semiconductor region 16 may be electrically connected to the first electrode 51. For example, the sixth semiconductor region 16 may be in contact with the first electrode 51. The first electrode 51 may include a first surface 51f. The first surface 51f faces the sixth semiconductor region 16. A first direction D1 intersects with the first surface 51f. The first direction D1 is, for example, perpendicular to the first surface 51f.

[0021] 1, the insulating member 40 includes a first insulating region 41. The first insulating region 41 is provided between the semiconductor member 10M and the third electrode 53. The first insulating region 41 electrically insulates the semiconductor member 10M from the third electrode 53. The first insulating region 41 may include a first insulating portion 41a. The first insulating portion 41a is provided between the fourth partial region 15d and the third electrode 53 in the first direction D1.

[0022] For example, the first insulating region 41 may include second insulating portions 41b that are provided in the second direction D2 between the third electrode 53 and the third semiconductor region 13, between the third electrode 53 and the second semiconductor region 12, between the third electrode 53 and the fourth semiconductor region 14, and between the third electrode 53 and the fifth partial region 15e.

[0023] For example, the current flowing between the first electrode 51 and the second electrode 52 can be controlled by the potential of the third electrode 53. The potential of the third electrode 53 may be, for example, a potential based on the potential of the second electrode 52. The first electrode 51 is, for example, a collector electrode. The second electrode 52 is, for example, an emitter electrode. The third electrode 53 is, for example, a gate electrode. The semiconductor device 110 is, for example, an IGBT (Insulated Gate Bipolar Transistor). At least a part of the second insulating portion 41b may function as a gate insulating film. The semiconductor device 110 is, for example, a power semiconductor switching element.

[0024] 1, for example, a trench 10T is provided in a semiconductor member 10M. A third electrode 53 is provided inside the trench 10T. A fourth partial region 15d of the fifth semiconductor region 15 is provided below the trench 10T. A fifth partial region 15e of the fifth semiconductor region 15 is provided in a region where the trench 10T is not provided. A fourth semiconductor region 14, a second semiconductor region 12, and a third semiconductor region 13 are provided in this order on the fifth partial region 15e.

[0025] The semiconductor device 110 is provided with the fifth semiconductor region 15. This stabilizes the operation, for example, in a region corresponding to the area under the third electrode 53, as will be described below. For example, avalanche that tends to occur at the bottom of the trench 10T can be suppressed. According to the embodiment, a semiconductor device that can obtain stable characteristics can be provided. According to the embodiment, for example, breakdown can be suppressed.

[0026] For example, in the on-state of an IGBT, a positive bias is applied to the gate voltage, which causes electrons to flow from the n-emitter layer to the n-type - On the other hand, holes are injected into the base layer from the p collector layer. - It is injected into the base layer, which results in the on-state. In IGBTs, it is desirable to increase the current density in order to increase the current. For example, the current density can be increased by increasing the area of ​​the current path per unit area. However, increasing the current density can easily cause element destruction. For example, when the IGBT is turned off, a dynamic avalanche occurs in the IGBT, causing an overcurrent to continue to flow. This can cause element destruction.

[0027] For example, in the first reference example, a floating (independent) p-layer is provided at the bottom of the trench 10T. In the first reference example, at the time of turn-off, the floating p-layer and n - A depletion layer extends from the junction with the base layer, which alleviates the electric field concentration at the bottom of the trench 10T. In the first reference example, it was found that avalanche is likely to occur at the bottom of the trench 10T when the device is turned off.

[0028] On the other hand, in the second reference example, the p-layer having a uniform thickness including the bottom of the trench 10T is - In the second reference example, the p-type layer is provided in a region away from the bottom of the trench 10T, and the n-type layer is provided in a region away from the bottom of the trench 10T. -Depletion occurs at the junction with the base layer. In the second reference example, it is thought that the electric field concentration at the bottom of the trench 10T is alleviated. In the second reference example, which employs a uniform p-layer, it is not easy in practice to form a uniform p-layer. For example, when the trench 10T is deep, ion implantation at high acceleration is required to form the p-layer. For example, ion implantation for a long time is required. In the second reference example, for example, diffusion by high-temperature annealing is required. In the second reference example, if an attempt is made to increase the impurity concentration (carrier concentration) at the bottom of the trench 10T, the impurity concentration (carrier concentration) of the p-layer other than the bottom of the trench 10T also increases accordingly. For this reason, in order to fully alleviate the electric field concentration, electrons must pass from the n-barrier layer through the p-barrier layer to the n-barrier layer. - This makes it difficult for the ions to be injected into the base layer, which increases the on-state voltage.

[0029] In the embodiment, instead of providing a uniform p-layer, the fourth partial region 15d and the fifth partial region 15e are provided. For example, the impurity concentration (carrier concentration) profile in the fourth partial region 15d can be controlled independently of the impurity concentration (carrier concentration) profile in the fifth partial region 15e. For example, the fourth partial region 15d can effectively suppress electric field concentration. An increase in on-resistance can be suppressed.

[0030] For example, at the time of turn-off, the fourth partial region 15d (part of the p-barrier layer) and the first partial region 11a (n - For example, at turn-off, depletion occurs between the fifth partial region 15e (another part of the p-barrier layer) and the third partial region 11c (n - Depletion begins at the junction between the trench 10T and another part of the base layer. Depletion occurs at a position away from the bottom of the trench 10T. Electric field concentration is alleviated, and breakdown resistance is improved.

[0031] In the embodiment, the profile of the impurity concentration (carrier concentration) in the thickness direction in the fourth partial region 15d may be independent of the profile of the impurity concentration (carrier concentration) in the thickness direction in the fifth partial region 15e. For example, as described below, impurities for forming the fourth partial region 15d are introduced into the bottom of the trench 10T. Separately, impurities for forming the fifth partial region 15e are introduced. According to the embodiment, even if the trench 10T is deep, the semiconductor device 110 can be manufactured in a short time. According to the embodiment, a semiconductor device with stable characteristics can be manufactured with high productivity.

[0032] In the embodiment, for example, the first semiconductor region 11 may be in contact with the sixth semiconductor region 16. For example, the fifth semiconductor region 15 may be in contact with the first semiconductor region 11. For example, the fourth semiconductor region 14 may be in contact with the fifth semiconductor region 15. For example, the second semiconductor region 12 may be in contact with the fourth semiconductor region 14. For example, the third semiconductor region 13 may be in contact with the second semiconductor region 12. The second electrode 52 may be in contact with the third semiconductor region 13.

[0033] For example, the concentration of the third impurity of the first conductivity type in the third semiconductor region 13 is higher than the concentration of the first impurity of the first conductivity type in the first semiconductor region 11. The first semiconductor region 11 is an n - The third semiconductor region 13 is an n-layer or n + The first impurity concentration is, for example, 1×10 10 cm -3 More than 1×10 15 cm -3 The third impurity concentration is, for example, 1×10 16 cm -3 More than 1×10 20 cm -3 The following is the result.

[0034] For example, the concentration of the fourth impurity of the first conductivity type in the fourth semiconductor region 14 may be higher than the concentration of the first impurity of the first conductivity type in the first semiconductor region 11. The fourth semiconductor region 14 may be, for example, an n-layer. The fourth impurity concentration may be, for example, 1×10 12 cm-3 More than 1×10 17 cm -3 The following is the result.

[0035] 1, the second semiconductor region 12 may further include a second semiconductor portion 12b. The third semiconductor region 13 is located between the third electrode 53 and the second semiconductor portion 12b in the second direction D2. The second semiconductor portion 12b is electrically connected to the second electrode 52. The second semiconductor portion 12b is, for example, a p-contact layer.

[0036] For example, the impurity concentration of the second conductivity type in the second semiconductor portion 12b (second semiconductor portion impurity concentration) is higher than the impurity concentration of the second conductivity type in the first semiconductor portion 12a (first semiconductor portion impurity concentration). The first semiconductor portion impurity concentration is, for example, 1×10 15 cm -3 More than 1×10 18 cm -3 The second semiconductor portion impurity concentration is, for example, 1×10 16 cm -3 More than 1×10 20 cm -3 The following is the result.

[0037] For example, the impurity concentration of the second conductivity type in the sixth semiconductor region 16 (sixth impurity concentration) may be higher than the impurity concentration of the second conductivity type in the fifth semiconductor region 15 (fifth impurity concentration, for example, average concentration). The sixth semiconductor region 16 may be, for example, a p layer or a p + The sixth impurity concentration may be, for example, 1×10 15 cm -3 More than 1×10 20 cm -3 The following is the result.

[0038] In the embodiment, the semiconductor member 10M includes silicon, and may include SiC or GaN.

[0039] 1, the insulating member 40 may further include a second insulating region 42. The second insulating region 42 is located between the third electrode 53 and the second electrode 52 in the first direction D1.

[0040] 1, a plurality of third electrodes 53 may be provided. For example, the direction from one of the plurality of third electrodes 53 to another of the plurality of third electrodes 53 is along the second direction D2. For example, the plurality of third electrodes 53 may extend along the Y-axis direction.

[0041] Some of the multiple third electrodes 53 may be dummy electrodes. The potential of the dummy electrodes may be the same as the potential of the second electrodes 52 (for example, emitter electrodes). For example, this can reduce switching losses (for example, turn-on losses).

[0042] FIG. 2 is a schematic cross-sectional view illustrating the semiconductor device according to the first embodiment. 2 shows the semiconductor device 110 illustrated in FIG. 1. As shown in FIG. 2, the semiconductor member 10M may include a first boundary b1 and a second boundary b2. The first boundary b1 is located between the first partial region 11a and the fourth partial region 15d in the first direction D1. The second boundary b2 is located between the third partial region 11c and the fifth partial region 15e in the first direction D1.

[0043] These boundaries are between the first semiconductor region 11 and the fifth semiconductor region 15. The first boundary b1 overlaps with the third electrode 53 in the first direction D1. The second boundary b2 does not overlap with the third electrode 53 in the first direction D1. The second boundary b2 overlaps with the fourth semiconductor region 14, the second semiconductor region 12, and the third semiconductor region 13.

[0044] 2, the distance along the first direction D1 between the first electrode 51 and the first boundary b1 is defined as a first distance d1. The distance along the first direction D1 between the first electrode 51 and the second boundary b2 is defined as a second distance d2. In the embodiment, the first distance d1 is shorter than the second distance d2. The position in the depth direction of the boundary between the first semiconductor region 11 and the fifth semiconductor region 15 changes in the second direction D2 in accordance with the third electrode 53.

[0045] For example, as will be described later, the impurity concentration becomes minimum at the first boundary b1 in the depth direction at a position that passes through the third electrode 53. For example, as will be described later, the impurity concentration becomes minimum at the second boundary b2 in the depth direction at a position that does not pass through the third electrode 53.

[0046] In the embodiment, for example, the concentration of the second conductivity type impurities in at least a part of the fourth partial region 15d is higher than the concentration of the second conductivity type impurities in at least a part of the fifth partial region 15e. For example, in the fifth semiconductor region 15 including the fourth partial region 15d and the fifth partial region 15e, the concentration of the second conductivity type impurities may be maximum in the fourth partial region 15d.

[0047] For example, dynamic avalanche is likely to occur at the bottom of the trench 10T. When the impurity concentration in the fourth partial region 15d is higher than the impurity concentration in the fifth partial region 15e, for example, a high breakdown voltage and a low on-voltage can be easily obtained.

[0048] An example of the impurity concentration in the semiconductor member 10M will be described below.

[0049] 3(a) and 3(b) are graphs illustrating the semiconductor device according to the first embodiment. In FIG. 3(a), the impurity concentration profile along the line A1-A2 in FIG. 2 is illustrated by a solid line. In FIG. 3(a), the impurity concentration profile along the line B1-B2 in FIG. 2 is illustrated by a dashed line. In FIG. 3(b), the impurity concentration profile along the line B1-B2 in FIG. 2 is illustrated by a solid line. In FIG. 3(b), the impurity concentration profile along the line A1-A2 in FIG. 2 is illustrated by a dashed line. The horizontal axis in these figures represents the position pZ in the Z-axis direction (depth direction). The vertical axis represents the impurity concentration CC1. The line A1-A2 passes through the third electrode 53 and extends along the first direction D1. The line B1-B2 passes through the fourth semiconductor region 14, the second semiconductor region 12, and the third semiconductor region 13 and extends along the first direction D1.

[0050] As shown in FIGS. 3(a) and 2, the fourth partial region 15d includes a first position p1. The first position p1 is located between the first partial region 11a and the third electrode 53 in the first direction D1. The first position p1 may be any one position in the fourth partial region 15d. As shown in FIGS. 3(b) and 2, the fifth partial region 15e includes a second position p2. The second position p2 may be one position in the fifth partial region 15e. In this example, the direction from the third position p3 to the second position p2 is along the second direction D2.

[0051] 3(a) and 3(b), the first-position impurity concentration Cp1 of the second conductivity type at the first position p1 is higher than the second-position impurity concentration Cp2 of the second conductivity type at the second position p2. Thus, the impurity concentration of the second conductivity type in at least a part of the fourth partial region 15d is higher than the impurity concentration of the second conductivity type in the fifth partial region 15e.

[0052] As shown in FIG. 3(a), for example, the concentration of the second conductivity type impurities in the fourth partial region 15d is highest at the first position p1 in the first direction D1.

[0053] For example, when the first position impurity concentration Cp1 is the maximum value of the impurity concentration, the first position impurity concentration Cp1 may be, for example, 1.5 times or more and 100 times or less the second position impurity concentration Cp2.

[0054] 3A and 2, the fourth partial region 15d may include a third position p3. The third position p3 is located between the first position p1 and the third electrode 53 in the first direction D1. A third-position impurity concentration Cp3 of the second conductivity type at the third position p3 may be lower than the first-position impurity concentration Cp1.

[0055] For example, the direction from the third position p3 to the second position p2 is along the second direction D2 (see FIG. 2). For example, the third-position impurity concentration Cp3 may be lower than the second-position impurity concentration Cp2. For example, the second-position impurity concentration Cp2 may be between two and 100 times the third-position impurity concentration Cp3.

[0056] 3(b) and 2, the fifth partial region 15e may include a fourth position p4. The direction from the fourth position p4 to the second position p2 is along the first direction D1. For example, the fourth position p4 is located between the third partial region 11c and the second position p2. The direction from the first position p1 to the fourth position p4 is along the second direction D2. As shown in FIG. 3(b), the second-position impurity concentration Cp2 is higher than the fourth-position impurity concentration Cp4 of the second conductivity type at the fourth position p4.

[0057] When the first-position impurity concentration Cp1 is the maximum value of the impurity concentration, the first-position impurity concentration Cp1 may be, for example, from 2 to 1000 times the fourth-position impurity concentration Cp4, and the second-position impurity concentration Cp2 may be, for example, from 2 to 1000 times the fourth-position impurity concentration Cp4.

[0058] As shown in FIGS. 3(a) and 2, the fourth partial region 15d may include a fifth position p5. The fifth position p5 is located between the first partial region 11a and the third position p3 in the first direction D1. As shown in FIGS. 3(b) and 2, the third partial region 11c may include a sixth position p6. The sixth position p6 is located between the sixth semiconductor region 16 and the fourth position p4 in the first direction D1. The direction from the fifth position p5 to the sixth position p6 is along the second direction D2.

[0059] As shown in Fig. 3(a), the fifth-position impurity concentration of the second conductivity type at the fifth position p5 may be lower than the third-position impurity concentration Cp3. As shown in Fig. 3(b), the sixth-position impurity concentration of the first conductivity type at the sixth position p6 may be lower than the fourth-position impurity concentration Cp4.

[0060] (Second embodiment) The second embodiment relates to a method for manufacturing a semiconductor device. 4 to 7 are schematic cross-sectional views illustrating the method for manufacturing the semiconductor device according to the second embodiment. 4, a first semiconductor member 11F that will become the first semiconductor region 11 of the first conductivity type is prepared. The first semiconductor member 11F contains, for example, silicon. The first semiconductor member 11F is, for example, n -The first semiconductor member 11F may be a silicon substrate. A mask member 11M is formed on a portion of the first semiconductor member 11F. For example, a film that becomes the mask member 11M may be formed from TEOS (Tetraethoxysilane) or the like. A portion of the film that becomes the mask member 11M is removed by, for example, photolithography and etching. As a result, an opening is formed in the mask member 11M.

[0061] 5, a portion of the first semiconductor member 11F is removed using the mask member 11M as a mask. As a result, a trench 10T is formed in the first semiconductor member 11F. The removal of the portion of the first semiconductor member 11F is performed by, for example, dry etching.

[0062] After that, an insulating film 45 is formed inside the trench 10T. The insulating film 45 may be formed by, for example, thermal oxidation. The thickness of the insulating film 45 may be, for example, 10 nm or more and 80 nm or less.

[0063] As shown in FIG. 6, second conductivity type impurities 18p are introduced into the bottom of the trench 10T. The region 15a into which the second conductivity type impurities 18p are introduced corresponds to at least a part of the fourth partial region 15d. The second conductivity type impurities 18p are, for example, boron. The introduction of the impurities 18p is performed by, for example, ion implantation. The introduction of the impurities 18p may be performed into the entire first semiconductor member 11F.

[0064] In this way, the impurities 18p of the second conductivity type are introduced into the bottom of the trench 10T provided in the first semiconductor member 11F, which will become the first conductivity type first semiconductor region 11. The impurities 18p are then activated by heat treatment, thereby forming at least a part of the fourth partial region 15d. After the introduction of the impurities 18p, the insulating film 45 may be removed.

[0065] 7, a first insulating region 41 (insulating member 40) is formed inside the trench 10T. The first insulating region 41 may be formed by thermal oxidation. The first insulating region 41 may also be formed by, for example, CVD.

[0066] The remaining space inside the trench 10T is filled with a conductive material. The conductive material may be, for example, polysilicon. The third electrode 53 is formed by the conductive material.

[0067] 7, the other portion 11A of the first semiconductor member 11F is a region (e.g., a mesa region) where the trench 10T is not formed. Impurities of the second conductivity type and impurities of the first conductivity type are introduced into the other portion 11A of the first semiconductor member 11F. For example, boron is introduced, phosphorus is introduced, and boron is introduced. Activation is performed by heat treatment.

[0068] In this way, a fifth semiconductor region 15 of the second conductivity type, a fourth semiconductor region 14 of the first conductivity type, and a second semiconductor region 12 of the second conductivity type (e.g., first semiconductor portion 12a) are obtained from the other portion 11A. As a result, the first semiconductor region 11 is obtained. The fifth semiconductor region 15 is located on the first semiconductor region 11. The fourth semiconductor region 14 is located on the fifth semiconductor region 15. The second semiconductor region 12 is located on the fourth semiconductor region 14. The introduction of impurities for forming the fourth semiconductor region 14 may be omitted. In this case, the impurity concentration of the first conductivity type in the fourth semiconductor region 14 may be the same as the impurity concentration in the first semiconductor region 11.

[0069] Thereafter, impurities of the first conductivity type are introduced to form a third semiconductor region 13 of the first conductivity type. Activation is performed by heat treatment. The third semiconductor region 13 is located on at least a portion of the second semiconductor region 12. For example, impurities of the second conductivity type may be introduced to form a second semiconductor portion 12b.

[0070] After this, the second electrode 52 is formed. The second electrode 52 is electrically connected to the third semiconductor region 13. The second electrode 52 may be electrically connected to the second semiconductor portion 12b.

[0071] A sixth semiconductor region 16 of the second conductivity type and a first electrode 51 are formed. The sixth semiconductor region 16 is located between the first electrode 51 and the first semiconductor region 11. By this method, the semiconductor device 110 can be manufactured.

[0072] In the embodiment, the fourth partial region 15d of the fifth semiconductor region 15 and the fifth partial region 15e of the fifth semiconductor region 15 are formed separately. The impurity concentrations in these regions can be appropriately set. This allows an efficient method for manufacturing a semiconductor device that can obtain stable characteristics.

[0073] In the embodiment, at least one of the first electrode 51 and the second electrode 52 includes, for example, at least one selected from the group consisting of Al, Ti, Ni, W, and Au. The third electrode 53 may include, for example, polysilicon. The insulating member 40 may include, for example, silicon and oxygen. The insulating member 40 may include, for example, silicon oxide.

[0074] In some embodiments, information about the length and thickness may be obtained by electron microscope observation, etc. In some embodiments, the impurity concentration may be a carrier concentration. In some embodiments, the impurity concentration may be a concentration corresponding to the doping amount of impurities. Information about the distribution and absolute value of the impurity concentration in the semiconductor region may be obtained by, for example, secondary ion mass spectrometry (SIMS). The relative relationship between the impurity concentrations in two semiconductor regions may be determined by, for example, scanning capacitance microscopy (SCM). Information about the distribution and absolute value of the impurity concentration may be obtained by, for example, spreading resistance analysis (SRA). SCM and SRA may provide information about, for example, the relative relationship and absolute value of the carrier concentrations in the semiconductor region. For example, by assuming an activation rate of the impurities, the measurement results of SCM and SRA may provide information about at least one of the relative relationship between the impurity concentrations in two semiconductor regions, the distribution of the impurity concentrations, and the absolute value of the impurity concentrations.

[0075] Embodiments may include the following features. (Configuration 1) A first electrode; a second electrode, the direction from the first electrode to the second electrode being along a first direction; a third electrode, the third electrode being between the first electrode and the second electrode; A semiconductor member, comprising: a first semiconductor region of a first conductivity type, the first semiconductor region including a first partial region, a second partial region, and a third partial region, the first partial region being between the first electrode and the third electrode in the first direction, a second direction from the first partial region to the second partial region intersecting the first direction, and the third partial region being between the second partial region and the second electrode in the first direction; a second semiconductor region of a second conductivity type, the second semiconductor region being provided between the third partial region and the second electrode, the second semiconductor region including a first semiconductor portion; a third semiconductor region of the first conductivity type, the third semiconductor region being provided between the first semiconductor portion and the second electrode and electrically connected to the second electrode; a fourth semiconductor region of the first conductivity type, the fourth semiconductor region being provided between the third partial region and the second semiconductor region in the first direction; a fifth semiconductor region of the second conductivity type, the fifth semiconductor region including a fourth partial region and a fifth partial region, the fourth partial region being between the first partial region and the third electrode in the first direction, the fifth partial region being between the third partial region and the fourth semiconductor region in the first direction, a direction from a part of the third electrode to the fifth partial region being along the second direction, and the fifth partial region being continuous with the fourth partial region; a sixth semiconductor region of the second conductivity type provided between the first electrode and the first semiconductor region; The semiconductor member comprising: an insulating member including a first insulating region, the first insulating region being provided between the semiconductor member and the third electrode; A semiconductor device comprising:

[0076] (Configuration 2) the semiconductor member includes a first boundary and a second boundary; the first boundary is between the first partial region and the fourth partial region in the first direction; the second boundary is between the third partial region and the fifth partial region in the first direction; 2. The semiconductor device of claim 1, wherein a first distance along the first direction between the first electrode and the first boundary is shorter than a second distance along the first direction between the first electrode and the second boundary.

[0077] (Configuration 3) 3. The semiconductor device according to configuration 2, wherein a concentration of the second conductivity type impurity in at least a portion of the fourth partial region is higher than a concentration of the second conductivity type impurity in at least a portion of the fifth partial region.

[0078] (Configuration 4) A first electrode; a second electrode, the direction from the first electrode to the second electrode being along a first direction; a third electrode, the third electrode being between the first electrode and the second electrode; A semiconductor member, comprising: a first semiconductor region of a first conductivity type, the first semiconductor region including a first partial region, a second partial region, and a third partial region, the first partial region being between the first electrode and the third electrode in the first direction, a second direction from the first partial region to the second partial region intersecting the first direction, and the third partial region being between the second partial region and the second electrode in the first direction; a second semiconductor region of a second conductivity type, the second semiconductor region being provided between the third partial region and the second electrode, the second semiconductor region including a first semiconductor portion; a third semiconductor region of the first conductivity type, the third semiconductor region being provided between the first semiconductor portion and the second electrode and electrically connected to the second electrode; a fourth semiconductor region of the first conductivity type, the fourth semiconductor region being provided between the third partial region and the second semiconductor region in the first direction; a fifth semiconductor region of the second conductivity type, the fifth semiconductor region including a fourth partial region and a fifth partial region, the fourth partial region being between the first partial region and the third electrode in the first direction, the fifth partial region being between the third partial region and the fourth semiconductor region in the first direction, a direction from a portion of the third electrode to the fifth partial region being along the second direction, and an impurity concentration of the second conductivity type in at least a portion of the fourth partial region being higher than an impurity concentration of the second conductivity type in at least a portion of the fifth partial region; a sixth semiconductor region of the second conductivity type provided between the first electrode and the first semiconductor region; The semiconductor member comprising: an insulating member including a first insulating region, the first insulating region being provided between the semiconductor member and the third electrode; A semiconductor device comprising:

[0079] (Configuration 5) the fourth partial region includes a first position and a third position; the fifth sub-region includes a second location; the first position is between the first partial region and the third electrode in the first direction; the third position is between the first position and the third electrode in the first direction; a direction from the third position to the second position along the second direction; a first-position impurity concentration of the second conductivity type at the first position is higher than a second-position impurity concentration of the second conductivity type at the second position; 5. The semiconductor device according to configuration 3 or 4, wherein a third-position impurity concentration of the second conductivity type at the third position is lower than the first-position impurity concentration.

[0080] (Configuration 6) 6. The semiconductor device according to configuration 5, wherein the first position impurity concentration is 1.5 to 100 times the second position impurity concentration.

[0081] (Configuration 7) 6. The semiconductor device according to configuration 5, wherein the third position impurity concentration is lower than the second position impurity concentration.

[0082] (Configuration 8) 8. The semiconductor device according to structure 6 or 7, wherein the impurity concentration of the second conductivity type in the fourth partial region is highest at the first position in the first direction.

[0083] (Configuration 9) the fifth sub-region includes a fourth position; a direction from the fourth position to the second position along the first direction; a direction from the first position to the fourth position along the second direction; 9. The semiconductor device of configuration 8, wherein the second position impurity concentration is higher than a fourth position impurity concentration of the second conductivity type at the fourth position.

[0084] (Configuration 10) 10. The semiconductor device according to configuration 9, wherein the first position impurity concentration is between 2 and 1000 times the fourth position impurity concentration.

[0085] (Configuration 11) the first insulating region further includes a second insulating portion; The semiconductor device according to any one of configurations 1 to 10, wherein the second insulating portion is provided in the second direction between the third electrode and the third semiconductor region, between the third electrode and the second semiconductor region, between the third electrode and the fourth semiconductor region, and between the third electrode and the fifth partial region.

[0086] (Configuration 12) 12. The semiconductor device according to any one of configurations 1 to 11, wherein a third impurity concentration of the first conductivity type in the third semiconductor region is higher than a first impurity concentration of the first conductivity type in the first semiconductor region.

[0087] (Configuration 13) 12. The semiconductor device according to any one of configurations 1 to 11, wherein a fourth impurity concentration of the first conductivity type in the fourth semiconductor region is higher than a first impurity concentration of the first conductivity type in the first semiconductor region.

[0088] (Configuration 14) the second semiconductor region further includes a second semiconductor portion; the third semiconductor region is located between the third electrode and the second semiconductor portion in the second direction; 14. The semiconductor device according to any one of configurations 1 to 13, wherein the second semiconductor portion is electrically connected to the second electrode.

[0089] (Configuration 15) 15. The semiconductor device according to configuration 14, wherein a second semiconductor portion impurity concentration of the second conductivity type in the second semiconductor portion is higher than a first semiconductor portion impurity concentration of the second conductivity type in the first semiconductor portion.

[0090] (Configuration 16) 16. The semiconductor device according to any one of configurations 1 to 15, wherein a sixth impurity concentration of the second conductivity type in the sixth semiconductor region is higher than a fifth impurity concentration of the second conductivity type in the fifth semiconductor region.

[0091] (Configuration 17) the insulating member further includes a second insulating region; 17. The semiconductor device according to any one of configurations 1 to 16, wherein the second insulating region is located between the third electrode and the second electrode in the first direction.

[0092] (Configuration 18) A plurality of the third electrodes are provided, 18. The semiconductor device according to any one of configurations 1 to 17, wherein a direction from one of the plurality of third electrodes to another of the plurality of third electrodes is along the second direction.

[0093] (Configuration 19) a collector electrode; a semiconductor member provided on the collector electrode; a gate electrode provided in a trench provided in the semiconductor member; Equipped with The semiconductor member is a first semiconductor region of a first conductivity type; a fifth semiconductor region of the second conductivity type provided around the bottom of the trench; Including, the first semiconductor region is between the collector electrode and the fifth semiconductor region, the fifth semiconductor region includes a portion below the trench and a portion other than the portion below the trench, a distance between the boundary between the lower portion and the first semiconductor region and the collector electrode is shorter than a distance between the boundary between the portion other than the lower portion and the first semiconductor region and the collector electrode.

[0094] (Configuration 20) doping impurities of a second conductivity type into a bottom of a trench provided in a first semiconductor member, the bottom of the trench being a first semiconductor region of a first conductivity type; forming an insulating member within the trench; filling the remaining space inside the trench with a conductive material to form a third electrode; impurities of the second conductivity type and impurities of the first conductivity type are introduced into a part of the other portion of the first semiconductor member, and a fifth semiconductor region of the second conductivity type, a fourth semiconductor region of the first conductivity type, a second semiconductor region of the second conductivity type, and a third semiconductor region of the first conductivity type are formed from the other portion, the fourth semiconductor region is on the fifth semiconductor region, the second semiconductor region is on the fourth semiconductor region, and the third semiconductor region is on at least a part of the second semiconductor region; forming a second electrode electrically connected to the third semiconductor region; A method for manufacturing a semiconductor device, comprising forming a first electrode and a sixth semiconductor region of the second conductivity type, the sixth semiconductor region being between the first electrode and the first semiconductor region.

[0095] According to the embodiment, it is possible to provide a semiconductor device that can obtain stable characteristics and a method for manufacturing the same.

[0096] The embodiments of the present invention have been described above with reference to specific examples. However, the present invention is not limited to these specific examples. For example, the specific configurations of the elements included in the semiconductor device, such as the semiconductor member, semiconductor region, electrode, and insulating member, are within the scope of the present invention as long as a person skilled in the art can implement the present invention in a similar manner and obtain similar effects by appropriately selecting them from known ranges.

[0097] Furthermore, any combination of two or more elements of each specific example within the scope of technical feasibility is also included within the scope of the present invention as long as it includes the gist of the present invention.

[0098] In addition, all semiconductor devices and manufacturing methods thereof that can be implemented by a person skilled in the art by making appropriate design modifications based on the semiconductor device and manufacturing method thereof described above as embodiments of the present invention also fall within the scope of the present invention, as long as they include the gist of the present invention.

[0099] In addition, within the scope of the concept of the present invention, a person skilled in the art may come up with various modifications and alterations, and it will be understood that these modifications and alterations also fall within the scope of the present invention.

[0100] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0101] 10M...semiconductor member, 10T...trench, 11-16...first to sixth semiconductor regions, 11A...other portions, 11F...first semiconductor member, 11M...mask member, 11a-11c...first to third partial regions, 12a, 12b...first and second semiconductor portions, 15a...region, 15d, 15e...fourth and fifth partial regions, 18p...impurity, 40...insulating member, 41, 42...first and second insulating regions, 41a, 41b...second insulating portion, 45...insulating film, 51-53...first to third electrodes, 51f...first surface, 53a...end, 53b...other end, 110...semiconductor device, CC1...impurity concentration, Cp1-Cp4...first to fourth position impurity concentrations, D1, D2...first and second directions, b1, b2...1st, 2nd boundary, d1, d2...1st, 2nd distance, p1~p6...1st~6th position, pZ...position

Claims

1. A first electrode; a second electrode, the direction from the first electrode to the second electrode being along a first direction; a third electrode, the third electrode being between the first electrode and the second electrode; A semiconductor member, comprising: a first semiconductor region of a first conductivity type, the first semiconductor region including a first partial region, a second partial region, and a third partial region, the first partial region being between the first electrode and the third electrode in the first direction, a second direction from the first partial region to the second partial region intersecting the first direction, and the third partial region being between the second partial region and the second electrode in the first direction; a second semiconductor region of a second conductivity type, the second semiconductor region being provided between the third partial region and the second electrode, the second semiconductor region including a first semiconductor portion; a third semiconductor region of the first conductivity type, the third semiconductor region being provided between the first semiconductor portion and the second electrode and electrically connected to the second electrode; a fourth semiconductor region of the first conductivity type, the fourth semiconductor region being provided between the third partial region and the second semiconductor region in the first direction; a fifth semiconductor region of the second conductivity type, the fifth semiconductor region including a fourth partial region and a fifth partial region, the fourth partial region being between the first partial region and the third electrode in the first direction, the fifth partial region being between the third partial region and the fourth semiconductor region in the first direction, a direction from a part of the third electrode to the fifth partial region being along the second direction, and the fifth partial region being continuous with the fourth partial region; a sixth semiconductor region of the second conductivity type provided between the first electrode and the first semiconductor region; The semiconductor member comprising: an insulating member including a first insulating region, the first insulating region being provided between the semiconductor member and the third electrode; Equipped with the semiconductor member includes a first boundary and a second boundary; the first boundary is between the first partial region and the fourth partial region in the first direction; the second boundary is between the third partial region and the fifth partial region in the first direction; a first distance along the first direction between the first electrode and the first boundary is shorter than a second distance along the first direction between the first electrode and the second boundary; the fourth partial region includes a first position and a third position; the fifth sub-region includes a second position; the first position is between the first partial region and the third electrode in the first direction; the third position is between the first position and the third electrode in the first direction; a direction from the third position to the second position along the second direction; a first-position impurity concentration of the second conductivity type at the first position is higher than a second-position impurity concentration of the second conductivity type at the second position; a third position impurity concentration of the second conductivity type at the third position is lower than the first position impurity concentration; The third position impurity concentration is lower than the second position impurity concentration.

2. A first electrode; a second electrode, the direction from the first electrode to the second electrode being along a first direction; a third electrode, the third electrode being between the first electrode and the second electrode; A semiconductor member, comprising: a first semiconductor region of a first conductivity type, the first semiconductor region including a first partial region, a second partial region, and a third partial region, the first partial region being between the first electrode and the third electrode in the first direction, a second direction from the first partial region to the second partial region intersecting the first direction, and the third partial region being between the second partial region and the second electrode in the first direction; a second semiconductor region of a second conductivity type, the second semiconductor region being provided between the third partial region and the second electrode, the second semiconductor region including a first semiconductor portion; a third semiconductor region of the first conductivity type, the third semiconductor region being provided between the first semiconductor portion and the second electrode and electrically connected to the second electrode; a fourth semiconductor region of the first conductivity type, the fourth semiconductor region being provided between the third partial region and the second semiconductor region in the first direction; a fifth semiconductor region of the second conductivity type, the fifth semiconductor region including a fourth partial region and a fifth partial region, the fourth partial region being between the first partial region and the third electrode in the first direction, the fifth partial region being between the third partial region and the fourth semiconductor region in the first direction, a direction from a part of the third electrode to the fifth partial region being along the second direction, and the fifth partial region being continuous with the fourth partial region; a sixth semiconductor region of the second conductivity type provided between the first electrode and the first semiconductor region; The semiconductor member comprising: an insulating member including a first insulating region, the first insulating region being provided between the semiconductor member and the third electrode; Equipped with the semiconductor member includes a first boundary and a second boundary; the first boundary is between the first partial region and the fourth partial region in the first direction; the second boundary is between the third partial region and the fifth partial region in the first direction; a first distance along the first direction between the first electrode and the first boundary is shorter than a second distance along the first direction between the first electrode and the second boundary; the fourth partial region includes a first position and a third position; the fifth sub-region includes a second position; the first position is between the first partial region and the third electrode in the first direction; the third position is between the first position and the third electrode in the first direction; a direction from the third position to the second position along the second direction; a first-position impurity concentration of the second conductivity type at the first position is higher than a second-position impurity concentration of the second conductivity type at the second position; a third position impurity concentration of the second conductivity type at the third position is lower than the first position impurity concentration; the impurity concentration of the second conductivity type in the fourth partial region is highest at the first position in the first direction, the fifth sub-region includes a fourth position; a direction from the fourth position to the second position along the first direction; a direction from the first position to the fourth position along the second direction; The semiconductor device, wherein the second position impurity concentration is higher than a fourth position impurity concentration of the second conductivity type at the fourth position.

3. A first electrode; a second electrode, the direction from the first electrode to the second electrode being along a first direction; a third electrode, the third electrode being between the first electrode and the second electrode; A semiconductor member, comprising: a first semiconductor region of a first conductivity type, the first semiconductor region including a first partial region, a second partial region, and a third partial region, the first partial region being between the first electrode and the third electrode in the first direction, a second direction from the first partial region to the second partial region intersecting the first direction, and the third partial region being between the second partial region and the second electrode in the first direction; a second semiconductor region of a second conductivity type, the second semiconductor region being provided between the third partial region and the second electrode, the second semiconductor region including a first semiconductor portion; a third semiconductor region of the first conductivity type, the third semiconductor region being provided between the first semiconductor portion and the second electrode and electrically connected to the second electrode; a fourth semiconductor region of the first conductivity type, the fourth semiconductor region being provided between the third partial region and the second semiconductor region in the first direction; a fifth semiconductor region of the second conductivity type, the fifth semiconductor region including a fourth partial region and a fifth partial region, the fourth partial region being between the first partial region and the third electrode in the first direction, the fifth partial region being between the third partial region and the fourth semiconductor region in the first direction, a direction from a part of the third electrode to the fifth partial region being along the second direction, and the fifth partial region being continuous with the fourth partial region; a sixth semiconductor region of the second conductivity type provided between the first electrode and the first semiconductor region; The semiconductor member comprising: an insulating member including a first insulating region, the first insulating region being provided between the semiconductor member and the third electrode; Equipped with the semiconductor member includes a first boundary and a second boundary; the first boundary is between the first partial region and the fourth partial region in the first direction; the second boundary is between the third partial region and the fifth partial region in the first direction; a first distance along the first direction between the first electrode and the first boundary is shorter than a second distance along the first direction between the first electrode and the second boundary; a position in the first direction of the highest impurity concentration in the fourth partial region differs from a position in the first direction of the highest impurity concentration in the fifth partial region;

4. 4. The semiconductor device according to claim 1, wherein a concentration of the second conductivity type impurity in at least a portion of the fourth partial region is higher than a concentration of the second conductivity type impurity in at least a portion of the fifth partial region.

5. the fourth partial region includes a first position and a third position; the fifth sub-region includes a second position; the first position is between the first partial region and the third electrode in the first direction; the third position is between the first position and the third electrode in the first direction; a direction from the third position to the second position along the second direction; a first-position impurity concentration of the second conductivity type at the first position is higher than a second-position impurity concentration of the second conductivity type at the second position; 4. The semiconductor device according to claim 3, wherein a third-position impurity concentration of said second conductivity type at said third position is lower than said first-position impurity concentration.

6. 6. The semiconductor device according to claim 1, wherein the first position impurity concentration is 1.5 to 100 times the second position impurity concentration.

7. 6. The semiconductor device according to claim 1, wherein the third position impurity concentration is lower than the second position impurity concentration.

8. 6. The semiconductor device according to claim 1, wherein the impurity concentration of the second conductivity type in the fourth partial region is highest at the first position in the first direction.

9. the fifth sub-region includes a fourth position; a direction from the fourth position to the second position along the first direction; a direction from the first position to the fourth position along the second direction; 6. The semiconductor device according to claim 1, wherein the second-position impurity concentration is higher than a fourth-position impurity concentration of the second conductivity type at the fourth position.

10. 3. The semiconductor device according to claim 2, wherein the first position impurity concentration is at least two times and at most 1000 times the fourth position impurity concentration.

11. doping a second conductivity type impurity into a bottom of a trench provided in a first semiconductor member to form a first semiconductor region of a first conductivity type; and forming a first portion of a fifth semiconductor region of the second conductivity type; forming an insulating member within the trench; filling the remaining space inside the trench with a conductive material to form a third electrode; Impurities of the second conductivity type and impurities of the first conductivity type are introduced into a part of the other part of the first semiconductor member, and a second part continuous with the first part of the fifth semiconductor region of the second conductivity type, a fourth semiconductor region of the first conductivity type, a second semiconductor region of the second conductivity type, and a third semiconductor region of the first conductivity type are formed from the other part, and the fourth semiconductor region is on the fifth semiconductor region, the second semiconductor region is on the fourth semiconductor region, and the third semiconductor region is on at least a part of the second semiconductor region, forming a second electrode electrically connected to the third semiconductor region; A method for manufacturing a semiconductor device, comprising forming a first electrode and a sixth semiconductor region of the second conductivity type, the sixth semiconductor region being between the first electrode and the first semiconductor region.

12. 12. The method for manufacturing a semiconductor device according to claim 11, wherein a distance between the boundary between the first portion of the fifth semiconductor region and the first semiconductor region and the first electrode is shorter than a distance between the boundary between the second portion of the fifth semiconductor region and the first semiconductor region and the first electrode.

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