memory device

Abstract

To improve a yield.SOLUTION: A memory device of an embodiment comprises first and second chips that are in contact on a surface divided into first areas AR, IDR, a second area DCR surrounding the first areas, and a third area ODR surrounding the second area. The first chip includes: a substrate provided with first and second diffusion areas; and first and second electrode parts BPd_2, BPd_3 surrounding the first area in the second area. The second chip includes: a wiring layer; a third electrode part BPd_2 surrounding the first area and in contact with the first electrode part in the second area; a fourth electrode part BPd_3 surrounding the first area and in contact with the second electrode part in the second area; a first wall part in contact with the wiring layer, surrounding the first area, and electrically connected with the first diffusion area; and a second wall part in contact with the wiring layer, surrounding the first area, and electrically connected with the second diffusion area. The first and third electrode parts and the first wall part include one continuous electric conductor. A first ratio of the area of the first and second electrode parts occupying the second area, and a second ratio of the area of the third and fourth electrode parts occupying the second area are both 3% or more and 40% or less.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] Embodiments relate to memory devices. [Background technology]

[0002] NAND flash memory is a well-known memory device capable of storing data nonvolatilely. Memory devices such as NAND flash memory employ a three-dimensional memory structure to achieve high integration and large capacity. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2021 / 0265314 [Patent Document 2] Japanese Patent Publication No. 2020-92146 [Patent Document 3] U.S. Patent No. 10,978,505 [Patent Document 4] U.S. Patent Application Publication No. 2021 / 0265293 Summary of the Invention [Problem to be solved by the invention]

[0004] To improve the yield of memory devices. [Means for solving the problem]

[0005] A memory device according to an embodiment includes a first chip and a second chip that are in contact with each other on a first surface. The first surface is divided into a first region, a second region surrounding the first region, and a third region surrounding the second region. The first chip includes a substrate, a first electrode portion, and a second electrode portion. The substrate includes: No. 1 diffusion area and andA second diffusion region is provided. The first electrode portion includes a single continuous conductor surrounding the first region in the second region. The second electrode portion surrounds the first region at a distance from the first electrode portion in the second region. The second chip includes a first wiring layer, a third electrode portion, a fourth electrode portion, a first wall portion, and a second wall portion. The third electrode portion includes a single continuous conductor surrounding the first region in the second region and is in contact with the first electrode portion. The fourth electrode portion surrounds the first region at a distance from the third electrode portion in the second region and is in contact with the second electrode portion. The first wall portion is in contact with the first wiring layer, includes a single continuous conductor surrounding the first region, and is electrically connected to the first diffusion region via the third electrode portion and the first electrode portion. The second wall portion is in contact with the first wiring layer, surrounds the first region at a distance from the first wall portion, and is electrically connected to the second diffusion region via the fourth electrode portion and the second electrode portion. A first ratio of an area occupied by the first electrode portion and the second electrode portion in the second region and a second ratio of an area occupied by the third electrode portion and the fourth electrode portion in the second region are each 3% or more and 40% or less. Each of the second electrode portion and the fourth electrode portion includes a plurality of conductors arranged apart from each other so as to surround the first region. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a block diagram showing an example of the configuration of a memory system including a memory device according to a first embodiment. [Figure 2] FIG. 2 is a circuit diagram showing an example of the circuit configuration of a memory cell array included in the memory device according to the first embodiment. [Figure 3] FIG. 1 is a perspective view showing an outline of a laminated structure of a memory device according to a first embodiment. [Figure 4] FIG. 2 is a plan view showing an example of a planar layout of a bonding pad of the memory device according to the first embodiment. [Figure 5] FIG. 3 is a plan view showing an example of a planar layout of a bonding pad in a discharge pad region of the memory device according to the first embodiment. [Figure 6] FIG. 3 is a plan view showing an example of a planar layout of bonding pads in an outer dummy pad region of the memory device according to the first embodiment. [Figure 7]FIG. 2 is a cross-sectional view showing an example of the cross-sectional structure of the memory device according to the first embodiment. [Figure 8] FIG. 3 is a plan view showing an example of a planar layout of a part of a wall structure and a bonding pad in a discharge pad region of the memory device according to the first embodiment. [Figure 9] FIG. 3 is a cross-sectional view showing an example of a cross-sectional structure of a bonding pad of the memory device according to the first embodiment. [Figure 10] FIG. 2 is a cross-sectional view showing an example of the cross-sectional structure of a memory cell array of the memory device according to the first embodiment. [Figure 11] 11 is a cross-sectional view taken along line XI-XI in FIG. 10, showing an example of the cross-sectional structure of a memory pillar of the memory device according to the first embodiment. [Figure 12] FIG. 10 is a cross-sectional view showing a first example of a cross-sectional structure of a bonding pad of a memory device according to a second embodiment. [Figure 13] FIG. 10 is a cross-sectional view showing a second example of the cross-sectional structure of the bonding pad of the memory device according to the second embodiment. [Figure 14] FIG. 11 is a plan view showing a first example of a planar layout of a part of a wall structure and a bonding pad in a discharge pad region of a memory device according to a third embodiment. [Figure 15] FIG. 11 is a plan view showing a first example of a planar layout of bonding pads in a discharge pad region of the memory device according to the third embodiment. [Figure 16] FIG. 11 is a plan view showing a second example of a planar layout of a part of the wall structure and bonding pads in the discharge pad region of the memory device according to the third embodiment. [Figure 17] FIG. 11 is a plan view showing a second example of a planar layout of bonding pads in a discharge pad region of the memory device according to the third embodiment. [Figure 18] FIG. 10 is a plan view showing an example of a planar layout of a bonding pad of a memory device according to a first modified example. [Figure 19] FIG. 10 is a cross-sectional view showing an example of a cross-sectional structure of a memory device according to a first modification. [Figure 20] FIG. 10 is a cross-sectional view showing an example of the cross-sectional structure of a memory device according to a second modification. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments will be described with reference to the drawings. The dimensions and proportions of the drawings are not necessarily the same as those in reality.

[0008] In the following description, components having substantially the same functions and configurations are denoted by the same reference numerals. When elements having similar configurations are to be particularly distinguished from one another, different letters or numbers may be added to the end of the same reference numerals.

[0009] 1. First embodiment 1.1 Configuration 1.1.1 Memory System Configuration FIG. 1 is a block diagram showing an example of the configuration of a memory system including a memory device according to the first embodiment. The memory system 1 is a storage device configured to be connected to an external host device (not shown). The memory system 1 is, for example, a storage device such as an SD TM The memory system 1 includes a memory controller 2 and a memory device 3. The memory system 1 may be a memory card, a universal flash storage (UFS), or a solid state drive (SSD).

[0010] The memory controller 2 is configured by an integrated circuit such as a system-on-a-chip (SoC). The memory controller 2 controls the memory device 3 based on a request from the host device. Specifically, for example, the memory controller 2 writes data requested to be written by the host device to the memory device 3. The memory controller 2 also reads data requested to be read by the host device from the memory device 3 and transmits the data to the host device.

[0011] The memory device 3 is a nonvolatile memory, such as a NAND flash memory, that stores data in a nonvolatile manner.

[0012] The communication between the memory controller 2 and the memory device 3 is compliant with, for example, an SDR (single data rate) interface, a toggle DDR (double data rate) interface, or an ONFI (Open NAND flash interface).

[0013] 1.1.2 Memory Device Configuration The internal configuration of the memory device according to the first embodiment will now be described with reference to the block diagram shown in Fig. 1. The memory device 3 includes, for example, a memory cell array 10, a command register 11, an address register 12, a sequencer 13, a driver module 14, a row decoder module 15, and a sense amplifier module 16.

[0014] The memory cell array 10 includes a plurality of blocks BLK0 to BLKn (n is an integer equal to or greater than 1). The number of blocks BLK included in the memory cell array 10 may be one. A block BLK is a set of a plurality of memory cells. A block BLK is used, for example, as a unit for erasing data. The memory cell array 10 is also provided with a plurality of bit lines and a plurality of word lines. Each memory cell is associated with, for example, one bit line and one word line. The detailed configuration of the memory cell array 10 will be described later.

[0015] The command register 11 stores the command CMD that the memory device 3 receives from the memory controller 2. The command CMD includes, for example, an instruction to make the sequencer 13 execute a read operation, a write operation, an erase operation, or the like.

[0016] The address register 12 stores address information ADD that the memory device 3 receives from the memory controller 2. The address information ADD includes, for example, a block address BAd, a page address PAd, and a column address CAd. For example, the block address BAd, the page address PAd, and the column address CAd are used to select a block BLK, a word line, and a bit line, respectively.

[0017] The sequencer 13 controls the overall operation of the memory device 3. For example, the sequencer 13 controls the driver module 14, the row decoder module 15, the sense amplifier module 16, etc. based on the command CMD held in the command register 11 to perform read operations, write operations, erase operations, etc.

[0018] The driver module 14 generates voltages used in read operations, write operations, erase operations, etc. Then, the driver module 14 applies the generated voltages to a signal line corresponding to a selected word line based on, for example, a page address PAd stored in the address register 12.

[0019] The row decoder module 15 selects one block BLK in the corresponding memory cell array 10 based on the block address BAd stored in the address register 12. Then, the row decoder module 15 transfers, for example, a voltage applied to a signal line corresponding to the selected word line to the selected word line in the selected block BLK.

[0020] In a write operation, the sense amplifier module 16 applies a desired voltage to each bit line in accordance with the write data DAT received from the memory controller 2. In a read operation, the sense amplifier module 16 determines the data stored in the memory cell based on the voltage of the bit line, and transfers the determination result to the memory controller 2 as read data DAT.

[0021] 1.1.3 Memory cell array circuit configuration Fig. 2 is a circuit diagram showing an example of the circuit configuration of a memory cell array included in the memory device according to the first embodiment. Fig. 2 shows one block BLK among multiple blocks BLK included in the memory cell array 10. As shown in Fig. 2, the block BLK includes, for example, five string units SU0 to SU4.

[0022] Each string unit SU includes a plurality of NAND strings NS associated with bit lines BL0 to BLm (m is an integer equal to or greater than 1). The number of bit lines BL may be one. Each NAND string NS includes, for example, memory cell transistors MT0 to MT7 and select transistors ST1 and ST2. Each memory cell transistor MT includes a control gate and a charge storage section, and stores data in a non-volatile manner. Each of the select transistors ST1 and ST2 is used to select the string unit SU during various operations.

[0023] In each NAND string NS, the memory cell transistors MT0 to MT7 are connected in series. The drain of the select transistor ST1 is connected to the associated bit line BL. The source of the select transistor ST1 is connected to one end of the memory cell transistors MT0 to MT7 connected in series. The drain of the select transistor ST2 is connected to the other end of the memory cell transistors MT0 to MT7 connected in series. The source of the select transistor ST2 is connected to a source line SL.

[0024] In the same block BLK, the control gates of memory cell transistors MT0 to MT7 are connected to word lines WL0 to WL7, respectively. The gates of select transistors ST1 in string units SU0 to SU4 are connected to select gate lines SGD0 to SGD4, respectively. The gates of multiple select transistors ST2 are connected to select gate line SGS.

[0025] A different column address is assigned to each of the bit lines BL0 to BLm. Each bit line BL is shared by NAND strings NS that are assigned the same column address among multiple blocks BLK. Each of the word lines WL0 to WL7 is provided for each block BLK. The source line SL is shared, for example, among multiple blocks BLK.

[0026] A set of memory cell transistors MT connected to a common word line WL within one string unit SU is called, for example, a cell unit CU. For example, the storage capacity of a cell unit CU including memory cell transistors MT each storing one bit of data is defined as "one page of data." A cell unit CU may have a storage capacity of two or more pages of data depending on the number of bits of data stored in the memory cell transistors MT.

[0027] The circuit configuration of the memory cell array 10 included in the memory device 3 according to the first embodiment is not limited to the configuration described above. For example, the number of string units SU included in each block BLK can be designed to be any number. The number of memory cell transistors MT and select transistors ST1 and ST2 included in each NAND string NS can be designed to be any number.

[0028] 1.1.4 Memory device bonding structure Next, an outline of the laminated structure of the memory device according to the first embodiment will be described.

[0029] 1.1.4.1 Overview of lamination structure FIG. 3 is a perspective view showing an outline of the laminated structure of the memory device according to the first embodiment.

[0030] 3, the memory device 3 includes a memory chip 100 and a CMOS chip 200. The memory chip 100 includes a structure corresponding to a memory cell array 10. The CMOS chip 200 includes a structure corresponding to, for example, a command register 11, an address register 12, a sequencer 13, a driver module 14, a row decoder module 15, and a sense amplifier module 16.

[0031] Each of the memory chip 100 and the CMOS chip 200 includes a plurality of bonding pads BP. The memory device 3 is formed by bonding the memory chip 100 and the CMOS chip 200 together via the plurality of bonding pads BP.

[0032] Hereinafter, the surface where the memory chip 100 and the CMOS chip 200 are bonded (bonding surface) will be referred to as the XY plane. Directions that are orthogonal to each other on the XY plane will be referred to as the X direction and the Y direction. Furthermore, the direction that is approximately perpendicular to the XY plane and faces from the memory chip 100 to the CMOS chip 200 will be referred to as the Z1 direction. The direction that is approximately perpendicular to the XY plane and faces from the CMOS chip 200 to the memory chip 100 will be referred to as the Z2 direction. When either the Z1 direction or the Z2 direction is not limited, it will be referred to as the Z direction.

[0033] 1.1.4.2 Planar layout of lamination pad Next, a description will be given of a planar layout of the bonding pad of the memory device according to Embodiment 1. Fig. 4 is a plan view showing an example of a planar layout of the bonding pad of the memory device according to Embodiment 1.

[0034] 4, the bonding surfaces of the memory chip 100 and the CMOS chip 200 of the memory device 3 are divided into, for example, an active pad area AR, an inner dummy pad area IDR, a discharge pad area DCR, an outer dummy pad area ODR, and a kerf area KR. The bonding pads BP are classified into bonding pads BPa, BPi, BPd, and BPo according to the area of ​​the bonding surface where they are located. The bonding pad BPd includes bonding pads BPd_2 and BPd_3.

[0035] The active pad area AR is a rectangular area located in the center of the memory device 3 when viewed in the Z direction. The number and shape of the active pad areas AR can be designed arbitrarily. A bonding pad BPa is arranged in the active pad area AR. The bonding pad BPa is a conductor that functions as a signal or power path when operating the memory device 3. The bonding pad BPa includes, for example, multiple electrodes, each of which is rectangular. The multiple electrodes included in the bonding pad BPa are arranged, for example, in a square lattice pattern.

[0036] The inner dummy pad region IDR is located inside the discharge pad region DCR when viewed in the Z direction, and is a rectangular ring-shaped region surrounding the outer periphery of the active pad region AR. The inner dummy pad region IDR has a bonding pad BPi arranged therein. The bonding pad BPi is located inside the discharge pad region DCR and is a conductor that does not function as a signal or power path when operating the memory device 3. The bonding pad BPi includes, for example, a plurality of rectangular electrodes. The plurality of electrodes included in the bonding pad BPi are arranged, for example, in a pattern other than a square lattice.

[0037] The discharge pad region DCR is a rectangular ring-shaped region surrounding the outer periphery of the inner dummy pad region IDR when viewed in the Z direction. The bonding pad region DCR is provided with bonding pads BPd_2 and BPd_3. Each of the bonding pads BPd_2 and BPd_3 is a conductor that functions as a discharge path for dissipating static electricity generated on the memory chip 100 side to the CMOS chip 200 side. Each of the bonding pads BPd_2 and BPd_3 includes, for example, one continuous electrode. The one electrode included in the bonding pad BPd_2 has a rectangular ring-shaped configuration that surrounds the bonding pads BPa and BPi. The one electrode included in the bonding pad BPd_3 has a rectangular ring-shaped configuration that surrounds the bonding pad BPd_2 while being spaced apart from the bonding pad BPd_2.

[0038] The outer dummy pad region ODR is a rectangular ring-shaped region surrounding the outer periphery of the discharge pad region DCR when viewed in the Z direction. A bonding pad BPo is arranged in the outer dummy pad region ODR. The bonding pad BPo is located outside the discharge pad region DCR and is a conductor that does not function as a path for either signals or power when operating the memory device 3. The bonding pad BPo includes, for example, multiple electrodes, each of which is rectangular. The multiple electrodes included in the bonding pad BPo are arranged in a pattern other than, for example, a square lattice. The arrangement pattern of the multiple electrodes included in the bonding pad BPo may be the same as or different from the arrangement pattern of the multiple electrodes included in the bonding pad BPi.

[0039] The kerf region KR is a quadrangular ring-shaped region surrounding the outer periphery of the outer dummy pad region ODR when viewed in the Z direction. The kerf region KR is in contact with the outermost periphery of the semiconductor substrate. No bonding pads are provided in the kerf region KR. For example, alignment marks used in manufacturing the memory devices 3 are provided in the kerf region KR. The structural portion in the kerf region KR may be removed by a dicing process in which multiple memory devices 3 formed on a wafer are cut into individual chips.

[0040] 1.1.4.3 Coverage of Laminating Pad Next, we will explain the coverage of the bonding pads of the memory device according to the first embodiment. The coverage of the bonding pads BP in a certain region of the bonding surface is the ratio of the area occupied by the bonding pads BP arranged in that region to that region.

[0041] 1.1.4.3.1 Coverage of the discharge pad area Fig. 5 is a plan view showing an example of a planar layout of bonding pads in the discharge pad region of the memory device according to the first embodiment. Fig. 5 shows a part of the bonding pads BPd_2 and BPd_3 arranged in the discharge pad region DCR shown in Fig. 4.

[0042] 5, the lamination pads BPd_2 and BPd_3 have widths D2 and D3, respectively. The widths D2 and D3 may be equal to or different from each other. The widths D2 and D3 are, for example, 0.1 micrometers (μm) or more and 1.0 micrometers or less.

[0043] The coverage of the bonding pads BPd_2 and BPd_3 in the discharge pad region DCR is calculated, for example, as the ratio of the area of ​​the bonding pads BPd_2 and BPd_3 to the area of ​​the unit region UDCR. The unit region UDCR is, for example, a rectangular region having a center line of the width D2 of the bonding pad BPd_2 and a center line of the width D3 of the bonding pad BPd_3 as two opposing sides. The length of the side connecting the center of the width D2 of the bonding pad BPd_2 and the center of the width D3 of the bonding pad BPd_3 in the unit region UDCR is defined as a distance P. As shown in FIG. 5, when each of the bonding pads BPd_2 and BPd_3 has a square ring shape, the coverage of the bonding pads BPd_2 and BPd_3 in the discharge pad region DCR is expressed, for example, as (D2 / 2+D3 / 2) / P. The coverage of the bonding pads BPd_2 and BPd_3 in the discharge pad region DCR is designed to be, for example, 3% or more and 40% or less. If the coverage of the bonding pads BPd_2 and BPd_3 in the discharge pad region DCR is less than 3%, it is not preferable because it may not function sufficiently as a discharge path for dissipating static electricity generated on the memory chip 100 side to the CMOS chip 200 side. If the coverage of the bonding pads BPd_2 and BPd_3 in the discharge pad region DCR exceeds 40%, it is not preferable because it may not be possible to sufficiently suppress bonding defects in the bonding process of the memory chip 100 and the CMOS chip 200.

[0044] 1.1.4.3.2 Coverage in outer dummy pad areas Fig. 6 is a plan view showing an example of a planar layout of the bonding pad in the outer dummy pad region of the memory device according to the first embodiment. Fig. 6 shows a part of a plurality of electrodes included in the bonding pad BPo arranged in the outer dummy pad region ODR shown in Fig. 4. In Fig. 6, for the sake of convenience of explanation, the outer dummy pad region ODR is shown divided into square lattice cells with a side length of L.

[0045] As shown in FIG. 6, in the outer dummy pad region ODR, one electrode included in the bonding pad BPo is arranged corresponding to one square. Note that the area of ​​one electrode included in the bonding pad BPo is the area of ​​one square (=L 2 ) may be equal to or different from

[0046] In the outer dummy pad area ODR, the plurality of electrodes included in the bonding pad BPo are arranged, for example, according to a predetermined pattern. In the example of Figure 6, a pattern in which 15 electrodes are arranged in a 15x15 unit area UODR is shown. In this case, with respect to the square where the reference electrode is arranged, additional electrodes are arranged in the squares 4 squares and 1 square away in the X direction and Y direction, respectively, and in the squares 1 square and 4 square away in the X direction and Y direction, respectively.

[0047] The coverage of the bonding pads BPo in the outer dummy pad region ODR is calculated, for example, as the ratio of the area of ​​the bonding pads BPo to the area of ​​the unit region UODR. In the example of FIG. 6, the coverage of the bonding pads BPo in the outer dummy pad region ODR is designed to be, for example, 3% or more and 20% or less. In addition, it is desirable to design the coverage of the bonding pads BPo in the outer dummy pad region ODR to be 1 / 3 or more and 2 / 3 or less of the coverage of the bonding pads BPd_2 and BPd_3 in the discharge pad region DCR. If the above conditions are not met, there is a possibility that bonding defects cannot be sufficiently suppressed in the bonding process of the memory chip 100 and the CMOS chip 200, which is not preferable.

[0048] 1.1.4.3.3 Coverage in Active Pad Area and Inner Dummy Pad Area Each of the coverage rates of the bonding pads BPa in the active pad areas AR is designed to be, for example, 25% or less (more specifically, for example, 16%).

[0049] The coverage of the bonding pads BPi in the inner dummy pad region IDR is preferably, for example, between the coverage of the bonding pads BPa in the active pad region AR and the coverage of the bonding pads BPd_2 and BPd_3 in the discharge pad region DCR.

[0050] 1.1.5 Cross-sectional structure of memory device Next, a description will be given of the cross-sectional structure of the memory device according to the first embodiment. Fig. 7 is a cross-sectional view showing an example of the cross-sectional structure of the memory device according to the first embodiment.

[0051] 7 , the memory chip 100 includes a semiconductor layer 101, insulating layers 102, 111, 112, 113, 114, 115, 117, 118, and 121, wiring layers 103, 106, 108, and 116, conductors 104, 105, 107, 109, and 120, an electrode 110, a surface protection layer 119, and memory pillars MP. The electrode 110 includes electrodes 110a, 110i, 110d, and 110o. The CMOS chip 200 includes a semiconductor substrate 201, an N-type impurity diffusion region NW, a P-type impurity diffusion region PW, a transistor TR, a gate insulating film 202, a gate electrode 203, conductors 204, 206, 208, and 210, wiring layers 205, 207, and 209, an electrode 211, and insulating layers 212 and 213. The electrodes 211 include electrodes 211a, 211i, 211d, and 211o.

[0052] 1.1.5.1 Cross-sectional structure of a memory chip First, the structure of the memory chip 100 will be described.

[0053] 1.1.5.1.1 Active Pad Area Structure The following describes the active pad area AR of the memory chip 100. The active pad area AR of the memory chip 100 is provided with the memory cell array 10 and various wirings for connecting the memory cell array 10 and the CMOS chip 200. In other words, the active pad area AR of the memory chip 100 includes a memory area where the memory cell array 10 is provided.

[0054] The semiconductor layer 101 extends in the X and Y directions. The semiconductor layer 101 provided in the active pad region AR functions as a source line SL. For example, the semiconductor layer 101 includes silicon. In the active pad region AR, a plurality of insulating layers 102 and a plurality of wiring layers 103 are alternately stacked one by one on the upper surface of the semiconductor layer 101 in the Z1 direction. In the example of FIG. 7, ten insulating layers 102 and ten wiring layers 103 are alternately stacked one by one. In other words, a plurality of wiring layers 103 are stacked and spaced apart in the Z direction between the CMOS chip 200 and the semiconductor layer 101. The wiring layers 103 extend in the X direction. The wiring layers 103 function as word lines WL and select gate lines SGD and SGS. The insulating layer 102 includes silicon oxide (SiO) as an insulating material. The wiring layer 103 includes, for example, tungsten (W) as a conductive material.

[0055] A plurality of memory pillars MP are provided in the active pad region AR. One memory pillar MP corresponds to one NAND string NS. The memory pillar MP has, for example, a cylindrical shape extending in the Z direction. The memory pillar MP penetrates (passes through) a plurality of insulating layers 102 and a plurality of wiring layers 103. The end (bottom surface) of the memory pillar MP in the Z2 direction reaches the semiconductor layer 101. The memory pillar MP includes a semiconductor layer. A portion of the semiconductor layer in the memory pillar MP contacts the semiconductor layer 101. The structure of the memory pillar MP will be described in detail later.

[0056] A conductor 104 is provided on the upper surface of the memory pillar MP in the Z1 direction. The conductor 104 has, for example, a cylindrical shape extending in the Z direction. A conductor 105 is provided on the upper surface of the conductor 104 in the Z1 direction. The conductor 105 provided in the active pad region AR has, for example, a cylindrical shape extending in the Z direction. Furthermore, a wiring layer 106 is provided on the upper surface of the conductor 105 in the Z1 direction. For example, a plurality of wiring layers 106 arranged in the X direction and each extending in the Y direction are provided in the active pad region AR. Each of the plurality of memory pillars MP is electrically connected to one of the plurality of wiring layers 106 via the conductors 104 and 105. The wiring layer 106 to which the memory pillar MP is connected functions as a bit line BL. The conductor 104 includes, for example, tungsten. The conductor 105 and the wiring layer 106 include, for example, copper (Cu).

[0057] A conductor 107 is provided on the upper surface of the wiring layer 106 in the Z1 direction. The conductor 107 provided in the active pad region AR has, for example, a cylindrical shape extending in the Z direction. A wiring layer 108 is provided on the upper surface of the conductor 107 in the Z1 direction. A conductor 109 is provided on the upper surface of the wiring layer 108 in the Z1 direction. The conductor 109 provided in the active pad region AR has, for example, a cylindrical shape extending in the Z direction. In the active pad region AR, an electrode 110a is provided on the upper surface of the conductor 109 in the Z1 direction. The electrode 110a is electrically connected to an electrode 211a of the CMOS chip 200. The electrodes 110a and 211a function as a bonding pad BPa.

[0058] Each of the multiple wiring layers 106 in the active pad region AR is electrically connected to one of the electrodes 110a via the conductor 107, the wiring layer 108, and the conductor 109. The conductors 107 and 109, the wiring layer 108, and the electrode 110a contain, for example, copper as a conductive material. The number of wiring layers provided between the wiring layer 106 and the electrode 110a is arbitrary.

[0059] Although not shown in Figure 7, in addition to the electrodes 110a described above, the active pad area AR is provided with electrodes 110a that electrically connect the wiring layer 103 and the CMOS chip 200, and electrodes 110a that electrically connect external devices and the CMOS chip 200.

[0060] The insulating layer 111 is provided so as to cover the insulating layer 102, the wiring layer 103, the memory pillar MP, the conductor 104, the conductor 105, the wiring layer 106, the conductor 107, the wiring layer 108, and the conductor 109. An insulating layer 112 is provided on the upper surface of the insulating layer 111 in the Z1 direction. A plurality of electrodes 110a are provided in the same layer as the insulating layer 112. The insulating layer 112 contacts the insulating layer 213 of the CMOS chip 200.

[0061] Insulating layers 113 and 114 are stacked on the upper surface of the semiconductor layer 101 in the Z2 direction. An insulating layer 115 is provided to cover the semiconductor layer 101 and the insulating layers 113 and 114. The insulating layers 113 and 115 contain, for example, silicon oxide as an insulating material. The insulating layer 114 uses an insulating material that has a function of preventing oxidation of metal (e.g., copper). The insulating layer 114 contains, for example, silicon carbonitride (SiCN) or silicon nitride (SiN). Note that the insulating layer 114 may be omitted.

[0062] A wiring layer 116 is provided on the upper surface of the insulating layer 115 in the Z2 direction. The wiring layer 116 provided in the active pad region AR contacts the semiconductor layer 101 in a region where the insulating layers 113 to 115 on the semiconductor layer 101 have been removed. By contacting the semiconductor layer 101, the wiring layer 116 provided in the active pad region AR functions as part of a wiring layer that electrically connects the semiconductor layer 101 (source line SL) and the CMOS chip 200. The wiring layer 116 contains, for example, aluminum (Al).

[0063] An insulating layer 117 is provided on the upper surface of the wiring layer 116 in the Z2 direction. An insulating layer 118 is provided on the upper surface of the insulating layer 117 in the Z2 direction. A surface protection layer 119 is provided on the upper surface of the insulating layer 118 in the Z2 direction. The insulating layer 117 contains, for example, silicon oxide as an insulating material. The insulating layer 118 contains, for example, silicon nitride as an insulating material with low water permeability. The surface protection layer 119 contains, for example, a resin material such as polyimide.

[0064] 1.1.5.1.2 Inner Dummy Pad Area Structure Next, the inner dummy pad region IDR of the memory chip 100 will be described.

[0065] In the inner dummy pad region IDR, a plurality of electrodes 110i are provided in the same layer as the insulating layer 112. Each of the plurality of electrodes 110i contacts a corresponding electrode 211i of the CMOS chip 200. The electrodes 110i and 211i function as bonding pads BPi. The plurality of electrodes 110i are electrically insulated from the memory cell array 10 and various wirings in the memory chip 100, and the semiconductor substrate 201 and various wirings in the CMOS chip 200.

[0066] An insulating layer 121 is provided inside the semiconductor layer 101 provided in the inner dummy pad region IDR. The semiconductor layer 101 provided in the inner dummy pad region IDR does not function as a source line SL.

[0067] 1.1.5.1.3 Discharge Pad Area Structure Next, the discharge pad region DCR of the memory chip 100 will be described.

[0068] The discharge pad region DCR is provided with wall structures W and various wirings for connecting the wall structures W to the CMOS chip 200. The wall structures W include, for example, wall structures W_1, W_2, W_3, and W_4. The wall structures W_1 to W_4 include conductors 120_1 to 120_4, respectively.

[0069] The conductor 120_1 has a rectangular ring shape surrounding the active pad region AR and the inner dummy pad region IDR when viewed in the Z direction. The conductor 120_2 has a rectangular ring shape surrounding the conductor 120_1 when viewed in the Z direction. The conductor 120_3 has a rectangular ring shape surrounding the conductor 120_2 when viewed in the Z direction. The conductor 120_4 has a rectangular ring shape surrounding the conductor 120_3 when viewed in the Z direction.

[0070] Each of the conductors 120_1 to 120_4 extends in the Z direction. The Z2-direction end of each of the conductors 120_1 and 120_4 contacts, for example, the insulating layer 115. The Z2-direction end of the conductors 120_1 and 120_4 may contact the semiconductor layer 101 or the wiring layer 116, or may be located inside the insulating layer 111. The Z2-direction end of each of the conductors 120_2 and 120_3 contacts, for example, the wiring layer 116 in a region where the semiconductor layer 101 and the insulating layers 113 to 115 have been removed.

[0071] The wiring layer 116 provided in the discharge pad region DCR is electrically insulated from the wiring layer 116 provided in the active pad region AR and the wiring layer 116 provided in the inner dummy pad region IDR. The wiring layer 116 provided in the discharge pad region DCR is covered with a surface protection layer 119 or the like.

[0072] The Z1-direction end portions of the conductors 120_1 and 120_4 are not connected to the conductor 105. The Z1-direction end portion of the conductor 120_2 and the Z1-direction end portion of the conductor 120_3 are electrically connected to the electrode 211d of the CMOS chip 200 via different conductors 105, the wiring layer 106, the conductor 107, the wiring layer 108, the conductor 109, and the electrode 110d, respectively.

[0073] Hereinafter, when specifying the wiring layer 108 electrically connected to the conductor 120_2 and the electrodes 110d and 211d, they will be referred to as the wiring layer 108_2 and the electrodes 110d_2 and 211d_2, respectively. When specifying the wiring layer 108 electrically connected to the conductor 120_3 and the electrodes 110d and 211d, they will be referred to as the wiring layer 108_3 and the electrodes 110d_3 and 211d_3, respectively.

[0074] The conductor 105, the wiring layer 106, the conductor 107, the wiring layer 108_2, the conductor 109, and the electrode 110d_2 electrically connected to the electrode 211d_2 have, for example, a rectangular ring shape surrounding the active pad region AR and the inner dummy pad region IDR when viewed in the Z direction. Furthermore, for example, the width of the wiring layer 108_2, which has a ring shape when viewed in the Z direction, is greater than the width of the wiring layer 106, which also has a ring shape. The conductor 105, the wiring layer 106, the conductor 107, the wiring layer 108_3, the conductor 109, and the electrode 110d_3 electrically connected to the electrode 211d_3 each have, for example, a rectangular ring shape surrounding the conductor 105, the wiring layer 106, the conductor 107, the wiring layer 108_2, the conductor 109, and the electrode 110d_2 electrically connected to the electrode 211d_2 when viewed in the Z direction. Also, for example, the width of the wiring layer 108_3 having a ring shape when viewed in the Z direction is larger than the width of the wiring layer 106 having a similar ring shape. The electrodes 110d_2 and 211d_2 function as a bonding pad BPd_2. The electrodes 110d_3 and 211d_3 function as a bonding pad BPd_3.

[0075] The portion of the wiring layer 108_2 to which the conductor 109 is connected is located closer to the inner dummy pad region IDR than the portion of the wiring layer 108_2 to which the conductor 107 is connected. In this way, the conductors 107 and 109 connected to the upper and lower surfaces of the wiring layer 108_2 do not overlap each other when viewed in the Z direction. As a result, the bonding pad BPd_2 is located closer to the inner dummy pad region IDR than the conductor 120_2. On the other hand, the portion of the wiring layer 108_3 to which the conductor 109 is connected is located closer to the outer dummy pad region ODR than the portion of the wiring layer 108_3 to which the conductor 107 is connected. In this way, the conductors 107 and 109 connected to the upper and lower surfaces of the wiring layer 108_3 do not overlap each other when viewed in the Z direction. As a result, the bonding pad BPd_3 is located closer to the outer dummy pad region ODR than the conductor 120_3. Therefore, the distance P between the bonding pad BPd_2 and the bonding pad BPd_3 is longer than the distance P0 between the conductor 120_2 and the conductor 120_3.

[0076] 8 is a plan view showing an example of a planar layout of a part of the wall structure and the bonding pads in the discharge pad region of the memory device according to the first embodiment. In FIG. 8, an example of a planar layout of the wall structures W_2 (conductor 120_2) and W_3 (conductor 120_3) and the bonding pads BPd_2 and BPd_3 is shown.

[0077] As shown in FIG. 8, the wall structure W_2 is provided to surround the lamination pad BPd_2 when viewed in the Z direction. The wall structure W_3 is provided to surround the wall structure W_2 when viewed in the Z direction. The lamination pad BPd_3 is provided to surround the wall structure W_3 when viewed in the Z direction. In this way, by making the distance P between the lamination pad BPd_2 and the lamination pad BPd_3 longer than the distance P0 between the wall structures W_2 and W_3, the coverage of the lamination pad BPd_2 and the lamination pad BPd_3 in the discharge pad region DCR can be reduced. Note that in the discharge pad region DCR, the width of the wiring layer 106 may be made larger than the width of the wiring layer 108, and the positions of the conductors 105 and 107 connected to the upper and lower surfaces thereof may be made different, so that the distance P between the lamination pad BPd_2 and the lamination pad BPd_3 may be made longer than the distance P0 between the conductors 120_2 and 120_3.

[0078] 1.1.5.1.4 Outer Dummy Pad Area Structure Next, referring again to FIG. 7, the outer dummy pad region ODR of the memory chip 100 will be described.

[0079] In the outer dummy pad region ODR, a plurality of electrodes 110o are provided in the same layer as the insulating layer 112. Each of the plurality of electrodes 110o contacts a corresponding electrode 211o of the CMOS chip 200. The electrodes 110o and 211o function as bonding pads BPo. The plurality of electrodes 110o are electrically insulated from various wirings in the memory chip 100 and various wirings in the CMOS chip 200.

[0080] The semiconductor layer 101 provided in the outer dummy pad region ODR is electrically insulated from the semiconductor layer 101 provided in the active pad region AR and the semiconductor layer 101 provided in the inner dummy pad region IDR. Hereinafter, when specifying the semiconductor layer 101 provided in the outer dummy pad region ODR, it will be referred to as the semiconductor layer 101_1. At least a portion of the semiconductor layer 101_1 is not covered (protected) by the surface protective layer 119. In other words, at least a portion of the semiconductor layer 101_1 is not provided between the CMOS chip 200 and the surface protective layer 119 in the Z direction.

[0081] A plurality of protruding portions PT extending in the Z2 direction are provided on the upper surface of the semiconductor layer 101_1 in the Z2 direction. The protruding portions PT, for example, penetrate the insulating layer 113. The upper surfaces of the protruding portions PT in the Z2 direction are in contact with the insulating layer 114. Portions of the insulating layer 121 provided inside the semiconductor layer 101_1 that overlap with the protruding portions PT when viewed in the Z direction are divided by the semiconductor layer 101_1. The protruding portions PT ground the semiconductor layer 101 to a substrate (not shown) of the memory chip 100 in the manufacturing process of the memory chip 100, and are used to suppress arcing due to charge-up of the semiconductor layer 101 during dry etching, for example. Note that the protruding portions PT do not necessarily have to be provided.

[0082] 1.1.5.1.5 Kerf Area Structure Next, the kerf region KR of the memory chip 100 will be described.

[0083] The kerf region KR is not provided with the electrode 110. Furthermore, the semiconductor layer 101, the wiring layer 116, and the surface protection layer 119 that protects them are not provided in the kerf region KR.

[0084] 1.1.5.2 Cross-sectional structure of a CMOS chip Next, the cross-sectional structure of the CMOS chip 200 will be described.

[0085] In the active pad region AR, a plurality of transistors TR are provided on the upper surface of the semiconductor substrate 201 in the Z2 direction. The transistors TR are used as elements in the command register 11, the address register 12, the sequencer 13, the driver module 14, the row decoder module 15, and the sense amplifier module 16. The transistor TR includes a gate insulating film 202, a gate electrode 203, and a source and a drain (not shown) formed on the semiconductor substrate 201. The gate insulating film 202 is provided on the upper surface of the semiconductor substrate 201 in the Z2 direction. The gate electrode 203 is provided on the upper surface of the gate insulating film 202 in the Z2 direction.

[0086] The gate insulating film 202 and the gate electrode 203 are not provided in the inner dummy pad region IDR, the discharge pad region DCR, and the outer dummy pad region ODR. On the other hand, the gate insulating film 202 and the gate electrode 203 that do not function as part of the transistor TR are provided in the kerf region KR. The gate insulating film 202 and the gate electrode 203 that do not function as part of the transistor TR in the kerf region KR are used, for example, to form an alignment mark. An end of the gate electrode 203 that does not function as part of the transistor TR may define a boundary between the kerf region KR and the outer dummy pad region ODR.

[0087] In the active pad region AR, a conductor 204 is provided on the upper surfaces in the Z2 direction of the gate electrode 203, the source, and the drain. The conductor 204 provided in the active pad region AR has a cylindrical shape extending in the Z direction. In the discharge pad region DCR, the conductor 204 is provided on the upper surfaces in the Z2 direction of the N-type impurity diffusion region NW provided in the semiconductor substrate 201 and the P-type impurity diffusion region PW provided in the semiconductor substrate 201.

[0088] A wiring layer 205 is provided on the upper surface of the conductor 204 in the Z2 direction. A conductor 206 is provided on the upper surface of the wiring layer 205 in the Z2 direction. A wiring layer 207 is provided on the upper surface of the conductor 206 in the Z2 direction. A conductor 208 is provided on the upper surface of the wiring layer 207 in the Z2 direction. A wiring layer 209 is provided on the upper surface of the conductor 208 in the Z2 direction. A conductor 210 is provided on the upper surface of the wiring layer 209 in the Z2 direction. The conductors 204, 206, 208, and 210 provided in the active pad region AR have, for example, a cylindrical shape extending in the Z direction. The conductors 204, 206, 208, and 210 and the wiring layers 205, 207, and 209 provided in the discharge pad region DCR have, for example, a rectangular ring shape surrounding the active pad region AR and the inner dummy pad region IDR when viewed in the Z direction. The N-type impurity diffusion region NW and the P-type impurity diffusion region PW provided in the discharge pad region DCR may also have a rectangular ring shape, or may be provided so as to have multiple regions aligned at a distance from each other along a rectangular ring shape so as to surround the active pad region AR and the inner dummy pad region IDR. The number of wiring layers provided in the CMOS chip 200 is arbitrary.

[0089] An insulating layer 212 is provided on the upper surface of the semiconductor substrate 201 in the Z2 direction. The insulating layer 212 is provided so as to cover the transistor TR, the conductor 204, the wiring layer 205, the conductor 206, the wiring layer 207, the conductor 208, the wiring layer 209, and the conductor 210. An insulating layer 213 is provided on the upper surface of the insulating layer 212 in the Z2 direction.

[0090] An electrode 211a is provided in the same layer as the insulating layer 213 on the upper surface in the Z2 direction of the conductor 210 provided in the active pad region AR. In the inner dummy pad region IDR, an electrode 211i is provided in the same layer as the insulating layer 213. In the outer dummy pad region ODR, an electrode 211o is provided in the same layer as the insulating layer 213. The multiple electrodes 211i and 211o are electrically insulated from various wirings in the memory chip 100 and various wirings in the CMOS chip 200. Electrodes 211d_2 and 211_3 are provided in the same layer as the insulating layer 213 on the upper surface in the Z2 direction of the conductor 210 provided in the discharge pad region DCR. The electrode 211d_2 has a rectangular ring shape surrounding the active pad region AR and the inner dummy pad region IDR when viewed in the Z direction. The electrode 211d_3 has a square ring shape surrounding the electrode 211d_2 when viewed in the Z direction.

[0091] The gate electrode 203, the conductors 204, 206, 208, and 210, the wiring layers 205, 207, and 209, and the electrodes 211a, 211i, 211d, and 211o are made of conductive materials and may include metal materials, p-type semiconductors, or n-type semiconductors. The electrodes 211a, 211i, 211d, and 211o include, for example, copper. The gate insulating film 202, the insulating layer 212, and the insulating layer 213 include, for example, silicon oxide as an insulating material.

[0092] 7, the conductor 120_2 of the memory chip 100 is electrically connected to the P-type impurity diffusion region PW of the semiconductor substrate 201 of the CMOS chip 200 via the electrodes 110d_2 and 211d_2. The conductor 120_3 of the memory chip 100 is electrically connected to the N-type impurity diffusion region NW of the semiconductor substrate 201 of the CMOS chip 200 via the electrodes 110d_3 and 211d_3. Note that the conductor 120_3 may be electrically connected to the P-type impurity diffusion region PW, and the conductor 120_2 may be electrically connected to the N-type impurity diffusion region NW.

[0093] 1.1.6 Cross-sectional structure of the adhesive pad Next, the cross-sectional structure of the bonding pad BP will be described.

[0094] 9 is a cross-sectional view showing an example of the cross-sectional structure of the bonding pad of the memory device according to the first embodiment. In the example of FIG. 9, the electrodes 110d and 211d (i.e., the electrodes 110d_2 and 211d_2, or the electrodes 110d_3 and 211d_3) included in the bonding pad BPd of the discharge pad region DCR are shown. Note that the following description of the bonding pad BPd also applies to the bonding pads BPa, BPi, and BPo.

[0095] As shown in Figure 9, in the process of bonding the memory chip 100 and the CMOS chip 200, the electrode 110d is connected to the electrode 211d. In the example of Figure 9, the area of ​​the electrode 110d and the area of ​​the electrode 211d on the bonding surface are approximately equal. In such a case, if copper is used for the electrode 110d and the electrode 211d, the copper of the electrode 110d and the copper of the electrode 211d may become integrated, making it difficult to confirm the boundary between the copper. However, the bonding can be confirmed by distortion of the bonded shape of the electrode 110d and the electrode 211d due to misalignment during bonding, and misalignment of the copper barrier metal (the occurrence of discontinuities on the side surfaces).

[0096] Furthermore, when the electrodes 110d and 211d are formed by the damascene method, the side surfaces of the electrodes 110d and 211d have tapered shapes, and therefore the cross section along the Z direction at the portion where the electrodes 110d and 211d are bonded together does not have straight sidewalls but has a non-rectangular shape.

[0097] Furthermore, when electrode 110d and electrode 211d are bonded together, the bottom, side, and top surfaces of the copper that forms them are covered with a barrier metal. In contrast, in a typical wiring layer using copper, an insulating layer (such as silicon nitride or silicon carbonitride) that functions to prevent copper oxidation is provided on the top surface of the copper, and no barrier metal is provided. Therefore, even if there is no misalignment in the bonding, it is possible to distinguish this from a typical wiring layer.

[0098] 1.1.7 Cross-sectional structure of memory cell array 10 is a cross-sectional view showing an example of the cross-sectional structure of the memory cell array of the memory device according to Embodiment 1. In FIG. 10, two memory pillars MP included in the memory cell array 10 are shown.

[0099] 10, the semiconductor layer 101 includes, for example, three semiconductor layers 101a, 101b, and 101c. The semiconductor layer 101b is provided on the upper surface of the semiconductor layer 101a in the Z1 direction. The semiconductor layer 101c is provided on the upper surface of the semiconductor layer 101b in the Z1 direction. The semiconductor layer 101b is formed, for example, by replacing the insulating layer 121 provided between the semiconductor layers 101a and 101c. The semiconductor layers 101a to 101c include, for example, silicon. The semiconductor layers 101a to 101c also include, for example, phosphorus (P) as a semiconductor impurity.

[0100] Ten insulating layers 102 and ten wiring layers 103 are alternately stacked on the upper surface of the semiconductor layer 101 in the Z1 direction. In the example of FIG. 10, the ten wiring layers 103 function, in order from the semiconductor layer 101 side, as the select gate line SGS, the word lines WL0 to WL7, and the select gate line SGD. Note that a plurality of wiring layers 103 functioning as the select gate lines SGS and SGD may be provided. For example, a titanium nitride (TiN) / tungsten (W) layer structure may be used as the conductive material of the wiring layer 103. In this case, TiN is formed to cover the tungsten. Titanium nitride functions as a barrier layer to suppress oxidation of tungsten when forming a tungsten film by, for example, chemical vapor deposition (CVD), or as an adhesion layer to improve the adhesion of the tungsten. The wiring layer 103 may also include a high-dielectric-constant material such as aluminum oxide (AlO). In this case, the high-dielectric-constant material is formed to cover the conductive material. For example, in each of the wiring layers 103, a high-dielectric-constant material is provided so as to be in contact with the insulating layers 102 and the side surfaces of the memory pillars MP provided above and below the wiring layer 103. Titanium nitride is then provided so as to be in contact with the high-dielectric-constant material. Tungsten is then provided so as to be in contact with the titanium nitride and to fill the interior of the wiring layer 103.

[0101] An insulating layer 111 is provided on the upper surface of the wiring layer 103 that functions as the select gate line SGD in the Z1 direction.

[0102] A plurality of memory pillars MP are provided in the memory cell array 10. The memory pillars MP have a generally cylindrical shape extending in the Z direction. The memory pillars MP penetrate through ten wiring layers 103. The bottom surfaces of the memory pillars MP reach the semiconductor layer 101. Note that the memory pillars MP may have a structure in which a plurality of pillars are connected in the Z direction.

[0103] Next, the internal configuration of the memory pillar MP will be described. The memory pillar MP includes a block insulating film 140, a charge storage film 141, a tunnel insulating film 142, a semiconductor film 143, a core film 144, and a cap film 145.

[0104] A block insulating film 140, a charge storage film 141, and a tunnel insulating film 142 are stacked on a portion of the side surface and the bottom surface in the Z2 direction of the memory pillar MP, in that order from the outside. More specifically, the block insulating film 140, the charge storage film 141, and the tunnel insulating film 142 on the side surface of the memory pillar MP are removed from the semiconductor layer 101b and its vicinity. A semiconductor film 143 is provided so as to contact the side surface and bottom surface of the tunnel insulating film 142 and the semiconductor layer 101b. The semiconductor film 143 is a region where channels of the memory cell transistor MT and the select transistors ST1 and ST2 are formed. The interior of the semiconductor film 143 is filled with a core film 144. At the upper part of the memory pillar MP in the Z1 direction, a cap film 145 is provided on the upper ends of the semiconductor film 143 and the core film 144. The side surface of the cap film 145 contacts the tunnel insulating film 142. The cap film 145 includes, for example, silicon. A conductor 104 is provided on the upper surface of the cap film 145 in the Z1 direction. A conductor 105 is provided on the upper surface of the conductor 104 in the Z1 direction. The conductor 105 is connected to a wiring layer .

[0105] Fig. 11 is a cross-sectional view taken along line XI-XI in Fig. 10, showing an example of the cross-sectional structure of a memory pillar of the memory device according to the first embodiment. More specifically, Fig. 11 shows the cross-sectional structure of a memory pillar MP in a layer including the wiring layer 103.

[0106] In a cross section including the wiring layer 103, the core film 144 is provided, for example, in the center of the memory pillar MP. The semiconductor film 143 surrounds the side surfaces of the core film 144. The tunnel insulating film 142 surrounds the side surfaces of the semiconductor film 143. The charge storage film 141 surrounds the side surfaces of the tunnel insulating film 142. The block insulating film 140 surrounds the side surfaces of the charge storage film 141. The wiring layer 103 surrounds the side surfaces of the block insulating film 140.

[0107] The semiconductor film 143 is used as a channel (current path) of the memory cell transistors MT0 to MT7 and the select transistors ST1 and ST2. The tunnel insulating film 142 and the block insulating film 140 each contain, for example, silicon oxide. The charge storage film 141 has a function of storing charges. The charge storage film 141 contains, for example, silicon nitride.

[0108] Memory cell transistors MT0 to MT7 are formed by combining a memory pillar MP with a wiring layer 103 that functions as word lines WL0 to WL7. Similarly, a select transistor ST1 is formed by combining a memory pillar MP with a wiring layer 103 that functions as a select gate line SGD. A select transistor ST2 is formed by combining a memory pillar MP with a wiring layer 103 that functions as a select gate line SGS. As a result, each memory pillar MP can function as one NAND string NS.

[0109] 1.2 Effects of the First Embodiment According to the first embodiment, it is possible to improve the yield of the memory devices 3. This effect will be explained below.

[0110] The bonding surfaces of the memory chip 100 and the CMOS chip 200 are divided into an active pad region AR, an inner dummy pad region IDR, a discharge pad region DCR, an outer dummy pad region ODR, and a kerf region KR. The discharge pad region DCR is provided with a bonding pad BPd_2 that electrically connects the wall structure W_2 and the P-type impurity diffusion region PW, and a bonding pad BPd_3 that electrically connects the wall structure W_3 and the N-type impurity diffusion region NW. Each of the bonding pad BPd_2 and the wall structure W_2 includes a single continuous conductor that surrounds the inner dummy pad region IDR and the active pad region AR. Each of the bonding pad BPd_3 and the wall structure W_3 includes a single continuous conductor that surrounds the bonding pad BPd_2 and the wall structure W_2. The coverage of the bonding pads BPd_2 and BPd_3 in the discharge pad region DCR is designed to be 3% or more and 40% or less. This prevents the difference between the coverage of the discharge pad region DCR and that of the surrounding region from becoming excessive. Therefore, when a process such as CMP (Chemical Mechanical Polishing) is performed in the process of forming the bonding surfaces of the memory chip 100 and the CMOS chip 200, it is possible to prevent the occurrence of steps due to erosion in the discharge pad region DCR. Therefore, it is possible to reduce the occurrence of bonding defects in the process of bonding the memory chip 100 and the CMOS chip 200.

[0111] Specifically, the distance P between the bonding pad BPd_2 and the bonding pad BPd_3 is longer than the distance P0 between the conductor 120_2 and the conductor 120_3. This makes it possible to reduce the coverage of the bonding pads BPd_2 and BPd_3 in the discharge pad region DCR compared to when the distance P is the same length as the distance P0, while satisfying the constraints of the wall structures W_1 to W_4.

[0112] Supplementally, the wall structure W_2 includes a conductor 120_2 that electrically connects the wiring layer 116 and the P-type impurity diffusion region PW. The wall structure W_3 includes a conductor 120_3 that electrically connects the wiring layer 116 and the N-type impurity diffusion region NW. The conductors 120_2 and 120_3 have a long (deep) structure in the Z direction. In order to form the conductors 120_2 and 120_3 with sufficiently precise lengths, it is desirable to simultaneously form the wall structure W_1 including the conductor 120_1 and the wall structure W_4 including the conductor 120_4, which are arranged to sandwich the conductors 120_2 and 120_3.

[0113] However, the area allocated to the formation of the wall structures W_1 to W_4 is limited. Therefore, when the distance P is equal to the distance P0, the coverage of the bonding pads BPd_2 and BPd_3 in the discharge pad area DCR may not be sufficient to prevent the occurrence of bonding defects. On the other hand, the area allocated to the formation of the P-type impurity diffusion area PW and the N-type impurity diffusion area NW on the CMOS chip 200 side is relatively large.

[0114] According to the first embodiment, when viewed in the Z direction, the portion of the wiring layer 108_2 overlapping with the bonding pad BPd_2 is located closer to the inner dummy pad region IDR than the portion overlapping with the conductor 120_2. When viewed in the Z direction, the portion of the wiring layer 108_3 overlapping with the bonding pad BPd_3 is located closer to the outer dummy pad region ODR than the portion overlapping with the conductor 120_3. This allows the distance P to be longer than the distance P0 while satisfying the constraints on the wall structures W_11 to W_4.

[0115] Furthermore, bonding pads BPo electrically insulated from the semiconductor substrate 201 are formed in the outer dummy pad region ODR. The coverage of the bonding pads BPo in the outer dummy pad region ODR is designed to be 3% or more and 20% or less. Alternatively, in each of the memory chip 100 and the CMOS chip 200, the coverage of the bonding pads BPo in the outer dummy pad region ODR is designed to be 1 / 3 or more and 2 / 3 or less of the coverage of the bonding pads BPd_2 and BPd_3 in the discharge pad region DCR. This makes it possible to make the coverage gradient between the kerf region KR, which has a coverage of 0%, and the discharge pad region DCR, which has a relatively large coverage, gentle. This makes it possible to suppress the occurrence of steps due to erosion in the discharge pad region DCR, the outer dummy pad region ODR, and the kerf region KR. This therefore reduces the occurrence of bonding defects in the bonding process of the memory chip 100 and the CMOS chip 200.

[0116] 2. Second embodiment Next, the memory device 3 according to the second embodiment will be described. The memory device 3 according to the second embodiment differs from the memory device 3 according to the first embodiment in that the area of ​​the bonding pad BP is different between the memory chip 100 side and the CMOS chip 200 side. In the following explanation, the explanation of the same configuration as the first embodiment will be omitted, and the configuration different from the first embodiment will be mainly explained.

[0117] 2.1 Cross-sectional structure of the bonding pad FIG. 12 is a cross-sectional view showing a first example of the cross-sectional structure of the bonding pad of the memory device according to the second embodiment. FIG. 13 is a cross-sectional view showing a second example of the cross-sectional structure of the bonding pad of the memory device according to the second embodiment. FIGS. 12 and 13 correspond to FIG. 9 in the first embodiment. In the example of FIG. 12, electrodes 110d and 211d' (i.e., electrodes 110d_2 and 211d_2', or electrodes 110d_3 and 211d_3') included in the bonding pad BPd' of the discharge pad area DCR are shown. In the example of FIG. 13, electrodes 110d' and 211d (i.e., electrodes 110d_2' and 211d_2, or electrodes 110d_3' and 211d_3) included in the bonding pad BPd' of the discharge pad area DCR are shown.

[0118] 12, an electrode 211d' is provided instead of the electrode 211d. The area of ​​the electrode 211d' on the bonding surface is smaller than the area of ​​the electrode 110d on the bonding surface.

[0119] 13, an electrode 110d' is provided instead of the electrode 110d. The area of ​​the electrode 110d' on the bonding surface is smaller than the area of ​​the electrode 211d on the bonding surface.

[0120] 2.2 Effects of the Second Embodiment According to the second embodiment, the area of ​​the bonding pad BPd' in the discharge pad region DCR on the bonding surface is different between the memory chip 100 side and the CMOS chip 200 side. This prevents the electrodes with smaller areas on the bonding surface from protruding from the electrodes with larger areas even if misalignment occurs between the memory chip 100 and the CMOS chip 200 during the bonding process.

[0121] Furthermore, the coverage of the electrodes, which has a reduced area on the bonding surface in the discharge pad region DCR, can be further reduced. This makes it possible to suppress the occurrence of steps due to erosion in the discharge pad region DCR. As a result, it is possible to reduce the occurrence of bonding defects in the bonding process of the memory chip 100 and the CMOS chip 200.

[0122] 3. Third embodiment Next, the memory device 3 according to the third embodiment will be described. The memory device 3 according to the third embodiment is different from the memory device 3 according to the first embodiment in that at least one of the bonding pads provided in the discharge pad region DCR is not in a square ring shape. In the following description, the description of the same configuration as in the first embodiment will be omitted, and the configuration different from the first embodiment will be mainly described.

[0123] 3.1 Planar layout of bonding pad First, a first example will be described. The first example corresponds to a case where the inner bonding pad in the discharge pad region DCR is not in a rectangular ring shape.

[0124] Fig. 14 is a plan view showing a first example of a planar layout of a part of a wall structure and a bonding pad in a discharge pad region of a memory device according to the third embodiment. Fig. 15 is a plan view showing a first example of a planar layout of a bonding pad in a discharge pad region of a memory device according to the third embodiment. Figs. 14 and 15 correspond to Figs. 9 and 5 in the first embodiment, respectively.

[0125] As shown in FIG. 14, bonding pads BPd_2" and BPd_3 are arranged in the discharge pad region DCR. The memory chip 100 is further provided with a wall structure W_2" corresponding to the bonding pad BPd_2" and a wall structure W_3 corresponding to the bonding pad BPd_3.

[0126] The bonding pad BPd_2" includes a plurality of rectangular conductors arranged at a distance from each other to surround the active pad area AR and the inner dummy pad area IDR. The wall structure W_2" includes a plurality of rectangular conductors arranged at a distance from each other to surround the bonding pad BPd_2" when viewed in the Z direction.

[0127] The wall structure W_3 has a rectangular ring shape surrounding the wall structure W_2''. The laminating pad BPd_3 has a rectangular ring shape surrounding the wall structure_3 when viewed in the Z direction.

[0128] The distance P between the laminating pad BPd_2'' and the laminating pad BPd_3 is longer than the distance P0 between the wall structure W_2'' and the wall structure W_3.

[0129] As shown in FIG. 15, the coverage of the bonding pads BPd_2" and BPd_3 in the discharge pad region DCR is calculated, for example, as the ratio of the area of ​​the bonding pads BPd_2" and BPd_3 to the area of ​​the unit region UDCR1. The unit region UDCR1 is, for example, a rectangular region having a center line of the width D2 of the bonding pad BPd_2" and a center line of the width D3 of the bonding pad BPd_3 as two opposing sides. Both ends of the sides along the center line of the width D2 of the bonding pad BPd_2" of the rectangular region that forms the unit region UDCR1 are each located, for example, at the center of two adjacent electrodes in the bonding pad BPd_2". The coverage of the bonding pads BPd_2" and BPd_3 in the discharge pad region DCR is designed, for example, to be 3% or more and 40% or less.

[0130] Next, a second example will be described. The second example corresponds to a case where the outer bonding pad in the discharge pad region DCR is not in a rectangular ring shape.

[0131] Fig. 16 is a plan view showing a second example of a planar layout of a part of a wall structure and a bonding pad in a discharge pad region of a memory device according to the third embodiment. Fig. 17 is a plan view showing a second example of a planar layout of a bonding pad in a discharge pad region of a memory device according to the third embodiment. Figs. 16 and 17 correspond to Figs. 9 and 5 in the first embodiment, respectively.

[0132] As shown in FIG. 16, in the discharge pad region DCR, bonding pads BPd_2 and BPd_3" are arranged. Then, a wall structure W_2 corresponding to the bonding pad BPd_2 and a wall structure W_3" corresponding to the bonding pad BPd_3" are further provided.

[0133] The bonding pad BPd_2 has a rectangular ring shape surrounding the active pad region AR and the inner dummy pad region IDR. The wall structure W_2 has a rectangular ring shape surrounding the bonding pad BPd_2 when viewed in the Z direction.

[0134] The wall structure W_3" includes a plurality of rectangular conductors arranged at a distance from each other to surround the wall structure W_2. The bonding pad BPd_3" includes a plurality of rectangular conductors arranged at a distance from each other to surround the wall structure W_3" when viewed in the Z direction.

[0135] The distance P between the laminating pad BPd_2 and the laminating pad BPd_3" is longer than the distance P0 between the wall structure W_2 and the wall structure W_3".

[0136] As shown in FIG. 17, the coverage of the bonding pads BPd_2 and BPd_3" in the discharge pad region DCR is calculated, for example, as the ratio of the area of ​​the bonding pads BPd_2 and BPd_3" to the area of ​​the unit region UDCR2. The unit region UDCR2 is, for example, a rectangular region having a center line of the width D2 of the bonding pad BPd_2 and a center line of the width D3 of the bonding pad BPd_3" as two opposing sides. Both ends of the sides along the center line of the width D3 of the bonding pad BPd_3" of the rectangular region forming the unit region UDCR2 are respectively located, for example, at the centers of two adjacent electrodes in the bonding pad BPd_3". The coverage of the bonding pads BPd_2 and BPd_3" in the discharge pad region DCR is designed, for example, to be 3% or more and 40% or less.

[0137] 3.2 Effects of the third embodiment According to the first example of the third embodiment, the bonding pad BP_2" includes a plurality of conductors that are arranged at a distance from each other and surround the active pad region AR and the inner dummy pad region IDR when viewed in the Z direction. According to the second example of the third embodiment, the bonding pad BPd_3" includes a plurality of conductors that are arranged at a distance from each other and surround the wall structure W_3" when viewed in the Z direction. This makes it possible to reduce the coverage of the bonding pad BPd in ​​the discharge pad region DCR compared to when both the bonding pads BPd_2 and BPd_3 are configured as a single continuous conductor. This makes it possible to suppress the occurrence of steps due to erosion in the discharge pad region DCR. Therefore, it is possible to reduce the occurrence of bonding defects in the bonding process of the memory chip 100 and the CMOS chip 200.

[0138] 4. Modifications, etc. 4.1 First Modification In the first, second, and third embodiments, the case where no additional wall structure is formed on the kerf region KR side of the wall structures W_1 to W_4 has been described, but this is not limiting. For example, additional wall structures may be formed on the kerf region KR side of the wall structures W_1 to W_4.

[0139] Fig. 18 is a plan view showing an example of a planar layout of a bonding pad of a memory device according to Modification 1. Fig. 18 corresponds to Fig. 4 in the first embodiment.

[0140] As shown in FIG. 18, in addition to the laminating pad BPo, a laminating pad BPc may be further arranged in the outer dummy pad region ODR. The laminating pad BPc includes, for example, one continuous electrode. The one electrode included in the laminating pad BPc has a square ring shape surrounding the laminating pad BPd_3. Note that at least a portion of the laminating pad BPo may be arranged between the laminating pad BPd_3 and the laminating pad BPc. At least a portion of the laminating pad BPo may be arranged between the laminating pad BPd_3 and the kerf region KR.

[0141] 19 is a cross-sectional view showing an example of the cross-sectional structure of a memory device according to Modification 1. Fig. 19 corresponds to Fig. 7 in the first embodiment.

[0142] 19, the outer dummy pad region ODR is provided with a wall structure W_5 provided on the memory chip 100 and various wirings connecting the wall structure W_5 and the semiconductor substrate 201. The wall structure W_5 includes a conductor 120_5.

[0143] The conductor 120_5 has a rectangular ring shape surrounding the conductor 120_4 when viewed in the Z direction. The conductor 120_5 extends in the Z direction. The Z2-direction end of the conductor 120_5 contacts, for example, the insulating layer 115 closer to the kerf region KR than the semiconductor layer 101_1. That is, the conductor 120_5 is located in an area not covered by the surface protective layer 119 when viewed in the Z direction. The conductor 120_5 is electrically connected to the electrode 211c of the CMOS chip 200 via the corresponding conductor 105, wiring layer 106, conductor 107, wiring layer 108, conductor 109, and electrode 110c. The electrodes 110c and 211c correspond to the bonding pad BPc. That is, the electrodes 110c and 211c each have a rectangular ring shape surrounding the electrodes 110d_3 and 211d_3 when viewed in the Z direction. The electrode 211c is electrically connected to the semiconductor substrate 201 via the corresponding conductor 210, wiring layer 209, conductor 208, wiring layer 207, conductor 206, wiring layer 205, and conductor 204.

[0144] The conductor 105, the wiring layer 106, the conductor 107, the wiring layer 108, and the conductor 109, which electrically connect the conductor 120_5 and the electrode 110c, each have, for example, a rectangular ring shape when viewed in the Z direction. The conductor 210, the wiring layer 209, the conductor 208, the wiring layer 207, the conductor 206, the wiring layer 205, and the conductor 204, which electrically connect the semiconductor substrate 201 and the electrode 211c, each have, for example, a rectangular ring shape when viewed in the Z direction.

[0145] With the above-described configuration, the wall structure W_5 and the various wirings connecting the wall structure W_5 and the semiconductor substrate 201 can function as part of a further wall structure (crack stopper) that prevents cracks or peeling from reaching the active pad region AR when cracks or peeling of the insulating layer occurs at the edge of the memory device 3 during the dicing process. This allows the yield of the memory device 3 to be improved.

[0146] 4.2 Second variant In addition, in the above-mentioned first embodiment, second embodiment, third embodiment, and first modified example, the wall structures W_2 and W_3 do not overlap with the bonding pads BPd_2 and BPd_3, respectively, when viewed in the Z direction. However, this is not limited to this. For example, the wall structures W_2 and W_3 may be configured to overlap with the bonding pads BPd_2 and BPd_3, respectively. Also, at least one of the wall structures W_1 and W_4 may be omitted. Below, the configuration different from the first modified example will be mainly described. The description of the configuration equivalent to the first modified example will be omitted.

[0147] Fig. 20 is a cross-sectional view showing an example of the cross-sectional structure of a memory device according to Modification 2. Fig. 20 corresponds to Fig. 19 in Modification 1.

[0148] 20, the discharge pad region DCR is provided with wall structures W_1 to W_3 provided on the memory chip 100 and various wirings connecting the wall structures W_1 to W_3 to the semiconductor substrate 201. The wall structure W_4 shown in FIG. 19 is not provided.

[0149] The wall structure W_2, the bonding pad BPd_2, and the conductor 105, wiring layer 106, conductor 107, wiring layer 108_2, and conductor 109 connecting the wall structure W_2 and the bonding pad BPd_2 overlap each other when viewed in the Z direction. In other words, the wall structure W_2, the bonding pad BPd_2, and the conductor 105, wiring layer 106, conductor 107, wiring layer 108_2, and conductor 109 connecting the wall structure W_2 and the bonding pad BPd_2 are aligned in the Z direction without bending along the XY plane as a whole.

[0150] Similarly, the wall structure W_3, the bonding pad BPd_3, and the conductor 105, wiring layer 106, conductor 107, wiring layer 108_3, and conductor 109 connecting the wall structure W_3 and the bonding pad BPd_3 overlap each other when viewed in the Z direction. In other words, the wall structure W_3, the bonding pad BPd_3, and the conductor 105, wiring layer 106, conductor 107, wiring layer 108_3, and conductor 109 connecting the wall structure W_3 and the bonding pad BPd_3 are aligned in the Z direction without bending along the XY plane as a whole.

[0151] As a result, the distance between the wall structure W_2 and the wall structure W_3 and the distance between the laminating pad BPd_2 and the laminating pad BPd_3 become substantially equal to the distance P'.

[0152] According to the second modified example, the wall structure W_4 is omitted, thereby relaxing the constraints on the area allocated to the formation of the wall structures W_1 to W_3. As a result, it is possible to ensure the distance P' between the laminating pad BPd_2 and the laminating pad BPd_3 while satisfying the requirement for coverage, without bending the structure between the wall structure W_2 and the laminating pad BPd_2 and the structure between the wall structure W_3 and the laminating pad BPd_3.

[0153] In addition, in the second modified example, a wall structure W_5 is provided. This allows the wall structure W_5 to function as a substitute for the omitted wall structure W_4. This reduces the effect of omitting the wall structure W_4 on the formation of the wall structures W_2 and W_3.

[0154] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the inventions and their equivalents as defined in the claims. [Explanation of symbols]

[0155] 1. Memory system 2...Memory controller 3...Memory device 10...Memory cell array 11...Command register 12...Address register 13...Sequencer 14...Driver module 15...Row decoder module 16...Sense amplifier module 100...memory chips 101...Semiconductor layer 102, 111, 112, 113, 114, 115, 117, 118, 121, 212, 213...insulating layer 103,106,108,116,205,207,209...Wiring layer 104, 105, 107, 109, 120, 204, 206, 208, 210...Conductors 110,211...electrode 119…Surface protective layer 140...Block insulating film 141...Charge storage film 142...Tunnel insulating film 143...Semiconductor film 144...Core membrane 145...Cap membrane 200...CMOS chip 201...Semiconductor substrate 202...Gate insulating film 203...Gate electrode

Claims

1. a first chip and a second chip that are in contact with each other at a first surface that is divided into a first region, a second region surrounding the first region, and a third region surrounding the second region; The first chip comprises: a substrate on which the first diffusion region and the second diffusion region are provided; a first electrode portion including a single continuous conductor surrounding the first region in the second region; a second electrode portion that is spaced apart from the first electrode portion in the second region and surrounds the first region; Including, The second chip is a first wiring layer; a third electrode portion including a single continuous conductor surrounding the first region in the second region and in contact with the first electrode portion; a fourth electrode portion that is spaced apart from the third electrode portion in the second region, surrounds the first region, and is in contact with the second electrode portion; a first wall portion that is in contact with the first wiring layer, includes one continuous conductor that surrounds the first region, and is electrically connected to the first diffusion region via the third electrode portion and the first electrode portion; a second wall portion that is in contact with the first wiring layer, that is spaced apart from the first wall portion and surrounds the first region, and that is electrically connected to the second diffusion region via the fourth electrode portion and the second electrode portion; Including, a first ratio of an area occupied by the first electrode portion and the second electrode portion in the second region, and a second ratio of an area occupied by the third electrode portion and the fourth electrode portion in the second region are each 3% or more and 40% or less; each of the second electrode portion and the fourth electrode portion includes a plurality of conductors arranged apart from each other so as to surround the first region; Memory device.

2. the first chip further includes a fifth electrode portion provided in the third region; the second chip further includes a sixth electrode portion provided in the third region and in contact with the fifth electrode portion; the fifth electrode portion and the sixth electrode portion are electrically insulated from the substrate; The memory device of claim 1 .

3. a third ratio of an area of ​​the fifth electrode portion to the third region and a fourth ratio of an area of ​​the sixth electrode portion to the third region are each 3% or more and 20% or less; The memory device of claim 2 .

4. a third ratio of the area of ​​the fifth electrode portion to the third region is equal to or greater than 1 / 3 and equal to or less than 2 / 3 of the first ratio; a fourth ratio of the area of ​​the sixth electrode portion to the third region is equal to or greater than 1 / 3 and equal to or less than 2 / 3 of the second ratio; The memory device of claim 2 .

5. a first chip and a second chip that are in contact with each other at a first surface that divides the first chip into a first region and a second region that surrounds the first region; The first chip comprises: a substrate having a first diffusion region and a second diffusion region; a first electrode portion surrounding the first region with the second region; a second electrode portion that is spaced apart from the first electrode portion in the second region and surrounds the first region; Including, The second chip is a first wiring layer; a third electrode portion that surrounds the first region in the second region and is in contact with the first electrode portion; a fourth electrode portion that is spaced apart from the third electrode portion in the second region and surrounds the first region and is in contact with the second electrode portion; a first wall portion that is in contact with the first wiring layer, surrounds the first region, and is electrically connected to the first diffusion region via the third electrode portion and the first electrode portion; a second wall portion that is in contact with the first wiring layer, that is spaced apart from the first wall portion and surrounds the first region, and that is electrically connected to the second diffusion region via the fourth electrode portion and the second electrode portion; Including, a distance between the third electrode portion and the fourth electrode portion is longer than a distance between the first wall portion and the second wall portion; Memory device.

6. a first chip and a second chip that are in contact with each other at a first surface that divides the first chip into a first region and a second region that surrounds the first region; The first chip comprises: A substrate; a first electrode pad including a single continuous conductor surrounding the first region in the second region; Including, The second chip is a second electrode pad including a single continuous conductor surrounding the first region in the second region and contacting the first electrode pad; a first wall portion including a single continuous conductor surrounding the first region and electrically connected to the substrate via the second electrode pad and the first electrode pad; Including, The second chip is a first conductor having a first portion and a second portion overlapping the first wall portion and the second electrode pad at different positions, respectively, when viewed in a first direction intersecting the first surface; a second conductor extending in the first direction and connecting the first wall portion and the first portion; a third conductor extending in the first direction and connecting the second electrode pad and the second portion; Further comprising: Memory device.

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