Substrate for printed wiring board and printed wiring board

Abstract

This printed wiring-board substrate comprises: a base film having a main surface; a sintered body layer which is disposed on the main surface of the base film and which is formed of a plurality of copper particles that were sintered; and an electroless copper plating layer which is disposed on the sintered body layer. The content of palladium in the sintered body layer is 0.1 at% or less.

Description

[Technical Field]

[0001] The present disclosure relates to a substrate for a printed wiring board and a printed wiring board. This application claims priority to Japanese Patent Application No. 2022-053406, filed on March 29, 2022. The entire contents of the Japanese patent application are incorporated herein by reference. [Background technology]

[0002] For example, International Publication No. 2019 / 208077 (Patent Document 1) describes a substrate for a printed wiring board. The substrate for a printed wiring board described in Patent Document 1 has a base film, a sintered body layer, and an electroless copper plating layer.

[0003] The base film has a main surface. A sintered body layer is disposed on the main surface of the base film. The sintered body layer is formed by sintering a plurality of copper particles. An electroless copper plating layer is disposed on the sintered body layer. The electroless copper plating layer is a copper layer formed by electroless plating.

[0004] A printed wiring board is formed using the substrate for printed wiring board described in Patent Document 1. In this process, first, a resist pattern having openings is placed on an electroless copper plating layer, and electrolytic plating is performed on the electroless copper plating layer exposed from the openings, thereby forming an electrolytic copper plating layer on the electroless copper plating layer.

[0005] Second, after the resist pattern is removed, the electroless copper plating layer and the sintered body layer exposed between adjacent electrolytic copper plating layers are removed by etching. In this way, using the printed wiring board described in Patent Document 1, a printed wiring board having wiring composed of a sintered body layer, an electroless copper plating layer, and an electrolytic copper plating layer laminated on the main surface of a base film is formed. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] International Publication No. 2019 / 208077 Summary of the Invention

[0007] The substrate for printed wiring boards of the present disclosure includes a base film having a main surface, a sintered body layer disposed on the main surface of the base film and formed of a plurality of sintered copper particles, and an electroless copper plating layer disposed on the sintered body layer. The palladium content in the sintered body layer is 0.1 atomic percent or less. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a cross-sectional view of a substrate 100 for a printed wiring board. [Figure 2] FIG. 2 is a process diagram showing a method for manufacturing the substrate 100 for a printed wiring board. [Figure 3] FIG. 3 is a cross-sectional view illustrating the preparation step S1. [Figure 4] FIG. 4 is a cross-sectional view illustrating the sintered body layer forming step S2. [Figure 5] FIG. 5 is a schematic diagram of a plating apparatus 300 used in the electroless plating step S3. [Figure 6] FIG. 6 is a cross-sectional view illustrating the first step S31. [Figure 7] FIG. 7 is a cross-sectional view illustrating the second step S32. [Figure 8] FIG. 8 is a cross-sectional view of the printed wiring board 200. [Figure 9] FIG. 9 is a process diagram showing a method for manufacturing printed wiring board 200. [Figure 10] FIG. 10 is a cross-sectional view illustrating the resist pattern forming step S4. [Figure 11] FIG. 11 is a cross-sectional view illustrating the electrolytic plating step S5. [Figure 12] FIG. 12 is a cross-sectional view illustrating the resist pattern removing step S6. [Figure 13] FIG. 13 is a plan view of the evaluation TEG. DETAILED DESCRIPTION OF THE INVENTION

[0009] [Problem to be solved by this disclosure] Typically, when an electroless copper plating layer is formed, palladium is applied as a catalyst to the surface of the sintered body layer (the surface of the sintered body layer opposite the main surface of the base film). Furthermore, when the electroless copper plating layer is formed, the base film on which the sintered body layer is formed is immersed in a plating solution. Because the sintered body layer is porous, the plating solution penetrates into the sintered body together with the palladium.

[0010] As a result, the palladium content in the sintered body layer increases in the substrate for printed wiring boards described in Patent Document 1. When the palladium content in the sintered body layer increases, the palladium needs to be removed during the etching process, making it difficult to achieve a fine pitch for the wiring formed on the main surface of the base film.

[0011] The present disclosure has been made in view of the above-described problems of the conventional art. More specifically, the present disclosure provides a substrate for a printed wiring board that enables fine-pitch wiring.

[0012] [Effects of this disclosure] According to the substrate for printed wiring board of the present disclosure, it is possible to achieve fine pitch wiring.

[0013] [Description of the embodiments of the present disclosure] First, embodiments of the present disclosure will be listed and described.

[0014] (1) A substrate for a printed wiring board according to an embodiment includes a base film having a main surface, a sintered body layer disposed on the main surface of the base film and formed of a plurality of sintered copper particles, and an electroless copper plating layer disposed on the sintered body layer. The palladium content in the sintered body layer is 0.1 atomic percent or less. The substrate for a printed wiring board according to (1) above allows for fine-pitch wiring.

[0015] (2) In the substrate for printed wiring boards of (1) above, the palladium content in the sintered body layer may be 0.005 atomic percent or more. According to the substrate for printed wiring boards of (2) above, it is possible to ensure adhesion between the sintered body layer and the base film.

[0016] (3) In the substrate for printed wiring board of (1) or (2), the content of nickel in the sintered body layer may be 0.5 atomic percent or less.

[0017] (4) In the substrate for printed wiring boards of (3) above, the nickel content in the sintered body layer may be 0.03 atomic percent or more. According to the substrate for printed wiring boards of (4) above, it is possible to ensure adhesion between the sintered body layer and the base film.

[0018] (5) In the substrate for printed wiring boards according to (1) to (4) above, the content of palladium in the electroless copper plating layer may be 0.1 atomic percent or less.

[0019] (6) In the substrate for printed wiring boards according to (1) to (5), the content of palladium in the base film on the main surface may be 0.01 atomic percent or less.

[0020] (7) A printed wiring board according to an embodiment includes a base film having a main surface and wiring disposed on the main surface of the base film. The wiring includes a sintered body layer disposed on the main surface of the base film and formed from a plurality of sintered copper particles, an electroless copper plating layer disposed on the sintered body layer, and an electrolytic copper plating layer disposed on the electroless copper plating layer. The palladium content in the sintered body layer is 0.1 atomic percent or less. The printed wiring board described above in (7) allows for fine-pitch wiring.

[0021] (8) In the printed wiring board of (7), the wiring may extend along a second direction perpendicular to a first direction that is a normal direction to the main surface of the base film, and may have a plurality of wiring portions arranged along a third direction perpendicular to the first and second directions. The distance between any two adjacent ones of the plurality of wiring portions may be 15 μm or less.

[0022] [Details of the embodiments of the present disclosure] Next, details of an embodiment of the present disclosure will be described with reference to the drawings. In the following drawings, the same or corresponding parts will be given the same reference numerals, and redundant explanations will not be repeated. A substrate for a printed wiring board and a printed wiring board according to the embodiment will be referred to as a substrate for a printed wiring board 100 and a printed wiring board 200, respectively.

[0023] (Configuration of printed wiring board substrate 100) The configuration of the printed wiring board substrate 100 will be described below.

[0024] 1 is a cross-sectional view of a substrate 100 for a printed wiring board. As shown in FIG. 1, the substrate 100 for a printed wiring board has a base film 10, a sintered body layer 21, and an electroless copper plating layer 31. Printed wiring board substrate 100 may further include a sintered body layer 22 and an electroless copper plating layer 32.

[0025] The base film 10 has a first main surface 10a and a second main surface 10b. The first main surface 10a and the second main surface 10b are end surfaces of the base film 10 in the thickness direction. The second main surface 10b is the surface opposite to the first main surface 10a. The base film 10 is made of a flexible insulating material. The base film 10 is made of, for example, polyimide, liquid crystal polymer, fluororesin, etc. However, the constituent materials of the base film 10 are not limited to these.

[0026] The palladium content in the base film 10 at the first principal surface 10a and the second principal surface 10b may be 0.01 atomic percent or less. The palladium content in the base film 10 at the first principal surface 10a and the second principal surface 10b may be, for example, 0.001 atomic percent or more. The nickel content in the base film 10 at the first principal surface 10a and the second principal surface 10b may be 0.05 atomic percent or less. The palladium content in the base film 10 is measured in a cross section perpendicular to the first principal surface 10a and the second principal surface 10b using an energy dispersive X-ray analyzer (SU8020 manufactured by Hitachi High-Technologies Corporation). The acceleration voltage during measurement is 6 kV. The palladium content in the base film 10 at the first principal surface 10a (second principal surface 10b) is defined as the palladium content in the base film 10 in an arbitrary region up to a position 100 nm away from the interface with the sintered body layer 21 (sintered body layer 22). The nickel content in the base film 10 is measured in the same manner.

[0027] The sintered body layer 21 is disposed on the first main surface 10a. The sintered body layer 21 is formed of a plurality of sintered copper particles. Therefore, the sintered body layer 21 is porous. The average particle size of the copper particles contained in the sintered body layer 21 may be 1 nm or more, or 30 nm or more. The average particle size of the copper particles contained in the sintered body layer 21 is 100 nm or less, or 500 nm or less. In other words, the copper particles contained in the sintered body layer 21 may be nano-copper particles. The average particle size of the copper particles contained in the sintered body layer 21 is measured using a particle size distribution measuring device (Microtrac Particle Size Distribution Meter UPA-150EX manufactured by Nikkiso Co., Ltd.).

[0028] The palladium content in the sintered body layer 21 is 0.1 atomic percent or less. The palladium content in the sintered body layer 21 is, for example, 0.005 atomic percent or more. By making the palladium content in the sintered body layer 21 0.005 atomic percent or more, it is possible to ensure adhesion to the base film 10 due to an anchoring effect. The palladium content in the sintered body layer 21 may be 0 atomic percent. In other words, the sintered body layer 21 may not contain palladium. The palladium content in the sintered body layer 21 is the palladium content in any region including the entire thickness direction from the interface between the base film 10 and the sintered body layer 21 to the interface between the sintered body layer 21 and the electroless copper plating layer 31. The palladium content in the sintered body layer 21 is measured using the same method as the palladium content in the base film 10, except for the measurement region.

[0029] The nickel content in the sintered body layer 21 is, for example, 0.5 atomic percent or less. The nickel content in the sintered body layer 21 is, for example, 0.03 atomic percent or more. By making the nickel content in the sintered body layer 21 0.03 atomic percent or more, it is possible to ensure adhesion to the base film 10 due to the anchoring effect. The nickel content in the sintered body layer 21 is the nickel content in any region including the entire thickness direction from the interface between the base film 10 and the sintered body layer 21 to the interface between the sintered body layer 21 and the electroless copper plating layer 31. The nickel content in the sintered body layer 21 is measured by the same method as the palladium content in the sintered body layer 21, except for the measurement region.

[0030] The sintered body layer 22 is disposed on the second main surface 10b. The sintered body layer 22 is formed of a plurality of sintered copper particles. Therefore, the sintered body layer 22 is porous. The average particle size of the copper particles contained in the sintered body layer 22 may be 1 nm or more, or 30 nm or more. The average particle size of the copper particles contained in the sintered body layer 22 may be 100 nm or less, or 500 nm or less. In other words, the copper particles contained in the sintered body layer 22 may be nano-copper particles. The average particle size of the copper particles contained in the sintered body layer 22 is measured by the same method as the average particle size of the copper particles contained in the sintered body layer 21.

[0031] The palladium content in the sintered body layer 22 is 0.1 atomic percent or less. The palladium content in the sintered body layer 22 is, for example, 0.005 atomic percent or more. By making the palladium content in the sintered body layer 22 0.005 atomic percent or more, it is possible to ensure adhesion to the base film 10 due to an anchoring effect. The palladium content in the sintered body layer 22 may be 0 atomic percent. In other words, the sintered body layer 22 may not contain palladium. The palladium content in the sintered body layer 22 is the palladium content in any region including the entire thickness direction from the interface between the base film 10 and the sintered body layer 22 to the interface between the sintered body layer 22 and the electroless copper plating layer 32. The palladium content in the sintered body layer 22 is measured by the same method as the palladium content in the sintered body layer 21, except for the measurement region.

[0032] The nickel content in the sintered body layer 22 is, for example, 0.5 atomic percent or less. The nickel content in the sintered body layer 22 is, for example, 0.03 atomic percent or more. By making the nickel content in the sintered body layer 22 0.03 atomic percent or more, it is possible to ensure adhesion to the base film 10 due to the anchoring effect. The nickel content in the sintered body layer 22 is the nickel content in any region including the entire thickness direction from the interface between the base film 10 and the sintered body layer 22 to the interface between the sintered body layer 22 and the electroless copper plating layer 32. The nickel content in the sintered body layer 22 is measured by the same method as the palladium content in the sintered body layer 22, except for the measurement region.

[0033] The electroless copper plating layer 31 is disposed on the sintered body layer 21. The electroless copper plating layer 31 is a copper layer formed by electroless plating. The palladium content in the electroless copper plating layer 31 is 0.1 atomic percent or less. When the electroless copper plating layer 31 is formed using palladium as a catalyst, it is not possible to form an electroless copper plating layer 31 with a palladium content of 0.1 atomic percent or less. The palladium content in the electroless copper plating layer 31 is the palladium content in any region including the entire thickness direction from the interface between the sintered body layer 21 and the electroless copper plating layer 31 to the surface of the electroless copper plating layer 31 opposite the interface. The palladium content in the electroless copper plating layer 31 is measured by the same method as the palladium content in the base film 10, except for the measurement region.

[0034] The nickel content in the electroless copper plating layer 31 is, for example, 0.03 atomic percent or more and 0.5 atomic percent or less. Nickel is added to relieve internal stress acting on the electroless copper plating layer 31. The nickel content in the electroless copper plating layer 31 is the nickel content in any region including the entire thickness direction from the interface between the sintered body layer 21 and the electroless copper plating layer 31 to the surface of the electroless copper plating layer 31 opposite to the interface. The nickel content in the electroless copper plating layer 31 is measured by the same method as the palladium content in the electroless copper plating layer 31, except for the measurement region.

[0035] The electroless copper plating layer 32 is disposed on the sintered body layer 22. The electroless copper plating layer 32 is a copper layer formed by electroless plating. The palladium content in the electroless copper plating layer 32 is 0.1 atomic percent or less. The palladium content in the electroless copper plating layer 32 is the palladium content in any region including the entire thickness direction from the interface between the sintered body layer 22 and the electroless copper plating layer 32 to the surface of the electroless copper plating layer 32 opposite the interface. The palladium content in the electroless copper plating layer 32 is measured by the same method as the palladium content in the electroless copper plating layer 31, except for the measurement region.

[0036] The nickel content in the electroless copper plating layer 32 is, for example, 0.03 atomic percent or more and 0.5 atomic percent or less. The nickel content in the electroless copper plating layer 32 is the nickel content in any region including the entire thickness direction from the interface between the sintered body layer 22 and the electroless copper plating layer 32 to the surface of the electroless copper plating layer 32 opposite to the interface. The nickel content in the electroless copper plating layer 32 is measured by the same method as the palladium content in the electroless copper plating layer 32, except for the measurement region.

[0037] <Modification> In the above, an example has been described in which the substrate 100 for printed wiring boards has the sintered body layer 22 and the electroless copper plating layer 32 in addition to the sintered body layer 21 and the electroless copper plating layer 31. However, the substrate 100 for printed wiring boards does not necessarily have to have the sintered body layer 22 and the electroless copper plating layer 32.

[0038] (Method of manufacturing the printed wiring board substrate 100) A method for manufacturing the printed wiring board substrate 100 will be described below.

[0039] Fig. 2 is a process diagram showing a method for manufacturing a substrate 100 for a printed wiring board. As shown in Fig. 2, the method for manufacturing a substrate 100 for a printed wiring board includes a preparation step S1, a sintered body layer forming step S2, and an electroless plating step S3. The sintered body layer forming step S2 is performed after the preparation step S1. The electroless plating step S3 is performed after the sintered body layer forming step S2.

[0040] Fig. 3 is a cross-sectional view illustrating the preparation step S1. In the preparation step S1, a base film 10 is prepared as shown in Fig. 3. In the base film 10 prepared in the preparation step S1, the sintered body layer 21 and the electroless copper plating layer 31 are not disposed on the first main surface 10a, and the sintered body layer 22 and the electroless copper plating layer 32 are not disposed on the second main surface 10b.

[0041] FIG. 4 is a cross-sectional view illustrating the sintered body layer forming step S2. In the sintered body layer forming step S2, as shown in FIG. 4, the sintered body layer 21 and the sintered body layer 22 are formed on the first main surface 10a and the second main surface 10b, respectively. In the sintered body layer forming step S2, first, a paste containing copper particles is applied to the first main surface 10a and the second main surface 10b. Second, the solvent contained in the applied paste is dried. Third, the dried paste is fired. As a result, the copper particles contained in the dried paste are sintered to each other, and the sintered body layer 21 and the sintered body layer 22 are formed.

[0042] Although not shown in the figure, after the sintered body layer forming process S2 is performed and before the electroless plating process S3 is performed, the surface of the sintered body layer 21 (i.e., the surface of the sintered body layer 21 opposite the first main surface 10a) and the surface of the sintered body layer 22 (i.e., the surface of the sintered body layer 22 opposite the second main surface 10b) are subjected to a degreasing process and an acid pickling process.

[0043] The electroless plating step S3 is performed using a plating apparatus 300. Fig. 5 is a schematic diagram of the plating apparatus 300 used in the electroless plating step S3. As shown in Fig. 5, the plating apparatus 300 includes a plating tank 310, a plurality of rollers 320, electrode rollers 331 and 332, and a power source 340.

[0044] A plating solution is stored in the plating tank 310. The plating solution contains copper. The plating solution may also contain nickel. An electrode 311 is disposed inside the plating tank 310. The electrode 311 is made of a conductive material. The electrode 311 is made of titanium, for example. The electrode 311 is immersed in the plating solution.

[0045] The rollers 320 are aligned along the transport direction (see the arrow in FIG. 5 ) of the base film 10. The base film 10 is transported along the transport direction by rotating the rollers 320. During the transport process, the base film 10 passes through a plating solution stored in a plating treatment tank 310.

[0046] The electrode rollers 331 and 332 are disposed at positions where they come into contact with the base film 10 before it passes through the plating solution. The electrode rollers 331 and 332 come into contact with the sintered body layer 21 and the sintered body layer 22, respectively. The electrode rollers 331 and 332 are made of, for example, stainless steel.

[0047] The power supply 340 is electrically connected to the electrode 311 and the electrode rollers 331 and 332. More specifically, the positive pole of the power supply 340 is electrically connected to the electrode 311, and the negative pole of the power supply 340 is electrically connected to the electrode rollers 331 and 332.

[0048] The plating apparatus 300 may be used to manufacture substrates for printed wiring boards other than the substrate 100 for printed wiring boards. When manufacturing substrates for printed wiring boards other than the substrate 100 for printed wiring boards, a pre-dip step of applying a palladium catalyst to the surfaces of the sintered body layer 21 and the sintered body layer 22, an activator step, and a reduction step are performed before the electroless plating step is performed. Therefore, palladium may adhere to the roller 320, and a small amount of the palladium may be mixed into the electroless copper plated layer 31 and the electroless copper plated layer 32 during the electroless plating step S3.

[0049] The electroless plating step S3 includes a first step S31 and a second step S32 that is performed after the first step S31. In the first step S31, a power source 340 applies electricity between the electrode 311 and the electrode rollers 331 and 332. FIG. 6 is a cross-sectional view illustrating the first step S31. Due to the electrical energy generated by this application of electricity, electroless copper plating layers 31 and 32 are rapidly formed on the surfaces of the sintered body layers 21 and 22, respectively, as shown in FIG. 6. The electroless copper plating layers 31 and 32 formed at this time suppress the penetration of the plating solution into the sintered body layers 21 and 22.

[0050] 7 is a cross-sectional view illustrating the second step S32. In the second step S32, the passage of current between the electrode 311 and the electrode rollers 331 and 332 is stopped. However, because the electroless copper plating layers 31 and 32 have been formed in the first step S31, the growth of the electroless copper plating layers 31 and 32 continues due to the autocatalytic action of copper, even without the use of a palladium catalyst, as shown in FIG. 7. In this manner, the printed wiring board substrate 100 having the structure shown in FIG. 1 is formed.

[0051] One of the reasons why trace amounts of palladium may be contained in the sintered body layer 21, the sintered body layer 22, the electroless copper plating layer 31, the electroless copper plating layer 32, and the base film 10 is that trace amounts of palladium may be contained in manufacturing equipment, etc. In the substrate for printed wiring boards of the present disclosure, regardless of how palladium is contained, the palladium in the sintered body layer 21 and the sintered body layer 22 is reduced to 0.1 atomic percent or less, thereby achieving the effect of enabling fine-pitched wiring.

[0052] (Configuration of printed wiring board 200) The configuration of the printed wiring board 200 will be described below.

[0053] Fig. 8 is a cross-sectional view of printed wiring board 200. As shown in Fig. 8, printed wiring board 200 has base film 10 and wiring 41. Printed wiring board 200 may further have wiring 42.

[0054] The normal direction of the first main surface 10a (second main surface 10b) is defined as a first direction DR1. The direction perpendicular to the first direction DR1 is defined as a second direction DR2. The direction perpendicular to the first direction DR1 and the second direction DR2 is defined as a third direction DR3.

[0055] The wiring 41 is disposed on the first main surface 10a. The wiring 41 has a sintered body layer 21 disposed on the first main surface 10a, an electroless copper plating layer 31 disposed on the sintered body layer 21, and an electrolytic copper plating layer 51 disposed on the electroless copper plating layer 31. The electrolytic copper plating layer 51 is a copper layer formed by electrolytic plating.

[0056] The wiring 42 is disposed on the second main surface 10b. The wiring 42 has a sintered body layer 22 disposed on the second main surface 10b, an electroless copper plating layer 32 disposed on the sintered body layer 22, and an electrolytic copper plating layer 52 disposed on the electroless copper plating layer 32. The electrolytic copper plating layer 52 is a copper layer formed by electrolytic plating.

[0057] Although not shown, wiring 41 and wiring 42 are electrically connected to each other by a conductor layer disposed on the inner wall surface of a through hole penetrating the base film 10 in the thickness direction (or embedded in the through hole).

[0058] The wiring 41 has a plurality of wiring portions 41a. The wiring portions 41a extend along the second direction DR2. The plurality of wiring portions 41a are arranged side by side along the third direction DR3. The distance in the third direction DR3 between any two adjacent ones of the plurality of wiring portions 41a is defined as a distance DIS1. The distance DIS1 may be 15 μm or less. The distance DIS1 may also be 10 μm or less, or may be 20 μm or less.

[0059] The wiring 42 has a plurality of wiring portions 42a. The wiring portions 42a extend along the second direction DR2. The plurality of wiring portions 42a are arranged side by side along the third direction DR3. The distance in the third direction DR3 between any two adjacent ones of the plurality of wiring portions 42a is defined as a distance DIS2. The distance DIS2 may be 15 μm or less. The distance DIS2 may also be 10 μm or less, or may be 20 μm or less.

[0060] <Modification> In the above, an example has been described in which printed wiring board 200 has wiring 42 in addition to wiring 41. However, printed wiring board 200 does not necessarily have to have wiring 42.

[0061] (Method of manufacturing printed wiring board 200) A method for manufacturing the printed wiring board 200 will be described below.

[0062] 9 is a process diagram showing a method for manufacturing printed wiring board 200. As shown in FIG. 9, the method for manufacturing printed wiring board 200 includes a resist pattern forming step S4, an electrolytic plating step S5, a resist pattern removing step S6, and an etching step S7.

[0063] The electrolytic plating step S5 is performed after the resist pattern forming step S4. The resist pattern removing step S6 is performed after the electrolytic plating step S5. The etching step S7 is performed after the resist pattern removing step S6. The printed wiring board 200 is formed using the substrate 100 for a printed wiring board.

[0064] 10 is a cross-sectional view illustrating the resist pattern forming step S4. In the resist pattern forming step S4, as shown in FIG. 10, a resist pattern 61 and a resist pattern 62 are formed on the electroless copper plating layer 31 and the electroless copper plating layer 32, respectively.

[0065] The resist pattern 61 has openings 61a. The openings 61a penetrate the resist pattern 61 in the thickness direction. The electroless copper plating layer 31 is exposed from the openings 61a. The resist pattern 62 has openings 62a. The openings 62a penetrate the resist pattern 62 in the thickness direction. The electroless copper plating layer 32 is exposed from the openings 62a.

[0066] In the resist pattern formation step S4, first, dry film resist is applied onto the electroless copper plating layer 31 and the electroless copper plating layer 32. Second, the applied dry film resist is exposed and developed. As a result, the remaining portions of the dry film resist that were not removed become the resist patterns 61 and 62, and the removed portions of the dry film resist become the openings 61a and 62a.

[0067] Fig. 11 is a cross-sectional view illustrating the electrolytic plating step S5. In the electrolytic plating step S5, as shown in Fig. 11, an electrolytic copper plating layer 51 is formed on the electroless copper plating layer 31 exposed from the opening 61a, and an electrolytic copper plating layer 52 is formed on the electroless copper plating layer 32 exposed from the opening 62a.

[0068] The electrolytic copper plating layer 51 and the electrolytic copper plating layer 52 are formed by passing a current through the electroless copper plating layer 31 and the electroless copper plating layer 32 in a copper-containing plating solution to perform electrolytic plating on the electroless copper plating layer 31 exposed from the opening 61a and on the electroless copper plating layer 32 exposed from the opening 62a.

[0069] Fig. 12 is a cross-sectional view illustrating the resist pattern removal step S6. In the resist pattern removal step S6, as shown in Fig. 12, the resist pattern 61 is removed from the electroless copper plating layer 31, and the resist pattern 62 is removed from the electroless copper plating layer 32. As a result, the electroless copper plating layer 31 and the sintered body layer 21 are exposed between two adjacent electrolytic copper plating layers 51, and the electroless copper plating layer 32 and the sintered body layer 22 are exposed between two adjacent electrolytic copper plating layers 52.

[0070] In the etching step S7, the portions of the electroless copper plating layer 31 and the sintered body layer 21 exposed between two adjacent electrolytic copper plating layers 51, and the portions of the electroless copper plating layer 32 and the sintered body layer 22 exposed between two adjacent electrolytic copper plating layers 52 are removed by etching. In this way, a printed wiring board 200 having the structure shown in FIG. 7 is formed.

[0071] (Effects of the printed wiring board substrate 100 and the printed wiring board 200) The effects of the printed wiring board substrate 100 will be described below.

[0072] In the substrate 100 for printed wiring boards, there is no need to apply a palladium catalyst to the surfaces of the sintered body layer 21 and the sintered body layer 22 in order to form the electroless copper plating layer 31 and the electroless copper plating layer 32. Therefore, according to the substrate 100 for printed wiring boards, the pre-dip step, activator step, and reduction step for applying a palladium catalyst can be omitted in the manufacturing process, and the manufacturing process can be simplified.

[0073] The effects of the printed wiring board 200 will be described below. In the manufacturing process of the substrate 100 for printed wiring boards, an electric current is applied between the electrode 311 and the electrode roller 331 and the electrode roller 332 at the beginning of the electroless plating step S3, whereby the electroless copper plating layer 31 and the electroless copper plating layer 32 are rapidly formed on the sintered body layer 21 and the sintered body layer 22, respectively, without using a palladium catalyst. As a result, the penetration of the plating solution into the sintered body layer 21 and the sintered body layer 22 is suppressed. Therefore, in the substrate 100 for printed wiring boards, the palladium and nickel contents in the sintered body layer 21 and the sintered body layer 22 are low.

[0074] If the palladium or nickel content in the sintered body layer 21 and the sintered body layer 22 is high, in the etching step S7, the palladium or nickel in the electroless copper plating layer 31 and the sintered body layer 21 that is exposed between two adjacent electrolytic copper plating layers 51, as well as the palladium or nickel in the electroless copper plating layer 32 and the sintered body layer 22 that is exposed between two adjacent electrolytic copper plating layers 52, must also be removed.

[0075] In this case, undercuts may occur in the wiring 41 and the wiring 42, so if the palladium or nickel content in the sintered body layer 21 and the sintered body layer 22 is high, it is difficult to achieve a fine pitch for the wiring 41 and the wiring 42.

[0076] However, since the printed wiring board 200 is formed using the substrate 100 for printed wiring boards in which the sintered body layers 21 and 22 have low contents of palladium and nickel, undercutting of the wiring 41 and the wiring 42 is unlikely to occur during the etching step S7, and the wiring 41 and the wiring 42 can be formed at a finer pitch. Note that the undercutting of the wiring 41 refers to a notch that occurs on the side surface of the wiring 41 between the electroless copper plating layer 31 and the electrolytic copper plating layer 51. Similarly, the undercutting of the wiring 42 refers to a notch that occurs on the side surface of the wiring 42 between the electroless copper plating layer 32 and the electrolytic copper plating layer 52.

[0077] (Example) Using Samples 1 to 5, the effect of the palladium content in the sintered body layer 21 on finer pitch of the wiring 41 was evaluated. The palladium content in the sintered body layer 21 was changed in Samples 1 to 5. In Samples 1, 3, and 4, the electroless copper plating layer 31 was formed using a first step S31 and a second step S32. In Sample 1, the nickel concentration in the plating solution used to form the electroless copper plating layer 31 was higher than in Samples 3 and 4. In Samples 2 and 5, the electroless copper plating layer 31 was formed by electroless plating using a palladium catalyst. In Sample 2, the nickel concentration in the plating solution used to form the electroless copper plating layer 31 was higher than in Sample 5.

[0078] In Samples 1 to 5, the palladium content in the electroless copper plating layer 31, the nickel content in the sintered body layer 21, and the palladium content in the base film 10 on the first main surface 10a were also changed.

[0079] [Table 1]

[0080] An evaluation TEG (Test Element Group) was used to evaluate the finer pitch of the wiring. FIG. 13 is a plan view of the evaluation TEG. As shown in FIG. 13, the evaluation TEG has a base film 10 and wiring 41. In the evaluation TEG, a first main surface 10a has 20 wiring formation regions R1, 20 wiring formation regions R2, and 20 wiring formation regions R3. The 20 wiring formation regions R1, 20 wiring formation regions R2, and 20 wiring formation regions R3 are arranged in rows along the left-right direction.

[0081] Wiring 41 having a plurality of wiring portions 41a is formed on wiring formation regions R1, R2, and R3. The wiring portions 41a formed on wiring formation region R1 extend in the vertical direction. The wiring portions 41a formed on wiring formation region R2 and wiring formation region R3 extend in directions inclined at 45° and −45° with respect to the vertical direction, respectively.

[0082] The L / S of the wiring portion 41a formed on the wiring formation region R1, which is the nth from the right (n is a natural number less than or equal to 20), is n μm / n μm. L is the width of the wiring portion 41a, and S is the distance DIS1. The wiring portions 41a formed on the wiring formation region R2 and the wiring portions 41a formed on the wiring formation region R3 also have similarly changed L / S. The aspect ratio of the wiring portion 41a (the value obtained by dividing the height of the wiring portion 41a by the width of the wiring portion 41a) is set to 1 or more and 2 or less.

[0083] For each of the 20 wiring formation regions R1, each of the 20 wiring formation regions R2, and each of the 20 wiring formation regions R3, the wiring 41 was observed using a SEM (Scanning Electron Microscope) to determine whether the wiring formation was performed properly.

[0084] When the minimum value of the width and distance DIS1 of the wiring portion 41a that can be properly formed is 10 μm or less, the evaluation was rated A. When the minimum value of the width and distance DIS1 of the wiring portion 41a that can be properly formed is more than 10 μm and less than 20 μm, the evaluation was rated B. When the minimum value of the width and distance DIS1 of the wiring portion 41a that can be properly formed is more than 20 μm and less than 30 μm, the evaluation was rated C. When the minimum value of the width and distance DIS1 of the wiring portion 41a that can be properly formed is more than 30 μm, the evaluation was rated D.

[0085] As shown in Table 1, when the palladium content in the sintered body layer 21 was 0.1 atomic percent or less, the fine pitch was evaluated as B or higher. On the other hand, when the palladium content in the sintered body layer 21 was more than 0.1 atomic percent, the fine pitch was evaluated as C or lower. This comparison reveals that the wiring 41 can be fine-pitched by setting the palladium content in the sintered body layer 21 to 0.1 atomic percent or less. In addition, in samples in which the palladium content in the sintered body layer 21 was 0.1 atomic percent or less, the palladium content in the electroless copper plating layer 31 and the palladium content in the base film 10 on the first main surface 10a were 0.1 atomic percent or less and 0.01 atomic percent or less, respectively.

[0086] For Samples 1 to 5, the rectangularity of the wiring 41 was also evaluated. In the evaluation of the rectangularity of the wiring 41, first, a cross-sectional image of the wiring 41 was obtained using an SEM. The SEM was, for example, an ULTRA55 manufactured by Carl Zeiss, and measurement conditions were used: an acceleration voltage of 3 kV, an aperture of 30 μm, a WD of 5 mm, and a tilt of 0°. The cross-sectional image was obtained at a cross section perpendicular to the extension direction of the wiring 41. Furthermore, prior to cross-sectional observation, each sample was prepared by embedding in epoxy resin, shaping and polishing, cross-section processing using a cross polisher (acceleration voltage of 6 kV x 4 hours), and carbon vapor deposition (2 nm).

[0087] The width of the upper surface of the wiring 41 and the width of the lower surface of the wiring 41 are defined as the first width and the second width, respectively. When the value obtained by dividing the first width by the second width was 0.9 or more, the rectangularity of the wiring 41 was evaluated as A. When the value obtained by dividing the first width by the second width was 0.8 or more and less than 0.9, the rectangularity of the wiring 41 was evaluated as B. When the value obtained by dividing the first width by the second width was 0.7 or more and less than 0.8, the rectangularity of the wiring 41 was evaluated as C. When the value obtained by dividing the first width by the second width was less than 0.7, the rectangularity of the wiring 41 was evaluated as D.

[0088] In Samples 3 and 4, the rectangularity of the wiring 41 was evaluated as B or higher. On the other hand, in Sample 1, the rectangularity of the wiring 41 was evaluated as D. Furthermore, in Samples 3 and 4, the nickel content in the sintered body layer 21 was 0.5 atomic percent or less. On the other hand, in Sample 1, the nickel content in the sintered body layer 21 was greater than 0.5 atomic percent. This comparison revealed that the rectangularity of the wiring 41 was improved by setting the palladium content in the sintered body layer 21 to 0.1 atomic percent or less and by setting the nickel content in the sintered body layer 21 to 0.5 atomic percent or less.

[0089] The embodiments disclosed herein are illustrative in all respects and should not be considered limiting. The scope of the present invention is defined by the claims, not by the above-described embodiments, and is intended to include all modifications within the meaning and scope of the claims. [Explanation of symbols]

[0090] 10 base film, 10a first main surface, 10b second main surface, 21 sintered body layer, 22 sintered body layer, 31 electroless copper plating layer, 32 electroless copper plating layer, 41 wiring, 41a wiring portion, 42 wiring, 42a wiring portion, 51, 52 electrolytic copper plating layer, 61 resist pattern, 61a opening, 62 resist pattern, 62a opening, 100 printed wiring board substrate, 200 printed wiring board, 300 plating apparatus, 310 plating treatment tank, 311 electrode, 320 roller, 331, 332 electrode roller, 340 power supply, DIS1 distance, DIS2 distance, DR1 first direction, DR2 second direction, DR3 third direction, S1 preparation step, S2 sintered body layer forming step, S3 electroless plating step, S4 resist pattern forming step, S5 electrolytic plating step, S6 Resist pattern removal step, S7 etching step, S31 first step, S32 second step.

Claims

1. a base film having a main surface; a sintered layer disposed on the main surface and formed of a plurality of sintered copper particles; an electroless copper plating layer disposed on the sintered body layer, the content of palladium in the sintered body layer is 0.1 atomic percent or less, the content of nickel in the sintered body layer is 0.03 atomic percent or more and 0.35 atomic percent or less, The substrate for printed wiring boards, wherein the nickel content in the electroless copper plating layer is greater than the nickel content in the sintered body layer.

2. 2. The substrate for printed wiring board according to claim 1, wherein the palladium content in the sintered body layer is 0.005 atomic percent or more.

3. 2. The substrate for printed wiring board according to claim 1, wherein the content of palladium in the electroless copper plating layer is 0.1 atomic percent or less.

4. 4. The substrate for printed wiring board according to claim 1, wherein the content of palladium in the base film on the main surface is 0.01 atomic percent or less.

5. a base film having a main surface; wiring disposed on the main surface, the wiring has a sintered body layer disposed on the main surface and formed of a plurality of sintered copper particles, an electroless copper plating layer disposed on the sintered body layer, and an electrolytic copper plating layer disposed on the electroless copper plating layer, the content of palladium in the sintered body layer is 0.1 atomic percent or less, the content of nickel in the sintered body layer is 0.03 atomic percent or more and 0.35 atomic percent or less, The printed wiring board, wherein the nickel content in the electroless copper plating layer is greater than the nickel content in the sintered body layer.

6. the wiring has a plurality of wiring portions extending along a second direction perpendicular to a first direction that is a normal direction of the main surface, and arranged along a third direction perpendicular to the first direction and the second direction; The printed wiring board according to claim 5 , wherein the distance between any two adjacent ones of the plurality of wiring portions is 15 μm or less.

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