Method for manufacturing nitride semiconductor light emitting device

Abstract

A method for manufacturing a nitride semiconductor light-emitting device is provided that can achieve a uniform in-plane distribution of emission wavelengths on the wafer to be manufactured. A method for manufacturing a nitride semiconductor light-emitting device in which a substrate, a buffer layer containing Al and N, an n-type semiconductor layer containing Al, Ga, and N, an active layer containing Al and N, and a p-type semiconductor layer are stacked in this order, is provided, the method comprising: III [μmol / min] vs. the flow rate F of the source gas of group V elements v [μmol / min] ratio F v / F III is defined as the V / III ratio, the V / III ratio when forming the buffer layer is defined as x, and the V / III ratio when forming the n-type semiconductor layer is defined as y, x and y satisfy the relationship y≦−x+650.

Description

[Technical Field]

[0001] The present invention relates to a method for manufacturing a nitride semiconductor light-emitting device. [Background technology]

[0002] Patent Document 1 discloses a method for manufacturing a nitride semiconductor light-emitting device in which a substrate, a buffer layer, an n-type semiconductor layer, an active layer, and a p-type semiconductor layer (i.e., a p-type cladding layer and a p-type contact layer) are stacked. In the method for manufacturing a nitride semiconductor light-emitting device described in Patent Document 1, the surface of the p-type contact layer is flattened by adjusting the V / III ratio, which is the flow rate ratio of raw material gases during the deposition of the p-type cladding layer and the p-type contact layer. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2023-108178 Summary of the Invention [Problem to be solved by the invention]

[0004] In Patent Document 1, the V / III ratio of layers other than the p-type semiconductor layer is not considered. However, a new problem has been found in this study: depending on the ratio between the V / III ratio when the buffer layer is formed and the V / III ratio when the n-type semiconductor layer is formed, the variation in the in-plane distribution of the emission wavelength in the manufactured wafer increases.

[0005] The present invention has been made in view of the above circumstances, and has an object to provide a method for manufacturing a nitride semiconductor light-emitting element that can achieve a uniform in-plane distribution of emission wavelengths in the wafer to be manufactured. [Means for solving the problem]

[0006] In order to achieve the above object, the present invention provides a substrate, a substrate containing Al and N. Single or multiple layerBuffer layer, containing Al, Ga, and N Single or multiple layer A method for manufacturing a nitride semiconductor light emitting device in which an n-type semiconductor layer, an active layer containing Al and N, and a p-type semiconductor layer are stacked in this order, the buffer layer and the n-type semiconductor layer are adjacent to each other, Flow rate of source gas of group III elements F III [μmol / min] vs. the flow rate F of the source gas of group V elements v [μmol / min] ratio F v / F III is defined as a V / III ratio, the V / III ratio when the buffer layer is formed is defined as x, and the V / III ratio when the n-type semiconductor layer is formed is defined as y, and x and y satisfy the relationship y≦−x+650. wherein, when the buffer layer is made up of a plurality of layers, x is the V / III ratio when a layer of the buffer layer closest to the n-type semiconductor layer is formed, and when the n-type semiconductor layer is made up of a plurality of layers, y is the V / III ratio when a layer of the n-type semiconductor layer closest to the buffer layer is formed. A method for manufacturing a nitride semiconductor light emitting device is provided. [Effects of the Invention]

[0007] According to the present invention, it is possible to provide a method for manufacturing a nitride semiconductor light-emitting device that can achieve a uniform in-plane distribution of emission wavelengths in the wafer to be manufactured. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a schematic diagram illustrating a configuration of a nitride semiconductor light emitting device according to an embodiment. [Figure 2] FIG. 10 is a diagram showing the relationship between the V / III ratio x during deposition of the buffer layer, the V / III ratio y during deposition of the n-type semiconductor layer, and the in-plane distribution of emission wavelengths in the wafer in an experimental example. [Figure 3] FIG. 10 is a diagram showing the relationship between the radius of curvature of an intermediate film-formed body and the coefficient of variation of wavelength distribution on a wafer in an experimental example. DETAILED DESCRIPTION OF THE INVENTION

[0009] [Embodiment Mode] An embodiment of the present invention will be described with reference to Fig. 1. The embodiment described below is shown as a preferred specific example for carrying out the present invention, and although various technically preferable technical matters are specifically exemplified, the technical scope of the present invention is not limited to this specific embodiment.

[0010] (Nitride semiconductor light emitting device 1) This embodiment relates to a method for manufacturing a nitride semiconductor light emitting device 1 (hereinafter also simply referred to as "light emitting device 1"). First, the light emitting device 1 manufactured by the manufacturing method of this embodiment will be described.

[0011] FIG. 1 is a schematic diagram illustrating the configuration of a nitride semiconductor light-emitting element 1. Note that in FIG. 1, the dimensional ratio of the stacking direction of each semiconductor layer of the light-emitting element 1 does not necessarily match the actual one. Hereinafter, the stacking direction of each semiconductor layer of the light-emitting element 1 will be referred to as the vertical direction. Furthermore, one side in the vertical direction, on which each semiconductor layer of the substrate 2 is grown (e.g., the upper side in FIG. 1), will be referred to as the upper side, and the opposite side (e.g., the lower side in FIG. 1) will be referred to as the lower side. Note that the expressions "upper" and "lower" are used for convenience and do not limit the orientation of the light-emitting element 1 relative to the vertical direction, for example, when the light-emitting element 1 is in use.

[0012] The light-emitting element 1 is, for example, a light-emitting diode (LED) or a semiconductor laser (LD: Laser Diode). In this embodiment, the light-emitting element 1 is a light-emitting diode that emits light with a wavelength in the ultraviolet region. In particular, the light-emitting element 1 in this embodiment emits ultraviolet light with a central wavelength of 240 nm or more and 365 nm or less. The light-emitting element 1 can be used in fields such as sterilization (e.g., air purification, water purification, etc.), medical care (e.g., phototherapy, measurement and analysis, etc.), UV curing, etc.

[0013] The light-emitting element 1 includes a buffer layer 3, an n-type semiconductor layer 4, a compositionally graded layer 5, an active layer 6, an electron blocking layer 7, and a p-type semiconductor layer 8, which are arranged in this order on a substrate 2. The light-emitting element 1 also includes an n-side electrode 11 provided on the n-type semiconductor layer 4, and a p-side electrode 12 provided on the p-type semiconductor layer 8.

[0014] The substrate 2 is made of a material that transmits the light emitted by the active layer 6. The substrate 2 can be, for example, a sapphire (Al2O3) substrate or a gallium oxide (Ga2O3) substrate containing oxygen as a parent phase element. In this embodiment, the substrate 2 is a sapphire substrate. In this embodiment, the thickness of the substrate 2 is 400 μm or more. The growth plane formed on the upper surface of the substrate 2 is a c-plane. This c-plane may have an off-axis angle. Note that the substrate 2 may also be a substrate that does not contain oxygen as a constituent element, such as an aluminum nitride (AlN) substrate or an aluminum gallium nitride (AlGaN) substrate.

[0015] The semiconductor constituting the light emitting element 1 is, for example, Al a Ga b In 1-a-b In this embodiment, a group III nitride semiconductor having two to four elements represented by the formula N (0≦a≦1, 0≦b≦1, 0≦a+b≦1) can be used. c Ga 1-c The semiconductor substrate 2 uses a binary or ternary group III nitride semiconductor represented by N (0≦c≦1). Some of these group III elements may be replaced with boron (B), thallium (Tl), etc. Furthermore, some of the nitrogen may be replaced with phosphorus (P), arsenic (As), antimony (Sb), bismuth (Bi), etc. In this embodiment, the total thickness of the semiconductor layers stacked on the substrate 2 (i.e., the thickness from the lower surface of the buffer layer 3 to the upper surface of the p-type semiconductor layer 8) is less than 6 μm.

[0016] The buffer layer 3 is formed on the substrate 2. In this embodiment, the buffer layer 3 is made of aluminum nitride. The buffer layer may have a single layer structure or a multi-layer structure. The buffer layer 3 may be made of undoped Al qGa 1-q It may include a semiconductor layer made of N (0≦q≦1).

[0017] The n-type semiconductor layer 4 is formed on the buffer layer 3. The n-type semiconductor layer 4 is, for example, Al doped with n-type impurities. r Ga 1-r The n-type cladding layer is formed of AlN (0≦r≦1). In this embodiment, silicon (Si) is used as the n-type impurity. The same applies to semiconductor layers containing n-type impurities other than the n-type semiconductor layer 4. Note that germanium (Ge), selenium (Se), tellurium (Te), etc. may also be used as the n-type impurity. The Al composition ratio r of the n-type semiconductor layer 4 is, for example, 45% or more and 65% or less. The n-type semiconductor layer 4 may have a single-layer structure or a multi-layer structure. Note that the Al composition ratio is also referred to as the AlN mole fraction.

[0018] The compositionally graded layer 5 is formed on the n-type semiconductor layer 4. The compositionally graded layer 5 is made of Al s Ga 1-s N (0≦s≦1). The Al composition ratio at each position in the vertical direction of the composition gradient layer 5 increases toward the upper side. Note that the composition gradient layer 5 may include a region in which the Al composition ratio does not increase toward the upper side, for example, in a very small region in the vertical direction (for example, a region of 5% or less of the entire vertical direction of the composition gradient layer 5).

[0019] The Al composition ratio of the lower end of the composition gradient layer 5 is preferably approximately the same (for example, within a difference of 5%) as the Al composition ratio of the upper end of the n-type semiconductor layer 4 adjacent to the lower side of the composition gradient layer 5. Furthermore, the Al composition ratio of the upper end of the composition gradient layer 5 is preferably approximately the same (for example, within a difference of 5%) as the Al composition ratio of the lower end of the barrier layer 61 adjacent to the upper side of the composition gradient layer 5.

[0020] The active layer 6 is formed on the composition gradient layer 5. The active layer 6 of this embodiment has a multiple quantum well structure having a plurality of well layers 62. In this embodiment, the active layer 6 has three barrier layers 61 and three well layers 62, and the barrier layers 61 and the well layers 62 are alternately laminated. In the active layer 6, the barrier layer 61 is located at the lower end and the well layer 62 is located at the upper end. Note that the present invention is not limited to this, and the active layer 6 may have a multiple quantum well structure having two or four or more well layers 62, or may have a single quantum well structure having only one well layer 62.

[0021] The band gap of the active layer 6 is adjusted so that it can emit ultraviolet light with a central wavelength of 240 nm or more and 365 nm or less. When the active layer 6 has a multiple quantum well structure as in this embodiment, from the viewpoint of improving the emission output, the central wavelength of the ultraviolet light emitted by the active layer 6 is preferably 250 nm or more and 300 nm or less, and more preferably 260 nm or more and 290 nm or less.

[0022] Each barrier layer 61 is formed of Al t GaN (0 <t ≦ 1). The Al composition ratio t of each barrier layer 61 is, for example, 75% or more and 95% or less. The film thickness of each barrier layer 61 is, for example, 2 nm or more and 50 nm or less.

[0023] The well layer 62 is formed of Al u GaN (0 <u <1). The Al composition ratio u of each well layer 62 is smaller than the Al composition ratio t of the barrier layer 61 (that is, u <t). For example, the Al composition ratio u is 25% or more and 55% or less. The film thickness of each well layer 62 is, for example, 2 nm or more and 6 nm or less. [[ID=

[21] ]

[0024] The electron blocking layer 7 is formed on the active layer 6. The electron blocking layer 7 has a role of improving the electron injection efficiency into the active layer 6 by suppressing the occurrence of an overflow phenomenon in which electrons leak from the active layer 6 to the p-type semiconductor layer 8 side (hereinafter also referred to as an electron blocking effect). The electron blocking layer 7 has a laminated structure in which a first layer 71 and a second layer 72 are laminated in order from the bottom.​​

[0025] The first layer 71 is provided on the active layer 6. The first layer 71 is, for example, Al v Ga 1-v N (0 < v ≤ 1). The Al composition ratio v of the first layer 71 is, for example, 90% or more, and in this embodiment, it is made of aluminum nitride. The film thickness of the first layer 71 is, for example, 0.5 nm or more and 5.0 nm or less.

[0026] The second layer 72 is, for example, Al w Ga 1-w N (0 < w < 1). The Al composition ratio w of the second layer 72 is smaller than the Al composition ratio v of the first layer 71 (that is, w < v), and is, for example, 70% or more and 90% or less. The film thickness of the second layer 72 is larger than the film thickness of the first layer 71, and is, for example, 15 nm or more and 100 nm or less.

[0027] Since a semiconductor layer with a larger Al composition ratio has a larger electrical resistance value, if the film thickness of the first layer 71 with a relatively high Al composition ratio is made too large, an excessive increase in the overall electrical resistance value of the light-emitting device 1 will occur. Therefore, it is preferable to make the film thickness of the first layer 71 somewhat smaller. On the other hand, if the film thickness of the first layer 71 is made small, the probability that electrons tunnel through the first layer 71 from the lower side to the upper side can increase. Therefore, in the light-emitting device 1 of this embodiment, by forming the second layer 72 on the first layer 71, the overall electron blocking layer 7 is suppressed from being tunneled through by electrons.

[0028] Each of the first layer 71 and the second layer 72 can be an undoped layer, a layer containing n-type impurities, a layer containing p-type impurities, or a layer containing both n-type and p-type impurities. As the p-type impurity, magnesium (Mg) can be used, but in addition to magnesium, zinc (Zn), beryllium (Be), calcium (Ca), strontium (Sr), barium (Ba), carbon (C), etc. may also be used. The same applies to semiconductor layers containing other p-type impurities. When each electron blocking layer 7 contains impurities, the impurities contained in each electron blocking layer 7 may be contained in the whole of each electron blocking layer 7 or may be contained in a part of each electron blocking layer 7.

[0029] The p-type semiconductor layer 8 is formed on the electron blocking layer 7. The p-type semiconductor layer 8 has a smaller Al composition ratio than the electron blocking layer 7 and is Al doped with p-type impurities x Ga 1-x formed by N (0 ≦ x < 1). In this embodiment, the p-type semiconductor layer 8 has a stacked structure in which a p-type cladding layer 81 and a p-type contact layer 82 are stacked in order from the bottom.

[0030] The p-type cladding layer 81 is provided so as to be in contact with the second layer 72. The p-type cladding layer 81 is composed of Al y Ga 1-y N (0 < y < 1). The Al composition ratio y of the p-type cladding layer 81 is, for example, not less than 45% and not more than 65%. The film thickness of the p-type cladding layer 81 is, for example, not less than 9 nm and not more than 105 nm.

[0031] The p-type contact layer 82 is a layer to which a p-side electrode 12 to be described later is connected, and is doped with a high concentration of p-type impurities. The p-type contact layer 82 is configured such that the Al composition ratio is low (for example, not more than 10%) in order to achieve an ohmic contact with the p-side electrode 12, and from this viewpoint, it is preferably formed of p-type gallium nitride (GaN). The film thickness of the p-type contact layer 82 is, for example, not less than 3 nm and not more than 50 nm. Note that the p-type semiconductor layer 8 may be a single layer or a plurality of layers.

[0032] The n-side electrode 11 is formed on an exposed surface 41 of the n-type semiconductor layer 4 that is exposed above the active layer 6. The n-side electrode 11 may be, for example, a multilayer film in which titanium (Ti), aluminum, titanium, and titanium nitride (TiN) are laminated in this order on the n-type semiconductor layer 4.

[0033] The p-side electrode 12 is formed on the upper surface of the p-type semiconductor layer 8. The p-side electrode 12 can be made of, for example, rhodium (Rh). In this embodiment, the p-side electrode 12 is a reflective electrode having a reflectance of 50% or more, preferably 60% or more, at the center wavelength of light emitted from the active layer 6, but is not limited to this.

[0034] The light-emitting element 1 is flip-chip mounted on a package substrate (not shown) for use. That is, the side of the light-emitting element 1 on which the n-side electrode 11 and the p-side electrode 12 are provided in the up-down direction faces the package substrate, and the n-side electrode 11 and the p-side electrode 12 are mounted on the package substrate via connecting members such as gold bumps. Light from the flip-chip mounted light-emitting element 1 is extracted from the substrate 2 side (i.e., the bottom side).

[0035] (Method of manufacturing nitride semiconductor light emitting element 1) Next, a method for manufacturing the light emitting device 1 of this embodiment will be described. In this embodiment, a buffer layer, an n-type semiconductor layer, a compositionally graded layer, an active layer, an electron blocking layer, and a p-type semiconductor layer are epitaxially grown in this order on a disk-shaped substrate by metal organic chemical vapor deposition (MOCVD). The substrate, buffer layer, n-type semiconductor layer, compositionally graded layer, active layer, electron blocking layer, and p-type semiconductor layer not labeled with reference numerals are portions that will become the substrate 2, buffer layer 3, n-type semiconductor layer 4, compositionally graded layer 5, active layer 6, electron blocking layer 7, and p-type semiconductor layer 8 of the light-emitting element 1 after the wafer is singulated, as described below. In this embodiment, the substrate has a diameter on the order of 10 mm (i.e., 10 mm to 99 mm), more specifically, 2 inches. The MOCVD method is also sometimes called metal organic vapor phase epitaxy (MOVPE). When epitaxially growing a semiconductor layer on a substrate, other epitaxial growth methods such as molecular beam epitaxy (MBE) and hydride vapor phase epitaxy (HVPE) can also be used.

[0036] When manufacturing the light-emitting element 1, a disk-shaped substrate is placed on a susceptor in a chamber (not shown), and source gases are introduced into the chamber while the susceptor is rotating, thereby growing each semiconductor layer on the substrate. The source gases used to epitaxially grow each semiconductor layer can include trimethylaluminum (TMA) as an aluminum source, trimethylgallium (TMG) as a gallium source, ammonia (NH3) as a nitrogen source, tetramethylsilane (TMSi) as a silicon source, and biscyclopentadienylmagnesium (Cp2Mg) as a magnesium source.

[0037] In this embodiment, in order to suppress the variation in the in-plane distribution of the emission wavelength in the wafer to be manufactured, the relationship between the V / III ratio during the deposition of the buffer layer and the V / III ratio during the deposition of the n-type semiconductor layer is devised. Here, the V / III ratio is defined as the flow rate F of the source gas of the group III element during the deposition of each semiconductor layer. III [μmol / min] vs. the flow rate F of the source gas of group V elements v [μmol / min] ratio F v / F III In this embodiment, the V / III ratio during deposition of the buffer layer made of AlN is the ratio of the flow rate [μmol / min] of ammonia to the flow rate [μmol / min] of trimethylaluminum. Also, the V / III ratio during deposition of the n-type semiconductor layer made of n-type AlGaN is the ratio of the flow rate [μmol / min] of ammonia to the total flow rate [μmol / min] of trimethylaluminum and trimethylgallium.

[0038] The V / III ratio during deposition of the buffer layer is defined as x, and the V / III ratio during deposition of the n-type semiconductor layer is defined as y. Here, x and y satisfy the inequality y≦−x+630. This results in a more uniform in-plane distribution of the emission wavelength in the wafer to be manufactured. Furthermore, it is preferable that x and y satisfy at least one of the relationships 1.1x≦y≦3.0x and y≦−x+550, from the viewpoint of further uniforming the in-plane distribution of the emission wavelength in the wafer to be manufactured. By satisfying these inequalities between x and y, the stress difference between the buffer layer and the n-type semiconductor layer can be reduced, thereby suppressing wafer warpage. It is presumed that suppressing wafer warpage results in a more uniform temperature distribution during wafer deposition, resulting in a more uniform in-plane distribution of the emission wavelength in the wafer to be manufactured. These inequalities are supported by experimental examples described below.

[0039] In this embodiment, x, which is the V / III ratio during deposition of the buffer layer, is preferably 100 or more, more specifically, 127 to 318. x is more preferably 250 or less. y, which is the V / III ratio during deposition of the n-type semiconductor layer, is preferably 200 or more, more specifically, 252 to 503. y is preferably 400 or less, more preferably 377 or less. When x and y each satisfy the above-mentioned ranges, it is believed that the crystallinity of the buffer layer and the n-type semiconductor layer is improved, and the light output of the wafer is increased. For example, when x satisfies the above-mentioned range, the half-width of the X-ray rocking curve (tilt) relative to the (0002) plane of the buffer layer is 250 arcsec or less. The smaller the half-width of the X-ray rocking curve (tilt) relative to the (0002) plane of the buffer layer, the higher the crystallinity.

[0040] If the buffer layer is composed of multiple layers, the V / III ratio x of the buffer layer means the V / III ratio when forming a semiconductor layer adjacent to the n-type semiconductor layer among the multiple semiconductor layers that make up the buffer layer. If the n-type semiconductor layer is composed of multiple layers, the V / III ratio y of the n-type semiconductor layer means the V / III ratio when forming a semiconductor layer adjacent to the buffer layer among the multiple semiconductor layers that make up the n-type semiconductor layer. This is because the buffer layer and the n-type semiconductor layer, adjacent layers, significantly contribute to stress generation.

[0041] The intermediate film after the n-type semiconductor layer is formed preferably has an absolute value of the radius of curvature of the upper surface of the n-type semiconductor layer of 5.2 m or more, more preferably 5.5 m or more, at the film formation temperature of the n-type semiconductor layer. The intermediate film is formed after the n-type semiconductor layer is formed and before the subsequent semiconductor layer (i.e., the semiconductor layer of the composition gradient layer or higher) is formed. Furthermore, the warpage of the intermediate film also depends on the temperature. Here, the radius of curvature of the upper surface of the n-type semiconductor layer is a value measured after the n-type semiconductor layer is formed, while the temperature inside the chamber is maintained at the film formation temperature of the n-type semiconductor layer, without removing the intermediate film from the chamber. The warpage of the intermediate film affects the subsequent formation of the active layer. It is believed that the greater the warpage of the intermediate film, the greater the in-plane temperature distribution during the active layer formation, resulting in a greater in-plane distribution of the emission wavelength in the manufactured wafer.

[0042] Other manufacturing conditions such as growth temperature, growth pressure, and growth time for epitaxially growing each semiconductor layer on the wafer can be general conditions according to the configuration of each semiconductor layer.

[0043] After forming each semiconductor layer on the disk-shaped substrate, a mask is formed on a portion of the p-type semiconductor layer, i.e., on the portion other than the portion that will become the exposed surface of the n-type semiconductor layer (see reference numeral 41 in FIG. 1). Then, the region where the mask is not formed is removed by etching from the top surface of the p-type semiconductor layer to halfway up and down the n-type semiconductor layer. This forms an exposed surface on the n-type semiconductor layer that is exposed upward. After the exposed surface is formed, the mask is removed.

[0044] Next, an n-side electrode is formed on the exposed surface of the n-type semiconductor layer, and a p-side electrode is formed on the p-type semiconductor layer. The n-side electrode and the p-side electrode may be formed by a well-known method such as electron beam evaporation or sputtering. The wafer thus completed is then subjected to a singulation process in which it is cut into pieces of desired dimensions, thereby producing a plurality of light-emitting devices 1 as shown in FIG. 1 from one wafer.

[0045] (Actions and Effects of the Embodiments) In the manufacturing method of the light-emitting element 1 of this embodiment, when the V / III ratio when forming the buffer layer is defined as x and the V / III ratio when forming the n-type semiconductor layer is defined as y, x and y satisfy the relationship y≦−x+650. This makes it possible to uniformize the in-plane distribution of the emission wavelength in the manufactured wafer. This value is supported by experimental examples described later.

[0046] Furthermore, x and y further satisfy the relationship 1.1x≦y≦3.0x. This allows for a more uniform in-plane distribution of the emission wavelength in the wafer to be manufactured. This value is supported by experimental examples described below.

[0047] Furthermore, x is 100 or greater, more specifically 127 or greater and 318 or less, and y is 200 or greater, more specifically 252 or greater and 503 or less. This makes it possible to uniformize the in-plane distribution of emission wavelengths in the manufactured wafers.

[0048] Furthermore, x and y further satisfy the relationship y≦−x+550. This makes it possible to further uniformize the in-plane distribution of the emission wavelength in the wafer to be manufactured. This value is supported by experimental examples described later.

[0049] Furthermore, the intermediate film after the n-type semiconductor layer is formed has a diameter of the order of 10 mm, and the absolute value of the radius of curvature of the surface of the n-type semiconductor layer at the film formation temperature of the n-type semiconductor layer is 5.2 m or more. By suppressing the warpage of the intermediate film in this way, the heat distribution of the wafer when the active layer is formed on the intermediate film is made uniform, and the in-plane distribution of the emission wavelength of the wafer is made uniform.

[0050] As described above, according to the present embodiment, it is possible to provide a method for manufacturing a nitride semiconductor light-emitting device that can achieve a uniform in-plane distribution of emission wavelengths on the wafer to be manufactured.

[0051] [Experimental Example] This experimental example evaluates the relationship between the V / III ratio x during the formation of the buffer layer, the V / III ratio y during the formation of the n-type semiconductor layer, and the in-plane distribution of the emission wavelength in the wafer to be manufactured.

[0052] In this experimental example, wafers according to Samples 1 to 11 were fabricated by varying the V / III ratio x during the deposition of the buffer layer and the V / III ratio y during the deposition of the n-type semiconductor layer. Unless otherwise noted, the wafers according to Samples 1 to 11 were fabricated using the same method as the fabrication method in the embodiment. The wafers according to Samples 1 to 11 are in a state before the n-side electrode and p-side electrode are formed. The film thickness, Al composition ratio, and deposition temperature, which are common to the wafers according to Samples 1 to 11, are shown in Table 1 below.

[0053] [Table 1]

[0054] The Al composition ratio of each layer listed in Table 1 is a value estimated from the Al secondary ion intensity measured by secondary ion mass spectrometry (SIMS). The column for "compositionally graded layer" in Table 1 indicates that the Al composition ratio at each position in the vertical direction of the compositionally graded layer gradually increases from 55% to 85% from the bottom to the top of the compositionally graded layer. The film formation temperature is, for example, the heater temperature or the substrate temperature.

[0055] In this experimental example, the PL (photoluminescence) spectra of the wafers according to Samples 1 to 11 were measured to evaluate the in-plane distribution of the emission wavelength. The coefficient of variation was used as an index of the in-plane distribution of the emission wavelength on the wafer. Specifically, the central wavelengths of multiple regions on the wafer surface were obtained, and the coefficient of variation was calculated from the obtained central wavelengths. The coefficient of variation is the ratio of the standard deviation to the average value (i.e., standard deviation / average value). By using the coefficient of variation as an index of the in-plane distribution of the emission wavelength on each wafer, it is possible to evaluate the in-plane distribution of the emission wavelength on the wafer regardless of the absolute value of the emission wavelength.

[0056] The results are shown in Table 2 and Figure 2. Table 2 shows the x, y, coefficient of variation of wavelength distribution in the wafer, and radius of curvature of wafers of Samples 1 to 11. As described in the embodiment, the radius of curvature was measured on the upper surface of the n-type semiconductor layer of the intermediate film formed by depositing up to the n-type semiconductor layer. Figure 2 shows the relationship between the V / III ratio x during deposition of the buffer layer, the V / III ratio y during deposition of the n-type semiconductor layer, and the in-plane distribution of emission wavelength in the wafer. In Figure 2, results for which the coefficient of variation of the wavelength distribution of the wafer is less than 50% are plotted with double circles, results in the 50% range (i.e., 50% to 60%) are plotted with circles, and results for 60% or more are plotted with triangles. The smaller the coefficient of variation of the wavelength distribution of the wafer, the more uniform the emission distribution of the wafer.

[0057] [Table 2]

[0058] As shown in Table 2, for Samples 1 to 3, the V / III ratio y during deposition of the n-type semiconductor layer was fixed at 377, and the V / III ratio during deposition of the buffer layer was changed. For Samples 4 to 7, the V / III ratio y during deposition of the n-type semiconductor layer was fixed at 503, and the V / III ratio during deposition of the buffer layer was changed. For Samples 8 to 11, the V / III ratio y during deposition of the n-type semiconductor layer was fixed at 252, and the V / III ratio during deposition of the buffer layer was changed. From Table 2, Samples 4 and 5 are plotted at the same position in FIG. 2, and similarly, Samples 8 and 9 are plotted at the same position in FIG. 2, but for ease of viewing, overlapping plots are shown side by side.

[0059] As can be seen from the graph in Figure 2, the lower both the V / III ratio x during the formation of the buffer layer and the V / III ratio y during the formation of the n-type semiconductor layer, the more uniform the in-plane distribution of the emission wavelength in the wafer becomes. In particular, in Figure 2, it can be seen that the in-plane distribution of the emission wavelength in the wafer becomes uniform in the region below the line y=-x+650, i.e., in the region y≦-x+650.

[0060] 2, it can be seen that the in-plane distribution of the emission wavelength on the wafer is more uniform in the region of y≦−x+650, which is the region surrounded by the lines y=1.1x and y=3.0x. Furthermore, in FIG. 2, the in-plane distribution of the emission wavelength on the wafer is further uniform in the region of y≦−x+550.

[0061] Furthermore, as shown in FIG. 2, in this experimental example, the V / III ratio x during deposition of the buffer layer was set to 100 or more, and the V / III ratio y during deposition of the n-type semiconductor layer was set to 200 or more. This is not intended to homogenize the in-plane distribution of the emission wavelength in the wafer, but is thought to improve the crystallinity of the buffer layer and the n-type semiconductor layer, thereby increasing the light emission output of the wafer. More specifically, x was set to 127 or more and 318 or less, and y was set to 252 or more and 503 or less. x is preferably 250 or less, and more preferably 150 or less. y is preferably 400 or less, more preferably 377 or less, and even more preferably 300 or less.

[0062] For wafers of samples 1 to 11, the relationship between the radius of curvature of the intermediate film formed when the n-type semiconductor layer was grown and the coefficient of variation of the wavelength distribution on the wafer is shown in Figure 3. It can be seen from Figure 3 that the larger the radius of curvature of the intermediate film formed, the smaller the coefficient of variation of the wavelength distribution on the wafer. In particular, the radius of curvature of the intermediate film formed is preferably 5.2 m or more, and more preferably 5.5 m or more.

[0063] (Summary of the embodiment) Next, the technical ideas grasped from the above-described embodiments will be described by using the reference numerals and the like in the embodiments. However, the reference numerals and the like in the following description do not limit the components in the claims to the members and the like specifically shown in the embodiments.

[0064] [1] A first embodiment of the present invention is a method for manufacturing a nitride semiconductor light-emitting device 1 in which a substrate 2, a buffer layer 3 containing Al and N, an n-type semiconductor layer 4 containing Al, Ga, and N, an active layer 6 containing Al and N, and a p-type semiconductor layer 8 are stacked in this order, III [μmol / min] vs. the flow rate F of the source gas of group V elements v [μmol / min] ratio F v / F III is defined as a V / III ratio, the V / III ratio when the buffer layer 3 is formed is defined as x, and the V / III ratio when the n-type semiconductor layer 4 is formed is defined as y, where x and y satisfy the relationship y≦−x+650. This makes it possible to make the in-plane distribution of the emission wavelength uniform on the wafer to be manufactured.

[0065] [2] A second embodiment of the present invention is the first embodiment, wherein the x and the y further satisfy the relationship 1.1x≦y≦3.0x. This makes it possible to make the in-plane distribution of the emission wavelength uniform on the wafer to be manufactured.

[0066] [3] A third embodiment of the present invention is the first or second embodiment, wherein x is 100 or more and y is 200 or more. This makes it possible to make the in-plane distribution of the emission wavelength uniform on the wafer to be manufactured.

[0067] [4] A fourth embodiment of the present invention is the third embodiment, wherein x is 127 or more and 318 or less, and y is 252 or more and 503 or less. This makes it possible to make the in-plane distribution of the emission wavelength uniform on the wafer to be manufactured.

[0068] [5] A fifth embodiment of the present invention is any one of the first to fourth embodiments, wherein the x and the y further satisfy the relationship y≦−x+550. This makes it possible to make the in-plane distribution of the emission wavelength uniform on the wafer to be manufactured.

[0069] [6] A sixth embodiment of the present invention is any one of the first to fifth embodiments, wherein the intermediate film after the formation of the n-type semiconductor layer 4 has a diameter of the order of 10 mm, and the absolute value of the radius of curvature of the surface of the n-type semiconductor layer 4 at the film formation temperature of the n-type semiconductor layer 4 is 5.2 m or more. This makes it possible to make the in-plane distribution of the emission wavelength uniform on the wafer to be manufactured.

[0070] (Addendum) Although the embodiments of the present invention have been described above, the invention according to the claims is not limited to the above-described embodiments. It should be noted that not all of the combinations of features described in the embodiments are necessarily essential to the means for solving the problems of the invention. Furthermore, the present invention can be appropriately modified and implemented within the scope of its spirit. [Explanation of symbols]

[0071] 1...Nitride semiconductor light emitting device 2...Substrate 3...Buffer layer 4...n-type semiconductor layer 6…Active layer 8...p-type semiconductor layer

Claims

1. 1. A method for manufacturing a nitride semiconductor light-emitting device in which a substrate, a single or multiple buffer layer containing Al and N, a single or multiple n-type semiconductor layer containing Al, Ga, and N, an active layer containing Al and N, and a p-type semiconductor layer are stacked in this order, the buffer layer and the n-type semiconductor layer are adjacent to each other, Flow rate F of source gas of group III element ＩＩＩ Flow rate F of the source gas of the V group element [μmol / min] ｖ Ratio F [μmol / min] ｖ / F ＩＩＩ is defined as a V / III ratio, the V / III ratio when the buffer layer is formed is defined as x, and the V / III ratio when the n-type semiconductor layer is formed is defined as y, the x and y satisfy the relationship y≦−x+650, When the buffer layer is composed of a plurality of layers, x is the V / III ratio when depositing a layer in the buffer layer that is closest to the n-type semiconductor layer, When the n-type semiconductor layer is composed of a plurality of layers, y is the V / III ratio when a layer in the n-type semiconductor layer that is closest to the buffer layer is formed. A method for manufacturing a nitride semiconductor light-emitting device.

2. The x and y further satisfy the relationship 1.1x≦y≦3.0x. The method for manufacturing the nitride semiconductor light-emitting device according to claim 1 .

3. The x is 100 or more, The y is 200 or more. The method for manufacturing the nitride semiconductor light-emitting device according to claim 1 or 2.

4. The x is equal to or greater than 127 and equal to or less than 318, The y is equal to or greater than 252 and equal to or less than 503. The method for manufacturing a nitride semiconductor light-emitting device according to claim 3 .

5. The x and y further satisfy the relationship y≦−x+550. The method for manufacturing the nitride semiconductor light-emitting device according to claim 1 or 2.

6. the intermediate film body after the formation of the n-type semiconductor layer has a diameter of the order of 10 mm, and the absolute value of the radius of curvature of the surface of the n-type semiconductor layer at the film formation temperature of the n-type semiconductor layer is 5.2 m or more; The method for manufacturing the nitride semiconductor light-emitting device according to claim 1 or 2.

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