High power electronic device and method for manufacturing same

Abstract

SOLUTION: To provide a high power electronic device that is formed of multiple layers including a molding compound, a printed circuit board, conductive contacts, at least one electronic component, and a molding compound, and is provided with a layer of a dielectric carrier, and a method of forming the same.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] (Related Applications) This application claims priority to U.S. Provisional Patent Application No. 63 / 121,524, filed December 4, 2020, and incorporated herein by reference.

[0002] The present disclosure is directed to high power electronic devices and methods of manufacturing the same. More particularly, the present disclosure relates to solid state devices and methods of manufacturing the same. [Background technology]

[0003] As the "mobile vehicle," industrial, commercial, and consumer markets become more electrified, the need for more reliable, smaller, lighter, and lower-cost electronic devices increases. With this trend comes the need for controls and switches that can be used to reliably and intelligently regulate electrical equipment.

[0004] In the past, relays were used to provide this function, but relays are large electromechanical devices with limited lifespan and performance that cannot meet the increasing requirements and are not a viable alternative for next generation electronic devices.

[0005] Solid-state switches using MOSFETs (Metal Oxide Field Effect Transistors) are a more reliable, smaller, lighter, and more cost-effective alternative to the relays used in the past. MOSFETs can be used individually or placed in parallel to carry hundreds of amperes of current in applications requiring this level of power.

[0006] One of the challenges associated with transmitting high power (high current) is the heat (I 2× R). Increased heat reduces the lifespan and performance of electronic devices. The key to minimizing the heat generated in the current path is to reduce the resistance in the system.

[0007] In traditional printed circuit board (PCB) packaging methods, the ability to carry high currents is limited by the thickness of the copper traces. For high-current applications, the practical limit due to the processes used to manufacture PCBs is circuit boards with 4-ounce (144-micron-thick) copper layers. In some cases, multiple layers are interconnected using electrical and thermal vias to be able to carry higher currents and remove heat. This creates several problems: the PCB becomes very expensive, it becomes difficult to remove heat from the inner layers, and it becomes very difficult to mix high-current layers with signal layers.

[0008] Applicant has a proprietary technology, referred to as ASEP Technology, which integrates the benefits of high current conductive metal stamping, high temperature dielectric material, and selectively metallized circuit patterns on the surface of the dielectric material to create systems that are often smaller, lighter, more reliable, and cost-effective. ASEP Technology enables designers to create high current carrying switches or modules using traditional manufacturing methods such as stamping and molding, eliminating the need for expensive (thick copper) PCBs, reducing the size of the system, and ultimately producing a very cost-effective product.

[0009] While ASEP technology enables the design and manufacture of high-power electronic devices that may not have been possible in the past, the process requires additional capital and tooling. For lower volume applications, the additional costs may be difficult to justify. Additionally, there may be some applications that can be produced using more conventional manufacturing methods.

[0010] Therefore, there is a need for improved high power electronic devices and improved methods of fabricating same. Summary of the Invention

[0011] Thus, in one embodiment, the present disclosure provides a high-power electronic device formed of a first layer of molding compound, a second layer over the first layer comprising a printed circuit board, a third layer over the second layer formed with conductive contacts, a fourth layer over the third layer formed with at least one electronic component, and a fifth layer over the fourth layer formed with molding compound.

[0012] In one embodiment, the present disclosure provides a high-power electronic device formed of a first layer of molding compound, a second layer over the first layer comprising a printed circuit board, a third layer over the second layer formed with conductive contacts, a fourth layer over the third layer formed with at least one electronic component, and a fifth layer over the fourth layer formed with molding compound.

[0013] In one embodiment, the present disclosure provides a method of forming a high-power electronic device, the method including: forming a stamping from a sheet of thick conductive material, the stamping including a lead frame portion and at least first and second electronic component attachment contacts coupled to the lead frame portion by fingers; and attaching an electronic component to the first and second electronic component attachment contacts to form an assembly, the electronic component having a plurality of terminals, one of the plurality of terminals of the electronic component not attached to the first and second electronic component attachment contacts. [Brief explanation of the drawings]

[0014] The present disclosure is illustrated by way of example and not limitation in the accompanying figures, in which like reference numerals indicate similar elements and in which:

[0015] [Figure 1] 1 shows a perspective view of a high-power electronic device. [Figure 2] 1A-1C show top views of components used in a first method of forming a high power electronic device. [Figure 3] 1A-1C show top views of components used in a first method of forming a high power electronic device. [Figure 4] 1A-1C show top views of components used in a first method of forming a high power electronic device. [Figure 5] 1A-1C show top views of components used in a first method of forming a high power electronic device. [Figure 6] 1A-1C show top views of components used in a first method of forming a high power electronic device. [Figure 7] 1A-1C show top views of components used in a first method of forming a high power electronic device. [Figure 8] 1A-1C show top views of components used in a first method of forming a high power electronic device. [Figure 9] 1A-1C show top views of components used in a first method of forming a high power electronic device. [Figure 10] 1A-1C show top views of components used in a first method of forming a high power electronic device. [Figure 11] 1 shows a top view of a component used in a second method of forming a high-power electronic device. [Figure 12] 1 shows a top view of a component used in a second method of forming a high-power electronic device. [Figure 13] 1 shows a top view of a component used in a second method of forming a high-power electronic device. [Figure 14] 1 shows a top view of a component used in a second method of forming a high-power electronic device. [Figure 15] 1 shows a top view of a component used in a second method of forming a high-power electronic device. [Figure 16] 1 shows a top view of a component used in a second method of forming a high-power electronic device. DETAILED DESCRIPTION OF THE INVENTION

[0016] The accompanying drawings illustrate embodiments of the present disclosure, it being understood that the disclosed embodiments are merely examples of the present disclosure, which may be embodied in various forms. Accordingly, the specific details disclosed herein should not be construed as limiting, but merely as a basis for the claims and as a representative basis for teaching those skilled in the art to employ the present disclosure in various ways.

[0017] Provided herein is a high-power electronic device 20 and improved methods of fabricating the same. One type of high-power electronic device 20 is a solid-state device, such as a solid-state switch, that requires one FET (Field Effect Transistor) to switch less than 50 amperes of power. In one embodiment, the FET is a MOSFET (Metal Oxide Field Effect Transistor).

[0018] The first manufacturing method is shown in FIGS. 1 to 10, and the second manufacturing method is shown in FIGS.

[0019] Attention is directed to a first manufacturing method illustrated in FIGS. 1-10, which is carried out by the following steps.

[0020] As shown in FIG. 2, stamping 22 is formed from a thick sheet of conductive material. In one embodiment, the material is copper. In another embodiment, the material is aluminum. The material has a thickness of about 200 microns to about 3,000 microns, and preferably about 500 microns to about 800 microns, which is much thicker than conventional traces provided on current printed circuit boards, as described above. Because stamping 22 has a large thickness, stamping 22 can carry high currents without having to stack multiple stampings on top of each other. Stamping 22 can be formed in a reel-to-reel (continuous flow) manufacturing process.

[0021] 2 and 3, stamping 22 includes a plurality of contact subassemblies 24a, 24b, 24c, 24d, each of which includes a leadframe section 26 and a plurality of contacts 28a, 28b, 28c, 28d and 32, 34, 36, 38, 40, 42, 44, 46, some of the plurality of contacts coupled to the leadframe section by leadframe connection fingers 48 and some connected to each other by contact connection fingers 50. Finger connection fingers 52 may be provided to connect contacts such as contacts 28b, 28d to leadframe connection fingers 48. Each contact subassembly 24a, 24b, 24c, 24d further includes circuit board contacts 54, 56, which may extend from one of the fingers 50 or from leadframe 26. In the embodiment as shown, each leadframe section 26 has first, second, third, and fourth leadframe portions 58, 60, 62, 64 that define an interior space 66 in which the contacts and fingers are provided. If only three leadframe portions 58, 60, 62 are provided, the interior space 66 is further defined by the first leadframe portions 58 of adjacent contact subassemblies 24a, 24b, 24c, 24d. The first and second leadframe portions 58, 60 of contact subassemblies 24a, 24b, 24c, 24d are parallel to one another, and the second and third leadframe portions 62, 64 of contact subassemblies 24a, 24b, 24c, 24d are contiguous with one another and perpendicular to the first and second leadframe portions 58, 60. The contacts of each contact subassembly 24a, 24b, 24c, 24d include at least first and second electronic component mounting contacts, designated as contacts 28a, 28b. Other contacts may be provided extending from one of the lead frame sections 26, as shown.

[0022] The first electronic component mounting contact 28a has a first mounting portion 68a adjacent to, parallel to, and spaced apart from the second mounting portion 68b of the electronic component mounting contact 28b. A space 70 is defined between the first mounting portion 68a and the second mounting portion 68b. One of the mounting portions 68a has a length greater than the length of the other mounting portion 68b, thus providing a gap 72. The circuit board contact 54 extends into the gap 72. The configurations shown in Figures 2 and 3 represent one example of contacts and fingers in a contact subassembly, and other configurations are within the scope of this disclosure.

[0023] 4 and 5, a signal terminal 74 of an electronic component 76, such as a FET, is electrically coupled to the circuit board contact 54, for example, by solder, wire, or ribbon bond, and the remaining contacts 78 of the electronic component 76 are electrically coupled to the first mounting portion 68a and the second mounting portion 68b, for example, by solder, wire, or ribbon bond. The electronic component 76 spans the space 70 between the first mounting portion 68a and the second mounting portion 68b. Additionally, electronic component mounting contacts 28c, 28d and the second circuit board contact 56 are formed as part of the stamping 22, to which a second electronic component 76, such as a FET, is similarly electrically coupled. This configuration protects the resulting switch from being switched when the battery voltage is reversed. If reverse battery protection is not required, the second electronic component 76, mounting contacts 28c, 28d, and second circuit board contact 56 would not be needed, although minor modifications, such as the addition of a zero-ohm resistor or strap, would be required to complete the circuit, as would be understood by one skilled in the art. Referring to Figure 5, a shunt 80 may be electrically coupled between the second electronic component mounting contacts 28b, 28d to allow for current measurement.

[0024] Thereafter, as shown in FIG. 6, the contact subassemblies 24a, 24b, 24c, 24d are singulated to form individual subassemblies 82a, 82b, 82c, 82d with the electronic components 76 mounted thereon.

[0025] A conventional populated printed circuit board (PCB) 84 is provided within PCB panel 86 of Figure 7, and individual subassemblies 82a, 82b, 82c, 82d are placed on PCB 84, as shown in Figure 8. Contacts 28a, 28b, 28c, 28d, 32, 34, 36, 38, 40, 42, 44, 46 of each subassembly 82a, 82b, 82c, 82d are then electrically coupled to traces on PCB 84 by, for example, one or more of solder, fasteners such as tapping screws, wire or ribbon bonds, etc. Other means for coupling may also be provided.

[0026] 10 , the lead frame sections 26 and fingers 48, 50, 52 of each subassembly 82a, 82b, 82c, 82d are then removed, leaving only the contacts 28a, 28b, 32, 34, 36, 38, 40, 42, 44, 46, 54 and electronic component 76 electrically coupled to each PCB 84 (and, if present, contacts 28c, 28d, second circuit board contacts 56, second electronic component 76, and shunt 80), thereby forming individual assemblies 90. Each individual assembly 90 is then removed from the PCB panel 86.

[0027] Finally, each individual assembly 90 is overmolded with molding compound 92 to create a miniature solid-state switch, as shown in Figure 1. A low pressure molding compound may be used.

[0028] The steps shown in FIG. 7 may be performed at any time before the steps shown in FIG.

[0029] In one embodiment, circuit board contacts 54 (and circuit board contacts 56 ) are eliminated, and signal terminals 74 of electronic components 76 are electrically coupled directly to PCB 84 .

[0030] 1-10 creates a sandwich structure of high-power electronic device 20 having the following layers: a first, bottom layer formed of molding compound 92; a second layer over the first layer formed of PCB 84; a third layer over the second layer formed of contacts 28a, 28b, 32, 34, 36, 38, 40, 42, 44, 46, 54 (and, if present, contacts 28c, 28d, second circuit board contact 56); a fourth layer over the third layer formed of electronic component 76 (and, if present, second electronic component 76, shunt 80); and a fifth layer over the fourth layer formed of molding compound 92. The fifth layer also overlies the portion of the second layer not covered by the third layer. The contacts 28a, 32, 34, 36, 38, 40, 42, 44, 46 extend outwardly from the molding compound 92 for connection to another electrical device (not shown).

[0031] When an embodiment having two FETs 76 is provided, the contacts form pins. One pin may be a current sense pin, one pin may be a fault detection pin (used to shut down device 20 if a fault is detected), one pin may be an enable pin (turning current on / off), one pin may be grounded, one pin may be configured to connect to a battery (power source), and one pin is configured to connect to a load (an item to be powered). In one embodiment, one FET 76 is connected to a battery pin and the other FET 76 is connected to a load pin, with a shunt 80 connected to each of the battery and load pins. Thus, device 20 essentially forms a smart solid-state relay.

[0032] Attention is directed to the second manufacturing method shown in FIGS. 1, 2 and 11-16, which is carried out by the following steps.

[0033] The stamping 22 is formed as shown in FIG. 2, the details of which will not be repeated here.

[0034] 11, contact subassemblies 24a, 24b, 24c, 24d are then singulated to form individual subassemblies. In this embodiment, electronic component 76 (and, if present, second electronic component 76, shunt 80) is not assembled on stamping 22 prior to singulation.

[0035] As shown in Figure 12, contact subassemblies 24a, 24b, 24c, 24d are insert molded into a dielectric carrier 92. Then, as shown in Figure 13, the lead frame section 26 and fingers 48, 50, 52 of each contact subassembly 24a, 24b, 24c, 24d are removed, leaving only contacts 28a, 28b, 32, 34, 36, 38, 40, 42, 44, 46, 54 (and contacts 28c, 28d, second circuit board contact 56, if present) on the carrier 92.

[0036] 14 , PCB 84 is placed on carrier 92 or inserted through opening 94 in carrier 92 so that edge 96 of PCB 84 is adjacent contacts 28 a, 28 b, 32, 34, 36, 38, 40, 42, 44, 46, 54 (and, if provided, contact 56). When PCB 84 is placed on carrier 92, PCB 84 may rest partially on at least some of the contacts. PCB 84 is bonded to carrier 92 to maintain its position on carrier 92. In some embodiments, PCB 84 is bonded to carrier 92 by heat staking.

[0037] As shown in FIG. 15 , electronic component 76 (and, if present, second electronic component 76, shunt 80) is electrically coupled to contacts 28 a, 28 b, 32, 34, 36, 38, 40, 42, 44, 46, 54 (and, if present, contact 56). As shown and described above, signal terminal 74 of electronic component 76 is electrically coupled to circuit board contact 54, for example, by solder, wire, or ribbon bond, and the remaining contacts 78 of electronic component 76 are electrically coupled to first mounting portion 68 a and second mounting portion 68 b, for example, by solder, wire, or ribbon bond. Electronic component 76 spans space 70 between first mounting portion 68 a and second mounting portion 68 b. Additionally, electronic component mounting contacts 28 c, 28 d and second circuit board contact 56 are formed as part of stamping 22, to which second electronic component 76, such as a FET, is similarly electrically coupled. This configuration protects the resulting switch from being switched with the battery voltage reversed. If reverse battery protection is not required, the second electronic component 76, mounting contacts 28c, 28d, and second circuit board contact 56 are not required, although minor modifications, such as the addition of a zero-ohm resistor or strap, would be required to complete the circuit, as would be understood by those skilled in the art. Referring to FIG. 5, a shunt 80 may be electrically coupled between the second electronic component mounting contacts 28b, 28d to enable current measurement.

[0038] Alternatively, the steps shown in FIG. 15 can be performed before the steps shown in FIG.

[0039] Contacts 28a, 28b, 32, 34, 36, 38, 40, 42, 44, 46, 54 (and, if provided, contacts 28c, 28d, second circuit board contact 56) are then electrically coupled to PCB 84, for example, by one or more of solder, fasteners such as tapping screws, wire or ribbon bonds, etc. Other means for coupling may also be provided.

[0040] In one embodiment, circuit board contacts 54 (and, if present, circuit board contacts 56 ) are eliminated, and signal terminals 74 of electronic components 76 are electrically coupled directly to PCB 84 .

[0041] Finally, as shown in Figure 1, the carrier 92, PCB 84, and contacts 28a, 28b, 32, 34, 36, 38, 40, 42, 44, 46, 54 (and contacts 28c, 28d, second circuit board contact 56, if present) are overmolded with molding compound 92 to create the miniature solid-state switch. A low-pressure molding compound may be used.

[0042] The second manufacturing method, shown in Figures 1, 2, and 11-16, produces a sandwich structure of high-power electronic device 20 having the following layers: a first, bottom layer formed of molding compound 92; a second layer over the first layer formed of carrier 92; a third layer over the second layer formed of PCB 84; a fourth layer over the third layer formed of contacts 28a, 28b, 32, 34, 36, 38, 40, 42, 44, 46, 54 (and, if present, contacts 28c, 28d, and second circuit board contact 56); a fifth layer over the fourth layer formed of electronic component 76 (and, if present, second electronic component 76 and shunt 80); and a sixth layer over the fifth layer formed of molding compound 92. The sixth layer also overlies the portions of the second and third layers not covered by the fourth layer. The contacts 28a, 32, 34, 36, 38, 40, 42, 44, 46 extend outwardly from the molding compound 92 for connection to another electrical device (not shown).

[0043] This second embodiment recognizes that solid-state devices suffer from the low junction temperatures of the integrated circuits used therein. Many of these devices use FETs and insulated-gate bipolar transistors (IGBTs), which generate their own heat during operation. This self-generated heat, plus the high temperatures present in their environment, necessitate thermal management to transfer heat away from the FETs so that junction temperatures do not reach them. Current solutions use bare dies with intimate thermal contact to a heat sink for heat rejection. This second embodiment solders the packaged FET / IC onto thick, thermally conductive contact terminal blades to transfer heat away from the device 20. The PCB 84 may be bonded to the packaged IC terminals using wire or ribbon bonds, and the PCB 84 may be bonded to the signal terminals 74 using wire or ribbon bonds. Fabrication of the above-described solid-state device is described and illustrated below.

[0044] While specific embodiments have been shown and described with reference to the drawings, it is anticipated that those skilled in the art may devise various modifications without departing from the spirit and scope of the appended claims. Accordingly, it will be understood that the disclosure and the appended claims are not limited to the specific embodiments shown in and discussed with reference to the drawings, and that modifications and other embodiments are intended to be included within the scope of the disclosure and the appended drawings. Furthermore, while the foregoing description and associated drawings describe exemplary embodiments in the context of particular example combinations of elements and / or functions, it will be understood that different combinations of elements and / or functions may be provided by alternative embodiments without departing from the scope of the disclosure and the appended claims. Furthermore, the foregoing description describes methods that enumerate the performance of several steps. Unless otherwise specified, one or more steps within a method may not be required, one or more steps may be performed in a different order than described, and one or more steps may occur substantially simultaneously. Finally, the drawings are not necessarily drawn to scale.

[0045] The disclosure provided herein describes features in terms of its preferred and exemplary embodiments, and many other embodiments, modifications, and variations within the scope and spirit of the appended claims will occur to those skilled in the art from a consideration of this disclosure.

Claims

[Claim 1] A high-power electronic device a first layer of molding compound; a second layer on the first layer comprising a printed circuit board; a third layer on the second layer formed with conductive contacts; a fourth layer formed of at least one electronic component on the third layer; and a fifth layer formed of a molding compound on the fourth layer; and a sixth layer between the first and second layers; The sixth layer comprises a dielectric carrier.

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